JP2002164813A - Matched-filter unit and method of matched-filtering in receiving set - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale of the whole unit. SOLUTION: In this matched-filer unit, n-bits input data are shifted sequentially while holding them individually at each of register groups 102-1 to 102-k, among the held n-bits data, i-th bit data corresponding to a count value i of a counter 112 are selected at each selector 104-1 to 104-k, the selected data are multiplied by codes for inverse spread held in each of registers 105-1 to 105-k at each of multipliers 106-1 to 106-k, respective multiplied data are added at an adder 107, the added data is shifted corresponding to the count value i at a shift circuit 108, this data and a selected value from a selector 111 are added at an adder 109, this added data is held at a resistor 110, the count value is incremented after holding, and at the count value i=1, 0 (zero) is made the selected value, and at the count value i≠1, the holding data at the register 110 is made the selected value at the selector 111.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CDMA (Code D)
In mobile communication systems to which the ivision Multiple Access (ivision Multiple Access) method is applied, mobile station devices such as mobile phones, information communication terminal devices having mobile phone functions and computer functions, and base station devices performing wireless communication with the mobile station devices. The present invention relates to a matched filter device applied to a receiving device and a matched filtering method in the receiving device.

[0002]

2. Description of the Related Art Conventionally, as a matched filtering method in a matched filter device and a receiving device of this type, there is one described in Japanese Patent Application Laid-Open No. 2000-82938.

FIG. 3 is a block diagram showing a configuration of a conventional matched filter device.

The matched filter device 30 shown in FIG.
0 is applied to, for example, a receiver of a CDMA mobile station apparatus or a base station apparatus, and is used by an A / D converter for converting a multilevel signal after baseband signal processing into a digital signal in a receiver (not shown). It is connected to the subsequent stage and performs matching filtering processing on multi-valued data.

[0005] This matched filter device 300 has an A /
K comprising n registers 301-1 to 301-n holding n-bit input data output from the D conversion means
Register groups 302-1 to 302-k and 303;
K registers 30 for holding codes for performing despreading
4-1 to 304-k and k multipliers 305-1 to 30-30
5-k and an adder 306.

Each of the register groups 302-1 to 302-k is
The n-bit input data output from the A / D conversion means are cascaded so as to sequentially shift to the subsequent stage while retaining the n-bit input data. It is connected between the connected register groups 302-1 to 302-k. Although only one register group 303 is shown in the figure, a plurality of register groups 303 are connected corresponding to a desired configuration of the matched filter device 300.

In such a configuration, n-bit input data is first held in the register group 302-1 and then stored in the register group 302-1.
Register group 303, register groups 302-2 to 302-k
Are held while being sequentially shifted.

The n-bit data held in each of the register groups 302-1 to 302-k is output to each of the multipliers 305-1 to 305-1.
At 05-k, it is despread by being multiplied by the code held in registers 304-1 to 304-k,
The despread data is added in adder 306, and the desired data is output.

[0009]

However, in the conventional apparatus, each of the multipliers 305-1 to 305-k
, A circuit scale for multiplying each of the n-bit data by the code is required, and the adder 306 also requires a circuit scale for adding all the n-bit data after the multiplication. There is a problem that the scale increases according to the number of bits of the input data.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a matched filter device and a matched filtering method in a receiving device that can reduce the circuit scale of the entire device.

[0011]

SUMMARY OF THE INVENTION A matched filter device according to the present invention comprises a plurality of registers connected in cascade so as to sequentially shift to a subsequent stage while holding n-bit input data, and a cyclic circuit of count values 0 to n. A counter for performing counting, first selection means for selecting the i-th held data corresponding to the count value i from the n-bit data held in the plurality of register groups, A plurality of multiplying means for multiplying the data of the i-th bit in each register group by a predetermined code; a first adding means for adding the multiplied data by each of the multiplying means; Shifting means for shifting in accordance with the count value i, second adding means for adding the data shifted by this means and the selected value, and holding the added data by this means; Holding means for instructing increment of the count value i later; and setting 0 as the selected value when the count value i = 1 and setting the data held in the holding means as the selected value when the count value i ≠ 1. And a second selecting means for outputting to the second adding means.

According to this configuration, each of the multiplication means, which must originally be configured to multiply all the data (n-bit data) held in the plurality of register groups by the code,
All that is required is to multiply the data of only one bit each by the sign. Also, originally, n
The first adding means, which must be configured to add all the multiplied data of bits, is one in each of the plurality of multiplying means.
It is sufficient only to add the bit multiplication data. Therefore, the circuit configurations of the plurality of multiplying units and the first adding unit can be reduced in size, so that the configuration of the entire matched filter device can be reduced.

A matched filter device according to the present invention includes a plurality of registers connected in cascade so as to sequentially shift to a subsequent stage while holding n-bit input data, and any one of n bits of the input data at an arbitrary period. Control means for designating one of the bits, and n stored in the plurality of register groups.
First selecting means for selecting, from the data of the bits, the held data of the x-th bit corresponding to the specified bit x;
A plurality of multiplying means for multiplying the data of the x-th bit in each register group selected by the means with a predetermined code, and a first multiplying means for adding the multiplied data by each of the multiplying means
Adding means, shifting means for shifting the added data by this means, second adding means for adding the data shifted by this means and the selected value, holding means for holding the added data by this means, A second selecting unit that sets 0 as the selected value when the designated bit x is switched, and outputs data held in the holding unit as the selected value to the second adding unit when the switching is not performed during the switching. Take.

According to this configuration, the control unit can specify the 1-bit data selected by the first selection unit at an arbitrary cycle.

The matched filter device of the present invention employs a configuration in which, when the n-bit input data is spread data, a code multiplied by a plurality of multiplying means is despread data.

According to this configuration, the same effect as any of the above can be obtained in the matched filter device for the spread spectrum processing.

The path search device of the present invention employs a configuration including a matched filter device having the same configuration as any of the above.

According to this configuration, in the path search device, the same operation and effect as any of the above can be obtained.

The mobile station apparatus of the present invention employs a configuration including the path search device having the above configuration.

According to this configuration, in the mobile station device,
The same operation and effect as any of the above can be obtained.

The base station apparatus according to the present invention employs a configuration including the path search device having the above configuration.

According to this configuration, in the base station apparatus,
The same operation and effect as any of the above can be obtained.

According to the matched filtering method in the receiving apparatus of the present invention, the input data of n bits is sequentially shifted to the subsequent stage while being held, and the n-bit data held in each stage corresponds to the count value i of the counter. The selected i-th held data is selected, the selected i-th data is multiplied by a predetermined code, the multiplied data is added, and the added data is shifted according to the count value i. Then, the shifted data and the selected value are added, the added data is held, and after the holding, an instruction to increment the count value i is issued. When the count value i = 1, 0 is set as the selected value, The count value i ≠
At the time of 1, the held addition data is used as the selection value, as in the receiving apparatus.

According to this method, the multiplication circuit which must originally multiply all the data (n-bit data) held in each holding stage by the sign is replaced with the data of only one bit each. With only multiplication by Also, an adder circuit which should originally be configured to add all n-bit multiplied data is 1
A configuration in which only bit multiplication data is added can be adopted. Therefore, the configuration of the entire matched filter can be reduced in size.

According to the matched filtering method in the receiving apparatus of the present invention, the input data of n bits are sequentially shifted to the subsequent stage while being held, and any one of the n-bit data held in each stage is selected at an arbitrary period. Bit, and selects the x-th held data corresponding to the specified bit x, multiplies the x-th data in each of the selected register groups by a predetermined code, and , The added data is shifted, the shifted data and the selected value are added, the added data is held, and 0 is set as the selected value when the designated bit x is switched, At the time other than the time of switching, the added data held is used as the selected value.

According to this method, 1-bit data to be selected from the held n-bit input data can be designated at an arbitrary cycle.

[0027]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing a configuration of a matched filter device according to Embodiment 1 of the present invention.

The matched filter device 10 shown in FIG.
0 is applied to, for example, a receiver of a CDMA mobile station apparatus or a base station apparatus, and is used by an A / D converter for converting a multilevel signal after baseband signal processing into a digital signal in a receiver (not shown). It is connected to the subsequent stage and performs matching filtering processing on multi-valued data. in particular,
The present invention is applied to a path search device that searches for an optimal signal path by detecting a correlation value of an optimal signal in a receiving device.

The matched filter device 100 has an A / A
K comprising n registers 101-1 to 101-n holding n-bit input data output from the D conversion means
Register groups 102-1 to 102-k and 103;
k selectors 104-1 to 104-k and k registers 105-1 to 105-1 for holding codes for performing despreading
05-k, k multipliers 106-1 to 106-k,
Adder 107, shift circuit 108, adder 109
, A register 110, a selector 111, and a counter 1
12 are provided.

Each of the register groups 102-1 to 102-k has
The n-bit input data output from the A / D conversion means are cascade-connected so as to sequentially shift to the subsequent stage while holding the data. It is connected between the connected register groups 102-1 to 102-k. Although only one register group 103 is shown in the figure, a plurality of register groups 103 are connected corresponding to a desired configuration of the matched filter device 100.

In such a configuration, n-bit input data is first held in the register group 102-1 and then stored in the register group 102-1.
Register group 103, register groups 102-2 to 102-k
Are held while being sequentially shifted.

The n-bit data held in each of the register groups 102-1 to 102-k is stored in each of the selectors 104-1 to 104-k.
Output to 104-k.

In each of the selectors 104-1 to 104-k,
Of the n-bit data, only one-bit data corresponding to the current count value i of the counter 112 is selected and output to the multipliers 106-1 to 106-k.

The selection operation of the selectors 104-1 to 104-k will be described by using the selector 104-1 as a representative. For example, if the count value i = 2, the selector 10
4-1 selects the second bit data from the register 101-2 that holds the second bit input data from the register group 102-1 and outputs it to the multiplier 106-1.

As described above, each of the selectors 104-1 to 104-1
The i-th data selected by −k is output to each multiplier 106
-1 to 106-k, the registers 105-1 to 105-1
The data is despread by being multiplied by the code held in 5-k, and the despread data is added in the adder 107.

That is, each of the multipliers 106-1 to 106-k
Are each multiplied by 1-bit data to form an adder 1
07, and the adder 107 outputs each of the multipliers 106-1 to 106-1.
1-bit data from 106-k is added.

This addition data is output to the shift circuit 108, where the addition data is shifted left by i−1 bits and output to the adder 109.

Here, the selector 111 sets the counter value i
When = 1, 0 is output to the adder 109, and when i ≠ 1, the value of the register 110 is output to the adder 109. The ground 113 connected to the selector 111 is for setting the value of the selector 111 to 0.

Therefore, in the adder 109, the shift circuit 1
08 and the output value of the selector 111 are added, and the added value is held in the register 110. After this holding, the value of the counter 112 is incremented by "1", and the above processing is repeated. After ending the processing when the count value i = n, the correlation value held in the register 110 is output.

However, the instruction for increment after the data is held in the register 110 is sent from the register 110 to the counter 112.
Alternatively, control means may be connected between the register 110 and the counter 112, and the control means may issue an instruction for increment after detection of holding.

As described above, according to the matched filter device 100 of the first embodiment, each of the register groups 102-1 to 102-1
02-k, sequentially shifting while individually holding n-bit input data, and selecting each of the selectors 104-1 to 104-k.
Then, of the n-bit data held in each of the register groups 102-1 to 102-k, the count value i of the counter 112 is set.
Is selected for the i-th bit held data. In each of the multipliers 106-1 to 106-k, the i-th data in each selected register group and each register 105
-1 to 105-k are multiplied by the held despreading code, and the adder 107 multiplies each of the multipliers 106-1 to 106-106.
Add the multiplication data at −k. Further, the shift circuit 10
8, the added data is shifted according to the count value i, the shifted data is added to the selected value from the selector 111, and the added data is held in the register 110. Gives an increment instruction. In the selector 111, the count value i = 1
In this case, 0 is used as the selection value, and when the count value i ≠ 1, the data held in the register 110 is used as the selection value.

Thus, each register group 102
Each of the multipliers 106-1 to 106-k, which must be configured to multiply all the data (n-bit data) held in -1 to 102-k by a code, has only one bit of data and a code. Only the multiplication of. Also,
Originally, the adder 107, which should be configured to add all the n-bit multiplication data in each of the plurality of multipliers 106-1 to 106-k,
It is only necessary to add 1-bit multiplication data in each of 6-k. Therefore, each of the multipliers 106-1 to 106-
Since the circuit configuration of k and the adder 107 can be reduced in size, the overall configuration of the matched filter device 100 can be reduced.

(Embodiment 2) FIG. 2 is a block diagram showing the configuration of a matched filter device according to Embodiment 2 of the present invention. However, in the second embodiment shown in FIG. 2, portions corresponding to the respective portions of the first embodiment in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

The matched filter device 20 shown in FIG.
0 is different from the matched filter device 100 shown in FIG.
And a shift circuit controller 202.

The selector controller 201 controls each selector 10
The bits selected by 4-1 to 104-k are specified for each symbol period of the input data, and the specified bits x are output to the selector 111.

The shift circuit controller 202 controls the shift circuit 1
08 specifies the number of bits to be shifted.

With such a configuration, each selector 10
In 4-1 to 104-k, each of the register groups 102-1 to 102-1
From the n-bit data held in 02-k, the x-th held data specified by the specified bit x is selected,
The selected x-th data is output to each multiplier 106-
1 to 106-k, the registers 105-1 to 105-105
The data is despread by being multiplied by the code held in −k, and the despread data is added in the adder 107.

The addition data is output to the shift circuit 108, where the addition data is supplied to the shift circuit controller 2
02 is shifted to the left by the number of bits designated by
Output to

Here, the selector 111 outputs 0 to the adder 109 at the time of the first bit processing when the designated bit x from the selector controller 201 switches, and otherwise, the data held in the register 110 is added to the adder 109. Output to

Therefore, in the adder 109, the shift circuit 1
08 and the output value of the selector 111 are added, and the added value is held in the register 110. When the processing of a plurality of arbitrary bits is completed, the correlation value is output from the register 110. Thereafter, the same processing as described above is repeated.

As described above, according to the matched filter device 200 of the second embodiment, each of the selectors 104-1 to 104-
Since the 1-bit data selected in k is specified for each symbol period of the input data, the same effect as that of the first embodiment can be obtained. And can be processed after selection.

[0053]

As described above, according to the present invention,
The circuit scale of the entire device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a matched filter device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a matched filter device according to Embodiment 2 of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional matched filter device.

[Explanation of symbols]

 100, 200 Matched filter device 101-1 to 101-n register 102-1 to 102-k, 103 register group 104-1 to 104-k, 111 selector 105-1 to 105-k, 110 register 106-1 to 106 −k Multiplier 107, 109 Adder 108 Shift circuit 112 Counter 113 Ground 201 Selector controller 202 Shift circuit controller

Claims (8)

[Claims] 1. A plurality of register groups cascaded so as to sequentially shift to a subsequent stage while holding n-bit input data, a counter for performing a cyclic count of count values 0 to n, and a plurality of register groups. First selecting means for selecting the held data of the i-th bit corresponding to the count value i among the held n-bit data, and the data of the i-th bit in each of the register groups selected by this means are predetermined. A plurality of multiplying means for multiplying the multiplied code, a first adding means for adding the multiplied data in each of the multiplying means, a shifting means for shifting the added data in this means according to the count value i, Second adding means for adding the data shifted by this means and the selected value, holding the added data by this means, and after this holding, giving an instruction to increment the count value i Holding means and the count value i = 1
And a second selecting means for outputting data held in the holding means as the selected value to the second adding means when 0 is the selected value at the time of the count value i ≠ 1. Matched filter device. 2. A plurality of register groups cascaded so as to sequentially shift to a subsequent stage while holding n-bit input data, and to designate any one of n bits of the input data at an arbitrary cycle. Control means, first selection means for selecting, from the n-bit data held in the plurality of register groups, x-th bit held data corresponding to the specified bit x, A plurality of multiplying means for multiplying the x-th data in each register group by a predetermined code; a first adding means for adding the multiplied data in each of the multiplying means; Shifting means, a second adding means for adding the data shifted by this means and the selected value, a holding means for holding the added data by this means, and 0 when the designated bit x is switched. And a second selection unit that outputs the data held in the holding unit as the selection value to the second addition unit as the selection value when the switching is not performed. 3. The matched device according to claim 1, wherein when the n-bit input data is spread data, a code multiplied by the plurality of multiplying means is data for despreading. Filter device. 4. A path search device comprising the matched filter device according to claim 1. Description: 5. A mobile station device comprising the path search device according to claim 4. 6. A base station apparatus comprising the path search device according to claim 4. 7. Shifting sequentially to a subsequent stage while holding n-bit input data, and selecting the i-th held data corresponding to the count value i of the counter from the n-bit data held in each stage. Then, the selected i-th bit data is multiplied by a predetermined code, the multiplied data is added, and the added data is shifted according to the count value i. The value is added, the added data is held, and after the holding, an instruction to increment the count value i is issued, and the count value i is incremented.
= 1, 0 is the selected value, and the count value i 値 1
A matched filtering method in the receiving apparatus, wherein the held added data is used as the selected value at the time of (i). 8. Shifting sequentially to the subsequent stage while holding the n-bit input data, designating any bit of the n-bit data held in each stage at an arbitrary cycle, and specifying the designated bit x Is selected, the x-th data held in each selected register group is multiplied by a predetermined code, and the multiplied data by each multiplication means is added. The added data is shifted, the shifted data and the selected value are added, and the added data is held. When the designated bit x is switched, 0 is used as the selected value, and when the designated bit x is switched, the held value is held except when the switching is performed. A matched filtering method in a receiving device, wherein the addition data is the selected value.