JP2002162904A - Hash function processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the speeding up of processing of the hash function processor of a HMAC method. SOLUTION: The hash function processor is provided with a key processing circuit 2 to perform first and second key processing for a first and a second input values A and B, respectively, and a data processing circuit 3 which makes the processing data of the second key processing into a second initial value Bo to perform second data processing to the output data X of a first data processing circuit, while making the processing data of the first key processing into a first initial value Ao to perform first data processing to processing object data D. The speeding up of hash processing can be realized by performing the second key processing in the key processing circuit 2 and the first data processing in the data processing circuit 3, in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for ensuring security in a computer network such as encryption of information communication data, and more particularly to a hash function processing device for converting a message into a hash value which is difficult to reversely convert.

[0002]

2. Description of the Related Art Conventionally, a hash function processing device of the HMAC system is processed by software. This method itself is called "" HMAC: Keyed-Hashing for Message Authenticati
on "RFC 2104 (1997)", MD5 and SH
An iterative cryptographic hash function such as A-1 is used in combination with a secret shared key. The hash function of the HMAC method obtains an XOR value from key data and set values A and B, and performs hashing by performing predetermined key processing and predetermined data processing. For these key processing and data processing, a hash function such as MD5 is applied. For a hash function such as MD5, a 128-bit initial value is set in advance, and processing data such as a message
The data is divided into 12 bits, and a transposition process or the like is repeated a predetermined number of times by leading to a hash function to obtain 128-bit output data.

[0003]

In the hash function processing device of the HMAC system, it is necessary to encrypt the target data to prevent the data from being easily decrypted. Therefore, complication of processing cannot be avoided. On the other hand, high-speed encryption is necessary, and studies for realizing it are desired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and when the configuration is realized by hardware in a hash function processing device of the HMAC system, the speeding up of hashing can be realized by hardware. It is an object of the present invention to provide a hash function processing device that performs .

[0005]

According to the first aspect of the present invention,
First and second key processing circuits for performing a hash operation on the first and second input values, respectively, and processing data from the first key processing circuit as processing target data as a first initial value. A first data processing circuit for performing a hash operation process; and a second data processing circuit for performing a hash operation process on output data of the first data processing circuit using the processing data from the second key processing circuit as a second initial value. A hash function processing circuit including a data processing circuit, wherein the second key processing circuit and the first data processing circuit are processed in parallel.

According to this configuration, since the first data processing and the second key processing are performed simultaneously, hashing can be speeded up accordingly.

According to a second aspect of the present invention, the first and second key processing circuits are shared, the first and second data processing circuits are shared, and the first and second input values are shared. Along with sequentially leading to the shared key processing circuit, a result of the shared data processing circuit performed as a first initial value using a result of the key processing performed on the first input value as processing target data, 2. The hash function processing circuit according to claim 1, wherein the data is re-input to the data processing circuit. According to this configuration, the number of the data processing circuits for performing the first and second data processing and the number of the key processing circuits for performing the first and second key processing are each one. 2 is simultaneously executed with the key processing of FIG.

According to a third aspect of the present invention, first and second input values are obtained by performing a logical operation between the first and second set values in correspondence with the first and second key data. A first and a second exclusive OR circuit, a first and a second key processing circuit for performing a hash operation on the first and second input values, respectively,
A first operation for performing a hash operation on data to be processed using the processing data from the first key processing circuit as a first initial value
And a second data processing circuit that performs a hash operation on output data of the first data processing circuit using the processing data from the second key processing circuit as a second initial value. A function processing device, comprising: first and second registers capable of storing data;
Storage processing means for storing a second initial value in first and second registers, respectively; and storing the first and second registers from the first and second registers in correspondence with first and second data processing operations.
And a switch means for outputting an initial value of the hash function.

According to this configuration, the first and second initial values are stored in the first and second registers, respectively, and the first and second initial values are stored in the first and second registers in response to the first and second data processing requests.
By reading the second initial value, there is no need to perform the first and second key processing, and the speed of the hash processing can be increased.

According to a fourth aspect of the present invention, the first and second data processing circuits have a memory section for temporarily storing first and second initial values, respectively, and the first and second data processing circuits are further provided. , And the switch means includes the first and second registers.
4. The hash function processing device according to claim 3, wherein the contents of the shared register are alternately exchanged with the memory unit in synchronization with the operation of the data processing circuit. According to this configuration, the number of the first and second registers is reduced to one, and the circuit is simplified.

According to a fifth aspect of the present invention, first and second input values are obtained by performing a logical operation between the first and second set values in correspondence with the first and second key data. A first and a second exclusive OR circuit, a first and a second key processing circuit for performing a hash operation on the first and second input values for each predetermined data length, and the first and the second key processing circuits; A first data processing circuit for performing a hash operation on data to be processed for each predetermined data length using processing data from the key processing circuit as a first initial value, and processing data from the second key processing circuit as a second data. A second data processing circuit that performs a hash operation on output data of the first data processing circuit as an initial value of the first and second data processing circuits. The second key processing circuit and the first data processing circuit The A hash function processing circuit, characterized in that it includes a processing control unit for parallel processing, the first, as well as a common second key data,
When the data length of the common key data exceeds the predetermined data length, a pre-stage circuit for generating the key data of the predetermined data length is provided, and the processing control means is configured to execute the first control until the processing by the pre-stage circuit ends. And a delay unit for delaying the start of processing of the data processing circuit.

According to this configuration, if the key data is longer than the predetermined data length, the first data processing is delayed for a predetermined time, so that the first data processing is terminated after the first key processing is completed. Processing is started, and an appropriate hash value is obtained.

According to a sixth aspect of the present invention, the first and second input values are respectively subjected to a hash operation process.
A key processing circuit, a first data processing circuit that performs a hash operation for each predetermined data length on the processing target data using the processing data from the first key processing circuit as a first initial value, and a second data processing circuit. A second data processing circuit that performs a hash operation on output data of the first data processing circuit with processing data from the key processing circuit as a second initial value, wherein the second key processing circuit and the second 1. A hash function processing circuit comprising: processing control means for performing parallel processing with one data processing circuit, wherein a length of data to be processed input to the first data processing circuit is equal to the predetermined data length. A data conversion circuit configured to perform a hash process on the data to be processed in the first data processing circuit for each predetermined data length until the data length reaches a predetermined data length; A hash function processing apparatus characterized by processing by the configuration has a delay means for delaying the output of the processing result of the second data processing circuit until the end.

According to this configuration, when the processing unit for the data to be processed is longer than the predetermined data length, the first data processing takes a longer time, but the second data processing takes a certain time. Because it is delayed, the first
After the data processing is completed, the second data processing is started, and an appropriate hash value is obtained.

[0015]

FIG. 1 is a diagram showing steps S1 to S4 of the basic processing of an HMAC type hash function processing apparatus. The first and second key processing and the first and second data processing shown in FIG. 1 have the same circuit configuration. In this embodiment,
A hash function processing circuit that performs hash processing such as MD5 that obtains a hash value from an input value using an initial value is employed. (Process S1) A first key value is applied to a first input value obtained by performing an XOR (exclusive OR) process on the key data and the set value A to obtain a first initial value Ao. (Process S2) First data processing is performed on the processing target data D using the first initial value Ao to obtain a data input value X. (Process S3) A second key process is performed on a second input value obtained by performing an XOR process on the key data and the set value B to obtain a second initial value Bo. (Process S4) A second data processing is performed on the second data input value X using the second initial value Bo to obtain a value Y. This value Y is a hash value.

As described above, according to the steps of FIG. 1, four steps are required to obtain a hash value. Hereinafter, embodiments of the present invention will be described.

(Embodiment 1) FIG. 2 shows a process of Embodiment 1 in which a first data process S2 and a second key process S3 are performed in parallel based on the process of FIG. As is clear from FIG. 1, the first data processing S2 and the second key processing S3 have no causal relationship in the processing. Therefore, the following processing steps can be adopted. (Process S1) A first key value is applied to a first input value obtained by performing an XOR (exclusive OR) process on the key data and the set value A to obtain a first initial value Ao. (Process S2) First data processing is performed on the processing target data D using the first initial value Ao to obtain a data input value X. At the same time, a second key processing is performed on a second input value obtained by performing an XOR processing on the key data and the set value B, and a second
Is obtained. (Process S3) A second data processing is performed on the second data input value X using the second initial value Bo to obtain a value Y. This value Y is a hash value.

As described above, according to the process of FIG. 2, the hash value is obtained in three processes, and the processing time can be reduced by reducing the number of processing processes by one process. By configuring each of the processes in FIG. 2 with a hash function processing circuit,
It is possible to realize a hash function processing device of the HMAC system in which the processing time is reduced.

FIG. 3 is a block diagram when the processing of the first embodiment shown in FIG. 2 is applied to an actual circuit. The XOR processing circuit 1 guides the key data, the set value A, and the set value B to the input side, and performs XOR processing alternately between the key data and the set value A and between the key data and the set value B. 1st, 2nd
Is generated. The key processing circuit 2 is composed of a hash function circuit and performs key processing on the first and second input values that are input alternately, and outputs the first and second output values Ao and Bo.
Are respectively output. The data processing circuit 3 receives the first and second initial values Ao and Bo alternately,
In synchronization with these, the processing target data D and the processing data X are inputted, the processing data X is obtained from the processing target data D using the initial value Ao, and the processing data Y is obtained from the processing data X using the initial value Bo. Things. The multiplexer 4 alternately outputs the processing target data D and the processing data X to the data processing circuit 3. The multiplexer 4 first outputs the processing target data D and the processing data X output from the data processing circuit 3 at this time. To the data processing circuit 3 again. The alternate input of the set values A and B to the XOR processing circuit 1 is performed by a controller (not shown).

According to this block configuration, 2 shown in FIG.
A key processing circuit for two times can be realized by one key processing circuit 2 and a data processing for two times can be realized by one data processing circuit 3. Can be configured by hardware.

(Embodiment 2) FIG. 4 is a view for explaining processing steps for realizing a higher processing speed than the basic processing steps of FIG.

In FIG. 4, the storage process of Ao is a process of storing the first initial value Ao obtained by the first key process in, for example, a register. The process of storing Bo is a process of storing the second initial value Bo obtained by the second key process in, for example, a register. In FIG. 1, the first and second key processes are executed each time, but in the present embodiment, the first and second initial values Ao and Bo are not values that change each time the process is performed. Focusing on this initial value Ao,
Once Bo is obtained, it is stored. (Process S1) The first input value obtained by performing the XOR process on the key data and the set value A is subjected to a first key process to obtain a first initial value Ao, and further, a first initial value Ao is obtained. Ao is subjected to the storage processing of Ao. (Process S2) The first initial value Ao is read out (or in parallel with the storage process of Ao), and the first
To obtain the data input value X1. At the same time, the second input value obtained by performing the XOR process on the key data and the set value B is subjected to a second key process to obtain a second initial value Bo. With respect to the second initial value Bo, Perform Bo storage processing. (Process S3) The second initial value Bo is read out (or in parallel with the process of storing Bo), and the second data input value X1 is read.
Is subjected to the second data processing to obtain a value Y1.

The first cycle is completed through the processes S1 to S3. Next, the processing shifts to the processing S4 to the second cycle (or subsequent cycles). (Process S4) The first initial value Ao is read, and the first key processing is performed on the processing target data D from the first initial value Ao to obtain the data input value X2 in the second cycle. (Process S5) The second initial value Bo is read out, and the second input value X2 in the second cycle is read from the second initial value Bo.
To obtain the output value of the second cycle and Y2.

After the steps S4 to S5, the second cycle is completed. Thereafter, if there is no change in key data,
After the third cycle, only the first initial value Ao and the second initial value Bo need to be read out instead of the first and second data processing steps, and the first and second key processes are omitted. And the processing time can be shortened accordingly.

FIG. 5 is a block diagram when the processing of the second embodiment shown in FIG. 4 is applied to an actual circuit. FIG.
In the block diagram shown in FIG. 3, a comparator 8, a multiplexer 7, a switch 9, a first register 5, and a second register 6 are laid.

The first register 5 corresponds to the storage processing of Ao in FIG.
Is stored. Second register 6
Is equivalent to the storing process of Bo in FIG. 4 and stores the second initial value Bo processed by the key processing circuit 2. The multiplexer 7 selectively switches outputs from the first register 5, the second register 6, and the key processing circuit 2 and guides the output to the data processing circuit 3.

The comparator 8 determines whether or not the key data read from the memory (not shown) is the same as the previous key data. If the key data is the same, the first of the first and second registers 5 and 6 is checked. , A switching instruction to the multiplexer 7 to pass the second initial values Ao and Bo, and when different, the multiplexer 7 to pass the first and second initial values obtained by the key processing circuit 2. Is given. The switch 9 switches the connection between the output side of the key processing circuit and the first and second registers 5 and 6 alternately, preferably only once, only when the key data is different from the previous one, so that the first and second initial values are changed. Ao and Bo are loaded into the first and second registers 5 and 6, respectively.

The key processing circuit 2 performs a predetermined key processing and outputs an identification signal indicating which one of the first and second initial values Ao and Bo is obtained to the switch 9 alternately.
When the first initial value Ao is obtained, the first register 5
And when the second initial value Bo is obtained, the second
Is connected to the register 5. The first initial value Ao is output from the first register 5 to the data processing circuit 3 via the multiplexer 7 at the timing of the first data processing by the data processing circuit 3. The second initial value Bo is output from the second register 6 to the data processing circuit 3 via the multiplexer 7 at the timing of the second data processing by the data processing circuit 3.

If there is a change in the previous key data, the processing data of the key processing circuit 2 is output to the data processing circuit 3 at the same time that the data processing circuit 3 performs the first and second data processing, and the switch is switched. 9 through 1st, 2nd
In the registers 5 and 6.

According to this configuration, if there is no change in the key data, only one XOR process is required, so that the first and second key processes need not be performed, and the processing time can be shortened accordingly. be able to.

(Embodiment 3) FIG. 6 shows a process in Embodiment 2 in which the two registers provided corresponding to the first initial value Ao and the second initial value Bo are reduced to one. FIG. As shown in FIG. 1, in the basic processing step of the hash function of the HAMC method, the data after each key processing is not used at the same time. Therefore, even if the two registers of the first register 5 and the second register 6 as shown in FIGS. 4 and 5 are not provided, one register and the register originally provided in the data processing circuit 3 are provided. And the data are alternately exchanged between these registers, so that the processing of the second embodiment can be performed only by providing one external register. Therefore, the following processing steps can be adopted. (Process S1) The same process as process S1 in FIG. 1 is performed. (Process S2) The same process as process S2 in FIG. 1 is performed. (Process S3) The first data processing is performed on the processing target data D using the first initial value Ao, and the first data input X1 is performed.
And outputs the first initial value Ao in the register in the data processing circuit to the register 10 at the same time. (Process S4) Using the second initial value Bo, the second data processing is performed on the first data input value to obtain the output Y1, and the data is exchanged between the register in the data processing circuit and the register 10. Then, the first initial value Ao is stored in a register in the data processing circuit, and the second initial value Bo is stored in a register in the data processing circuit. (Process S5) A first data processing is performed on the processing target data D by using the first initial value Ao, and the second input value X
2 and at the same time, the data is exchanged between the registers in the data processing circuit to obtain the first initial value A.
o is transferred to a register, and the second initial value Bo is transferred to a register in the data processing circuit. (Processing S6) The second data input value X2 is subjected to the second data processing using the second initial value Bo and output Y2
And, at the same time, the data is exchanged between the registers as in the process 5, and the first data is stored in the register in the data processing circuit.
Is stored in the register and the second initial value Bo is stored in the register.

FIG. 6 further shows the data storage state of the register according to the processing steps.
3, the data stored in the register is changed in conjunction with the processes S4, S5, and S6.

FIG. 7 is a block diagram when the processing of the third embodiment shown in FIG. 6 is applied to an actual circuit. FIG. 8A shows circuits around the register 31 and the register 10 in the data processing circuit 3 in the circuit configuration of FIG.
(B) is a time chart.

This circuit differs from the first embodiment in that a register 10 is used for the first and second registers 5 and 6 in FIG. The input side of the register 10 is connected to the output terminal of the internal register 31 of the key processing circuit 2 and the initial value output terminal of the data processing circuit 3, and the output side is connected to the multiplexer 7. Then, in conjunction with the data processing circuit 3 performing the first data processing and the second data processing, the multiplexer 7 is connected between the register 10 and the internal register 31 of the data processing circuit 3 in accordance with an instruction from the comparator 8. The first and second initial values Ao and Bo are exchanged via the CPU. That is, when the first initial value Ao is read from the register 10, the first initial value Ao is guided to the internal register 31 of the first data processing circuit 3 via the multiplexer 7 and the first initial value Ao is read from the internal register 31. Initial value B of 2
o is read and updated in the register 10. When the data processing using the initial value Ao is completed in the data processing circuit 3, the register 10
, The second initial value Bo is guided to the internal register 31 via the multiplexer 7, and the first initial value Ao is read from the internal register 31 and written in the register 10 in an updated manner.

Referring to FIG. 8B, the period T1
Then, the first initial value Ao (for example, 00
00) is stored in the register 10 as a second initial value Bo (for example, F
FFF) is stored. When the control signal is output with the value and the period shifts to the period T2, the data is exchanged between the register 10 and the internal register 31, and the register 31
The second initial value Bo is stored in the register 10.
Is stored. Next, a control signal is output for a period T3.
, The data is exchanged in the same manner as in the period T2, and the register 31 stores the second initial value Bo and the register 10 stores the first initial value Ao.

In this way, the processing can be sped up while simplifying the circuit configuration only by employing one register.

(Embodiment 4) FIG. 9 is a diagram showing processing for performing processing when the data length of key data is longer than a predetermined length.

In the HMAC hash function processing apparatus, when the data length of the key data exceeds 512 bits, the original key data is divided every 512 bits and divided key data K1, divided key data K2,. . . Is subjected to hash processing to obtain the final key data K
Pre-processing to generate o is required. This pre-processing is
Extra time is required in accordance with the number of divisions of the original key data as compared with the first embodiment, and the first processing is performed at normal processing timing in accordance with a processing command signal from a control unit (not shown) or the like.
, The hash processing using the proper first initial value Ao generated based on the key data Ko cannot be performed. As a result, the proper hash value Y Can not get. For this reason, in the present embodiment, processing for delaying the first data processing until key data Ko is generated and an appropriate first initial value Ao is obtained is added. This processing will be described.
(Process S1) For example, 1024-bit original key data K
In the case of, the key data K is divided every 512 bits.
1, K2. A first hash process is performed on the divided key data K1 to obtain a first hash value K11. A second hash process is performed on the first hash value K11 using the divided key data K2 to obtain a second hash value K21. Second
The hash value K21 of is 128 bits, but requires 512 bits as key data. Therefore, “0” for the required bits is added to the second hash value K21 to obtain 5 bits.
A “0” putting process of 12 bits is performed and 51
Generate 2-bit key data Ko. (Process S2) A first key process is performed on a first input value obtained by performing an XOR process on the key data Ko and the set value A,
A first initial value Ao is obtained. (Process S3) XO from the generated key data Ko and the set value B
A second key process is performed on the second input value obtained by performing the R process to obtain a second initial value Bo. (Process S4) After at least waiting for the end of the first key processing (Wait), the first key processing is performed on the processing target data D using the first input value Ao to obtain the data input value X. (Process S5) Data input value X using second initial value Bo
Is subjected to the second data processing to obtain an output Y. This value Y is a hash value.

As described above, according to the process shown in FIG. 9, since the first data processing is performed after the end of the first key processing, an appropriate hash value can be obtained.

FIG. 10 is a circuit diagram when the processing steps shown in FIG. 9 are realized in an actual circuit. This circuit is
It comprises a processing circuit 1, a key processing circuit 2, a data processing circuit 3, a multiplexer 4, a detector 11, a multiplexer 12, and a "0" putting processing circuit 13.

The key processing circuit 2 is composed of a hash function circuit, performs hash processing using the divided key data K1 and K2, and performs hash processing using the first and second input values obtained from each exclusive OR processing. The processing is performed. When the divided key data K1 is input, the key processing circuit 2 feeds back a first hash value K12 obtained by performing the first hash processing, and uses the value K12 to
A second hash process is performed on the divided key data K2,
Is obtained. When the first and second input values are input, the key processing circuit 2 performs first and second key processing to determine first and second initial values Ao and Bo. The data processing circuit 3 has the same function as the data processing circuit 3 of FIG. 3, and performs the first data processing after the completion of the first key processing in accordance with the delay instruction from the detector 11. It is configured as follows.

The detector 11 monitors the operation of the key processing circuit 2 and detects whether or not the first initial value Ao has been obtained. The transmission of the signal is canceled, thereby instructing the data processing circuit 3 to start the first data processing. The multiplexer 12 alternately outputs the divided key data K1, K2 and the first and second input values to the key processing circuit 2, and outputs the divided key data K1, the divided key data K2, the first input value, Output to the key processing circuit 2 in the order of the second input value. "0" putting processing circuit 13
Is to add “0” to the upper or lower predetermined bit position with respect to the 128-bit second key data K12.

According to this block configuration, the key data K
Has a long data length of more than 512 bits, the first data processing of the data processing circuit 3 is waited until the second key processing of the key processing circuit 2 is completed. Can be obtained.

(Embodiment 5) FIG.
Is large and exceeds, for example, 512 bits,
The process according to the fifth embodiment, in which an appropriate hash value can be obtained by waiting the second data process, is shown.

The data length of the processing target data D is large 51
In the case of exceeding 2 bits, the data processing circuit cannot process data of 512 bits or more as an input value at a time, and therefore, divides the processing target data D into 512 bits, and Must be processed. Through these steps, the data input value X1 is obtained, and the input value of the second data processing can be obtained.
A second data processing can be performed. However, if the second data processing is performed before the end of the first data processing, an appropriate hash value cannot be obtained.

Therefore, the following processing steps are performed.

(Process S1) Process S1 of the basic process of FIG.
Perform the same processing as.

(Process S2) The same process as the process S2 of the basic process in FIG. 1 is performed.

(Processing S3) For example, the 1024-bit data D to be processed is divided into 512-bit data to be divided data D1 and D2, and the first data D1 is divided into the first data D1 using the first initial value Ao. Data processing is performed to obtain a first data processing value D12.

(Processing S4) The first processing value D12 is used to perform first data processing on the division target data D2 to obtain a data input value X.

(Process S5) After waiting for the end of the first data processing, the data input value X is subjected to the second data processing using the second initial value Bo to obtain the output Y.

As described above, an appropriate hash value can be obtained by performing the second data processing after the completion of the first data processing.

FIG. 12 is a circuit diagram when the processing steps of FIG. 11 are applied to an actual circuit. In this circuit, the XOR processing circuit 1, multiplexer 4, and detector 11 have the same functions as the corresponding circuit blocks in FIG. 10 and the key processing circuit 2 has the same functions as the corresponding circuit blocks in FIG. I do.

The data processing circuit 3 comprises a hash processing circuit, performs first data processing on each of the divided data D1 and D2, obtains a data input value X, and further outputs a second data output from the multiplexer 13. The second data processing is performed on the data input value X input via the multiplexer 4 by feedback using the initial value Bo of the above, and an output value Y is obtained. Further, the data processing circuit 3
According to the instruction of the detector 11, the second data processing is performed after the first data processing is completed. Therefore, an appropriate hash value Y can be obtained.

The multiplexer 13 is a data processing circuit 3
The appropriate data is output to the data processing circuit 3 in synchronization with the timing of the data processing. That is, when the data processing circuit 3 performs the first data processing, the first processing value D12 or the first initial value Ao is used. When the data processing circuit 3 performs the second data processing, the second processing value D12 is used. Output to the data processing circuit 3.

According to this configuration, the second data processing is performed by the first data processing.
It is possible to start the process after waiting for the end of the data process, and to obtain an appropriate hash value.

(Embodiment 6) FIG. 13 shows a process of Embodiment 6 in which the same effects as those of Embodiment 5 can be obtained by slightly changing the procedure of the processing steps of Embodiment 5. Since the second data processing does not start unless the second key processing is completed, the second key processing is started simultaneously with the start of the first data processing of the processing target data D2, and the second data processing is started. By delaying the processing, even when the data amount of the processing target data D is large, similar to the fifth embodiment,
An appropriate hash value can be obtained.

(Process S1) The same process as process S1 of the fifth embodiment is performed.

(Process S2) The same process as process S2 of the fifth embodiment is performed, but is performed simultaneously with process S4. For this reason,
The input of the data input value X and the second initial value Bo to the data processing circuit can be synchronized, and an appropriate hash value can be obtained.

(Process S3) The same process as process S3 of the fifth embodiment is performed.

(Process S4) The same process as process S4 of the fifth embodiment is performed.

(Process S5) The same process as process S5 of the fifth embodiment is performed.

According to this configuration, an appropriate hash value can be obtained as in the case of the fifth embodiment in which the data amount of the data to be processed is large.

[0064]

According to the first aspect of the present invention, the number of processing stages can be reduced by overlapping the processing steps in the HMAC type hash function processing apparatus, and the hash processing can be speeded up. According to the invention of claim 2, the circuit configuration can be simplified.

According to the third aspect of the invention, the speed of the hash processing can be increased by using two registers. Further, according to the invention of claim 4, simplification of the circuit can be realized with one register.

According to the fifth and sixth aspects of the present invention, an appropriate hash value can be obtained by performing a predetermined delay process.

[Brief description of the drawings]

FIG. 1 is a basic processing diagram of a hash function processing device of the HAMC system.

FIG. 2 is a process chart of the first embodiment.

FIG. 3 is a circuit block diagram of the first embodiment.

FIG. 4 is a process chart of a second embodiment.

FIG. 5 is a circuit block diagram according to a second embodiment.

FIG. 6 is a process chart of a third embodiment.

FIG. 7 is a circuit block diagram of a third embodiment.

FIG. 8 shows a register 31 in the data processing circuit according to the third embodiment.
FIG. 2 is a diagram showing a relationship between the register and a register.

FIG. 9 is a process chart of a fourth embodiment.

FIG. 10 is a circuit block diagram of a fourth embodiment.

FIG. 11 is a process chart of a fifth embodiment.

FIG. 12 is a circuit block diagram according to a fifth embodiment.

FIG. 13 is a process chart of a sixth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 XOR processing circuit 2 Key processing circuit 3 Data processing circuit 4 7 12 13 Multiplexer 5 6 10 Register 8 Comparator 9 Switch 11 Detector 31 Internal register

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tatsuo Masuda 1048 Kadoma Kadoma, Osaka Pref.Matsushita Electric Works, Ltd. ) Inventor: Miyazaki, Keiichi 1048, Kadoma, Kadoma, Osaka, Japan Matsushita Electric Works, Ltd. AA18 NA12 NA22

Claims (6)

[Claims] A first key processing circuit for performing a hash operation on each of the first and second input values, and processing data from the first key processing circuit as a first initial value. A first data processing circuit for performing a hash operation on data to be processed, and a hash operation on output data of the first data processing circuit using the processing data from the second key processing circuit as a second initial value. And a second data processing circuit that performs the following, and the second key processing circuit and the first data processing circuit are processed in parallel. 2. The first and second key processing circuits are shared, and the first and second data processing circuits are shared.
The first and second input values are sequentially led to a shared key processing circuit, and the result of the key processing performed on the first input value is used as a first initial value. 2. The hash function processing circuit according to claim 1, wherein a result of the processing circuit is re-input to the data processing circuit as data to be processed. 3. A logical operation is performed between first and second set values corresponding to first and second key data to perform first and second key data.
First and second exclusive OR circuits for obtaining input values of the first and second input processing values, first and second key processing circuits for performing hash calculation processing on the first and second input values, respectively, A first data processing circuit that performs a hash operation on data to be processed using the processing data from the key processing circuit as a first initial value; and a processing data from the second key processing circuit as a second initial value. A hash function processing device comprising: a second data processing circuit that performs a hash operation on output data of a first data processing circuit, wherein the first and second registers are capable of storing data; Storage processing means for storing a second initial value in first and second registers, respectively; and storing the first and second registers from the first and second registers in correspondence with first and second data processing operations. Switch means for outputting the initial value of Hash function processing apparatus characterized by a. 4. The first and second data processing circuits have a memory section for temporarily storing first and second initial values, respectively, and further share the first and second registers. 4. The switching unit according to claim 3, wherein the contents of the shared register are alternately exchanged with the memory unit in synchronization with an operation of the first and second data processing circuits. Hash function processing device. 5. A method according to claim 1, wherein a logical operation is performed between the first and second set values in correspondence with the first and second key data.
First and second exclusive OR circuits for obtaining input values of the first and second key processing circuits; and first and second key processing circuits for performing a hash operation on the first and second input values for each predetermined data length. A first data processing circuit for performing a hash operation on data to be processed for each predetermined data length using the processing data from the first key processing circuit as a first initial value; The processing data is set as the second initial value and the first
A second data processing circuit that performs a hash operation on output data of the data processing circuit, and performs processing by the first and second data processing circuits at a predetermined cycle.
A hash function processing circuit comprising processing control means for performing parallel processing of the second key processing circuit and the first data processing circuit, wherein the first and second key data are shared. When the data length of the common key data exceeds the predetermined data length, a pre-stage circuit for generating key data of the predetermined data length is provided, and the processing control means terminates the processing by the pre-stage circuit. A hash function processing device comprising: delay means for delaying the start of processing of the first data processing circuit until the first time. 6. A first and a second key processing circuit for performing a hash operation on first and second input values, respectively, and processing data from the first key processing circuit as a first initial value. A first data processing circuit for performing a hash operation on the data to be processed for each predetermined data length, and processing data from the second key processing circuit as a second initial value.
A second data processing circuit for performing a hash operation on output data of the data processing circuit, and a processing control means for performing parallel processing of the second key processing circuit and the first data processing circuit. A hash function processing circuit, wherein when the processing target data length input to the first data processing circuit exceeds the predetermined data length, the processing target data is divided by the first data processing length for each predetermined data length. The data processing circuit has a conversion circuit configuration for performing hash processing until a predetermined data length is reached, and the processing control means delays the output of the processing result of the second data processing circuit until the processing by the conversion circuit configuration ends. A hash function processing device, comprising: