JP2002158269A - Manufacturing method of wafer quality evaluation MOS and thin film forming apparatus - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To easily and quickly manufacture a wafer quality evaluation MOS for wafer quality evaluation. -Enables quick feedback to the manufacturing process, and
Even if a new MOS fabrication line is constructed for wafer quality evaluation, a method for fabricating a wafer quality evaluation MOS that does not require a large amount of capital investment and a wide installation space is provided. To do. A wafer quality evaluation MO for evaluating the quality of a wafer based on the withstand voltage of an oxide film of a MOS capacitor.
In the method for producing S, an oxide film forming step of forming an oxide film on the surface of the wafer, and a patterning means having an electrode-shaped opening by transporting the wafer into the thin film forming apparatus,
A process of arranging on a wafer placed on a sample stage in a thin film forming apparatus, and thereafter, growing a conductive film, thereby growing a conductive film only on an electrode-shaped opening on an oxide film. And forming a conductive film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wafer quality evaluation MOS and a thin film forming apparatus for evaluating the quality of a wafer based on the oxide film breakdown voltage of a MOS capacitor. The present invention relates to a thin film forming apparatus suitable for manufacturing a wafer quality evaluation MOS.

[0002]

2. Description of the Related Art A MOS oxide film withstand voltage method (Gate Oxide Integ
The rity (GOI) method is a method that has been often used in the past as one of the wafer quality evaluation methods. This is because a wafer is subjected to a thermal oxidation treatment, electrodes are formed, a MOS is formed on the wafer, an electric stress is applied to the MOS, and a non-defective rate based on a preset judgment value is determined. The quality of the oxide film is determined based on the total charge injected into the oxide film before the oxide film breakdown, and the light point defect (LPD), processing defect, and contamination degree of the wafer before the thermal oxidation treatment are determined. Etc. are relatively evaluated.

[0003] The formation of the electrode is performed by reducing the resistance of n + po
Generally, ly Si is used. The step of forming this electrode is usually carried out by a chemical vapor deposition (CV) method as described in Examples of JP-A-10-242230.
A film forming process of polycrystalline silicon by the method D) and a predetermined area and a predetermined number of electrodes are patterned by photolithography.
And the process of training.

[0004] Further details of these processes are shown in FIG.
y Process of depositing Si over the entire surface of wafer, process of lowering resistance by diffusing P (phosphorus), process of removing ring lath, photolithography (photosensitive resin (resist) application / exposure / phenomena process, etching process) ), The step of removing the back surface oxide film, and the step of removing the etching mask (resist).

[0005] Low resistance materials other than poly Si (conductive materials)
Is formed on the entire surface of the wafer by CVD, sputtering, vacuum evaporation, or the like, the P (phosphorus) diffusion step is not required.
A polishing step and an etching mask removal step are required, and a great deal of time and effort is required to fabricate the MOS before the electrical characteristics are evaluated.

For this reason, a simple evaluation method of the breakdown voltage of an oxide film has been conventionally proposed in order to more quickly obtain the evaluation results of the electric characteristics. This is because, for example, the density of an infrared scatterer (Japanese Patent Laid-Open No. 06-112292),
06-349923), the number of pits after SC-1 cleaning (JP-A-10-335402), the wavelength component intensity of laser reflected scattered light (JP-A-08-288351) and the like. It evaluates the quality of c. In any of these evaluation methods, the correlation between these measured values and the MOS oxide film breakdown voltage is investigated in advance to obtain a calibration curve, and thereafter, the MOS oxide film breakdown voltage corresponding to these measured values is indirectly calculated. This is a method to evaluate the quality of a wafer by
Although the oxide withstand voltage is not directly evaluated, a problem remains in reliability.

[0007]

As described above, in the step of forming a MOS electrode for evaluating the quality of a wafer, a desired electrode pattern is formed from the film forming process and the patterning process. However, these processes involve a large number of steps, and the fabrication of MOS requires a great deal of time and labor. The oxide film formed also on the back surface of the wafer in the thermal oxidation process is usually peeled off for electrical contact when the breakdown voltage of the MOS oxide film is evaluated. For the front side (M
Each step of forming a protective film on the OS fabrication side), removing the back oxide film, and removing the front protective film was also required. Thus M
Since a great deal of time was required to manufacture the OS, rapid feedback of the result of the evaluation of the MOS oxide film breakdown voltage to the wafer manufacturing process was hindered.

[0008] Further, in the case of using n + poly Si as an electrode material, for example, a device / system required in a MOS electrode forming step includes a poly Si CVD furnace, a phosphorus diffusion furnace, a phosphorus glass removal system, a resist coater, Exposure machine, developing device, po
The ly Si etching system and the resist removal system have a problem that a large amount of capital investment and a wide installation space are required to introduce a new MOS fabrication line. Further, there is a problem that raw materials and maintenance required in each apparatus / system require cost and labor.

In the method for simply evaluating the oxide film breakdown voltage, if a database (calibration curve) of the correlation between each measured value to be evaluated and the oxide film breakdown voltage is prepared, Although it is possible to indirectly evaluate the withstand voltage of the oxide film, there are multiple causes for the wafer quality, such as the influence of the processing on the wafer and contamination in the wafer cleaning process. In such a case, there is a problem that there is a limit in a simple evaluation method of the oxide film breakdown voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is possible to easily and quickly manufacture a wafer quality evaluation MOS for evaluating wafer quality.
Therefore, it is possible to promptly feed back the result of the MOS oxide film withstand voltage evaluation to the wafer manufacturing process, and further configure a new MOS production line for evaluating the quality of the wafer. Another object of the present invention is to provide a method for manufacturing a wafer quality evaluation MOS which does not require a large amount of capital investment and a wide installation space, and a thin film forming apparatus suitable for manufacturing a wafer quality evaluation MOS. .

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, a MOS for evaluating wafer quality according to the present invention is provided.
The manufacturing method (1) is a method for manufacturing a wafer quality evaluation MOS for evaluating the quality of a wafer based on the oxide film breakdown voltage of a MOS capacitor, wherein the oxide film is formed on the surface of the wafer. Forming step, transferring the wafer into a thin film forming apparatus, and arranging a patterning means having an electrode-shaped opening on a wafer mounted on a sample stage in the thin film forming apparatus. The method is characterized by including a step of forming a conductive film on the oxide film only by growing a conductive film on the oxide film by growing a conductive film thereafter.

According to the method (1) for fabricating a wafer quality evaluation MOS, the patterning means has an electrode-shaped opening. Way with oxide film formed on table
By disposing the conductive film in contact with C and then growing the conductive film, a conductive film can be grown only on the electrode-shaped opening on the oxide film (mask film forming method). For this reason, the patterning process is performed simultaneously with the film forming process, and the photolithography process is not required.
The production of S can be performed easily and in a short time. Therefore, the feedback of the MOS oxide film breakdown voltage evaluation result to the wafer manufacturing process can be promptly performed. Further, various apparatuses and systems conventionally required for patterning can be made unnecessary, and even when a new MOS production line is constructed for wafer quality evaluation. No large capital investment and wide installation space are required.

Further, the wafer quality evaluation M according to the present invention.
The OS manufacturing method (2) is based on the MO for wafer quality evaluation described above.
In the method (1) for producing S, the conductive film is made of an AlSiCu alloy or Ti, and a sintering process is not performed after the conductive film forming step.

According to the manufacturing method (2) of the MOS for evaluating wafer quality, the conductive film is made of AlSiCu alloy or Ti.
No sintering (heat treatment) for reducing the interface state is performed after the conductive film forming step. When heat treatment is performed after the conductive film forming step, in the case of AlSiCu, Cu and Si diffuse into the oxide film, deteriorating the current-voltage characteristics of the MOS capacitor. In the case of Ti, the reduction reaction by Ti proceeds at the electrode / oxide film interface, the effective oxide film thickness decreases, and the current-voltage characteristics of the MOS capacitor change. Thus, if sintering is performed after the conductive film forming step, accurate wafer quality evaluation becomes difficult. According to the manufacturing method (2) of the wafer quality evaluation MOS, since the heat treatment for reducing the interface state is not performed, the MOS can be manufactured more easily and in a short time. Therefore, the feedback of the MOS oxide film breakdown voltage evaluation result to the wafer manufacturing process can be performed more quickly.

Further, the wafer quality evaluation M according to the present invention.
The OS fabrication method (3) is based on the MO for wafer quality evaluation described above.
In the method (1) or (2) for producing S, the oxide film is intentionally formed like a back surface seal oxide film for the purpose of suppressing out-diffusion of a dopant in a low-resistance wafer. In the case where the oxide film is not a film, the withstand voltage evaluation of the oxide film is performed by either the voltage stress or the current stress,
The method is characterized in that, in the oxide film forming step, a step of removing the oxide film that has also grown on the back surface of the wafer is not performed.

According to the method (3) for manufacturing the wafer quality evaluation MOS, the MOS can be manufactured more easily and in a short time. Therefore, the wafer of the MOS oxide film breakdown voltage evaluation result can be obtained. (C) The feedback to the manufacturing process can be performed more quickly.

In evaluating the withstand voltage of the oxide film, it is general to remove the oxide film on the back surface of the wafer formed during thermal oxidation in order to make electrical contact. However, according to the manufacturing method (3) of the wafer quality evaluation MOS, the oxide film is formed as a back-side seal oxide film for the purpose of suppressing out-diffusion of a low-resistance wafer. In the case where the oxide film is not formed intentionally and the withstand voltage of the oxide film is evaluated by either voltage stress or current stress, the oxide film that has also grown on the back surface of the wafer in the oxide film forming step. No film stripping step is performed.

In the case of current stress, the amount of current passing through the MOS oxide film to be evaluated does not change even if an oxide film is present on the back surface or not, so that it does not affect the evaluation. . On the other hand, in the case of voltage stress, it can be considered that the effect of the backside oxide film can be theoretically ignored as follows.

As shown in FIG. 2, the equivalent circuit for the MOS evaluation is a MOS capacitor (C ₁ ) for evaluating the breakdown voltage and a capacitor (C ₁ ) formed by the back oxide film existing between the wafer and the measurement stage. C ₂ ). When a stress voltage V _S is applied to both ends, MO
Assuming that the voltage applied to the S capacitor is V ₁ and the voltage applied to the back oxide film is V ₂ , in this equivalent circuit, C ₁ · V ₁ = C ₂ · V ₂ ··· (1) V _S = V ₁ + V ₂ ... (2) holds.

From the above equations (1) and (2), V ₁ = {C ₂ / (C ₁ + C ₂ )} V _S (3), and C ₁ and C ₂ are given by the following (4) ) And (5), the above equation (3) is also represented by the following equation (6).

C ₁ = ε · εox · S ₁ / t (4) C ₂ = ε · εox · S ₂ / t (5) V ₁ = {S ₂ / (S ₁ + S) _{2)} V S ···· (6} ) where epsilon: vacuum permittivity ox: oxide film dielectric constant S _1: withstand voltage rating MOS area S _2: web - Ha area t: formed oxide film thickness (at the same time Therefore, the MOS oxide film thickness and the back surface oxide film thickness are equal).

Here, S ₂ (for example, 200 mm diameter wafer)
C: about 314 cm ² , 300 mm diameter wafer: about 707
cm ² ), an effective M for wafer quality evaluation
Since the OS area S ₁ is about 1 cm ² or less, (6)
From the equation, a voltage that is slightly smaller than the stress voltage V _S and is substantially equal is applied to the MOS oxide film to be evaluated. Experimentally, as shown in FIG. 3, when the stress voltage V _S is applied in the accumulation direction with the entire back surface as one MOS, the characteristics of the initial failure are exhibited. Has been proven not to have
It is considered that there is no voltage drop due to the depletion layer. As described above, even if the back surface oxide film peeling step is omitted, there is no problem in the oxide film breakdown voltage evaluation for wafer quality evaluation.

Further, the thin film forming apparatus according to the present invention (1)
Is characterized in that patterning means having an electrode-shaped opening used for growing a conductive film via an oxide film on the surface of a wafer for quality evaluation is provided. According to the thin film forming apparatus (1), the patterning means is arranged in contact with the wafer on which the oxide film is formed placed on the sample stage in the reaction chamber, and thereafter, the conductive film is grown. Thereby, a conductive film can be grown only on the opening in the electrode shape on the oxide film. For this reason, the patterning process is performed simultaneously with the film forming process, and the photolithography process is not required.
Can be easily and quickly performed.

Further, the thin film forming apparatus according to the present invention (2)
Is characterized in that in the above thin film forming apparatus (1), the mask portion constituting the patterning means is made of ceramic, SUS, or Inconel as a forming material. Ceramics are resistant to heat, cause almost no thermal deformation even when irradiated with plasma, have good conductivity in SUS or Inconel, suppress charge shift, and Q _bd
The measurement can be performed accurately.

Further, the thin film forming apparatus according to the present invention (3)
Is characterized in that in the above-mentioned thin film forming apparatus (1), the mask portion is made of ceramic, and a conductive film is formed on at least the surface and the side surface of the opening of the electrode shape. According to the thin film forming apparatus (3), the ceramic is resistant to heat, hardly undergoes thermal deformation even when irradiated with plasma, and furthermore, by forming the conductive film, the charge amount shift in _Qbd measurement can be suppressed. .

Further, the thin film forming apparatus according to the present invention (4)
Is characterized in that in the thin film forming apparatus (1), the mask portion is made of ceramic, and a conductive film is formed on a front surface, a back surface, and a side surface of the opening of the electrode shape. According to the thin film forming apparatus (4), since the conductive film is also formed on the back surface of the mask portion, the charge shift in the _Qbd measurement can be further suppressed by the conductive film.

Further, the wafer quality evaluation M according to the present invention.
The OS fabrication method (4) is based on the MO for wafer quality evaluation described above.
In the method (1) for producing S, the mask portion constituting the patterning means is made of ceramic, and an aluminum alloy film is formed on at least the surface and the side surface of the opening of the electrode shape. The conductive film to be grown is made of an aluminum alloy, and the temperature of the mask portion when growing the conductive film is set to 500 ° C. or more. According to the wafer quality evaluation MOS manufacturing method (4), the temperature of the mask portion is set to 500 ° C.
By setting as described above, the fluidity of the aluminum alloy film formed on the side surface of the opening of the electrode shape is increased, and the connection between the aluminum alloy film and the conductive film grown on the wafer is controlled by the process. Can be realized early, and Q
The charge shift in the _db measurement can be further reduced.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for manufacturing a wafer quality evaluation MOS and a thin film forming apparatus according to the present invention will be described below with reference to the drawings. In this embodiment, the MOS
A magnetron sputtering apparatus will be described as an example of a thin film forming apparatus used in the electrode forming step of the fabrication. FIG. 4 is a plan partial sectional view schematically showing the entire magnetron sputtering apparatus, and FIG. 5 is a sectional view showing a main part of a sputtering chamber (reaction chamber).

In the figure, reference numeral 10 denotes a load lock chamber.
The two load-lock chambers 10 are supplied with wafers 2 (FIG. 5) that have been oxidized and housed in cassettes (not shown). These load lock chambers 10
Is connected to a transfer chamber 12 via an aligner chamber 11, and the transfer chamber 12 is provided with a loading grip 14a for gripping the wafer 2 and a horizontal grip 14b for unloading. A transfer robot 14 is provided. Transfer room 1
A sputtering chamber 13 is connected to a portion facing the second aligner chamber 11. These load lock chambers 10,
A transfer system for transferring the wafer 2 in a vacuum state including the aligner chamber 11 and the transfer chamber 12 equipped with the horizontal transfer robot 14 is constituted, and the wafer 2 placed on the sample stage 4 is provided.
Can be replaced in a vacuum state by the horizontal transfer robot 14 constituting the transfer system. For this reason, wafer-by-wafer continuous processing of the wafer 2 is possible.

A sample stage 4 is disposed in the sputtering chamber 13, and the wafer 2 is mounted on the sample stage 4. A flat plate-like electrode forming material (for example, AlSiCu alloy or
A target 6 made of Ti) is arranged, and the DC power supply 5 is connected to the target 6. A magnet 7 is further disposed above the target 6 so that an electric field and a magnetic field can be simultaneously applied to the discharge space, and the target 6 is sputtered in the sputtering chamber 13. A supply system (not shown) for supplying Ar gas is connected.

On the wafer 2 mounted on the sample stage 4, an opening 1 in the form of a MOS electrode formed on the wafer 2 is formed.
The lowering shield 3 is disposed around the patterning means 1 and the lower shielding shield 3 is provided around the patterning means 1. The elevating mechanism 9 is connected to the outer periphery of the. Lower shield shield 3
A flange 3a is formed on the inner peripheral portion of the lower cover 3 to engage with the outer peripheral portion of the patterning means 1. The lower protective shield 3 is moved up and down by driving the elevating mechanism 9, and the lower protective shield 3 is moved. The patterning means 1 is held by the lower shield shield 3 and moves up and down with the vertical movement of the shield 3.

FIG. 6 shows the details of the patterning means 1. The patterning means 1 is made of ceramic or SU.
S, made of metal such as Inconel,
A large number of openings 1a are formed in the patterning means 1 according to the shape of the electrodes of the MOS formed on the wafer 2. Around the openings 1a, wafers of sputtered film material particles 8 are formed. -Tape so as not to hinder the arrival at C-2
A portion 1b (FIG. 5) is formed. Patterning means 1
When a metal such as SUS or Inconel is used as a material, the conductivity is good, but when it receives heat from the plasma, there is a possibility that distortion or warpage may occur. It is desirable to use a hard ceramic.

When the patterning means 1 is made of ceramic, a conductive film (not shown) is formed on at least its surface and the side surface (taper portion 1b) of the opening of the electrode shape. It is desirable. More preferably, a conductive film is formed on the front surface, the back surface, and the side surface of the opening of the electrode.

In the Q _bd method, in which a current stress is applied to an oxide film and the breakdown voltage of the oxide film is evaluated based on the amount of charge passed through the oxide film until the dielectric breakdown of the oxide film occurs, the charge in the sputtering process is affected by the influence of the sputtering process. In some cases, the amount greatly shifts, and a correct oxide film breakdown voltage evaluation cannot be performed.

FIGS. 7A and 7B are schematic views for explaining the outline of the Q _bd method. When a voltage is applied between the wafer 2 and the electrode 2b so that the current changes stepwise with respect to time, electrons pass through the oxide film 2a.
Although only one electrode 2b is shown in FIG. 7A, in actuality, 100 or more electrodes 2b are formed on the oxide film 2a.
Is formed, and Q _{bd is} usually applied to all these electrodes 2b.
Apply the law. Then, the voltage applied to each electrode 2b is divided by the film thickness of the oxide film 2a, and the time change of the electric field strength is obtained.
When the graph is superimposed on two graphs, if the quality of the wafer 2 under the electrode 2b is good, the dielectric breakdown of the oxide film 2a is slow, but if the quality is poor, the dielectric breakdown occurs early. . Therefore, the amount of electric charge passing through the oxide film 2a can be known from the electric field strength at the time of dielectric breakdown, and the quality and distribution of the wafer 2 can be evaluated based on the amount of electric charge.

However, when the electrode 2b is formed by the plasma sputtering method, electrons in the plasma may pass through the oxide film 2a during the plasma processing. In such a case, the amount of charge to be measured is measured to be small, and correct evaluation cannot be performed.

FIG. 8 is a sectional view schematically showing a state in which an electrode 2b is formed on an oxide film 2a by a plasma sputtering method. The oxide film 2a is formed on the wafer 2 in advance by a thermal oxidation process.

The plasma 15 contains charged particles (ions and electrons). Since these charged particles flow into an object (in FIG. 8, ceramic patterning means 1, oxide film 2a, or electrode 2b) in contact with plasma 15, these objects are charged (charged up). Become.

Usually, since the plasma 15 is not uniformly distributed, there are a high density area (high density area) 15a and a low density area (low density area) 15b. In the high-density region 15a and the low-density region 15b, the plasma 15
Of the high-density region 15
a 2b1 in the low density region 15b and the electrode 2b1 in the low density region 15b.
2 differs in potential during plasma processing. That is, a potential difference occurs between the electrodes 2b1 and 2b2.

This potential difference is caused by the difference between the electrode 2b1 and the oxide film 2.
a, an electric field 17 is generated through the wafer 2 toward the electrode 2b2, and an electron current flows in a direction opposite to the electric field 17. That is, the oxide film 2a is formed by the plasma processing.
The charged particles pass through the inside.

Therefore, as described above, when the patterning means 1 is made of ceramic, the conductive film 1c is formed on at least the surface and the side surface (taper portion 1b) of the opening of the electrode shape. Is desirable. More preferably, the conductive film 1c is formed on the front surface, the back surface, and the side surface of the opening of the electrode shape. By forming the conductive film 1c on the surface and on the side surface of the opening of the electrode shape, the potential can be made constant over the entire surface of the patterning means 1 regardless of the non-uniformity of the plasma 15. The potential difference generated between 2b1 and 2b2 can be reduced.

FIGS. 9A and 9B show that the conductive film 1c is formed on the surface.
2 shows a state in which the electrode 2b is formed by plasma sputtering using the ceramic patterning means 1 on which the electrode 2b is formed. FIG. 9A shows the state immediately after the start of the formation of the electrode 2b.
(B) shows a state when the electrode 2b becomes thick to some extent. As shown in FIG. 9A, in the initial stage of the formation of the electrode 2b by plasma sputtering, the thickness of the electrode 2b is extremely thin, and the electrode 2b is not formed on the entire surface of the opening 1a. -If the conductive film 1c formed on the part 1b is not connected and the plasma 15 is not uniform, a potential difference is generated between the electrodes 2b.

As shown in FIG. 9B, as the formation of the electrode 2b by plasma sputtering progresses and the thickness of the electrode 2b increases, the electrode 2b is formed over the entire surface of the opening 1a. 2b is connected to the conductive film 1c formed on the side surface of the opening 1a, and the potential difference between the electrodes 2b is eliminated even if the plasma 15 is not uniform. Therefore, when the ceramic patterning means 1 having the conductive film 1c formed on the surface is used, the charge shift in the _Qbd measurement can be reduced.

The material of the conductive film 1c formed on the surface of the ceramic patterning means 1 does not need to be the same as the material of the electrode 2b, but may be any material that is functionally conductive. However, considering contamination etc.,
It is desirable that the constituent material of the electrode 2b is the same as that of the conductive film 1c. When both the forming material of the conductive film 1c and the forming material of the electrode 2b are aluminum alloy, the ceramic patterning means 1 must be previously heated to 500 ° C. or more. When the plasma sputtering is performed after the heating, the fluidity of the aluminum alloy (conductive film 1c) increases, and the conductive film 1c on the surface of the ceramic patterning means 1 and the electrode 2b are easily connected at an early stage. Therefore, the charge shift in the Q _bd measurement can be reduced.

A cassette (not shown) supplied to the load lock chamber 10 can accommodate wafers 2 in units of, for example, 13 wafers. It can be accommodated.

Next, a wafer was weighed using the DC magnetron sputtering apparatus for a 300 mm diameter according to the embodiment.
A manufacturing process for manufacturing a quality evaluation MOS will be described.

First, a 300 mm diameter wafer on which an oxide film 2a is formed is placed in a load lock chamber 10 which is open to the atmosphere.
After setting 13 pieces of c in a cassette dedicated to a wafer having a diameter of 300 mm, the c is placed and then the load lock chamber 10 is evacuated to a vacuum state. Normally, the aligner chamber 11 and the transfer chamber 12 other than the load lock chamber 10 are always kept in a vacuum state.

When the load lock chamber 10 is in a vacuum state,
The horizontal transfer robot 14 extends the carrying grip 14a through the aligner chamber 11, takes out the first wafer 2 from the cassette, performs centering and angle correction of the wafer 2 in the aligner chamber 11, The wafer 2 is supplied onto the sample stage 4 in the sputtering chamber 13. At this time, the patterning means 1 installed in the sputtering chamber 13 is supported by the flange 3a of the lower shield 3 and moves away from the sample table 4 as the lifting mechanism 9 rises. 4, so that the horizontal transfer robot 14 does not prevent the wafer 2 from being loaded onto the sample table 4.

When the wafer 2 is placed on the sample stage 4,
The elevating mechanism 9 is driven to descend, and the lower shield 3 holding the patterning means 1 is also lowered until the flange 3a is at a position lower than the height of the wafer 2. For,
The patterning means 1 is mounted on the wafer 2.

Thereafter, when the sputtering process is started, the film-forming material particles 8 fly out from the surface of the target 6 as the Ar particles are sputtered on the target 6 and move toward the wafer 2. The protruding film material particles 8 are deposited on the wafer 2 and film formation proceeds. Way
Since the surface of the wafer 2 is covered by the patterning means 1, the portion on the surface of the wafer 2 where the film material 8 can be deposited is limited to the opening 1 a of the patterning means 1. For this reason, the film is formed while being patterned in the shape of the MOS electrode 2b.
And the polishing step are performed simultaneously.

When the sputtering process is completed, the elevating mechanism 9 is driven to ascend, and the lower deposition shield 3 ascends while supporting the patterning means 1 with this ascent.
The patterning means 1 is separated from the sample stage 4 and held at a position above the sample stage 4. As the patterning means 1 rises, the wafer 2 can be unloaded by the horizontal transfer robot 14, and the unloading gripper 14b of the horizontal transfer robot 14 moves the wafer on the sample stage 4 after the processing. -Unload the chamber 2 from the sputtering chamber 13 and hold it.
During the processing of the previous wafer 2, the next wafer 2 to be processed
The wafer 2 is taken out of the cassette by using the carrying grip 14a, is aligned in the aligner chamber 11, is in a standby state, and the wafer 2 is immediately carried into the sputtering chamber 13. Thereafter, the wafer 2 on which the processing has been completed is stored in a cassette in the load lock chamber 10.

When the next wafer 2 is mounted on the sample table 4, the lifting mechanism 9 is driven again to descend, and the lower shield 3 holding the patterning means 1 is also moved. Then, the flange 3a is lowered to a position lower than the height position of the wafer 2, the patterning means 1 is placed on the wafer 2, and the sputtering process is started. These operations are performed as a series of operations, all of which are controlled by a control system (not shown), and the processing of a plurality of wafers 2 is performed continuously.

When the processing of the wafer 2 stored in the cassette in one of the load lock chambers 10 is completed,
Thereafter, the processing of the wafer 2 stored in the cassette in the other load lock chamber 10 is successively performed, during which the load lock chamber 10 in which the previously processed wafer 2 is stored. Is purged to atmospheric pressure, the wafer 2 is replaced, and evacuated to a vacuum. Therefore, a plurality of lots can be continuously and efficiently processed without a waiting time in the sputtering chamber 13.

The target 6 is made of an AlSiCu alloy or
When Ti is used, no sintering (heat treatment) for reducing the interface state is performed after the electrode forming step. When this heat treatment is applied, in the case of AlSiCu, Cu, Si
Diffuses into the oxide film 2a, deteriorating the current-voltage characteristics of the MOS capacitor. This is because in the case of Ti, the reduction reaction by Ti proceeds at the electrode / oxide film interface, the effective oxide film thickness decreases, and the current-voltage characteristics of the MOS capacitor change. By not performing heat treatment, M
The OS can be manufactured more easily and in a shorter time.

The oxide film 2a is formed on the low resistance wafer.
When the oxide film 2a is not intentionally formed as in the back surface seal oxide film 2a for the purpose of suppressing punt outward diffusion,
In the case where the withstand voltage evaluation is performed by either of the voltage stress method and the current stress method, the oxide film 2a formed on the back surface of the wafer 2 is not removed in the oxide film 2a forming step. This makes it possible to manufacture the MOS more easily and in a shorter time.

According to the method of fabricating a wafer quality evaluation MOS according to the above-described embodiment, since the patterning means 1 has the opening 1a in the shape of the electrode 2b, the patterning means 1 Is placed in contact with the wafer 2 on which the oxide film 2a is formed, which is placed on the sample stage 4 in the sputtering chamber 13, and then Ar gas is supplied into the sputtering chamber 13 to form the target 6. When the film material 8 is supplied to the wafer 2 by sputtering, the electrode 2b is formed on the oxide film 2a.
The material film of the electrode 2b can be formed only in the opening 1a having a shape (mask film forming method).

For this reason, the patterning process is performed simultaneously with the film forming process, so that the photolithography step is not required, and the MOS can be manufactured easily and in a short time. Therefore, the feedback of the MOS oxide film breakdown voltage evaluation result to the wafer manufacturing process can be promptly performed.

Further, since a patterning process can be performed simultaneously with the formation of the electrode material film, conventionally, for example, n + poly
Poly Si CVD needed for Si electrode fabrication
Various devices and systems such as a furnace, a phosphorus diffusion furnace, a phosphorus glass removing system, a resist coater, an exposure machine, a developing device, a poly Si etching system, and a resist removing system can be made unnecessary. For this reason, even when a new MOS production line is constructed for evaluating the quality of a wafer, a large capital investment and a wide installation space are not required. In addition, the footprint can be suppressed, the raw materials required in each step of the patterning process can be made unnecessary, and the maintenance and inspection items of the apparatus can be greatly reduced. .

Further, the magnetron sputtering apparatus used in the method of manufacturing the wafer quality evaluation MOS according to the above-described embodiment is provided with a transfer system for transferring the wafer 2 in a vacuum state. The wafer 2 placed on the table 4 can be replaced in a vacuum state by the horizontal transfer robot 14 constituting the transfer system.
(C) Single-wafer continuous processing becomes possible.

Further, according to the magnetron sputtering apparatus used in the method of fabricating the wafer quality evaluation MOS according to the above-described embodiment, since the patterning means 1 is equipped with the lifting mechanism 9, the wafer is provided. When replacing 2
The moving means 1 can be moved upward away from the wafer 2 placed on the sample stage 4, and the horizontal transfer robot 14 automatically replaces the wafer 2 while maintaining a vacuum state. Large and medium amount of wafers
It is possible to prevent the processing of C2 from being hindered.

In the method of manufacturing a wafer quality evaluation MOS according to the above-described embodiment, a magnetron sputtering apparatus has been described as an example of a thin film forming apparatus to be used. The thin film forming apparatus used in the method for manufacturing MOS is not limited to a magnetron sputtering apparatus, but may be any other sputtering apparatus, vacuum evaporation apparatus, or plasma CVD apparatus.
Various thin film forming apparatuses such as an apparatus can be used similarly.

[0062]

Examples and Comparative Examples Hereinafter, examples and comparative examples of a method of manufacturing a MOS for evaluating wafer quality according to the present invention will be described. <Example 1 and Comparative Example> poly Si electrode, AlSiCu electrode, Ti
Electrode, pure Al electrode, 150mm diameter, p-type CZ way
A MOS capacitor was fabricated in (c) and the breakdown voltage was evaluated. MO
In the case of a poly Si electrode, the conventional general method shown in FIG. 1 is applied to the S preparation process, and in the case of other AlSiCu, Ti, and pure Al electrodes, the method according to the present invention is used. The mask film forming method shown in FIG. 1 was applied. All the back surface oxide films were removed. The current-voltage characteristics at an oxide film thickness of 25 nm and an electrode area of 8 mm ² are shown in FIGS. FIG.
0 indicates that no sintering treatment was performed after the film formation.
Indicates a case where sintering is performed after film formation. In the case of the AlSiCu electrode and Ti electrode which were not subjected to the sintering, the current was almost the same as that of the poly Si electrode.
Voltage characteristics are obtained.

In the case of the AlSiCu electrode and the Ti electrode subjected to the sintering treatment, the current-voltage characteristics are deteriorated or changed. In the case of the pure Al electrode, regardless of whether the sintering treatment is performed or not, the current-voltage characteristics are both poly. Current different from that of Si electrode
Voltage characteristics are obtained, and the wafer
It was confirmed that it was not suitable for quality evaluation of c. <Example 2 and Comparative Example> Three types of 200 mm diameter, p-type way
The quality evaluation based on the oxide film breakdown voltage of (c) was made by applying the conventional general method shown in FIG. 1 for (a) poly Si electrodes, and (b) FIG. 1 for AlSiCu electrodes. Each was manufactured by applying the mask film forming method shown in FIG.

In the case of a poly Si electrode, as shown in FIG. 12A, there is no back oxide film 2a. In the case of an AlSiCu electrode, as shown in FIG. The oxide film breakdown voltage was measured with the oxide film 2a attached.
The formation of the oxide film 2a was performed by dry oxidation at 950 ° C. using a horizontal furnace, and the film thickness was set to 25 nm. FIG.
The electrode formation of (b) was performed using the apparatus shown in FIGS. This is a device that can perform wafer-to-wafer continuous processing in single wafer processing. Figure 12 for MOS capacitor fabrication
It took two days for the one shown in FIG. 12A and 0.7 days for the one shown in FIG.

For the withstand voltage evaluation of the oxide film 2a, the Step Voltage (SV) method as a voltage stress and the Const
Both ant Current (CC) methods were applied. Both are MOS
The polarity was set in the direction in which the capacitor was accumulated (electron injection from the electrode), and an object having an area of 8 mm ² was measured.

In the SV method, the voltage application time in each step was 0.5 sec in 0.5 V steps, and those having an electric field of 1 MV / cm or more at 1 mA were judged to be good. In the CC method, a sample which was injected at a current of 1 mA / cm ² for 500 msec and maintained at 8 MV / cm or more was regarded as a good product.

FIGS. 13 and 14 show the correspondence between the yield rate of the poly Si electrode (a) and the yield rate of the AlSiCu electrode (b) obtained by such a measurement method. In both cases, almost equal non-defective products are obtained with wafers of the same level. The wafer quality was found to be good in the order of A group, B group, and C group.

In the MOS fabrication process for obtaining the same result in the wafer quality evaluation based on the MOS oxide film breakdown voltage,
Compared with the conventional method, in the method according to the present invention, the back oxide film 2a
If the process does not remove, 65% (1.
3 days / 2 days), and the evaluation results can be obtained quickly.

Example 3 and Comparative Example An AlSiCu electrode was formed by applying the mask film forming method shown in FIG. 1 under the same conditions as in Example 1 except that the patterning means 1 was different.
_Qbd evaluation of the S structure was performed. FIG. 15 (a) shows a case where a patterning means in which a conductive film (AlSiCu) is formed on the front and back surfaces and the side surface of the opening is used, and FIG. 15 (b) shows a conductive film (AlSiCu) on the surface and side surfaces of the opening. FIG. 15C shows the case where the patterning means having no conductive film (AlSiCu) is used.
FIG. 15D shows a _Qbd evaluation as a comparative example when a MOS is manufactured by forming a poly Si electrode by photolithography. Here, in order to make the quality of the wafer the same and to clarify the difference due to the MOS electrode forming method, an epitaxial wafer was used as the wafer.

The horizontal axis in FIG. 15 indicates the amount of charge passing through the oxide film per unit area until the breakdown occurs (C / cm ² :
The vertical axis indicates the ratio of MOS electrodes that have broken down, that is, the cumulative failure rate, among all the MOS electrodes in the wafer plane.

In the case of the poly Si electrode shown in FIG. 15D, all the MOSs in the wafer plane did not break down to a passing charge amount sufficiently larger than 0.1 C / cm ² . This is presumably because no plasma process is used when the poly Si electrode is formed by photolithography, so that no charge passes through the oxide film when the MOS electrode is formed. When determining the quality of a _{wafer by the Qbd} method, one of the determination criteria is 0.1 C / cm ² ,
It is understood that the quality of the wafer can be correctly determined by using the poly Si electrode. However, in this case, poly S
The i-electrode is formed by photolithography, and as described in the subject section, has the disadvantage that formation of the MOS electrode requires a great deal of time and labor.

When a MOS electrode is formed by using a ceramic patterning means in which no conductive film (AlSiCu) is formed at all in FIG.
OS breaks down at 0.1 C / cm ² or less. Approximately 1 with the case of the poly Si electrode of FIG.
The difference in the amount of charge passing through the oxide film of the order of magnitude is not due to the difference in wafer quality because the epitaxial wafer is used for the wafer as described above, but is introduced into the oxide film during electrode formation. This is considered to be caused by the presence or absence of damage. That is, when a MOS electrode is formed using a patterning means on which no conductive film (AlSiCu) is formed, it is difficult to evaluate the quality of a wafer based on a criterion of 0.1 C / cm ^2. I can say.

In the case of a MOS fabricated by using a patterning means in which a conductive film (AlSiCu) is formed on the front and back surfaces and the side surfaces of the opening in FIG. 15A, the front surface and the opening in FIG. In the case of a MOS fabricated by using a patterning means having a conductive film (AlSiCu) formed on the side surface, in each case, all MOSs on the wafer surface are 0.1 C / cm.
^If the passing charge amount is ² or less, the breakdown does not occur.
It was possible to evaluate the quality of the wafer with 0.1 C / cm ² as a criterion. Moreover, in these cases, FIG.
Unlike the case of forming the poly Si electrode of (d), the patterning process is performed simultaneously with the film forming process, so that the photolithography process is not required, and the MOS can be easily and quickly performed. Therefore, the feedback of the MOS oxide film breakdown voltage evaluation result to the wafer manufacturing process can be promptly performed.

<Embodiment 4> Using a patterning means in which a conductive film (AlSiCu) is formed on the front and back surfaces and the side surfaces of the opening,
AlSiCu electrodes are formed on wafers by different processes, and MO
_Qbd evaluation of the S structure was performed. First, the first wafer among the wafers housed in the 300 mm wafer dedicated cassette placed in the load lock chamber 10 opened to the atmosphere is replaced with a dummy wafer which is not subjected to an original treatment. And The dummy wafer was supplied onto the sample stage 4 in the above-mentioned usual process, Ar gas was introduced into the sputtering chamber 13, and the DC power supply 5 was energized to generate plasma. The patterning means is heated with the generation of the plasma. The plasma discharge is continued until the temperature of the patterning means becomes 500 ° C. or higher, and then the plasma discharge is temporarily stopped, and the dummy wafer and the wafer for forming the MOS are exchanged.
Thereafter, the wafer was subjected to a plasma sputtering process to form a MOS electrode. The temperature of the patterning means was determined based on the plasma discharge time by using a thermocouple to previously determine the relationship between the plasma discharge time and the temperature of the patterning means.

The thus formed MOS structure Q _bd
FIG. 16 shows the results of the evaluation. If all the MOSs in the wafer plane have a passing charge of 0.1 C / cm ² or less, the MOS
As a result, the quality of the wafer could be evaluated based on 0.1 C / cm ² as a criterion. Moreover, FIG.
In this case, the breakdown resistance is further improved as compared with the embodiment shown in FIG. 1 and the result that the influence of the plasma process on the MOS can be reduced. This is because the fluidity of the conductive film (AlSiCu) formed on the surface of the patterning means is increased by starting the sputtering process by setting the temperature of the patterning means to 500 ° C. or higher, and the early stage of the plasma sputtering process is started. This suggests that conduction between the electrode and the conductive film (AlSiCu) of the patterning means was achieved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a comparison between a MOS fabrication flow according to a conventional method and a MOS fabrication flow according to the present invention.

FIG. 2 is a circuit diagram showing an equivalent circuit when a withstand voltage measurement voltage of a MOS is applied.

FIG. 3 is a graph in which an electrode material is formed on the entire back surface and current-voltage characteristics are examined.

FIG. 4 is a partial plan sectional view schematically showing the entire sputtering apparatus according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view schematically showing a main part of a sputtering chamber of the sputtering apparatus according to the embodiment.

FIG. 6 shows a pattern of a sputtering apparatus according to an embodiment.
FIG. 4 is a plan view showing a lining means.

FIGS. 7A and 7B are schematic diagrams for explaining an outline of a Q _bd method.

FIG. 8 is a cross-sectional view schematically showing how an electrode is formed on an oxide film by a plasma sputtering method.

FIGS. 9A and 9B are cross-sectional views showing a case where an electrode is formed by plasma sputtering using a ceramic patterning means having a conductive film formed on the surface.

FIG. 10: poly Si electrode, AlSiCu electrode, Ti electrode, pure A
4 is a graph showing current-voltage characteristics when a sintering process is not performed after forming an electrode.

FIG. 11: poly Si electrode, AlSiCu electrode, Ti electrode, pure A
l Current after sintering after electrode formation
4 is a graph showing voltage characteristics.

FIG. 12A is a cross-sectional view showing a wafer with a MOS according to a conventional method, and FIG. 12B is an MO manufactured by a method according to the embodiment.
It is sectional drawing which shows the wafer with S.

FIG. 13 shows the case of a poly Si electrode obtained by the SV method and the case of Al
9 is a graph showing a correspondence relationship between a non-defective product rate and a case of a SiCu electrode.

FIG. 14 shows the case of a poly Si electrode obtained by the CC method and the case of Al
9 is a graph showing a correspondence relationship between a non-defective product rate and a case of a SiCu electrode.

FIG. 15 (a) shows a case where a patterning means in which a conductive film (AlSiCu) is formed on the front and back surfaces and side surfaces of an opening is used, and (b) shows a conductive film (AlSiCu) on the front surface and side surfaces of an opening.
(C) uses a patterning means in which no conductive film (AlSiCu) is formed, and (d) uses a poly Si electrode as a comparative example. It is a graph which shows _Qbd evaluation at the time of manufacturing a MOS formed by lithography, respectively.

FIG. 16 is a graph showing the results of Q _bd evaluation of a MOS structure manufactured by the method according to the example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Patterning means 1a Opening 2 Wafer 2a Oxide film 3 Lower deposition shield 4 Sample stand 5 DC power supply 6 Target 7 Magnet 8 Film forming material particles 9 Lifting mechanism 10 Load lock chamber 11 Aligner chamber 12 transfer room 13 sputtering room 14 horizontal transfer robot

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Sumio Miyazaki 2201 Kamioda, Kokita-cho, Kishima-gun, Saga Prefecture Within the Sitix Division of Sumitomo Metal Industries, Ltd. (72) Inventor Kenji Kihara Kami-Oda, Ekita-cho, Kishima-gun, Saga 2201 Sumitomo Metal Industries Co., Ltd., Sitix Business Unit (72) Inventor Tomomi Murakami 2201 Kamida, Ekita-cho, Kishima-gun, Saga Prefecture F-term (reference) 4M106 AA01 AB01 CA14 CA29 CA70 CB19

Claims (8)

[Claims] A wafer quality evaluation MO for evaluating the quality of a wafer based on an oxide film breakdown voltage of a MOS capacitor.
In the method for producing S, an oxide film forming step of forming an oxide film on the surface of the wafer; and a patterning means having an electrode-shaped opening, transferring the wafer into a thin film forming apparatus, Disposing the conductive film on the wafer placed on the sample stage in the thin film forming apparatus; An MO for wafer quality evaluation, comprising: a conductive film forming step of growing a conductive film.
Method for producing S. 2. A wafer quality evaluation MOS according to claim 1, wherein said conductive film is made of AlSiCu alloy or Ti, and no sintering is performed after said conductive film forming step. Method. 3. When the oxide film is not an oxide film formed intentionally, such as a back surface seal oxide film for suppressing out-diffusion of a dopant in a low-resistance wafer, the oxide film is 2. The method according to claim 1, wherein the step of removing the oxide film that has also grown on the back surface of the wafer is not performed in the step of forming the oxide film, regardless of whether the withstand voltage evaluation is performed by either the voltage stress method or the current stress method. 3. A method for manufacturing a MOS for evaluating wafer quality according to claim 2. 4. A pattern evaluation means having an electrode-shaped opening used for growing a conductive film via an oxide film on a surface of a quality evaluation wafer is provided. Thin film forming equipment. 5. The thin-film forming apparatus according to claim 4, wherein the mask portion constituting the patterning means is made of ceramic, SUS, or Inconel. 6. The thin film forming apparatus according to claim 4, wherein said mask portion is made of ceramic, and a conductive film is formed on at least a surface thereof and a side surface of said opening of said electrode shape. 7. The thin film forming apparatus according to claim 4, wherein said mask portion is made of ceramic, and a conductive film is formed on a front surface, a back surface, and a side surface of said opening of said electrode shape. 8. A mask portion constituting said patterning means is made of ceramic, and an aluminum alloy film is formed on at least the surface thereof and on the side surface of said electrode-shaped opening, and a conductive film to be grown on said wafer is formed. 2. The method of manufacturing a wafer quality evaluation MOS according to claim 1, wherein the conductive film is made of an aluminum alloy, and the temperature of the mask portion when growing the conductive film is set to 500 ° C. or higher.