JP2002152184A - Device and method for generating circuit emulation clock - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for circuit emulation clock generation which make it possible to adjust the optimum buffer storage depth when data transmission delay is reduced by an adaptive block method and also make it possible to adjust buffer storage depth even in operation by providing a protection buffer for underflow prevention. SOLUTION: A buffer control part 5 optionally varies the center position of a buffer 1. A buffer storage quantity variation monitor part 4 monitors the variation quantity of data stored in the buffer 1 according to a period T set in a timer 6. The buffer control part 5 shifts the monitored center position of the buffer 1 to an arbitrary position according to the result of the monitoring by the monitor part 4. Further, the monitor part 4 finds a statistical protection buffer from the variation quantity and the buffer control part 5 computes an offset value set to the buffer according to the protection buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit emulation clock recovery apparatus and method, and more particularly, to a circuit emulation clock recovery apparatus and an improvement method for an adaptive clock method.

[0002]

2. Description of the Related Art Conventionally, as an interworking specification in connection between an ATM network and a fixed network (CBR: Constant Bit Rate) of n × 64 kbps (n is an integer) in an N-ISDN or a digital leased line, etc.・ Emulation service (CE
S: Curcuit Emulation Service).

In this circuit emulation service, there is an adaptive clock method as a method for establishing a point-to-point synchronization instead of an end-to-end synchronization. This is a method used when it is difficult to establish end-to-end synchronization in, for example, international communication via a plurality of communication companies.

In the adaptive clock method, as a method for achieving clock synchronization on the slave side, ITU-
As described in TI 363.1, a method of reproducing the clock on the slave side by accumulating data in the buffer and adjusting the read clock so that the accumulated amount of the buffer becomes the central point of the whole is adopted. ing. Traditionally,
In many cases, the method described in this recommendation is used as it is.

However, this method has a problem in that data is not read from the buffer until the data is accumulated up to the center of the buffer, so that a delay in transmission occurs.

[0006] As a prior art for solving such a problem, Japanese Patent No. 2950231 (hereinafter referred to as "prior art 1") discloses a "reassembling buffer control apparatus and control method for cellular transfer data". Exists.

In the prior art 1, by automatically adjusting the storage depth of the buffer to absorb the delay variation of the cell,
Let the delay in data transmission be the minimum value. For this reason,
The prior art 1 is configured to absorb the delay variation of the cellularized transfer data by sequentially reading the cellularized transfer data and reading it out in a FIFO manner when the cellularized transfer data is reassembled into time-division multiplexed transmission. In the reassembly buffer control device, a new training period is provided, during which the buffer is read, an overflow or an underflow is detected for a predetermined period, and the depth of the buffer storage is determined based on the detection result. Is configured to vary.

[0008]

However, in the technique disclosed in the above-mentioned prior art 1, the period during which the depth of buffer storage is changed is limited to the training period as described above. Has a problem that makes it impossible to use. This is because there is a possibility that valid data may be lost when the above-described related art 1 is operated during operation.

Accordingly, the present invention has been made in view of the above problems, and it is possible to start the optimal adjustment of the buffer storage depth from the center position of the buffer when reducing the data transmission delay in the adaptive clock method. In addition, an object of the present invention is to provide a circuit emulation clock reproducing apparatus and a method thereof, in which a protection buffer for preventing underflow is provided so that the buffer storage depth can be adjusted even during operation.

[0010]

In order to achieve the above object, according to the present invention, a buffer for temporarily storing data received from a line, and a clock for generating a clock signal for reading data from the buffer are provided. Generating means;
A clock control unit that controls an operation of outputting a clock signal by the clock generation unit; a buffer accumulation amount variation monitoring unit that monitors a variation amount of data accumulated in the buffer; and a clock control unit based on the data accumulation amount of the buffer. Buffer control means for controlling the output of the clock signal from the clock generation means, wherein the buffer control means changes the buffer center position based on the fluctuation amount notified from the buffer accumulation amount fluctuation monitoring means. It is characterized by.

According to the second aspect of the present invention, in the circuit emulation clock reproducing apparatus according to the first aspect, the buffer control means may be arranged so that, when the variation amount is larger than the storage capacity up to the current center position of the buffer. The center position is changed to a deep position in the buffer, and when the variation is smaller than the storage capacity up to the current center position of the buffer, the center position is changed to a shallow position in the buffer.

According to a third aspect of the present invention, in the circuit emulation clock reproducing apparatus according to the first or second aspect, the buffer control means sets the upper limit of the set center position to the center position of the entire buffer. Features.

According to a fourth aspect of the present invention, in the circuit emulation clock reproducing apparatus according to any one of the first to third aspects, the buffer accumulation amount fluctuation monitoring means is configured to monitor the fluctuation of one or more times. An offset value to be set in the buffer is statistically calculated based on the amount, and the buffer control means sets the lower limit of the set center position as the offset value.

According to a fifth aspect of the present invention, in the circuit emulation clock reproducing apparatus according to any one of the first to fourth aspects, the buffer comprises:
(N is a natural number), the buffer accumulation amount fluctuation monitoring means monitors the fluctuation amount and the data accumulation amount for each divided area, and the buffer control means sets one of the divided areas as a center position. It is characterized by doing.

According to a sixth aspect of the present invention, in the circuit emulation clock reproducing apparatus according to any one of the first to fifth aspects, the buffer control means includes a storage capacity for storing the data storage amount up to the center position. If the number is larger than that, the clock control means is controlled to shorten the cycle of the clock signal output from the clock generation means,
When the data storage amount is smaller than the storage capacity up to the center position, the clock control unit is controlled to increase the period of the clock signal output from the clock generation unit.

According to a seventh aspect of the present invention, there is provided a buffer for temporarily storing data received from a line, clock generating means for generating a clock signal for reading data from the buffer, and the clock generating means outputting a clock signal. Clock control means for controlling the operation of the buffer, buffer fluctuation monitoring means for monitoring the fluctuation amount of data stored in the buffer, and a clock signal from the clock generation means to the clock control means based on the data storage amount of the buffer. Buffer control means for controlling to output
The buffer control means changes the storage capacity of the buffer based on the fluctuation amount notified from the buffer storage fluctuation monitoring means.

According to the invention of claim 8, in the circuit emulation clock reproducing apparatus of claim 7, the buffer control means manages the center position of the buffer corresponding to the currently set storage capacity, If the variation is larger than the storage capacity up to the current center position of the buffer, the center position is changed to a deep position in the buffer.If the variation is smaller than the storage capacity up to the current center position of the buffer, the center position is changed. The feature is to change to a shallow position in the buffer.

According to a ninth aspect of the present invention, in the circuit emulation clock reproducing apparatus according to the seventh or eighth aspect, the buffer control means sets the upper limit of the storage capacity to be set to the storage capacity of the entire buffer. Features.

According to a tenth aspect of the present invention, in the circuit emulation clock reproducing apparatus according to any one of the seventh to ninth aspects, the buffer accumulation amount fluctuation monitoring means is configured to monitor the fluctuation of one or more times. An offset value to be statistically set in the buffer is calculated based on the amount, and the buffer control means uses the lower limit of the set storage capacity as the offset value.

According to an eleventh aspect of the present invention, in the circuit emulation clock reproducing apparatus according to any one of the seventh to tenth aspects, the buffer comprises:
n (n is a natural number), the buffer accumulation amount fluctuation monitoring means monitors the fluctuation amount and the data accumulation amount for each of the divided areas, and the buffer control means assigns one of the divided areas to the storage capacity. It is characterized in that it is set as the upper end.

According to a twelfth aspect of the present invention, in the circuit emulation clock reproducing apparatus according to any one of the seventh to eleventh aspects, the buffer control means may include a storage capacity for storing the data storage amount up to the center position. If it is larger than the number, the clock control means is controlled to shorten the cycle of the clock signal output from the clock generation means, and if the data storage amount is smaller than the storage capacity up to the center position, the clock control means is controlled. It is characterized in that control is performed so as to lengthen the cycle of the clock signal output from the clock generation means.

A thirteenth aspect of the present invention is a circuit emulation clock reproducing method for reading data stored based on a storage capacity up to a center position set in a buffer, wherein the variation of the data stored in the buffer is varied. The method is characterized by comprising a data accumulation fluctuation amount monitoring step of periodically monitoring the amount and a center position changing step of changing the center position based on the fluctuation amount.

According to a fourteenth aspect of the present invention, in the circuit emulation clock reproducing method according to the thirteenth aspect, the center position changing step is performed when the amount of variation is larger than the storage capacity up to the current center position of the buffer. The center position is changed to a deep position in the buffer, and if the amount of change is smaller than the storage capacity up to the current center position of the buffer, the center position is changed to a shallow position in the buffer.

According to a fifteenth aspect of the present invention, in the circuit emulation clock reproducing method according to the thirteenth or fourteenth aspect, in the center position changing step, the upper limit of the set center position is set to the center position of the entire buffer. It is characterized by.

[0025] Further, the invention described in claim 16 is based on claim 1.
16. The circuit emulation clock recovery method according to any one of items 3 to 15, wherein an offset value for statistically calculating an offset value to be set in the buffer based on at least one variation monitored in the data accumulation variation monitoring step. The method further includes a calculating step, and the center position changing step includes:
It is characterized in that the lower limit of the set center position is an offset value.

According to a seventeenth aspect of the present invention, in the circuit emulation clock reproducing method according to any one of the thirteenth to sixteenth aspects, the buffer is divided into n (n is a natural number), and The accumulated amount monitoring step monitors the amount of change for each of the divided areas, and the center position changing step sets one of the divided areas as the center position.

The invention according to claim 18 is the first invention.
18. The circuit emulation clock regeneration method according to any one of 3 to 17, wherein when the stored data is larger than the storage capacity up to the center position, control is performed so as to shorten the cycle of the read clock of the data stored in the buffer. When the stored data is smaller than the storage capacity up to the center position, the method further comprises a read clock control step of controlling the read clock cycle of the data stored in the buffer to be longer.

The invention according to claim 19 is a circuit emulation clock reproducing method for reading out data stored based on the storage capacity up to the center position set in the buffer, wherein the variation of the data stored in the buffer is changed. It is characterized by comprising a data accumulation fluctuation monitoring step of periodically monitoring the amount, and a storage capacity changing step of changing the storage capacity of the buffer based on the fluctuation.

The invention according to claim 20 is the first invention.
9. The circuit emulation clock reproducing method according to claim 9, further comprising a center position calculating step of calculating a center position of the buffer corresponding to the storage capacity currently set in the buffer, and wherein the storage capacity changing step includes the step of: If the storage capacity up to the center position of the buffer is larger, the center position is changed to a deep position in the buffer.If the amount of change is smaller than the storage capacity up to the current center position of the buffer, the center position is changed to a shallow position in the buffer. It is characterized by doing.

According to a twenty-first aspect of the present invention, in the circuit emulation clock reproducing method according to the ninth or twelfth aspect, in the storage capacity changing step, the upper limit of the storage capacity to be set is set to the storage capacity of the entire buffer. It is characterized by.

The invention according to claim 22 is the first invention.
22. The circuit emulation clock recovery method according to any one of 9 to 21, wherein an offset value for statistically calculating an offset value to be set in the buffer based on at least one variation monitored in the data accumulation variation monitoring step. The method further includes a calculating step, and the storage capacity changing step includes:
It is characterized in that the lower limit of the storage capacity to be set is an offset value.

According to a twenty-third aspect of the present invention, in the circuit emulation clock reproducing method according to any one of the nineteenth to twenty-second aspects, the buffer is divided into n (n is a natural number), and The accumulated amount monitoring step monitors the amount of change for each of the divided areas, and the accumulated capacity changing step sets one of the divided areas as the upper end of the accumulated capacity.

The invention according to claim 24 is the first invention.
24. In the circuit emulation clock reproducing method according to any one of 9 to 23, when the stored data is larger than the storage capacity up to the center position, control is performed so as to shorten the cycle of the read clock of the data stored in the buffer. When the stored data is smaller than the storage capacity up to the center position, the method further comprises a read clock control step of controlling the read clock cycle of the data stored in the buffer to be longer.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the present invention are that, in buffer control by the adaptive clock method, a mechanism for changing the center position of the buffer is provided, and underflow during buffer reading is prevented.

In the present invention, the change in the center position of the buffer is performed by monitoring the accumulated amount of the buffer in each cycle, and when the change amount is large, the center position of the buffer is changed more deeply. If the variation is small,
This is to make the center position of the buffer shallower. At this time, in order to prevent a buffer underflow due to a sudden change in the data amount, the present invention newly provides a mechanism for setting a protection buffer based on statistical information.

With such a mechanism, in the present invention, it is possible to reproduce the read clock according to the amount of data stored in the buffer, and to provide a protection buffer against a sudden change in the data amount based on the statistical information. Thus, the predicted control can be performed. Thus, the present invention minimizes the delay in data transmission.

As a configuration for realizing the above-described mechanism, a preferred embodiment of a circuit emulation clock reproducing apparatus and a method thereof according to the present invention will be described in detail with reference to the drawings.

[First Embodiment] First, a first embodiment of the present invention will be described in detail with reference to the drawings.

(Configuration of the First Embodiment) FIG. 1 is a block diagram showing the configuration of the present embodiment. Referring to FIG. 1, this embodiment includes a buffer 1, a clock control unit 2, a clock generation unit 3, a buffer accumulation amount fluctuation monitoring unit 4, a buffer control unit 5, and a timer 6.

In the above configuration, the buffer 1, the clock control unit 2 and the clock generation unit 3 are disclosed by the prior art. More specifically, a commonly used buffer is applied. Further, the clock control unit 2 monitors whether the data accumulation amount exceeds or falls below the center position of the buffer, so that the fluctuation direction of the data accumulation amount of the buffer 1 always faces the position defined as the center of the entire buffer. To control the clock generator 3. Further, the clock generator 3 generates a read clock for the buffer 1 according to the instruction of the clock controller 2 and
To read the data stored in.

In contrast to such a configuration, a buffer accumulation amount fluctuation monitoring unit 4, a buffer control unit 5, and a timer 6 are newly provided as a unique configuration of the present embodiment.

In this new configuration, the buffer control unit 5 is provided between the buffer 1 and the clock control unit 2, and operates to manage the center position of the buffer 1 and arbitrarily change it. Further, the buffer accumulation amount fluctuation monitoring unit 4
Monitors the amount of change in the data stored in the buffer 1 based on the cycle T set in the timer 6. Therefore, the buffer control unit 5 changes the center position of the managed buffer 1 to an arbitrary position based on the result of monitoring by the buffer accumulation amount monitoring unit 4. That is, the buffer control unit 5 determines that the amount of change in the data stored in the buffer 1 is smaller than the storage capacity up to the center position set in the buffer 1 by the buffer storage amount change monitoring unit 4.
The center position in the buffer 1 is changed to an appropriate value or lower at an appropriate interval. On the other hand, the amount of change in the data stored in the buffer 1 by the buffer storage amount change monitoring unit 4 is changed to the center set in the buffer 1. If it is determined that the storage capacity is larger than the storage capacity up to the position, the center position in the buffer 1 is changed to an appropriate value or higher at appropriate intervals.

Here, the center position of the buffer 1 is managed by the buffer control unit 5, and the buffer control unit 5 controls the change amount of the stored data notified from the buffer storage amount change monitoring unit 4. Is compared with the storage capacity up to the center position of the managed buffer 1, and the center position of the managed buffer 1 is changed based on the result of this comparison.

Further, the buffer control unit 5 compares the amount of data stored in the buffer 1 with the storage capacity that can be stored up to the managed center position, and based on the result of this comparison, performs clock control. A request is made to the section 2 to generate and control a read clock for reading data stored in the buffer 1.

The buffer accumulation amount fluctuation monitoring section 4 monitors the fluctuation of the data accumulation amount stored in the buffer 1 and also prevents the buffer underflow due to the rapid fluctuation of the data accumulation amount from occurring. The protection buffer amount (or the offset value of the buffer 1) is calculated based on the statistical information of the data fluctuation amount, and this is notified to the buffer control unit 5.

Therefore, the buffer control unit 5 according to the present embodiment sets the center position of the buffer 1 to a value that does not fall below the offset value based on the statistical information. That is, the lower limit of the center position set in the buffer 1 is the offset value notified from the buffer accumulation amount fluctuation monitoring unit 4. On the other hand, in the buffer 5 according to the present embodiment, the upper limit of the center position set in the buffer 1 is limited to half of the total storage capacity of the buffer 1.

Here, as a method of calculating the offset value added to the storage depth of the buffer 1, for example, the period T
It is considered that a method of averaging the fluctuation amount of the data accumulation amount measured in step h for the h period and calculating the value is effective.
Although the value of the number of samples h to be averaged is arbitrarily set, it is preferable that the value be determined based on the cycle of statistical fluctuation of the traffic volume in data transmission. However, regarding this method,
The present invention is not particularly limited, and various modifications can be made without departing from the gist of the present invention. Here, the buffer 1 has the protection buffer amount and the offset value in the protection accumulation area in the buffer 1 in which the protection buffer amount is calculated from the statistical information, and the offset value protects the protection buffer region. It is because it is a value set for.

With the above-described configuration, in this embodiment, when the data transmission delay is reduced in the adaptive clock method, the optimal adjustment of the buffer storage depth is realized by changing the center position of the buffer. ,
By providing a protection buffer for preventing underflow, it is possible to adjust the buffer storage depth even during operation.

(Operation of First Embodiment) Next, the operation of the above-described embodiment will be described in detail with reference to the drawings.

In the first embodiment shown in FIG. 1, the operation of the buffer control unit 5 for changing the center position of the buffer 1 based on the information from the buffer accumulation amount fluctuation monitoring unit 4 is shown in FIG.
This will be described in detail with reference to a buffer image diagram of FIG.

Referring to FIG. 2, in the present embodiment, the buffer 1 is divided into n equal parts. This is used when the buffer storage amount fluctuation monitoring unit 4 determines the amount of data stored in the buffer 1 every predetermined period (cycle T), and is provided as a value of the center position set in the buffer control unit 5. Have been. Here, the value of the division number n may be arbitrary. In describing FIG. 2, the center position of the entire buffer 1 with respect to the storage capacity is m (max). Further, in describing the present embodiment, the respective regions of the buffer 1 divided into n are described as 1, 2, 3,.
(max),... n. Further, the center position currently set in the buffer control unit 5 is set to m. Therefore, in the present embodiment, the center position of the buffer 1 is determined from the offset value notified from the buffer accumulation amount variation control unit 4 (this offset value is assumed to be m (min) in the present description), for example. max). Here, in the present embodiment, the offset value m (min)
Is a value obtained based on the statistical information in the buffer accumulation amount fluctuation control unit 4.

In the present embodiment configured as described above, the fluctuation amount of the data accumulation amount (accumulation fluctuation amount) measured for each cycle T set in the timer 6 by the buffer accumulation amount fluctuation monitoring unit 4 is determined by the buffer control. The notification is sent to the unit 5.

Therefore, the buffer control unit 5 judges the change of the center position set in the buffer 1 by comparing the notified variation amount with the storage capacity up to the center position of the buffer 1.

When the buffer control unit 5 determines that the notified fluctuation amount is smaller than the storage capacity up to the center position of the buffer 1, for example, the buffer control unit 5 determines the center position of the entire buffer 1, for example, m as the original setting. When it is located at the position, the position is changed from the position of m to the position of m-1 which is a shallow position.
This is to solve the underflow that occurs at the time of reading due to the fact that the fluctuation amount is smaller than the data amount accumulated up to the center position.

On the other hand, when the buffer 5 determines that the notified fluctuation amount is larger than the storage capacity up to the center position of the buffer 1, the buffer 5 determines the center position of the entire buffer 1, for example, m as the original setting. If it is located at the position, the position is changed from this m position to the deep position m + 1.
This is to solve an overflow that occurs at the time of reading due to the fact that the fluctuation amount is larger than the data amount accumulated up to the center position.

In this embodiment, a protection buffer area is provided as a lower limit for the center position set in the buffer 1. This is to prevent an extremely shallow center position from being set in response to a sudden change in the amount of accumulation fluctuation in the buffer 1, particularly a sudden decrease in the amount of accumulation fluctuation.

As described above, the protection buffer area is determined by the buffer storage amount fluctuation monitoring unit 4 based on the statistical information on the fluctuation amount of the data stored in the buffer 1. As the statistical information, as exemplified above, a method of calculating from the average value of the measured fluctuation amounts for h periods, or the like can be considered.

Further, the buffer accumulation amount fluctuation monitoring section 4 calculates an offset value based on the protection buffer amount calculated in this way, and notifies the buffer control section 5 of the calculated offset value. The buffer control unit 5 uses the thus notified offset value as a lower limit (offset) for setting the center position of the buffer 1. In addition, as a method for specifying the offset value, a method of adding 1 (m (min) in FIG. 2) to a position (m (min) -1 in FIG. 2) corresponding to the calculated protection buffer amount, or the like. Can be considered. However, this is not particularly limited, and various modifications can be made without departing from the gist of the present invention. Therefore, detailed description is omitted here.

With this configuration, the center position m set by the buffer control unit 5 is set to an area (at least an area where the buffer 1 is divided into n) that does not fall below the protection buffer amount at least.

Further, the buffer control unit 5 sets the center position m (ma) in the entire buffer 1 against the above lower limit.
x) is the upper limit of the set center position. Therefore, in the example of FIG. 2, the upper limit of the center position set in the buffer 1 is m (max), and the lower limit is m (min).

Next, the operation of this embodiment described above will be described in detail with reference to the flowcharts shown in FIGS. However, the flowcharts shown in FIG. 3 and FIG. 4 are started as processes for operating each configuration.

Process for Controlling Center Position of Buffer 1 FIG. 3 is a flowchart showing an algorithm of an operation for controlling the center position of the buffer 1 which is the gist of the present invention in the above description.

Referring to FIG. 3, in the present embodiment, first, the adaptive clock function is set to the ON state (step S101).

Next, in the buffer accumulation amount fluctuation monitoring unit 4, the fluctuation amount B _n of the data accumulation amount accumulated in the buffer 1 measured in the period T based on the count value notified from the timer 6 is set to B _0. ( _Bn = _B0 ) is recorded (step S102). At this time, in the normal state, the previously read fluctuation amount _Bn is held in a register or the like stored in the buffer accumulation amount fluctuation monitoring unit 4 or the like.
₀ to, but immediately after the start-up state, since the fluctuation amount B _n previously read not held in a register or the like, buffer fullness change monitoring unit 4 at this time, substitutes the value of 0 to B _0.

Next, the buffer accumulation amount fluctuation monitoring section 4 reads the accumulation amount of the data stored in the buffer 1 (step S103). At this time, the read accumulation amount is set to _Bn . Further, the timing of this reading is after T counting from the time when the previous reading was performed.

Thereafter, the buffer accumulation amount fluctuation monitoring unit 4
In order to calculate the variation amount (or also referred to as the variation amount) B of the data accumulation amount in the cycle T of the buffer 1, (B _n −
B ₀ ) is calculated (step S104).

After calculating the accumulated fluctuation amount B for each cycle T in the data accumulated in the buffer 1 as described above, the buffer accumulated amount fluctuation monitoring unit 4 determines whether the calculated accumulated fluctuation amount B is 0 or not. (Step S105). In this determination, when the accumulated fluctuation amount B is 0 (step S1)
05), the buffer accumulation amount fluctuation monitoring unit 4 next determines whether or not the time (or the counter value) t measured by the timer 6 is T (step S1).
06). However, the determination at this time is not (t = T),
(T ≧ T). This step S106
Is repeatedly performed until the time t reaches or exceeds the time t (No in step S106).

In the determination in step S106,
When the time t of the timer 6 has reached or exceeded T (Yes in step S106), the operation of setting the center position m is to determine whether or not the adaptive clock function is currently set to the ON state. Determine (Step S10
7) If it is in the ON state (Y in step S107)
es), the process returns to step S102. In addition, in the determination in step S107, the adaptive clock function is currently in the OFF state (step S10
7), the present embodiment ends the series of processes illustrated in FIG.

On the other hand, if it is determined in step S105 that the calculated accumulation fluctuation amount B is not 0 (No in step S105), the buffer accumulation amount fluctuation monitoring unit 4
The buffer controller 5 is notified of the calculated accumulation fluctuation amount (step S108).

The buffer control unit 5 notified of the accumulated fluctuation amount B first determines whether or not the accumulated fluctuation amount B is larger than 0 (step S109). In this determination, when the accumulated fluctuation amount B is larger than 0 (step S1).
09 (Yes), the buffer controller 5 increments the value of the center position m set in the buffer 1 by, for example, 1 (step S110).

However, in the present embodiment, the upper limit of the center position set in the buffer 1 is limited so as not to exceed m (max) which is the center position of the entire buffer 1. Therefore,
The buffer control unit 5 determines that the center position m of the buffer 1 set in step S110 is the center position m (ma
x) is determined (step S11)
1). In the determination in step S111, when the set center position m does not exceed m (max) (step S111).
The operation of setting the center position m shifts to step S106.

In the determination in step S111,
If the set center position m exceeds m (max) (Yes in step S111), the buffer controller 5 replaces the value of the center position m set in the buffer 1 with m (max) (step S112). . Thereafter, the operation of setting the center position m shifts to Step S106.

On the other hand, if it is determined in step S109 that the accumulated fluctuation amount B is smaller than 0 (step S109).
109, No), the buffer control unit 5 decrements the value of the center position m set in the buffer 1 by, for example, 1 (step S113).

However, in the present embodiment, the lower limit of the center position set in the buffer 1 is determined by the buffer accumulation amount fluctuation monitor 4
Is limited so as not to fall below the offset value notified from. Therefore, the buffer control unit 5 determines in step S1
It is determined whether the center position m of the buffer 1 set in step 13 is smaller than the offset value m (min) (step S13).
114). In the determination in step S114, if the set center position m is not less than m (min) (No in step S114), the operation of setting the center position m is as follows.
Move to step S106.

In the determination in step S114,
When the set center position m is smaller than m (min) (Yes in step S114), the buffer control unit 5 replaces the value of the center position m set in the buffer 1 with m (min) (step S115). . Thereafter, the operation of setting the center position m shifts to Step S106.

With the above operation, in the present embodiment, when reducing the data transmission delay in the adaptive clock method, the optimal adjustment of the buffer storage depth is realized by changing the center position of the buffer, and the underflow is achieved. By providing a protection buffer for prevention, the buffer storage depth can be adjusted even during operation.

Process for Controlling Read Clock in Accordance with Buffer Accumulation Fluctuation Next, an operation for controlling a clock for reading data from the buffer 1 will be described with reference to FIG. FIG. 4 is a flowchart showing an algorithm of an operation for controlling the read clock in accordance with the buffer accumulation fluctuation amount.

Referring to FIG. 4, in the present embodiment, first, the adaptive clock function is set to the ON state (step S201).

Next, the buffer controller 5 acquires the amount of data currently stored in the buffer 1 (data storage amount) (step S202).

When the data storage amount is obtained in this manner, the buffer control unit 5 determines whether the data storage amount exceeds, falls below, or is equal to or smaller than the storage capacity up to the center position m set in the buffer 1. Is determined (step S203).

If it is determined in step S203 that the data storage amount is equal to the storage capacity up to the center position m (m = storage amount in step S203), the processing for controlling the read clock shifts to step S204, and the adaptive clock It is determined whether or not the function is currently set to the ON state (step S204). If the function is set to the ON state (Yes in step S204), step S20 is performed.
Return to 2. In addition, in the determination in step S204, when the adaptive clock function is currently in the OFF state (No in step S204), the present embodiment ends the series of processes illustrated in FIG.

On the other hand, if it is determined in step S203 that the data storage amount is smaller than the storage capacity up to the center position m (m <storage amount in step S203), the buffer control unit 5 On the other hand, control is performed so that the read clock of the buffer 1 output from the clock generation unit 3 is increased (step S205). Thereafter, in the process of controlling the read clock, the read clock of the buffer 1 is quickly controlled by the clock generator 3 (step S206), and the process proceeds to step S204.

Further, in the determination in step S203,
When the data storage amount is larger than the storage capacity up to the center position m (m> storage amount in step S203), the buffer control unit 5 reads the buffer 1 output from the clock generation unit 3 to the clock control unit 2. Control is performed so as to slow down the clock (step S207). Thereafter, in the process of controlling the read clock, the clock generation unit 3 controls the read clock of the buffer 1 later (step S208), and proceeds to step S204.

With this operation, in the present embodiment, it is possible to generate a read clock according to the situation according to the changing center position m of the buffer 1.

[Second Embodiment] In the first embodiment, the center position of the buffer 1 is changed to prevent data delay at the time of transmission. The same effect can be obtained by making the entire storage capacity of the first embodiment variable.

Hereinafter, the circuit emulation clock reproducing apparatus and method according to the present embodiment will be described in detail with reference to the drawings.

The configuration in this embodiment is similar to the configuration shown in FIG. However, in the first embodiment,
In the algorithm of the operation for changing the storage capacity (FIG. 3), the operation of the buffer control unit 5 includes steps S110, S112, S113, and S11.
5, the center position m is changed, but in the present embodiment, the entire storage capacitance N is changed instead of the center position m.

Such an operation will be described in detail with reference to a buffer image diagram shown in FIG. Referring to FIG. 5, in the present embodiment, n (= N
(max)), N as the storage capacity of the buffer 1 set in the buffer control unit 5, and the minimum value of the storage capacity of the buffer 1 set based on the offset value notified from the buffer storage amount fluctuation monitoring unit 4. Is defined as N (min).

Here, the offset value is a protection area for the storage capacity N of the buffer 1 set in the present embodiment, similarly to the protection area for the set center position m calculated in the first embodiment. This is calculated based on the protection buffer amount specified based on the statistical information calculated by the buffer storage amount fluctuation monitoring unit 4.

Therefore, in this embodiment, the value of the storage capacity N set in the buffer control unit 5 is notified from the buffer storage amount fluctuation monitoring unit 4 from the storage capacity n (the maximum value of the storage capacity) of the entire buffer 1. Offset value N (min)
(The minimum value of the storage capacity).

Next, an algorithm for controlling the storage capacity of the buffer 1 according to the present embodiment will be described in detail with reference to the flowchart of FIG.

Process for Controlling Storage Capacity of Buffer 1 Referring to FIG. 6, in the present embodiment, first, the adaptive clock function is set to the ON state (step S3).
01).

Next, in the buffer accumulation amount fluctuation monitoring unit 4, the fluctuation amount B _n of the data accumulation amount accumulated in the buffer 1 measured in the period T based on the count value notified from the timer 6 is set to B _0. (B _n = B ₀₎ is recorded (step S302). At this time, in the normal state, the previously read fluctuation amount _Bn is held in a register or the like stored in the buffer accumulation amount fluctuation monitoring unit 4 or the like.
₀ to, but immediately after the start-up state, since the fluctuation amount B _n previously read not held in a register or the like, buffer fullness change monitoring unit 4 at this time, substitutes the value of 0 to B _0.

Next, the buffer accumulation amount fluctuation monitoring section 4 reads the accumulation amount of the data stored in the buffer 1 (step S303). At this time, the read accumulation amount is set to _Bn . Further, the timing of this reading is after T counting from the time when the previous reading was performed.

Thereafter, the buffer accumulation amount fluctuation monitoring unit 4
In order to calculate the variation amount (or also referred to as the variation amount) B of the data accumulation amount in the cycle T of the buffer 1, (B _n −
B ₀ ) is calculated (step S304).

After calculating the accumulation fluctuation amount B for each cycle T in the data accumulated in the buffer 1 in this way, the buffer accumulation amount fluctuation monitoring unit 4 determines whether the calculated accumulation fluctuation amount B is 0 or not. (Step S305). In this determination, when the accumulated fluctuation amount B is 0 (step S3
05, the buffer accumulation amount fluctuation monitoring unit 4 next determines whether the time (or the counter value) t measured by the timer 6 is T (step S3).
06). However, the determination at this time is not (t = T),
(T ≧ T). This step S306
Is repeatedly performed until the time t reaches or exceeds T (No in step S306).

In the determination in step S306,
When the time t of the timer 6 has reached or exceeded T (Yes in step S306), the operation for setting the storage capacity N is to determine whether the adaptive clock function is currently set to the ON state. Judge (Step S30
7) If it is in the ON state (Y in step S307)
es), the process returns to step S302. Also, in the determination of step S307, if the adaptive clock function is currently in the OFF state (step S30
7), this embodiment ends the series of processes illustrated in FIG.

On the other hand, if it is determined in step S305 that the calculated accumulation fluctuation amount B is not 0 (No in step S305), the buffer accumulation amount fluctuation monitoring unit 4
The calculated accumulation fluctuation amount is notified to the buffer control unit 5 (step S308).

Up to here, FIG. 3 in the first embodiment has been described.
The operation is the same as that described above. On the other hand, in the present embodiment, the subsequent operations are as follows.

The buffer control unit 5 notified of the accumulation fluctuation amount B first determines whether or not the accumulation fluctuation amount B is larger than 0 (step S309). In this determination, when the accumulated fluctuation amount B is larger than 0 (step S3
09 (Yes), the buffer controller 5 increments the value of the storage capacity N set in the buffer 1 by, for example, 1 (step S110).

However, in the present embodiment, the upper limit of the storage capacity set in the buffer 1 is limited so as not to exceed N (max), which is the storage capacity of the entire buffer 1. Therefore,
The buffer control unit 5 determines that the storage capacity N of the buffer 1 set in step S310 is equal to the storage capacity N (ma
x) is determined (step S31)
1). If the determined storage capacity N does not exceed N (max) in the determination in step S311 (step S311).
311), the operation of setting the storage capacity N proceeds to step S306.

In the determination in step S311,
When the set storage capacity N exceeds N (max) (Yes in step S311), the buffer control unit 5 replaces the value of the storage capacity N set in the buffer 1 with N (max) (step S312). . Thereafter, the operation of setting the storage capacity N proceeds to step S306.

On the other hand, if it is determined in step S309 that the accumulated fluctuation amount B is smaller than 0 (step S309).
(No at 309), the buffer controller 5 decrements the value of the storage capacity N set in the buffer 1 by, for example, 1 (step S313).

However, in the present embodiment, the lower limit of the storage capacity set in the buffer 1 is determined by the buffer storage amount fluctuation monitor 4
Is limited so as not to fall below the offset value notified from. Therefore, the buffer control unit 5 determines in step S3
It is determined whether the storage capacity N of the buffer 1 set in step S13 is smaller than the offset value N (min) (step S13).
314). In the determination in step S314, if the set storage capacity N is not less than N (min) (No in step S314), the operation of setting the storage capacity N is as follows.
Move to step S306.

In the determination in step S314,
When the set storage capacity N is smaller than N (min) (Yes in step S314), the buffer control unit 5 replaces the value of the storage capacity N set in the buffer 1 with N (min) (step S315). . Thereafter, the operation of setting the storage capacity N proceeds to step S306.

As described above, according to the present embodiment, an effect equivalent to the effect of the first embodiment is obtained by changing the storage capacity of the entire buffer 1 instead of changing the center position in the buffer 1. It becomes possible.
Further, the algorithm for controlling the read clock in accordance with the buffer accumulation fluctuation amount in the present embodiment is the same as the operation shown in the flowchart of FIG. 4, and thus the detailed description is omitted here. However, in the present embodiment, the center position m used by the buffer control unit 5 to control the read clock is calculated based on the storage capacity currently set in the buffer 1 by the buffer control unit 5. Since the configuration for calculating the center position m can be easily implemented by the division circuit, the detailed description of this configuration is also omitted in the present embodiment.

[0107]

As described above, according to the first embodiment of the present invention, it is possible to reproduce the read clock in accordance with the amount of data stored in the buffer, and furthermore, to cope with a sudden change in the data amount. Also, by providing the protection buffer, it is possible to perform control predicted based on the statistical information. This allows the present invention to minimize delays in data transmission. In addition, these effects
The present invention is configured so that it can be realized even during operation.

Further, according to the second embodiment of the present invention,
The same effect as in the first embodiment can be obtained by using the buffer 1
Can be realized by making the storage capacity of the buffer 1 variable, instead of making the center position set to be variable.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration according to a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration image of a buffer 1 according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing an algorithm of an operation for controlling the center position of the buffer 1 in the first embodiment of the present invention.

FIG. 4 is a flowchart illustrating an algorithm of an operation of controlling a read clock in accordance with a buffer accumulation variation amount in the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration image of a buffer 1 according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing an algorithm of an operation for controlling the storage capacity of the buffer 1 according to the second embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 buffer 2 clock control unit 3 clock generation unit 4 buffer accumulation amount fluctuation monitoring unit 5 buffer control unit 6 timer B accumulation amount of buffer 1 B ₀ accumulation amount of buffer 1 (one cycle before) B _n accumulation amount of buffer 1 ( M) The central position of the buffer (current) m (max) The central position of the entire buffer 1 m (min), N (min) The offset value of the buffer 1 n The number of divisions of the buffer 1, the total storage capacity of the buffer 1 N buffer No. 1 storage capacity (current) N (max) Total storage capacity of buffer 1 t Elapsed time T Storage fluctuation amount calculation cycle of buffer 1

Claims (24)

[Claims] 1. A buffer for temporarily storing data received from a line, a clock generator for generating a clock signal for reading data from the buffer, and a clock for controlling an operation of the clock generator for outputting a clock signal. Control means; buffer accumulation amount fluctuation monitoring means for monitoring the fluctuation amount of data accumulated in the buffer; and a clock signal output from the clock generation means to the clock control means based on the data accumulation amount of the buffer. Circuit emulation, wherein the buffer control means changes the center position of the buffer based on the fluctuation amount notified from the buffer accumulation amount fluctuation monitoring means. Clock regeneration device. 2. The buffer control means according to claim 1, wherein, when said variation is larger than a storage capacity up to a current center position of said buffer, said buffer control means changes said center position to a deeper position in said buffer, and 2. The circuit emulation clock reproducing apparatus according to claim 1, wherein when the storage capacity is smaller than the current center position, the center position is changed to a shallow position in the buffer. 3. The circuit emulation clock reproducing apparatus according to claim 1, wherein said buffer control means sets an upper limit of said set center position as a center position of said entire buffer. 4. The buffer accumulation amount fluctuation monitoring means statistically calculates an offset value to be set in the buffer based on the observed fluctuation amount of one or more times, and the buffer control means sets the center to be set. 4. The circuit emulation clock reproducing apparatus according to claim 1, wherein a lower limit of a position is set to the offset value. 5. The buffer is divided into n (n is a natural number), the buffer accumulation amount fluctuation monitoring means monitors the fluctuation amount and the data accumulation amount for each divided area, and the buffer control means , One of the divided areas
5. The circuit emulation clock reproducing device according to claim 1, wherein one of the two is set as the center position. 6. The buffer control unit, when the data storage amount is larger than the storage capacity up to the center position, shortens a cycle of the clock signal output from the clock generation unit to the clock control unit. And controlling the clock control means to increase the cycle of the clock signal output from the clock generation means when the data storage amount is smaller than the storage capacity up to the center position. The circuit emulation clock reproducing device according to any one of claims 1 to 5, wherein: 7. A buffer for temporarily storing data received from a line, clock generating means for generating a clock signal for reading data from the buffer, and a clock for controlling an operation of the clock generating means for outputting a clock signal. Control means; buffer accumulation amount fluctuation monitoring means for monitoring the fluctuation amount of data accumulated in the buffer; and a clock signal output from the clock generation means to the clock control means based on the data accumulation amount of the buffer. Circuit emulation, wherein the buffer control means changes the accumulation capacity of the buffer based on the fluctuation amount notified from the buffer accumulation amount fluctuation monitoring means. Clock regeneration device. 8. The buffer control means manages a center position of the buffer corresponding to a currently set storage capacity, and when the fluctuation amount is larger than the storage capacity up to the current center position of the buffer, When the center position is changed to a deep position in the buffer, and the amount of change is smaller than the storage capacity up to the current center position of the buffer,
8. The circuit emulation clock reproducing apparatus according to claim 7, wherein said center position is changed to a shallow position in said buffer. 9. The circuit emulation clock reproducing apparatus according to claim 7, wherein said buffer control means sets an upper limit of said storage capacity to be the storage capacity of the entire buffer. 10. The buffer accumulation amount fluctuation monitoring means,
An offset value to be set in the buffer is statistically calculated based on the amount of fluctuation observed for one or more times, and the buffer control means sets a lower limit of the set storage capacity as the offset value. The circuit emulation clock reproduction device according to claim 7. 11. The buffer is divided into n (n is a natural number), the buffer accumulation amount fluctuation monitoring means monitors the fluctuation amount and the data accumulation amount for each divided area, and the buffer control means , One of the divided areas
11. The circuit emulation clock reproducing apparatus according to claim 7, wherein one is set as an upper end of the storage capacitor. 12. The buffer control means according to claim 1, wherein said data storage amount is larger than a storage capacity up to said center position.
The clock control unit controls the clock control unit to shorten the cycle of the clock signal output from the clock generation unit, and when the data storage amount is smaller than the storage capacity up to the center position, the clock control unit 12. The circuit emulation clock reproducing apparatus according to claim 7, wherein control is performed such that a period of the clock signal output from the clock generating means is extended. 13. A circuit emulation clock recovery method for reading data stored based on a storage capacity up to a center position set in a buffer, wherein a fluctuation amount of data stored in the buffer is periodically monitored. A circuit emulation clock reproducing method, comprising: a data accumulation fluctuation amount monitoring step; and a center position changing step of changing the center position based on the fluctuation amount. 14. The center position changing step, when the amount of change is larger than the storage capacity up to the current center position of the buffer, changes the center position to a deeper position in the buffer, and the amount of change is 14. The circuit emulation clock reproduction method according to claim 13, wherein when the storage capacity is smaller than the current center position of the buffer, the center position is changed to a shallow position in the buffer. 15. The circuit emulation clock reproducing method according to claim 13, wherein in the center position changing step, an upper limit of the set center position is set as a center position of the entire buffer. 16. An offset calculating step of statistically calculating an offset value to be set in the buffer based on one or more fluctuation amounts monitored in the data accumulation fluctuation amount monitoring step, wherein the center position 14. The changing step, wherein a lower limit of the center position to be set is set as the offset value.
16. The circuit emulation clock recovery method according to any one of items 15 to 15. 17. The buffer according to claim 1, wherein the buffer is divided into n (n is a natural number), the data storage amount monitoring step monitors the variation amount for each divided area, and the center position changing step includes One of the areas
17. The circuit emulation clock reproducing method according to claim 13, wherein one of the two is set as the center position. 18. When the stored data is larger than the storage capacity up to the center position, control is performed to shorten a cycle of a read clock of data stored in the buffer, and the stored data is stored in the center. 18. A read clock control step of controlling the read clock cycle of data stored in the buffer to be longer when the storage capacity is smaller than the storage capacity up to the position. 3. The circuit emulation clock regeneration method according to 1. 19. A circuit emulation clock recovery method for reading data stored based on a storage capacity up to a center position set in a buffer, wherein a fluctuation amount of data stored in the buffer is periodically monitored. A circuit emulation clock reproducing method, comprising: a data accumulation variation monitoring step; and a storage capacity changing step of changing an accumulation capacity of the buffer based on the variation. 20. The method according to claim 20, further comprising: a center position calculating step of calculating a center position of the buffer corresponding to a storage capacity currently set in the buffer. If the storage capacity is larger than the storage capacity up to the center position of the buffer, the center position is changed to a deep position in the buffer, and if the variation is smaller than the storage capacity of the buffer up to the current center position, the center position is changed to 20. The circuit emulation clock recovery method according to claim 19, wherein the position is changed to a shallow position in the buffer. 21. The circuit emulation clock reproducing method according to claim 19, wherein in the storage capacity changing step, an upper limit of the storage capacity to be set is set to a storage capacity of the entire buffer. 22. An offset calculating step of statistically calculating an offset value to be set in the buffer based on one or more fluctuations monitored in the data accumulation fluctuation monitoring step, and 20. The changing step, wherein a lower limit of the storage capacity to be set is set as the offset value.
22. The circuit emulation clock regeneration method according to any one of claims 21 to 21. 23. The buffer, wherein the buffer is divided into n (n is a natural number), the data storage amount monitoring step monitors the variation amount for each divided area, and the storage capacity changing step includes: One of the areas
23. The circuit emulation clock reproducing method according to claim 19, wherein one of the two is set as an upper end of the storage capacitor. 24. When the stored data is larger than the storage capacity up to the center position, control is performed so as to shorten the cycle of a read clock of data stored in the buffer, and the stored data is stored in the center. 24. The method according to claim 19, further comprising: a read clock control step of controlling a period of a read clock of data stored in the buffer to be longer when the storage capacity to the position is smaller. 3. The circuit emulation clock regeneration method according to 1.