JP2002152034A - Switching circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a switching circuit with a simplified circuit configuration and a downsized mount area that reduces an output trailing time so as to improve the switching speed. SOLUTION: The switching circuit is provided with enhancement MOS FETs 14, 15a that are connected in series between a power supply 11 and a GND 12 and configures a push-pull circuit and with a differentiation circuit including a bipolar transistor(TR) 16 that is provided to a gate side of the MOSFETs and instantaneously pulls in a current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching circuit, and more particularly to a switching circuit which is expected to be applied in various fields as an inverter type logic circuit using an enhancement type MOSFET.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a conventional switching circuit. In this conventional circuit, a switching operation is performed by a push-pull circuit in which two enhancement-type MOSFETs are connected in series between a power supply and GND, and an input pulse of H level (0 V) and L level (-5 V) , And H level (3.
5V) and an L level (0 V) output pulse. In the figure, 21 is a positive power supply (+ 5V), 22 is ground (GND), 23 is a negative power supply (-5V), 24 is a P-channel enhancement type MOSFET, 25a,
25b is an N-channel enhancement type MOSFET,
26a and 26b are resistors, 27 is an input terminal, and 28 is an output terminal.

The two MOSFETs 24 and 25a constitute a push-pull circuit for performing a switching operation.
b is connected in series between the positive power supply 21 and the GND 22. Further, a resistor 2 is connected between the positive power supply 21 and the negative power supply 23.
6a and MOSFET 25b are connected in series,
a is connected to the drain of the MOSFET 25b by the MOSF
Connected to the gates of ETs 24 and 25a. The input terminal 27 is connected to the gate of the MOSFET 25b, and the output terminal 28 is connected to the connection point between the resistor 26b and the drain of the MOSFET 25a. The resistor 26b is used to adjust the H level of the output pulse.
5b sets the gate voltage of the MOSFETs 24 and 25a to H /
This is for converting L = 5V / -5V.

Next, the operation will be described. Input terminal 2
When the input pulse of No. 7 is 0 V, the MOSFET 25b is turned on.
A voltage of 5 V is applied, the MOSFET 24 is turned on, and the MO
The SFET 25a is turned off, and 3.5V is applied to the output terminal 28.
Is obtained. When the input pulse at the input terminal 27 is -5 V, the MOSFET 25b is turned off. Therefore, a voltage of 5 V is applied to the gates of the MOSFETs 24 and 25a, and the MOSFET 24 is turned off.
25a is turned on, and an output pulse of 0 V is obtained at the output terminal 28.

In the circuit shown in FIG. 2, an integrating circuit is formed by the gate capacitances of the two MOSFETs 24 and 25a and the pull-up resistor 26a.
The rise of the gate voltage of 4, 25a is delayed, and as a result, the fall of the output is delayed. Although it depends on the size of the gate capacitance and the resistance of the MOSFET, the rise time is several tens (n).
The fall time for s) can be up to several hundred (ns).

[0006]

Therefore, the conventional switching circuit described above has a problem that the output fall time becomes long due to the influence of the gate capacitance and the pull-up resistance of the MOSFET constituting the push-pull circuit.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to improve the switching speed as compared with the conventional circuit, and to reduce the size, cost, and power consumption. It is an object to provide a switching circuit.

[0008]

According to a first aspect of the present invention, there is provided a switching circuit comprising: a plurality of enhancement type MOSFETs connected in series between a power supply and GND;
And a current drawing means provided on the gate side of the ET to perform an instantaneous current drawing operation.

According to a second aspect of the present invention, in the switching circuit according to the first aspect, the plurality of enhancement type MOSFETs constitute a push-pull circuit.

A switching circuit according to a third aspect of the present invention is the switching circuit according to the first or second aspect, wherein a differentiating circuit is used as the current drawing means.

A switching circuit according to a fourth aspect of the present invention is the switching circuit according to the third aspect, wherein the differentiating circuit is a MOSF.
It includes a bipolar transistor connected to the gate side of ET.

A switching circuit according to a fifth aspect of the present invention is the switching circuit according to the third or fourth aspect of the present invention, wherein the switching circuit is provided on the input side of the differentiating circuit, and limits an instantaneous current drawing operation time to the gate side of the MOSFET. It is provided with limiting means.

According to a sixth aspect of the present invention, in the switching circuit according to the fifth aspect of the present invention, a capacitor is used as the limiting means.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described.
Description will be made based on the drawings. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention. In the figure, 11 is a positive power supply (+5
V), 12 is ground (GND), 13 is a negative power supply (-
5V) and 14 are P-channel enhancement type MOSFs
Reference numerals ET, 15a and 15b denote N-channel enhancement type MOSFETs, and 16 denotes a bipolar transistor. This bipolar transistor 16 is for causing an input side of a subsequent push-pull circuit to perform an instantaneous current drawing operation.

Reference numerals 17a to 17d denote resistors.
c and 17d are emitters of the bipolar transistor 16.
Adjust the base-to-base current. Reference numeral 18 denotes a capacitor as limiting means for limiting an instantaneous current drawing operation time. 19 is an input terminal, and 20 is an output terminal. Note that the bipolar transistor 16 and the resistor 1
7d substantially constitutes a differentiating circuit as current drawing means.

The two MOSFETs 14 and 15a constitute a push-pull circuit for performing a switching operation.
b is connected in series between the positive power supply 11 and the GND 12. A resistor 1 is connected between the positive power supply 11 and the negative power supply 13.
7a and MOSFET 15b are connected in series,
a is connected to the drain of the MOSFET 15b by the MOSF
Connected to the gates of ETs 24 and 25a. The input terminal 19 is connected to the gate of the MOSFET 15b, and the output terminal 20 is connected to the connection point between the resistor 17b and the drain of the MOSFET 15a.

The emitter of the bipolar transistor 16 is connected to the positive power supply 11, and the collector is connected to a resistor 17a.
And the connection point of the drain of the MOSFET 15b,
The base is connected to an input terminal 19 via a resistor 17d and a capacitor 18. The resistor 17c is connected between a connection point of the resistor 17d and the capacitor 18 and the positive power supply 11. Note that the resistor 17b is for adjusting the H level of the output pulse, and lowers the voltage from + 5V to + 3.5V, for example. Further, the MOSFET 15b responds to the input pulse H / L = 0V / -5V by the MOSFET14,
This is for converting the gate voltage of 15b to -5V / + 5V, whereby the push-pull circuit at the subsequent stage can operate.

Next, the operation will be described. Input terminal 1
When the input pulse of No. 9 becomes 0 V, the MOSFET 15b is turned on and the push-pull circuit of the subsequent stage,
The voltage input to the gates of 4, 15a is -5V.
When the input voltage becomes -5 V, the MOSFET 15b is turned off, the bipolar transistor 16 is turned on momentarily, and a current (differential current) flows through the gates of the MOSFETs 14 and 15 momentarily. MOSFET1
MOSFE by pulling into the gate of 4,15a
The gate voltage rise delay time by the integrating circuit constituted by the gate capacitances of T14 and 15a and the pull-up resistor can be reduced, and as a result, the output fall time can be reduced.

Since the differential current pull-in time can be adjusted by the capacity of the capacitor 18, fine adjustment of the output fall time is also possible. In addition, since the push-pull circuit is a circuit configured by MOSFETs, the current consumption is as small as several mA, and the device is driven with low power consumption. Further, the circuit configuration is very simple, and the mounting area can be reduced.

As described above, in this embodiment, the MOSF
A differentiating circuit that performs instantaneous current draw operation is provided on the gate side of the ET, so that the output fall time is shortened and switching speed is increased, and the circuit configuration is simple and the mounting area is small. Further, the cost is low and the power consumption is low.

[0021]

As described above, according to the first aspect of the present invention, a plurality of enhancement-type MOSFETs connected in series between a power supply and GND, and an instantaneous current draw provided on the gate side of the MOSFETs Since it has a current drawing means for performing an operation, it is possible to improve the switching speed by shortening the output fall time, to simplify the circuit configuration, to reduce the mounting area, and to reduce the cost. And power consumption can be reduced.

According to the second aspect of the present invention, since the plurality of enhancement type MOSFETs constitute a push-pull circuit, the circuit configuration can be simplified, the mounting area can be reduced, the cost can be reduced, and the power consumption can be reduced. There is an effect that it can contribute to the conversion.

According to the third aspect of the present invention, since a differentiating circuit is used as the current drawing means, there is an effect that the output fall time can be shortened and the switching speed can be improved.

According to the fourth aspect of the present invention, the differentiating circuit includes a bipolar transistor connected to the gate of the MOSFET, so that the output fall time of the push-pull circuit can be reduced. .

According to the fifth aspect of the present invention, there is provided the limiting means provided on the input side of the differentiating circuit for limiting the instantaneous current drawing operation time to the gate side of the MOSFET. There is an effect that the pull-in time can be adjusted and the output fall time can be finely adjusted.

Furthermore, according to the invention of claim 6, since a capacitor is used as the limiting means, the output fall time can be finely adjusted with a simple circuit configuration, which contributes to an improvement in switching speed. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional switching circuit using an enhancement type MOSFET push-pull circuit.

[Explanation of symbols]

11, 13 power supply, 12 GND, 14 P-channel enhancement type MOSFET, 15 a, 15 b
N-channel enhancement type MOSFE, 16P
NP type bipolar transistor, 17a, 17b, 1
7c, 17d resistor, 18 capacitor.

Claims (6)

[Claims] 1. A semiconductor device comprising: a plurality of enhancement type MOSFETs connected in series between a power supply and a GND; and a current drawing means provided on a gate side of the MOSFET and performing an instantaneous current drawing operation. Switching circuit. 2. The plurality of enhancement type MOSFs
2. The switching circuit according to claim 1, wherein the ET forms a push-pull circuit. 3. The switching circuit according to claim 1, wherein a differentiation circuit is used as the current drawing means. 4. The switching circuit according to claim 3, wherein said differentiating circuit includes a bipolar transistor connected to a gate side of a MOSFET. 5. The switching device according to claim 3, further comprising a limiter provided on an input side of said differentiating circuit, for limiting an instantaneous current drawing operation time to a gate side of said MOSFET. circuit. 6. The switching circuit according to claim 5, wherein a capacitor is used as said limiting means.