JP2002151602A - Semiconductor device, writing and reading method and integrated circuit using the semiconductor device and the method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate irregularity of a realized threshold value in each cell which is generated by irregularity of manufacturing even if writing is performed by using the same gate voltage. SOLUTION: In a semiconductor device of an MIS type structure wherein a gate part has a charge accumulating part sandwiched between insulators, the charge accumulating part is connected with a drain region via a switching element. In a writing method of data which uses the semiconductor device, charges are supplied to the charge accumulating part through an inversion layer formed by applying a gate voltage and further through a diode or the switching element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device for electrically writing data. More specifically, the present invention relates to a floating gate type storage device.

[0002]

2. Description of the Related Art In a normal floating gate type EEPROM or flash memory having a charge storage portion, charges are stored in a charge storage layer called a floating gate, and the threshold value of a memory cell is controlled in accordance with the content of information to be stored. I am trying to do it. For example, JP-A-6-13
As shown in FIG. 11, the substrate 10
1, a normal floating gate type method including a source region 103, a drain region 104, a gate electrode 105, an insulating film 106, a charge storage portion 107, and a gate insulating film 2002 is shown. On the other hand, with respect to multi-value, in JP-A-11-8325, the insulating film is multilayered.

[0003]

However, in the technique disclosed in Japanese Patent Application Laid-Open No. H11-8325, like the ordinary floating gate type memory,
Since charges in a high energy state such as hot electrons are stored in the charge storage portion through the insulating film, even if the same voltage is applied to the control gate, the amount of charge stored in the charge storage portion varies due to manufacturing variations of the insulating film. Therefore, the threshold value after writing also varies. Further, in the case of multi-value, it is necessary to make the insulating film multilayer and thin, and this variation is further increased, and it is difficult to put the multi-value into practical use. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for suppressing threshold variation without requiring a complicated structure or a complicated circuit in a control system. An object of the present invention is to provide the above multi-value storage device.

[0004]

According to the device of the present invention, there is provided [1] a gate portion having a charge storage portion sandwiched between insulators;
In the semiconductor device having the S-type structure, the charge accumulation portion and the drain region are connected via a diode.

[2] A semiconductor device having a MIS structure in which a gate portion has a charge storage portion sandwiched between insulators, wherein the charge storage portion and the drain region are connected via a switching element. .

Hereinafter, the mechanism of the present invention will be described. For example, in a memory device having a structure in which a charge storage portion 107 is inserted into a gate portion of a MOS transistor which is a kind of a semiconductor device having a MIS structure as shown in FIG. Are connected via the switch element 2001 connected to the switch. In the memory device, reference numeral 2002 denotes a gate insulating film;
Is a source region, 104 is a drain region, 105 is a gate electrode, 106 is an insulating film, and 101 is a substrate. Reference numeral 108 denotes an inversion layer, which does not exist when a voltage higher than the threshold is not applied to the gate.

When writing is performed, the switch element is turned on, and the drain region 104 and the charge storage section 107 are electrically connected. Next, when a voltage higher than the threshold is applied to the gate electrode, the inversion layer 108 is formed. Source area 103
Is connected to ground, and the source region 10 is connected to ground.
3, inversion layer 108, drain region 104, switch 20
The electrons are sequentially injected into the charge storage unit 107 through the line 01.

[0008] When electrons are injected, the effective electric field applied under the gate decreases. In other words, the threshold increases. When the charge injection proceeds more than a certain degree, the inversion layer cannot be finally formed. When the inversion layer 108 disappears, the inflow path of electrons from the ground is cut off, so that the injection of electrons into the charge storage unit 107 is also stopped. After the writing, the switch element 2001 is turned off to prevent the charge from leaking from the charge storage unit 107.

In the above example, the description has been made using electrons as charges. However, it is needless to say that holes can be used as charges. When this mechanism is used, since the threshold value after writing is determined by the gate voltage at the time of writing, there is a great advantage that there is no variation in threshold value.

[3] In a writing method of a semiconductor device having a MIS structure in which a gate portion has a charge storage portion sandwiched between insulators, the gate portion passes through an inversion layer formed by applying a gate voltage, and further flows from the drain to the charge storage portion. Is supplied with electric charges. Therefore, for the same reasons as above,
The threshold variation after writing does not occur due to the manufacturing variation of the film formation or the like, and the threshold value after writing can be precisely aligned even if the manufacturing variation of the film formation occurs.

[4] A method for writing data using the semiconductor device according to claim 3, wherein the step of making the drain and the charge storage section conductive is a step of applying a gate voltage to form an inversion layer. The method is characterized in that the method includes a step of disconnecting the drain from the charge storage unit and a step of stopping the application of the gate voltage. Therefore, for the same reason as described above, there is no threshold variation after writing due to manufacturing variations in film formation and the like, and even after manufacturing variations in film formation, the thresholds after writing can be aligned with high accuracy.

[5] Multi-level recording is performed by a combination of a gate voltage and a substrate bias. Therefore, the threshold value can be changed by the substrate bias effect and the threshold value can be lowered, so that an inversion layer is formed even at a sufficiently low gate voltage, and writing with a low gate voltage is performed in a device that performs writing through the inversion layer. Is possible, and the power consumption is excellent.

[6] Multi-value recorded data is read by changing the combination of the gate voltage and the substrate bias. If the data writing method and the reading method are used, for example, by changing the substrate bias so that the threshold value is lowered at the time of reading, it is possible to set the gate voltage to be applied at the time of reading low, and the risk of erroneous writing occurring Performance can be reduced, non-destructive reading is possible, and reliability and low power consumption are improved.

[7] A writing method using a semiconductor device, wherein a step of applying a gate voltage or a substrate bias or a combination of a gate voltage and a substrate bias to be applied in accordance with write data, and detecting a channel current Using a data write confirmation method including the step of determining a threshold value, and further applying a write gate voltage when it is determined that writing is insufficient, and Comprises the step of completing a series of operations. By using the writing method, it is possible to simultaneously check whether or not writing has been performed and rewrite when writing is insufficient, eliminating the need to repeat the checking operation and the writing operation for correction, and reducing the number of operations. Power consumption can be reduced.

[8] The present invention is an integrated circuit using the semiconductor device according to claim 1 or 2 as a memory element.

[9] The present invention is an integrated circuit using the semiconductor device according to claim 1 or 2 as a transistor of a logic section.

[10] The present invention is an integrated circuit characterized in that connection between circuits is performed by using the device according to claim 1 or 2.

According to the present invention, by using a reconfigurable logic circuit, it is possible to improve the processing speed and the power consumption by configuring a circuit suitable for the intended use. Therefore,
In addition to being able to function as a conventional logic unit, by setting a threshold value as needed, it can be set to an always-off state or an always-on state. According to the present invention, it is possible to separate or combine circuits at arbitrary positions, and it is possible to configure an extremely flexible circuit, and not only as a conventional element for simply connecting between circuit blocks, but also for example, Since the transistor operates as a transistor for performing calculations, the efficiency is high. In addition, since the threshold can be set accurately, various circuits can be formed by setting different thresholds depending on the transistors.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. [Embodiment 1] FIG. 2 schematically shows one configuration of a first embodiment of the present invention in which a diode is used. 2 (a) is a plan view, FIG. 2 (b) is a sectional view taken along the line AA in FIG. 2 (a), and FIG. 2 (c) is a sectional view taken along the line BB in FIG. 2 (a). It is sectional drawing. Reference numeral 2110 in FIGS. 2B and 2C denotes an interlayer insulator, which is not shown in FIG.

The feature of the present embodiment is that a drain plug 104 is connected to the drain plug 104 of FIG.
That is, a diode contact 2109 is provided via the contact 119. For example, a diode in which an N-type semiconductor and a P-type semiconductor are joined is formed. Further, the diode contact 2109 is connected to the charge storage unit 107 via a wiring (not shown) and the charge storage unit contact 2107. In the device of the present embodiment, the charge easily flows into the charge storage unit 107 through the diode,
The electric charge once accumulated in the electric charge accumulating unit 107 is hard to be released, and is excellent in memory retention characteristics.

When a diode is used as described above, a power supply for operating the diode is not required, and no wiring is required. Therefore, fabrication is easy, which is advantageous for miniaturization. FIG. 2 is a diagram for explanation, and does not limit the present invention. For example, as shown in FIG. 3, the diode plug 2119 is directly connected to the charge storage unit 107 without using the wiring connecting the charge storage unit contact 2107, the diode contact 2109, and the wiring connecting the charge storage unit contact 2107 and the diode contact 2109. Can be eliminated and the size can be reduced.

Next, the write operation will be described with reference to FIGS. For example, assume that the threshold value when no charge is stored in the charge storage unit 107, that is, the gate voltage at which the inversion layer is formed is 2V. At the time of writing, 0
When V is applied and 5 V is applied to the gate electrode 105, the inversion layer 108 is formed. Charge is supplied from the source region 103, and the inversion layer 108, the drain region 104, the diode plug 2119, the diode contact 2109,
The charge is injected into the charge storage unit 107 through a wiring (not shown) and a charge storage unit contact 2107. As the injection proceeds, the threshold rises and finally reaches 5V. Since the gate voltage is 5 V, the inversion layer disappears at this point. Therefore, the charge supply path from the source region 103 to the drain region 104 is lost, and the injection into the charge storage unit 107 stops. That is, the threshold value after writing is 5 V, and all cells written with a gate voltage of 5 V are aligned with 5 V.

As described above, the threshold value after writing is determined by the gate voltage at the time of writing, and is independent of film formation variation.
Threshold variation can be suppressed with a simple structure. When erasing, that is, writing data “0”, a high voltage at which a reverse current flows through the diode, for example, 0 V is applied to the gate electrode and 10 V is applied to the drain region 104, and the charge is extracted from the charge storage unit 107. The application of the gate voltage may be stopped when the value of the current flowing through the channel of the storage device becomes equal to or less than a specified value.

The specified value is basically equal to the off-current value. However, by setting the specified value large within an allowable range, the write operation can be ended quickly. Therefore, if the operation speed is prioritized, the predetermined current value is increased, and if the threshold value after writing is more accurately aligned, the specified value may be closer to the off-current value.

In addition, for example, when speed is prioritized, for example, frequent rewriting, and when priority is given to low power consumption by multi-value or low voltage, such as by increasing the amount of information that can be stored, depending on the case or usage. The method of changing the setting of the specified value is also effective.

For example, when the speed is further increased, the charge injection into the charge storage layer occurs rapidly immediately after the formation of the inversion layer, and almost no charge injection into the charge storage layer occurs immediately before the disappearance of the inversion layer. By taking advantage of this fact, a method of finishing writing before the inversion layer completely disappears is adopted. Even when this method is used, the upper limit of the charge injection is defined by the write gate voltage as compared with the conventional method, so that the threshold variation is small. The possibility of insufficient charge injection can be solved by setting the lower limit of the threshold for the write state sufficiently low or by using a more desirable write method described later.

If the upper and lower limits of the channel current value at which writing is completed are determined, the threshold value is determined from the current value, so that the range of the threshold value can be determined without fail. Therefore, if a channel current value at which writing is completed is determined, a high voltage is applied at the time of writing to perform high-speed writing. Since the threshold value after writing corresponds to the channel current value, the threshold values after writing are the same. More preferably,
A writing method is used while checking write data.

That is, a read operation is performed on the written cell to determine whether the channel current is less than or equal to a specified value. If the channel current is equal to or more than the specified value, the writing operation is performed again. The above confirmation steps are repeated until the channel current becomes less than the specified value. Here, the specified value is a value for judging whether the channel is in the on state or the off state, and is a value close to zero, but more specifically, a value close to the channel current value when a threshold voltage is added. desirable.

The following method is also effective in the storage device of the present invention. That is, if a read operation is performed in the write confirmation step, the channel current of the insufficiently written cell becomes equal to or more than the specified value, and carriers are injected into the charge storage layer of the cell. That is, the same phenomenon as the write operation occurs. Therefore, if the read operation is continued until the channel current becomes less than the specified value to perform the write confirmation step, the repetitive operation becomes unnecessary, which is desirable.

Since the checking operation and the rewriting operation are performed at the same time, the processing speed can be increased. There is no need to repeat the confirmation operation and the write operation for correction,
The number of operations can be reduced, and power consumption can be reduced.

An example will be described below. For example, source and drain voltages during a read operation and a gate voltage during a write operation are added. If the writing has already been sufficiently performed, the threshold value is higher than the applied gate voltage and the inversion layer is not formed, so that the channel is off. On the other hand, if writing is insufficient, the threshold value is equal to or lower than the applied gate voltage, an inversion layer is formed, the channel is turned on, a channel current of a specified value or more flows, and carriers are injected into the charge storage layer. If the gate voltage is continuously applied, the injection of carriers into the charge storage layer proceeds, and the threshold gradually increases. When the threshold reaches the applied gate voltage, the inversion layer disappears and the channel is turned off, so that the channel current value becomes equal to or less than the specified value. Therefore, by detecting the channel current value and continuing to apply the source and drain voltages during the read operation and the gate voltage during the write operation until the channel current value becomes equal to or less than the specified value, it is possible to confirm whether or not the write operation has been completed and to re-execute when the write operation is insufficient. Writing can be performed simultaneously.

Next, the read operation will be described. First, to set the gate voltage V _r for reading the data from the memory cell. In this embodiment mode, the threshold voltage of a cell to which writing is not performed is about 2 V, and the threshold of a cell to which writing is performed is about 5 V. Next, apply a 3V as the gate voltage V _r. Next, a drain current flowing between the source region 103 and the drain region 104 under an appropriate drain voltage is detected by a sense amplifier or the like, and it is determined whether or not the threshold value is 3 V or more. When a current equal to or greater than the specified value does not flow through the channel region, the threshold value is 3 V or more, and it is determined that the memory cell is being written. Conversely, when a current equal to or more than the specified value flows, the threshold value is less than 3 V, and it is determined that the memory cell has not been written.

When a diode is used, the voltage applied to the drain region 104 retains the charge stored in the charge storage unit 107 unless junction breakdown of the diode occurs.

[Embodiment 2] FIG. 4 schematically shows one configuration of an embodiment of the present invention in which a switching element is used. In this embodiment mode, a transistor is used as a switching element. 4 (a) is a plan view, FIG. 4 (b) is a sectional view taken along the line AA in FIG. 4 (a), and FIG. 4 (c) is a sectional view taken along the line BB in FIG. 4 (a). It is sectional drawing. Reference numeral 2110 in FIGS. 4B and 4C denotes an interlayer insulator, which is not shown in FIG. 4A.

A feature of this embodiment is that a transistor 2302 is connected to the drain region 104 in FIG. For example, the drain region 104 is shared as the source region of the transistor 2302,
302 having a drain region 2304 (ie, 2
304 is a drain region of the transistor 2302). Further, the drain region 2304 includes a drain contact 2314, a wiring (not shown) and a charge storage portion contact 2
It is connected to the charge storage unit 107 via 107. In the device of this embodiment mode, since the transistor 2302 is turned on, the charge easily flows into the charge storage portion 107 because the transistor 2302 is connected.
By making the state 302 non-conductive, the electric charge once accumulated in the electric charge accumulating unit 107 is hard to be released, and is excellent in memory retention characteristics. In the present embodiment, MO is used as the switching element.
Although an example of an S-type transistor has been described, it is apparent that the present invention is not limited to this.

When a switching element is used, it is easy to select a writing cell and a non-writing cell by turning the switching element on and off, and a high voltage is applied to the gate electrode and the drain region by mistake. Even if the holding state is maintained, the convenience and reliability are excellent.

Next, the write operation will be described. For example, a threshold value when no charge is stored in the charge storage unit 107,
That is, the gate voltage at which the inversion layer is formed is 2V. At the time of writing, if 0 V is applied to the source region 103 and 5 V is applied to the gate electrode 105, the inversion layer 108 is formed. Further, when the transistor 2302 is turned on, charge is supplied from the source region 103 and the inversion layer 108,
Drain region 104, channel region of transistor 2302, drain region 2304, drain contact 23
14. Wiring not shown, contact 2107 for charge storage portion
And is injected into the charge storage unit 107. As the injection proceeds, the threshold rises and finally reaches 5V. Gate voltage is 5
Since it is V, the inversion layer disappears at this point. Therefore, the charge supply path from the source region 103 to the drain region 104 is lost, and the injection into the charge storage unit 107 stops.
That is, the threshold value after writing is 5 V, and the gate voltage is 5 V
All the cells written in are aligned at 5V. Next, the transistor 2302 is turned off.

Thus, even if the application of the gate voltage is stopped, the electrons stored in the charge storage unit 107 are retained.

Next, the application of the gate voltage is stopped. In this way, the threshold value after writing is determined by the gate voltage at the time of writing, and the variation in threshold value can be suppressed with a simple structure regardless of the film formation variation. In the case of erasing, that is, writing data “0”, a voltage that generates an electric field in a direction of extracting charges from the charge storage unit 107, for example, a gate voltage of 0 V and a voltage of 5 V to the drain region 104 is applied to turn on the transistor, The charge is extracted from the storage unit 107. When a transistor is used, there is an advantage that a voltage required for erasing may be low. More preferably, a method of writing while confirming write data is used as in the first embodiment. However, in the case of this embodiment, an operation of turning on the switching element when a gate voltage is applied and an operation of turning off the switching element after writing is correctly determined are added.
The reading method is the same as the method using a diode. Since the switching element is used, it is preferable to keep the switching element in a non-conductive state, since the electric charge accumulated in the electric charge accumulating unit 107 is retained. Further, since a switching element is used, selection of a write cell and a non-write cell and selection of a read cell and a non-read cell are easy. FIG. 4 is a diagram for explanation, and does not limit the present invention.

As will be described in detail below, the memory cell manufactured according to the present invention can reduce the variation in the threshold value after writing, and can easily reduce the voltage and increase the number of levels. . In other words, the injection is stopped by utilizing the fact that the inversion layer disappears as the charges are injected into the charge storage portion. Therefore, if the gate voltage at the time of the injection is set to V _g , the threshold value after the injection, that is, after the writing, is accurate. _Vg . Therefore, an operation margin for threshold variation can be reduced. The threshold value at the time of data storage can be accurately aligned with the write voltage at the time of data writing, and the reliability is extremely high regardless of manufacturing variations. Further, since the write voltage can be finely changed, a multi-level memory device with a low voltage can be realized.

[Third Embodiment] As a semiconductor device, the same device as that of the first embodiment can be used for multi-value recording. One embodiment of the multi-value recording method will be described. Multi-value recording is performed by changing the gate voltage applied according to (the value of) the write data.

Therefore, even if the number of values increases, the problem can be solved by increasing the gate voltage. When performing multi-value conversion,
This can be realized by setting the gate voltage applied according to (the value of) the write data to an appropriate value. In particular, according to the present invention, the variation of the threshold value at the time of writing can be made extremely small, so that the step of multi-leveling can be reduced (the writing voltage can be finely changed). Can be realized.

First, a multilevel recording method according to the present invention using the diode of the first embodiment will be described. First, consider the case where nothing has been written. The threshold at this time is V _th
And

Next, when writing "1" as data,
In this case, the source region 103 is set to the ground potential. Gate electrode 1
05 is V_thSet the appropriate values above and set an example
For example, V _w1Is applied. At this time, under the gate insulating film 102,
Is formed with an inversion layer 108 and supplied with electric charge. Katsuda
Iodine is transferred from the drain region 104 to the charge storage portion 107.
The direction of injecting charge into the
Charge passing through, the inversion layer 108 and
Charge passes through the diode through the drain region 104
Then, the charge is injected into the charge storage unit 107 and stored.

As charges are stored in the charge storage section 107, the effective voltage applied to the gate insulating film 102 decreases.
In other words, the threshold increases. When the threshold reaches V _w1 , the inversion layer 108 disappears, so that no charge is supplied to the drain region 104. Therefore, there is almost no charge that can be injected into the charge storage unit 107 via the diode, and the injection of the charge into the charge storage unit 107 stops. This means that data "1" is stored in the memory cell. Thereafter, even if the application of the voltage is stopped, the charge does not flow out of the charge storage unit 107 by the diode.

Similarly, when writing data "2", the source region 103 is set to the ground potential. For example, V _w2 is applied to the gate electrode 105. Here, it is also assumed that V _w2 > V _w1 . At this time, an inversion layer 108 is formed below the gate insulating film 102, and a charge is similarly supplied. In any case, similarly, the injection of charges into the charge storage unit 107 stops. This means that data "2" has been stored in the memory cell.

Next, one embodiment of the multilevel recording method according to the present invention using a switching element, for example, a transistor, will be described. This is almost the same as the method using a diode, except that the operation of turning on the transistor is performed after the gate voltage is applied. Since the transistor is turned on, electric charge passes through the transistor through the inversion layer 108 and the drain region 104, is injected into the electric charge accumulating portion 107, and is accumulated.

After the data "1" is stored in the memory cell, the transistor is turned off to turn off the transistor. Thereafter, the application of the write voltage is stopped. The same applies to the case of writing data “2”.

Next, a method of reading multi-value recorded data will be described. In this embodiment, the threshold distribution characteristics are as shown in FIG. The threshold value of a cell to which data has not been written, that is, a cell storing data “0” is V _w0.
And

Similarly, it is assumed that the threshold value of the cell storing the data “1” is V _w1 . First, the read voltage _{Vr is set} to V
_w0 is set to a value that satisfies the <V _r «V _w1. Next, _Vr is applied to the gate. At this time, an appropriate voltage is applied between the source region 103 and the drain region 104. The appropriate voltage is a normally used voltage that does not cause undesired phenomena as an element such as junction breakdown.

Next, the source region 103 and the drain region 1
A current flowing through the channel region between the current detecting circuit and the current detecting circuit is detected by a sense amplifier or the like. When a sufficient current equal to or more than the specified value flows in the channel region, it is determined that the storage state of the memory cell is storing data “0”. Conversely, if a current equal to or greater than the specified value does not flow through the channel region, it is determined that data “1” or “2” is stored in the memory cell, and the process proceeds to the next step. It is assumed that the threshold value of the cell storing the data “2” is V _w2 . Read voltage _Vr2 to V
_w1 <is set to a value that satisfies the V _r2 «V _{w2. Apply Vr2} . At this time, the source region 103 and the drain region 104
, An appropriate voltage, for example, 0.5 V is applied here.

Next, the source region 103 and the drain region 1
04 is detected by a sense amplifier or the like. If a current equal to or greater than the specified value flows through the channel region, it is determined that the storage state of the memory cell is storing data “1”. Conversely, if a current equal to or greater than the specified value does not flow through the channel region, data "2" is stored in the memory cell.
Is determined to be stored. According to the present invention, writing and reading of multilevel data can be performed. In the present embodiment, the case of three values has been described, but the case of four or more values can be realized by the same method.

[Embodiment 4] Next, an embodiment of the present invention which uses a substrate bias will be described with reference to FIG. 6 as an example of a method of reading multi-value recorded data. In this embodiment, the threshold distribution characteristics are as shown in FIG. The threshold voltage decreases when a bias is applied to the substrate due to the substrate bias effect. Here MO
Inversion threshold voltage V _th (hereinafter, “threshold”) of an S-type transistor
May be abbreviated. ) And the substrate bias _Vb can be expressed by a simplified equation, which is expressed by the following equation (1). V _th = 2Φ _b + V _FB + (2qN _SW ε _S (2Φ _b −V _b )) ^1/2 / C _OX (1)

Where Φb is the Fermi potential, N
_SW is the impurity concentration in the shallow well region, εS is the dielectric constant of the shallow well region, q is the amount of electron charge, C _OX is the gate insulating film capacitance per unit area, and V _FB is the flat band voltage. When the shallow well region is biased in the forward direction, the absolute value of the threshold voltage decreases as shown in the above equation (1).

In this embodiment, the value of the substrate bias is V
_br1 . The decrease of the threshold value ΔV _t1 due to V _br1 is approximately ΔV _t1 = (2qN _SW ε _S V _br1 ) ^1/2 / C _OX (2) from the equation (1). The threshold value of a cell to which data has not been written, that is, a cell storing data “0” is V _th0 when there is no substrate bias, and the threshold V _tr1 when the substrate bias V _br1 is applied is approximately V _tr1 = V _th0 + △ V _t1 = 2Φ _b + V _FB + (2qN _SW ε _S ) ^1/2 (2Φ _b ) ^1/2 − (V _br1 ) ^1/2 ) / C _OX (3) Similarly when there is no threshold bias of cells storing data "1", "threshold V _wr1 approximately V _wr1 = V when the substrate bias V _br1 is applied as _w1 'V _w1 + △ V _t1 (4)

[0056] First of all, S101 a read voltage V _r in V
_tr1 <set so as to satisfy the V _r <V _wr1. Next, S1
Applying a substrate bias V _br1 02, applying a V _r at S103. At this time, the source region 103 and the drain region 10
4 and an appropriate voltage is applied in advance. Also, S102
And S103 may be performed simultaneously.

In the next step S104, the source region 1
The current flowing through the channel region between the drain region 03 and the drain region 104 is detected by a sense amplifier or the like. If a current equal to or more than the specified value flows in the channel region, it is determined that the storage state of the memory cell is storing data "0" (S1).
05). Conversely, if no current equal to or greater than the specified value flows in the channel region, it is determined that data “1” or “2” is stored in the memory cell (S106), and the process proceeds to the next step.

In the next step S107, a substrate bias _Vbr2 is applied. The decrease in threshold value due to V _br2 △ V _t2 is (1)
Roughly a _{V t2 = V FB + (2qN} SW ε S V br2) 1/2 / C OX ... (5) from the equation. The threshold value of the cell storing the data “1” is V ′ _w1 when there is no substrate bias.
The threshold value V _w1r2 when _br2 is applied is approximately V _w1r2 = V ′ _w1 + △ V _t2 (6).

[0059] Similarly data threshold store that cell "2" when there is no substrate bias, the threshold V _W2r2 an approximate _V w2r2 = V when the substrate bias V _br2 because it is V _'w2 is applied ' _w2 + △ V _t2 (7) The read voltage V _r2 is set to a value that satisfies V _w1r2 <V _r2 <V _w2r2 . V _r2 can be set so that V _r2 = V _r . In step S107, the substrate bias V
applying a _br2, applying a V _r2 at step S108. At this time, an appropriate voltage is applied between the source region 103 and the drain region 104.

In the next step S109, the source region 1
A drain current flowing between the drain region 03 and the drain region 104 is detected by a sense amplifier or the like. When a current equal to or greater than the specified value flows in the channel region, the storage state of the memory cell is
It is determined that data “1” is stored. Conversely, when a current equal to or greater than the specified value does not flow through the channel region, it is determined that data “2” is stored in the memory cell.

According to this method, as compared with the case where no substrate bias is applied, a high gate voltage is not required and reading can be performed with a low gate voltage, and the risk of erroneous writing can be reduced. , Reliability and low power consumption are improved. Furthermore, even in a cell having a common word line, that is, a gate electrode connected to the same wiring, and a gate voltage cannot be applied separately, if a substrate bias can be applied separately, reading can be performed collectively and the speed can be increased. Although the reading method has been described as an example, a method of applying a substrate bias can also be used in the writing method, and for example, writing can be performed with a low gate voltage.

Further, a substrate bias can be used as shown in FIG. 7 by the same method as the writing method in the first embodiment. That is, a read operation is performed on the written cell under a substrate bias for confirmation, and it is determined whether the channel current is less than or equal to a specified value. When a switching element is used, a step of bringing the switching element into a conductive state between steps S153 and S154 and a step of putting the switching element into a non-conductive state after S155 are added. The read operation is continued until the channel current becomes less than the specified value. More specifically, during the normal read operation, the one that prevented writing to the charge storage layer is replaced by, for example, setting the substrate bias to the same bias as that during the write operation. Set so that writing to the storage layer is executed.

For example, a source / drain voltage during a read operation and a gate voltage and a substrate voltage during a write operation are applied. If the writing has already been sufficiently performed, the threshold value is higher than the applied gate voltage and the inversion layer is not formed, so that the channel is off. On the other hand, if writing is insufficient, the threshold value is equal to or lower than the applied gate voltage, an inversion layer is formed, the channel is turned on, a channel current of a specified value or more flows, and carriers are injected into the charge storage layer. If the gate voltage is continuously applied, the injection of carriers into the charge storage layer proceeds, and the threshold gradually increases.
When the threshold reaches the applied gate voltage, the inversion layer disappears and the channel is turned off, so that the channel current value becomes equal to or less than the specified value. Therefore, by observing the channel current value and continuing to add the source and drain voltages during the read operation and the gate voltage and the substrate voltage during the write operation until the value becomes equal to or less than the specified value, it is possible to confirm whether the write operation has been performed and to determine whether the write operation is insufficient. And rewriting can be performed simultaneously.

[Embodiment 5] Any of the apparatuses according to the present invention,
One embodiment in which a circuit configuration is performed using a method will be described using several devices for easy understanding. With the device of the present invention, it is not only a mere storage device,
For example, two types of circuits may be incorporated, and the circuits may be separated electrically using the device of the present invention as necessary.
Or reconnect. As a result, only a necessary part can be used from a plurality of circuits only when necessary. Further, by adjusting the threshold value, the circuit configuration can be arbitrarily changed. To describe the simplest example, for example, as shown in FIG. 8, one ordinary transistor 801 and a storage device 80 of the present invention are used.
2, 803 are connected. Here, writing is performed by an input unit (not shown) as a storage device to the apparatus of the present invention. Since writing is nothing other than changing the threshold, for example, if 802 is equal to the threshold in the reading state and 801 is lowered and the threshold is lowered to be always open, it is equivalent to two parallel circuits of the transistor 801. Become.
This time, if the threshold value of 802 is raised to make it normally closed and the threshold value of 803 in the read state is made the same as 801, it is equivalent to a two-series circuit of the transistor 801.

As described above, according to the storage device of the present invention, it can be applied not only to connection switching between circuits but also to a transistor of a logic circuit. Therefore, it functions not only as a switch between circuits such as a conventional reprogrammable circuit, for example, an FPGA, but also as a transistor forming a logic circuit or as a memory forming a storage circuit.

Another simple example of the device according to the present invention will be described with reference to FIG. As shown in FIG. 9, two devices according to the present invention 8
11 and 812 and two resistors 813 and 814 constitute a circuit. The writing means (not shown in FIG. 9)
11 and 812 are written, and the threshold _values at the time of reading are set to V _th1 and V _th2 , respectively. This circuit may convert the signal V _in the signal I _out. Furthermore, V _th1 and V
By changing the set value of _th2 , FIG.
An output like 0 (b) can be obtained. Thus, various signal conversions can be easily performed. In the present embodiment, an example in which several elements are used for explanation is described, but it is apparent that the present invention can be applied to a large-scale integrated circuit.

Further, the function as a transistor and the function as a memory can be selectively used as needed. One of the simplest examples is a circuit having functions of both a logic circuit and a storage circuit. For example, when the device according to the present invention is operated by the transistor function, the wiring necessary to function as a logic circuit as a whole, and when the device according to the present invention is operated by the memory function, it is necessary to function as a storage circuit as a whole. And two wirings are provided. This circuit functions as a logic circuit or a storage circuit as needed. For example, in a system incorporating a circuit according to the present invention, when the memory capacity of the system is insufficient, the memory capacity shortage can be solved by causing the circuit according to the present invention to function as a storage circuit. If your system has enough memory,
By functioning as a logic circuit, processing capability can be improved. In particular, the circuit of the present invention is effective for a system requiring a small scale and low power consumption such as a portable terminal. Needless to say, it is desirable to share wiring necessary for functioning as a logic circuit and wiring necessary for functioning as a storage circuit as much as possible, because it is possible to reduce the size.

The device according to the present invention does not require power once the circuit is reconfigured, and is more economical than using a conventional transistor. Further, in some cases, by utilizing the fact that a substrate bias can be applied, the threshold can be changed by the substrate bias effect, and the circuit can be reconfigured at high speed by omitting the write operation. This is advantageous when the reconfiguration operation is performed many times in a short time.

The element used in the circuit of the present invention may be any element that uses a change in threshold value. For example, when the threshold value is changed by the substrate bias effect or the like, it is necessary to continuously apply a substrate bias. The use of a non-volatile memory having a variable power consumption is more excellent in low power consumption. Further, as a nonvolatile memory whose threshold value changes, for example, MNOS
Although a type memory or a flash memory can be used, the use of the threshold self-alignment device according to the present invention makes it easier to control the threshold, lower the voltage, lower the power consumption, and the manufacturing process when incorporating it into a conventional logic circuit. Excellent easiness.

As described above, in addition to being able to function as a conventional logic unit, by setting a threshold value as needed, it is possible to always turn off or always on. According to the present invention, it is possible to separate or combine circuits at arbitrary locations, and it is possible to configure an extremely flexible circuit, and not only as a conventional element for simply connecting between circuit blocks, but also For example, the transistor operates as a transistor for performing calculations, so that efficiency is high. In addition, since the threshold can be set accurately, various circuits can be formed by setting different thresholds depending on the transistors.

Thus, any of the devices, methods,
By performing a circuit configuration using a recording medium and using a reconfigurable logic circuit according to the present invention, a circuit suitable for a purpose of use can be configured, thereby improving processing speed and power consumption. In this embodiment, the semiconductor device has been described. However, it is needless to say that the present invention is applicable not only to a semiconductor device but also to a field-effect element that controls a current with another gate voltage.

[0072]

The device according to the present invention has a simple structure, and can accurately align the threshold value at the time of data storage with the write voltage at the time of data write. Can be finely changed, so that a low-voltage, multi-value level storage device can be realized.

A charge storage unit according to the present invention, and stores data in accordance with the amount of charge stored in the charge storage unit;
Further, in the storage device having a mechanism in which the charge is supplied from the charge supply unit to the charge storage unit through the inversion layer formed by the electric field when the charge is supplied to the charge storage unit, as the charge is stored in the charge storage unit, A constant electric field continues to be generated until the inversion layer disappears due to the relaxation of the electric field. Alternatively, if a data writing method is used such that a constant electric field is continuously generated until the channel current value reaches a certain value, the threshold after writing is determined by the initially generated constant electric field and the conventional method is used. Compared with the applied voltage, applied time, and threshold variation due to manufacturing variation of the cell when used, the threshold can be controlled very accurately, and the reliability is improved.

Further, by using the write / read method according to the present invention, multi-level data can be written / read. If a method of changing the value of the substrate bias is used, writing can be prevented from being performed at the time of reading, and a writing cell and a reading cell can be selected.

According to the present invention, it is possible to suppress the threshold variation in a self-aligned manner without requiring a complicated circuit system, and it is possible to realize a storage device having a very high degree of integration on a small chip. Further, the present invention is applicable not only to a memory device but also to a very wide variety of semiconductor devices having a MOS type or a similar structure as means for suppressing variation in threshold value. Further, since the threshold value can be set variously, it can be used as various kinds of transistors, and a variable circuit that can be recombined can be constructed.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining a writing mechanism according to the present invention.

FIG. 2 is a schematic diagram for explaining a first embodiment according to the present invention.

FIG. 3 is a schematic diagram for explaining a first embodiment according to the present invention.

FIG. 4 is a schematic diagram for explaining a second embodiment according to the present invention.

FIG. 5 is a schematic diagram for explaining a reading method according to the present invention.

FIG. 6 is a flowchart illustrating an example of a reading method according to the present invention.

FIG. 7 is a flowchart illustrating an example of a writing method according to the present invention.

FIG. 8 is a circuit diagram illustrating an example of a circuit according to the present invention.

FIG. 9 is a circuit diagram for explaining an example of a circuit according to the present invention.

FIG. 10 is a graph illustrating an example of a circuit according to the present invention.

FIG. 11 is a schematic view showing an example of a conventional semiconductor memory device. .

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 ... Substrate 2002 ... Gate insulating film 103 ... Source region 104, 2304 ... Drain region 105 ... Gate electrode 106 ... Insulating film 107 ... Charge accumulation part 108 ... Inversion layer 801, 2302 ... Transistors 802, 803, 811, 812 ... The present invention 813, 814 ... resistor 2001 ... switch element 2103 ... source contact 2104, 2314 ... drain contact 2105, 2312 ... gate contact 2107 ... charge storage contact 2109 ... diode contact 2110 ... interlayer insulator 2119 ... diode plug

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/788 H01L 29/78 371 29/792 (72) Inventor Hiroshi Iwata 22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka No. 22 F-term in Sharp Corporation (reference) 5B025 AA03 AB01 AC02 AD04 AD05 AD09 AD12 AE08 5F001 AA02 AB02 AF20 5F083 EP02 EP22 GA01 GA05 GA09 NA08 ZA21 5F101 BA02 BB02 BF05

Claims (10)

[Claims] 1. A semiconductor device having an MIS structure in which a gate portion has a charge storage portion sandwiched between insulators, wherein the charge storage portion and a drain region are connected via a diode. . 2. A semiconductor device having an MIS structure in which a gate portion has a charge storage portion sandwiched between insulators, wherein the charge storage portion and the drain region are connected via a switching element. apparatus. 3. A writing method for a semiconductor device having a MIS structure in which a gate portion has a charge storage portion sandwiched between insulators, wherein the gate portion passes through an inversion layer formed by applying a gate voltage, and further from the drain to the charge storage portion. A writing method characterized by supplying electric charge. 4. A method of writing data using a semiconductor device according to claim 3, wherein the step of making the drain and the charge storage portion conductive is the step of applying a gate voltage to form an inversion layer. And a step of stopping the application of the gate voltage. 5. A writing method, wherein multi-level recording is performed by a combination of a gate voltage and a substrate bias. 6. A method for reading multi-value recorded data by a combination of a gate voltage and a substrate bias. 7. A writing method using a semiconductor device, the method comprising: applying a gate voltage or a substrate bias or a combination of a gate voltage and a substrate bias to be applied in accordance with write data; A step of continuously applying a write gate voltage if it is determined that writing is insufficient, and a series of steps if it is determined that writing is sufficient. Completing the operation. 8. An integrated circuit using the semiconductor device according to claim 1 as a memory element. 9. An integrated circuit, wherein the semiconductor device according to claim 1 is used as a transistor in a logic unit. 10. An integrated circuit, wherein connection between circuits is performed by using the device according to claim 1. Description: