JP2002151353A - Dielectric thin film, manufacturing method therefor, and temperature-compensating capacitor - Google Patents

Dielectric thin film, manufacturing method therefor, and temperature-compensating capacitor

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Publication number
JP2002151353A
JP2002151353A JP2000347988A JP2000347988A JP2002151353A JP 2002151353 A JP2002151353 A JP 2002151353A JP 2000347988 A JP2000347988 A JP 2000347988A JP 2000347988 A JP2000347988 A JP 2000347988A JP 2002151353 A JP2002151353 A JP 2002151353A
Authority
JP
Japan
Prior art keywords
thin film
temperature
film
dielectric thin
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000347988A
Other languages
Japanese (ja)
Inventor
Yoshiomi Tsuji
義臣 辻
Makoto Sasaki
真 佐々木
Hitoshi Kitagawa
均 北川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP2000347988A priority Critical patent/JP2002151353A/en
Publication of JP2002151353A publication Critical patent/JP2002151353A/en
Withdrawn legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Inorganic Insulating Materials (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a temperature-compensating capacitor, in which the capacity temperature coefficient has negative sign and an absolute value of the order of 100 ppm/K. SOLUTION: A temperature-compensating capacitor 1 of the present invention includes a silicon hydride oxidation film composed of a silicon atom, an oxidation atom, and a hydrogen atom between a lower electrode layer 3 and an upper electrode layer 5, and a dielectric thin film 4, having a negative capacity temperature coefficient, is interposed therebetween. The silicon oxidation hydride film has an Si-OH bond, and the ratio of hydrogen atoms contained in the film is set at 0.5 to 7 atomic percent.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、誘電体薄膜及びそ
の製造方法並びに温度補償用コンデンサに関し、特に共
振回路等の電気回路内の温度補償用コンデンサに用いて
好適な誘電体薄膜に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric thin film, a method for manufacturing the same, and a capacitor for temperature compensation, and more particularly to a dielectric thin film suitable for use as a capacitor for temperature compensation in an electric circuit such as a resonance circuit. .

【0002】[0002]

【従来の技術】薄膜コンデンサは、一般に基板上に薄膜
状の下部電極層、誘電体層、上部電極層を順次積層した
構造であり、場合によっては下部電極層としての機能を
有する半導体基板の上に誘電体層と上部電極層とを積層
した構造を採ることもある。この種の薄膜コンデンサに
おいては、誘電体層の比誘電率が大きく、0を中心とし
て正または負の任意の温度係数を有するように設計され
る。薄膜コンデンサはこれ自体小型であり、これを実装
する回路基板の小型化が図れるといった面から、各種電
子機器への応用が高まっている。
2. Description of the Related Art A thin film capacitor generally has a structure in which a thin film-like lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on a substrate. In some cases, a thin film capacitor is formed on a semiconductor substrate having a function as a lower electrode layer. In some cases, a structure in which a dielectric layer and an upper electrode layer are laminated is adopted. In this type of thin film capacitor, the dielectric layer is designed to have a large relative dielectric constant and to have any positive or negative temperature coefficient centered on zero. The thin film capacitor itself is small in size, and the application to various electronic devices is increasing from the viewpoint that the size of a circuit board on which the thin film capacitor is mounted can be reduced.

【0003】この種の薄膜コンデンサを電気回路の温度
補償用コンデンサとして用いることができる。その使用
例を図5に示す。図5に示す電気回路は共振回路の一例
であって、コイルLに対してコンデンサC0とバラクタ
ダイオードDcを並列接続し、バラクタダイオードDc
温度補償用の薄膜コンデンサC1を並列接続し、薄膜コ
ンデンサC1の上部電極と下部電極にそれぞれ入出力端
子50,51を接続し、入出力端子50,51と薄膜コ
ンデンサC1の一方の電極との間に抵抗Rを組み込んで
いる。
[0003] Such a thin film capacitor can be used as a temperature compensating capacitor for an electric circuit. An example of its use is shown in FIG. The electric circuit shown in FIG. 5 is an example of a resonance circuit in which a capacitor C 0 and a varactor diode D c are connected in parallel to a coil L, and a thin film capacitor C 1 for temperature compensation is connected in parallel to the varactor diode D c. connects the respective output terminals 50 and 51 to the upper and lower electrodes of the thin film capacitor C 1, it incorporates a resistor R between one of the electrodes of the input and output terminals 50 and 51 and the thin-film capacitor C 1.

【0004】この共振回路において、バラクタダイオー
ドDcは電圧によってキャパシタンスが変化するもので
あり、このバラクタダイオードDcの温度係数は通常、
正の値をとる。そのため、このバラクタダイオードDc
の温度係数を、温度係数が負の値を持つ薄膜コンデンサ
1で相殺することによって、温度安定性に優れた共振
回路を実現することができる。
In this resonance circuit, the capacitance of the varactor diode D c changes according to the voltage, and the temperature coefficient of the varactor diode D c is usually
Takes a positive value. Therefore, this varactor diode D c
Temperature coefficient of, by the temperature coefficient to offset a thin film capacitor C 1 having a negative value, it is possible to achieve excellent resonant circuit temperature stability.

【0005】[0005]

【発明が解決しようとする課題】ところで、図5に示し
た共振回路において、バラクタダイオードDcの温度係
数は通常、+200〜+500ppm/K程度の値をと
る。したがって、これを相殺するために、温度補償用薄
膜コンデンサの温度係数は−200〜−500ppm/
K程度の値をとることが要求される。薄膜コンデンサに
用いられるごく一般的な誘電体膜としてシリコン酸化膜
(SiO2)が挙げられるが、シリコン酸化膜の場合、
種々の論文や特許公報等に記載されているように、容量
温度係数は0±50ppm/K程度で一般的には正の値
を示す。したがって、一般的なシリコン酸化膜で符号が
負、絶対値が100ppm/Kオーダーの容量温度係数
を得ることはできず、例えばペロブスカイト型複合酸化
物系などの特殊な膜を選択する必要があった。
[SUMMARY OF THE INVENTION Incidentally, in the resonant circuit shown in FIG. 5, the temperature coefficient of the varactor diode D c usually takes a value of about + 200~ + 500ppm / K. Therefore, in order to offset this, the temperature coefficient of the thin film capacitor for temperature compensation is -200 to -500 ppm /
It is required to take a value of about K. A very common dielectric film used for a thin film capacitor is a silicon oxide film (SiO 2 ). In the case of a silicon oxide film,
As described in various papers and patent publications, the temperature coefficient of capacitance generally indicates a positive value at about 0 ± 50 ppm / K. Therefore, it is impossible to obtain a temperature coefficient of capacitance of a general silicon oxide film having a negative sign and an absolute value of the order of 100 ppm / K, and it is necessary to select a special film such as a perovskite-type composite oxide. .

【0006】本発明は、上記の課題を解決するためにな
されたものであって、シリコン酸化膜系の誘電体膜を用
いることを前提とし、符号が負で絶対値が100ppm
/Kオーダーの容量温度係数を持つ誘電体薄膜とその製
造方法、およびこれを用いた温度補償用コンデンサを提
供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is based on the premise that a silicon oxide film-based dielectric film is used.
It is an object of the present invention to provide a dielectric thin film having a capacitance / temperature coefficient of the order of / K, a method of manufacturing the same, and a capacitor for temperature compensation using the same.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明の温度補償用コンデンサ用誘電体薄膜は、
珪素原子と酸素原子と水素原子とから構成される水素化
酸化珪素からなり、負の容量温度係数を有することを特
徴とする。特に前記水素化酸化珪素は、Si−OH結合
を有し、膜中に含まれる水素原子の割合が0.5ないし
7原子パーセントの範囲にあることが望ましい。
In order to achieve the above object, a dielectric thin film for a temperature compensating capacitor according to the present invention comprises:
It is made of hydrogenated silicon oxide composed of silicon atoms, oxygen atoms, and hydrogen atoms, and has a negative temperature coefficient of capacitance. In particular, it is preferable that the hydrogenated silicon oxide has a Si-OH bond, and the proportion of hydrogen atoms contained in the film is in the range of 0.5 to 7 atomic percent.

【0008】本発明者らは、一般のシリコン酸化膜の場
合、上述したように、容量温度係数が0±50ppm/
K程度で正の値を示すのに対し、Si(珪素)原子と0
(酸素)原子に加えてH(水素)原子を含む水素化酸化
珪素膜の場合、特にSi−OH結合を有する場合にはS
i−OH結合の双極子分極によって容量温度係数が負の
値を示すことを見い出した。膜中に含まれる水素原子の
割合が0.5原子パーセントを下回ると、一般的なシリ
コン酸化膜の特性とほとんど変わらなくなって容量温度
係数が正の値を示し、7原子パーセントを越えると、高
周波Q値が小さく(誘電損失が大きく)なりすぎること
から、膜中に含まれる水素原子の割合は0.5〜7原子
パーセントの範囲にあることが望ましい。
The present inventors have found that, in the case of a general silicon oxide film, the capacitance temperature coefficient is 0 ± 50 ppm /
While it shows a positive value at about K, Si (silicon) atom and 0
In the case of a hydrogenated silicon oxide film containing an H (hydrogen) atom in addition to an (oxygen) atom, especially when the silicon oxide film has a Si—OH bond,
It has been found that the capacitance temperature coefficient shows a negative value due to the dipole polarization of the i-OH bond. When the ratio of hydrogen atoms contained in the film is less than 0.5 atomic percent, the characteristics are almost the same as those of a general silicon oxide film, and the temperature coefficient of capacitance shows a positive value. Since the Q value becomes too small (dielectric loss becomes too large), the ratio of hydrogen atoms contained in the film is preferably in the range of 0.5 to 7 atomic percent.

【0009】本発明の温度補償用コンデンサ用誘電体薄
膜の製造方法は、原料ガスとしてモノシランガスと一酸
化二窒素ガスと不活性ガスの混合ガスを用いた2周波励
起プラズマCVD法により上記本発明の温度補償用コン
デンサ用誘電体薄膜を成膜することを特徴とする。
The method for producing a dielectric thin film for a temperature compensating capacitor according to the present invention is a method for producing a dielectric thin film according to the present invention using a dual frequency excitation plasma CVD method using a mixed gas of monosilane gas, dinitrogen monoxide gas and an inert gas as a source gas. A dielectric thin film for a temperature compensating capacitor is formed.

【0010】この方法によれば、容量温度係数が負の値
を持つ上記本発明の水素化酸化珪素膜を簡便な方法で成
膜することができ、成膜時の諸条件を適宜調整すること
によって容量温度係数の値やQ値を所望の値とすること
ができる。
According to this method, the silicon hydride oxide film of the present invention having a negative temperature coefficient of capacitance can be formed by a simple method, and various conditions at the time of film formation can be appropriately adjusted. Accordingly, the value of the capacitance temperature coefficient and the Q value can be set to desired values.

【0011】本発明の温度補償用コンデンサは、一対の
電極間に、上記本発明の温度補償用コンデンサ用誘電体
薄膜が挟持されたことを特徴とする。この温度補償用コ
ンデンサを例えば共振回路等の電子回路に用いることに
より、温度安定性に優れた共振回路を実現することがで
きる。
The temperature compensating capacitor of the present invention is characterized in that the above-mentioned dielectric thin film for a temperature compensating capacitor of the present invention is sandwiched between a pair of electrodes. By using this capacitor for temperature compensation in an electronic circuit such as a resonance circuit, a resonance circuit having excellent temperature stability can be realized.

【0012】[0012]

【発明の実施の形態】以下、本発明の一実施の形態を図
1〜図3を参照して説明する。図1は本実施の形態の温
度補償用コンデンサを示す平面図、図2は図1のII−II
線に沿う断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a plan view showing a temperature compensating capacitor according to the present embodiment, and FIG.
It is sectional drawing which follows a line.

【0013】本実施の形態の温度補償用コンデンサ1
は、図1および図2に示すように、平面視矩形状の基板
2の上面に、各々が平面視矩形状の下部電極層3、誘電
体薄膜4、上部電極層5が順次積層されている。基板2
は、その材質等を特に限定するものではないが、コンデ
ンサ全体に適度な剛性を付与するために充分な厚さを有
するととともに、各々が薄膜状の下部電極層3、誘電体
薄膜4、上部電極層5を成膜法により基板2上に形成す
る際に成膜処理温度に耐え得るものであればよい。以上
のような条件を満たす基板材料の例として、ガラス、シ
リコン、アルミナ等のセラミクスなどが挙げられる。
The temperature compensating capacitor 1 of the present embodiment
As shown in FIGS. 1 and 2, a lower electrode layer 3, a dielectric thin film 4, and an upper electrode layer 5, each having a rectangular shape in plan view, are sequentially laminated on the upper surface of a substrate 2 having a rectangular shape in plan view. . Substrate 2
Is not particularly limited in its material and the like, but has a thickness sufficient to impart appropriate rigidity to the entire capacitor, and has a thin-film lower electrode layer 3, a dielectric thin film 4, When forming the electrode layer 5 on the substrate 2 by a film forming method, any material can be used as long as it can withstand the film forming processing temperature. Examples of substrate materials satisfying the above conditions include ceramics such as glass, silicon, and alumina.

【0014】下部電極層3および上部電極層5は、銅、
銀、金、白金等の金属からなる単層構造でもよいし、こ
れら金属の組み合わせからなる積層構造であってもよ
い。膜厚は1000〜3000nm程度とすることが望
ましく、例えば1500nmとすることができる。図1
における上部電極層5の平面寸法は例えば50〜100
0μm×50〜1000μm程度であり、これがコンデ
ンサの実質的な面積となる。
The lower electrode layer 3 and the upper electrode layer 5 are made of copper,
It may have a single-layer structure made of a metal such as silver, gold, or platinum, or may have a laminated structure made of a combination of these metals. The thickness is desirably about 1000 to 3000 nm, for example, 1500 nm. FIG.
Of the upper electrode layer 5 is, for example, 50 to 100.
It is about 0 μm × 50 to 1000 μm, which is a substantial area of the capacitor.

【0015】誘電体薄膜4は水素化酸化珪素膜からな
り、Si−OH結合を有し、膜中に含有する水素原子の
割合が0.5〜7原子パーセントの範囲にあることが望
ましく、負の容量温度係数を有している。膜厚は50〜
1000nm程度とすることが望ましく、例えば300
nmとすることができる。
The dielectric thin film 4 is made of a hydrogenated silicon oxide film, has a Si--OH bond, and preferably contains hydrogen atoms in the film in the range of 0.5 to 7 atomic percent. Capacity temperature coefficient. The film thickness is 50 ~
It is desirable that the thickness be about 1000 nm, for example, 300
nm.

【0016】このような負の容量温度係数を持つ水素化
酸化珪素膜は、図3に示す2周波励起プラズマCVD装
置を用いて成膜することができる。この2周波励起プラ
ズマCVD装置10では、第1の高周波電源11とプラ
ズマ励起電極12との間にこれらの間のインピーダンス
の整合を得るための整合回路が介在しており、第1の高
周波電源11からの高周波電力は整合回路を通して給電
板13によりプラズマ励起電極12に供給される。これ
ら整合回路および給電板13は導電体からなるハウジン
グ14により形成されるマッチングボックス15内に収
納されている。
Such a hydrogenated silicon oxide film having a negative temperature coefficient of capacitance can be formed by using a two-frequency excitation plasma CVD apparatus shown in FIG. In the two-frequency excitation plasma CVD apparatus 10, a matching circuit for obtaining impedance matching between the first high-frequency power supply 11 and the plasma excitation electrode 12 is interposed. Is supplied to the plasma excitation electrode 12 by the power supply plate 13 through the matching circuit. The matching circuit and the power supply plate 13 are housed in a matching box 15 formed by a housing 14 made of a conductor.

【0017】プラズマ励起電極12の下には、多数の孔
16が形成されたシャワープレート17が設けられ、プ
ラズマ励起電極12とシャワープレート17で区画され
た空間18が形成されており、この空間18にはガス導
入管19が設けられている。ガス導入管19から導入さ
れたガスは、シャワープレート17の孔16を介してチ
ャンバ壁20により形成されたチャンバ室21内に供給
される。なお、符号22はチャンバ壁20とプラズマ励
起電極12とを絶縁する絶縁体である。また、図3では
排気系の図示は省略してある。
A shower plate 17 having a large number of holes 16 is provided below the plasma excitation electrode 12, and a space 18 defined by the plasma excitation electrode 12 and the shower plate 17 is formed. Is provided with a gas introduction pipe 19. The gas introduced from the gas introduction pipe 19 is supplied into the chamber 21 formed by the chamber wall 20 through the hole 16 of the shower plate 17. Reference numeral 22 denotes an insulator that insulates the chamber wall 20 from the plasma excitation electrode 12. The illustration of the exhaust system is omitted in FIG.

【0018】一方、チャンバ室21内には、基板2を載
置するとともに他方のプラズマ励起電極ともなるウェハ
サセプタ23(サセプタ電極)が設けられており、その
周囲にはサセプタシールド24が設けられている。ウェ
ハサセプタ23およびサセプタシールド24はベローズ
25により昇降可能となっており、プラズマ励起電極1
2とウェハサセプタ23との間の距離の調整ができる構
成となっている。そして、ウェハサセプタ23にはマッ
チングボックス26内に収納された整合回路を介して第
2の高周波電源27が接続されている。また、符号28
a,28b,29a,29bは共振回路であって、バン
ドエリミネータあるいはフィルタとして機能する。
On the other hand, a wafer susceptor 23 (susceptor electrode) on which the substrate 2 is placed and which serves as the other plasma excitation electrode is provided in the chamber 21, and a susceptor shield 24 is provided around the wafer susceptor 23. I have. The wafer susceptor 23 and the susceptor shield 24 can be moved up and down by a bellows 25.
The distance between the wafer 2 and the wafer susceptor 23 can be adjusted. A second high frequency power supply 27 is connected to the wafer susceptor 23 via a matching circuit accommodated in a matching box 26. Also, reference numeral 28
a, 28b, 29a and 29b are resonance circuits, which function as band eliminators or filters.

【0019】本実施の形態の場合、第1の高周波電源1
1、第2の高周波電源27からプラズマ励起電極12、
ウェハサセプタ23に異なる高周波電力をそれぞれ印加
するとともに、チャンバ室21内にSiH4ガス(モノ
シランガス)とN2Oガス(一酸化二窒素ガス)とHe
ガス、Arガス等の不活性ガスの混合ガスを導入する、
いわゆる2周波励起プラズマCVD法を用いて誘電体薄
膜4を成膜すれば、負の容量温度係数を持つ水素化酸化
珪素膜を成膜することができる。
In the case of this embodiment, the first high-frequency power supply 1
1, the plasma excitation electrode 12 from the second high frequency power supply 27,
Different high-frequency powers are applied to the wafer susceptor 23, and SiH 4 gas (monosilane gas), N 2 O gas (dinitrogen monoxide gas), and He
Gas, introducing a mixed gas of an inert gas such as Ar gas,
If the dielectric thin film 4 is formed by using a so-called two-frequency excitation plasma CVD method, a silicon hydride oxide film having a negative temperature coefficient of capacitance can be formed.

【0020】[0020]

【実施例】本発明者らは、上記実施の形態の成膜方法を
用いて誘電体薄膜を有するコンデンサを実際に製作し、
容量温度係数、Q値などの特性評価を行った。以下にそ
の結果を報告する。
EXAMPLES The present inventors actually manufactured a capacitor having a dielectric thin film using the film forming method of the above embodiment,
Characteristics such as temperature coefficient of capacitance and Q value were evaluated. The results are reported below.

【0021】下の表1に示すように、SiH4ガス流
量、N2Oガス流量、Heガス(またはArガス)流量
[sccm]、チャンバ内圧力[Pa]、プラズマ励起電極
(f:40MHz)に印加するRFパワー(表1ではR
Fパワー1と記す)、ウェハサセプタ(f:1.6MH
z)に印加するRFパワー(表1ではRFパワー2と記
す)、上下電極間距離等の成膜条件を振った4種類のサ
ンプル(サンプルA〜D)を作製した。膜厚は300n
mで統一した。
As shown in Table 1 below, SiH 4 gas flow rate, N 2 O gas flow rate, He gas (or Ar gas) flow rate [sccm], chamber pressure [Pa], plasma excitation electrode (f: 40 MHz) RF power (R in Table 1)
F power 1), wafer susceptor (f: 1.6 MH)
Four types of samples (samples A to D) were prepared in which the film forming conditions such as the RF power applied to z) (RF power 2 in Table 1) and the distance between the upper and lower electrodes were varied. The film thickness is 300n
m.

【表1】 [Table 1]

【0022】上で作製した4種類のサンプルについて、
膜中の水素含有量、容量温度係数(Tcc)、耐電圧強度
(Ebd)、Q値[f:1GHz]等の評価項目について
測定を行った。膜中水素含有量はSIMS(2次イオン
質量分析法)を用いて測定した。なお、Si−OH結合
の存在についてはFT−IR(フーリエ変換赤外分光
法)を用いて確認することができる。耐電圧強度につい
ては全てのサンプルにわたって10MV/cmと同等の値が
得られた。その他の項目については、図4に結果をまと
めた。図4は容量温度係数およびQ値の水素含有量依存
性を示すグラフであり、横軸が膜中水素含有量[atom
%]、左側の縦軸が容量温度係数[ppm/K]、右側の縦
軸がQ値[−]である。図4においては、容量温度係数
を「□」、Q値を「●」で示す。このとき、各サンプル
の構造は、図1に示したものと同じであり、上部電極層
1の面積を1mm2とし、シート容量は120ないし1
30pF/mm2となった。
For the four types of samples prepared above,
Measurements were made on evaluation items such as the hydrogen content in the film, the temperature coefficient of capacitance (Tcc), the withstand voltage strength (Ebd), and the Q value [f: 1 GHz]. The hydrogen content in the film was measured using SIMS (secondary ion mass spectrometry). Note that the presence of the Si—OH bond can be confirmed using FT-IR (Fourier transform infrared spectroscopy). Regarding the withstand voltage strength, a value equivalent to 10 MV / cm was obtained over all the samples. FIG. 4 summarizes the results of other items. FIG. 4 is a graph showing the hydrogen content dependency of the capacity temperature coefficient and the Q value, and the horizontal axis represents the hydrogen content in the film [atom.
%], The vertical axis on the left side is the capacitance temperature coefficient [ppm / K], and the vertical axis on the right side is the Q value [-]. In FIG. 4, the capacity temperature coefficient is indicated by “□”, and the Q value is indicated by “●”. At this time, the structure of each sample is the same as that shown in FIG. 1, the area of the upper electrode layer 1 is 1 mm 2 , and the sheet capacity is 120 to 1
It was 30 pF / mm 2 .

【0023】図4から明らかなように、膜中水素含有量
が0.5〜7atom%の範囲は、容量温度係数の符号が負
の領域であり、膜中水素含有量の増加に伴って絶対値が
増加し、膜中水素含有量が7atom%のときに−300pp
m/K 以下(絶対値で300ppm/K 以上)の容量温度係数
が得られることが確認された。一方、Q値を見ると、膜
中水素含有量の増加に伴ってQ値が減少し、膜中水素含
有量が7atom%で30程度にまで小さくなることが確認
された。この結果に基づき、容量温度係数の符号が負で
100ppm/K オーダーの絶対値が得られ、Q値もある程
度の値が確保できるという観点から、膜中水素含有量を
0.5〜7atom%の範囲で制御するのがよいことが実証
された。
As is apparent from FIG. 4, when the hydrogen content in the film is in the range of 0.5 to 7 atom%, the sign of the temperature coefficient of capacitance is in the negative region, and the absolute value increases with the increase in the hydrogen content in the film. -300pp when the hydrogen content in the film is 7 atom%
It was confirmed that a capacity temperature coefficient of m / K or less (absolute value of 300 ppm / K or more) was obtained. On the other hand, when looking at the Q value, it was confirmed that the Q value decreased with an increase in the hydrogen content in the film, and the hydrogen content in the film was reduced to about 30 at 7 atom%. Based on this result, from the viewpoint that the sign of the capacity temperature coefficient is negative and an absolute value of the order of 100 ppm / K is obtained, and the Q value can be secured to a certain value, the hydrogen content in the film is set to 0.5 to 7 atom%. It has been demonstrated that it is better to control the range.

【0024】本発明によれば、上記のような水素化酸化
珪素膜を誘電体薄膜としたコンデンサを作製することに
より、符号が負で絶対値が100ppm/Kオーダーの
容量温度係数を持つ温度補償用コンデンサを容易に実現
することができ、この温度補償用コンデンサを例えば共
振回路等の電子回路に用いることにより、温度安定性に
優れた共振回路を実現することができる。
According to the present invention, by forming a capacitor using the above-mentioned silicon hydride oxide film as a dielectric thin film, a temperature compensation having a negative sign and an absolute value having a capacitance temperature coefficient of the order of 100 ppm / K is achieved. By using the temperature compensation capacitor in an electronic circuit such as a resonance circuit, a resonance circuit having excellent temperature stability can be realized.

【0025】なお、本発明の技術範囲は上記実施の形態
に限定されるものではなく、本発明の趣旨を逸脱しない
範囲において種々の変更を加えることが可能である。例
えばコンデンサを構成する各膜の材料、膜厚、平面寸
法、成膜条件等の具体的な記載はほんの一例に過ぎず、
適宜変更が可能である。
The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, specific descriptions of materials, film thicknesses, plane dimensions, film forming conditions, etc. of each film constituting the capacitor are merely examples,
It can be changed as appropriate.

【0026】[0026]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、符号が負で絶対値が100ppm/Kオーダー
の容量温度係数を持つ温度補償用コンデンサを実現する
ことができ、この温度補償用コンデンサを共振回路等の
電子回路に用いることにより、温度安定性に優れた共振
回路を実現することができる。
As described above in detail, according to the present invention, it is possible to realize a temperature compensating capacitor having a negative sign and an absolute value having a temperature coefficient of capacitance of the order of 100 ppm / K. By using the compensation capacitor in an electronic circuit such as a resonance circuit, a resonance circuit having excellent temperature stability can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の一実施の形態の温度補償用コンデン
サを示す平面図である。
FIG. 1 is a plan view showing a temperature compensation capacitor according to an embodiment of the present invention.

【図2】 図1のII−II線に沿う断面図である。FIG. 2 is a sectional view taken along the line II-II in FIG.

【図3】 同、コンデンサを構成する誘電体薄膜の成膜
時に用いる2周波励起プラズマCVD装置の概略構成を
示す断面図である。
FIG. 3 is a cross-sectional view showing a schematic configuration of a two-frequency excitation plasma CVD apparatus used for forming a dielectric thin film forming a capacitor.

【図4】 本発明の実施例であるサンプルの評価結果を
示す図であり、容量温度係数およびQ値の水素含有量依
存性を示すグラフである。
FIG. 4 is a graph showing evaluation results of a sample which is an example of the present invention, and is a graph showing a hydrogen content dependency of a capacity temperature coefficient and a Q value.

【図5】 温度補償用コンデンサを用いた共振回路の等
価回路図である。
FIG. 5 is an equivalent circuit diagram of a resonance circuit using a temperature compensation capacitor.

【符号の説明】[Explanation of symbols]

1 温度補償用コンデンサ 2 基板 3 下部電極層 4 誘電体薄膜 5 上部電極層 DESCRIPTION OF SYMBOLS 1 Temperature compensation capacitor 2 Substrate 3 Lower electrode layer 4 Dielectric thin film 5 Upper electrode layer

フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H01G 13/00 391 H01G 4/06 102 (72)発明者 北川 均 東京都大田区雪谷大塚町1番7号 アルプ ス電気株式会社内 Fターム(参考) 4K030 AA01 AA06 BA44 FA03 LA11 5E082 AB03 BC15 FG03 FG27 FG42 KK01 PP03 5G303 AA01 AB06 AB11 BA03 CA01 CB30 DA01 Continued on the front page (51) Int.Cl. 7 Identification FI FI Theme Court II (Reference) H01G 13/00 391 H01G 4/06 102 (72) Inventor Hitoshi Kitagawa 1-7 Yukitani Otsukacho, Ota-ku, Tokyo Alps F term (reference) in Electric Co., Ltd. 4K030 AA01 AA06 BA44 FA03 LA11 5E082 AB03 BC15 FG03 FG27 FG42 KK01 PP03 5G303 AA01 AB06 AB11 BA03 CA01 CB30 DA01

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 珪素原子と酸素原子と水素原子とから構
成される水素化酸化珪素からなり、負の容量温度係数を
有することを特徴とする温度補償用コンデンサ用誘電体
薄膜。
1. A dielectric thin film for a temperature compensating capacitor, comprising a hydrogenated silicon oxide composed of silicon atoms, oxygen atoms, and hydrogen atoms, having a negative temperature coefficient of capacitance.
【請求項2】 前記水素化酸化珪素がSi−OH結合を
有し、膜中に含まれる水素原子の割合が0.5ないし7
原子パーセントの範囲にあることを特徴とする請求項1
記載の温度補償用コンデンサ用誘電体薄膜。
2. The hydrogenated silicon oxide has a Si—OH bond, and the ratio of hydrogen atoms contained in the film is 0.5 to 7
2. The method according to claim 1, wherein the ratio is in the range of atomic percent.
A dielectric thin film for a capacitor for temperature compensation according to the above.
【請求項3】 原料ガスとしてモノシランガスと一酸化
二窒素ガスと不活性ガスの混合ガスを用いた2周波励起
プラズマCVD法により請求項1記載の温度補償用コン
デンサ用誘電体薄膜を成膜することを特徴とする温度補
償用コンデンサ用誘電体薄膜の製造方法。
3. The temperature-compensating capacitor dielectric thin film according to claim 1, which is formed by a two-frequency excitation plasma CVD method using a mixed gas of monosilane gas, nitrous oxide and an inert gas as a source gas. A method for producing a dielectric thin film for a temperature compensating capacitor, comprising:
【請求項4】 一対の電極間に、請求項1記載の温度補
償用コンデンサ用誘電体薄膜が挟持されたことを特徴と
する温度補償用コンデンサ。
4. A temperature compensating capacitor characterized in that the dielectric thin film for a temperature compensating capacitor according to claim 1 is sandwiched between a pair of electrodes.
JP2000347988A 2000-11-15 2000-11-15 Dielectric thin film, manufacturing method therefor, and temperature-compensating capacitor Withdrawn JP2002151353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000347988A JP2002151353A (en) 2000-11-15 2000-11-15 Dielectric thin film, manufacturing method therefor, and temperature-compensating capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000347988A JP2002151353A (en) 2000-11-15 2000-11-15 Dielectric thin film, manufacturing method therefor, and temperature-compensating capacitor

Publications (1)

Publication Number Publication Date
JP2002151353A true JP2002151353A (en) 2002-05-24

Family

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004001334A1 (en) * 2002-06-20 2003-12-31 Ubukata Industries Co., Ltd. Capacitance-type liquid sensor
JP2007514376A (en) * 2003-12-09 2007-05-31 シナジー マイクロウェーブ コーポレーション Voltage controlled oscillator with user-configurable thermal drift

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004001334A1 (en) * 2002-06-20 2003-12-31 Ubukata Industries Co., Ltd. Capacitance-type liquid sensor
US7360424B2 (en) 2002-06-20 2008-04-22 Ubukata Industries, Co., Ltd. Capacitance-type liquid sensor
CN100453971C (en) * 2002-06-20 2009-01-21 株式会社生方制作所 Electrostatic capacity type liquid sensor
JP2007514376A (en) * 2003-12-09 2007-05-31 シナジー マイクロウェーブ コーポレーション Voltage controlled oscillator with user-configurable thermal drift
JP4939228B2 (en) * 2003-12-09 2012-05-23 シナジー マイクロウェーブ コーポレーション Voltage controlled oscillator with user-configurable thermal drift

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