JP2002149393A - Information processor and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor and a display device with which a low-cost interface can be realized between the information processor and the display device without lowering drawing performance even though the high resolution of display is made. SOLUTION: This display device is provided with a 1st interface circuit for receiving display data from an external device, a frame buffer for storing the display data received by the 1st interface circuit and a display screen on which the display data read from the frame buffer is displayed. This information processor is provided with a 2nd interface circuit for transmitting display data to the display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing device such as a personal computer and a display device (monitor device) for displaying display data transferred from the information processing device.

[0002]

2. Description of the Related Art Conventionally, an information processing device such as a personal computer and a display device (monitor device) such as a CRT
A cable is connected to the display device, and R, G, and B are transmitted from the information processing device to the display device via the cable.
Are transmitted along with the horizontal synchronizing signal and the vertical synchronizing signal to display various information on the display screen of the display device.

Conventionally, these information processing devices and display devices are configured, for example, as shown in FIG. An information processing device 50 such as a personal computer includes a C (not shown).
A bus (for example, a PCI bus) 51 connected to the PU is provided, and the bus 51 is connected to the bus interface circuit 5.
2, a drawing circuit 53, a frame buffer 54, and a display circuit 55 are connected. A CPU (not shown) transmits data displayed on a display screen 61 of a display device 60 to a bus 51.
The data is written to the frame buffer 54 via the bus interface circuit 52.

The drawing circuit 53 is provided for drawing a figure or the like to be displayed on the frame buffer 54. An image to be displayed is stored in the frame buffer 54 in a bitmap data format. Display circuit 55
Reads the bitmap data stored in the frame buffer 54 from time to time and transfers the read bitmap data to the interface circuit 62 of the display device 60 via the display interface circuit 56 and the cable 57 so that the display screen 61 is displayed via the interface circuit 62. The data is displayed.

In recent years, there has been a demand for an improvement in the resolution of a display device.
It is becoming stronger in various information processing systems. As described above, as the display resolution of the display device increases, the bit transfer frequency of the data transferred on the cable increases.

Therefore, when the frequency increases, the interface between the information processing device 50 and the display device 60 is parallelized, or the display interface circuit 56 operates at a high speed corresponding to a high frequency and is expensive. It is necessary to configure using parts. Therefore, inexpensive realization of a high resolution display device is desired.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to solve these conventional drawbacks. Even if the resolution of the display is increased, the image processing apparatus and the display can be displayed without deteriorating the drawing performance. It is an object of the present invention to provide an information processing device and a display device capable of realizing an inexpensive interface with the device.

[0008]

According to the present invention, there is provided an interface circuit for receiving display data from an external device, a frame buffer for storing the display data received by the interface circuit, and a display data read from the frame buffer. And a display screen for displaying the same.

According to such a configuration, it is possible to realize a display device in which an inexpensive interface with the information processing device is provided without deteriorating the drawing performance even if the display resolution is increased.

The present invention also provides a first method for receiving display data.
Information for transferring data to be displayed on a display device having an interface circuit, a frame buffer for storing display data received by the interface circuit, and a display screen for displaying display data read from the frame buffer. An information processing device, comprising: a second interface circuit that transfers data to be displayed on a display screen of a display device to the first interface circuit.

According to such a configuration, it is possible to realize an information processing apparatus in which an inexpensive interface is provided with the display device without deteriorating the drawing performance even if the display resolution is increased.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a system diagram showing a first embodiment of the present invention. In FIG. 1, an information processing device 10 such as a personal computer is connected to a display device 20 for displaying data via a cable 17. The information processing apparatus 10 is provided with a bus 11 such as a PCI bus to which a CPU (not shown) is connected. A bus interface circuit 12 is connected to the bus 11, and a display interface circuit A13 is connected to the bus interface circuit 12. The display device 20 is provided with a bus 22. This bus 22
Includes a drawing circuit 23, a frame buffer 24, and a display circuit 2.
5. The display interface circuit B21 is connected. The display circuit 25 is connected to a display screen. The display interface circuit A13 of the information processing device 10 and the display interface circuit B21 of the display device 20 are connected via a cable 17.

The data to be displayed on the display screen 26 of the display device 20 is transmitted by a CPU (not shown) to a frame buffer via a bus 11, a bus interface circuit 12, a display interface circuit A13, a cable 17, a display interface circuit B21, and a bus 22. 24 is written. The drawing circuit 23 receives a command from a CPU (not shown) via the bus 11, the bus interface circuit 12, the display interface circuit A13, the cable 17, the display interface circuit B21, and the bus 22, and displays the graphics (to be displayed on the display screen 26). It has a function of generating data such as a straight line or a circle and writing the data into the frame buffer 24. The frame buffer 24 is a memory that stores an image to be displayed in a bitmap data format. The display circuit 25 includes a frame buffer 24
Is read out at a predetermined timing, transferred to the display screen 26, and displayed.

FIG. 2 shows a display interface circuit A.
13 and the detailed configuration of the display interface circuit B21 are illustrated. Display interface circuit A1
3 has a driver circuit 131 and a receiver circuit 132. The driver circuit 131 is a bus interface circuit 1
2 is a circuit for transferring data and commands from the device 2 to the display interface circuit B21 via a cable. The receiver circuit 132 is a circuit for receiving the data transferred from the display interface circuit B21.
Is output to Display interface circuit B21
Are the driver circuit 213, the receiver circuit 211, and the
O circuit (First In First Out circuit)
212. The driver circuit 213 receives data read from the drawing circuit 23, the frame buffer 24, and the display circuit 25 via the bus 22 based on a read command from a CPU (not shown) of the information processing device 10, and receives the display interface circuit A13 is a circuit for outputting to the receiver circuit 132. Receiver circuit 211
Is a circuit for receiving data and commands transferred from the driver circuit 131 of the display interface circuit A13 via the cable 17, and the received data and commands are output to the FIFO circuit 212. FIF
The O circuit 212 is a circuit for adjusting a difference in processing speed between the information processing device 10 and the display device 20.

In the first embodiment having such a configuration, the display resolution is increased, and the transfer frequency (transfer rate) of data transferred from the frame buffer 24 to the display screen 26 via the display circuit 25 is determined by the information. Bus 1 of processing device 10
1, the data transfer frequency (transfer rate) between the display interface circuit A13 and the display interface circuit B21 is higher than the bus 11 of the information processing apparatus 10.
May be the same as the data transfer frequency (transfer rate) in.

For this reason, the display interface circuit A13, the display interface circuit B21 and the cable 17 can be composed of conventionally used parts, and the interface between the information processing apparatus 10 and the display apparatus 20 can be easily realized. Moreover, it can be realized at low cost.

Next, a second embodiment will be described with reference to FIG. The same components as those in FIG. 1 are denoted by the same reference numerals. In the case of the first embodiment described above, the data transfer frequency (transfer rate) between the display interface circuit A13 and the display interface circuit B21 is set to the data transfer frequency (transfer rate) on the bus 11 of the information processing device 10. Otherwise, the drawing performance may not be ensured.

However, most of the actual use of the data transfer frequency (transfer rate) in the bus is performed when displaying a large amount of data transfer such as a binary image or a photograph. For this reason, in the second embodiment, FIG.
And a display interface circuit A and a display interface circuit by adding a compression circuit and an expansion circuit for compressing / expanding data such as a binary image and a photograph to the circuit configuration of the first embodiment shown in FIG. Rendering performance can be secured even if the data transfer frequency (transfer rate) with B is lowered.

FIG. 3 is a diagram showing a circuit configuration of the second embodiment. In FIG. 3, a data compression circuit 28 and a data decompression circuit 29 are added to the information processing apparatus 10 and The difference from the circuit configuration of the first embodiment is that a data compression circuit 31 and a data decompression circuit 30 are added to FIG.

Next, a third embodiment will be described with reference to FIG. Even in the circuit configuration of the second embodiment shown in FIG. 3, when drawing display data from a CPU (not shown) of the information processing apparatus in the frame buffer, data transfer between the display interface circuit A and the display interface circuit B is performed. The frequency (transfer rate) becomes a bottleneck, and the drawing performance may decrease.

The third embodiment is for preventing such a decrease in the drawing performance of the second embodiment, and its detailed circuit configuration is shown in FIG. In FIG. 4, an information processing apparatus 10 such as a personal computer has a C (not shown).
A bus 11 (for example, a PCI bus) connected to the PU is provided.
2, the drawing circuit 23 and the first frame buffer 3
2. The reading circuit 33 is connected. The read circuit 33 is connected to the parallel / serial conversion circuit 34. The parallel / serial conversion circuit 34 is connected to a driver circuit 35 as an interface circuit.
Then, the data to be displayed is once written in the first frame buffer 32. After that, the read circuit 33
Reads the display data from the first frame buffer 32, converts the read display data into serial data by the parallel / serial conversion circuit 34, and transfers it to the display device 20 via the driver circuit 35 and the cable 17.

On the other hand, the display device 20 has a receiver circuit 36 as an interface circuit, a serial / parallel conversion circuit 37, a writing circuit 38, a second frame buffer 39, a display circuit 25, and a display screen 26. The serial data transferred via the driver circuit 25 and the cable 14 is converted into parallel data by a serial / parallel conversion circuit 37, and is written to a second frame buffer 39 by a writing circuit 38. The display data written in the second frame buffer 39 is transmitted to the display circuit 2
5 and transferred to the display screen 26 for display. Thus, the information processing device 10 and the display device 2
By providing the frame buffers on both the 0 side, the data transfer frequency (transfer rate) between the display interface circuit A13 and the display interface circuit B21 can be further reduced.

[0023]

According to the present invention, an inexpensive interface can be realized between an information processing apparatus and a display device without deteriorating the drawing performance even if the display resolution is increased.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing details of a display interface circuit in FIG. 1;

FIG. 3 is a diagram showing a second embodiment of the present invention.

FIG. 4 is a diagram showing a third embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a conventional information processing device and a display device.

[Explanation of symbols]

 Reference Signs List 10 information processing device 11 bus 12 bus interface circuit 13 display interface circuit A 17 cable 20 display device 21 display interface circuit B 22 bus 23 drawing circuit 24 {Frame buffer 25} Display circuit 26} Display screen

Claims (5)

[Claims] An interface circuit for receiving display data from an external device, a frame buffer for storing display data received by the interface circuit, and a display screen for displaying display data read from the frame buffer. A display device, comprising: A first interface circuit for receiving the display data, a frame buffer for storing the display data received by the interface circuit, and a display screen for displaying the display data read from the frame buffer. An information processing device for transferring data to be displayed on a display device, comprising: a second interface circuit for transferring data to be displayed on the display screen of the display device to the first interface circuit. Information processing device. 3. An interface circuit for receiving display data compressed from an external device, a decompression circuit for decompressing the compressed display data received by the interface circuit, and storing the display data decompressed by the decompression circuit. A display device comprising: a frame buffer that performs display; and a display screen that displays display data read from the frame buffer. 4. A first interface circuit for receiving compressed display data, an expansion circuit for expanding the compressed display data received by the first interface circuit, and a display expanded by the expansion circuit. An information processing apparatus for transferring compressed display data to a display device having a frame buffer for storing data and a display screen for displaying display data read from the frame buffer, comprising: An information processing apparatus, comprising: a compression circuit that compresses display data to be displayed on a screen; and a second interface circuit that transfers the display data compressed by the compression circuit to the first interface circuit. 5. A first method for receiving display data from an external device.
A first frame buffer for storing display data received by the first interface circuit, and a display screen for displaying display data read from the first frame buffer. An information processing device for transferring display data to the display device, comprising: a second frame buffer for storing display data to be displayed on the display device; and a first interface for reading the display data read from the second frame buffer. An information processing apparatus, comprising: a second interface circuit that transfers the data to a circuit.