JP2002149353A - Disk array controller and disk array control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily restore the damage of data when data in a data cache memory part installed inside is damaged by a hardware fault in a disk array controller. SOLUTION: The disk array controller 100 is provided with a plurality of data cache memory parts 105-1 to 105-3 and a parity cache memory part 106. Host adapter parts 103-1 and 103-4 and disk adapter parts 104-1 to 104-4 divide writing data into a plurality of division data at the time of writing data, write division data into corresponding data cache memory parts 105-1 to 105-3 and write the logic parity of writing data into the parity cache memory part 106. At the time of reading data, data are checked and damaged data are restored in accordance with the logic parity which is read from the parity cache memory part 106.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a disk array control technique for dividing and storing data in a plurality of disk devices.

[0002]

2. Description of the Related Art Conventionally, in order to improve input / output performance, data is divided and stored in a disk array composed of a plurality of magnetic disk devices. FIG. 9 is a block diagram for explaining this kind of conventional technology.

As shown in FIG. 9, a conventional disk array system comprises a disk array controller 1, a plurality of host computers 2-1 and 2-2, and a plurality of disk arrays 3-1 and 3-.
And 2. Disk arrays 3-1 and 3-2 are
Each is composed of a plurality of magnetic disk devices.

[0004] The disk array controller 1 includes host adapter units 11-1 and 11-2 corresponding to the host computer 2-1.
And host adapter units 11-3 and 11-4 corresponding to the host computer 2-2, disk adapter units 12-1 and 12-2 corresponding to the disk array 3-1 and disk array 3-2. It comprises disk adapter units 12-3 and 12-4, cache memory units 13-1 and 13-2, and a shared bus 14.

When a write request is issued from the host computer 2-1, the host adapter unit 11-1 uses the shared bus 14 to write data to the cache memory unit 13-1 or 13-2. Thereafter, the host adapter unit 11-1 notifies one of the disk adapter units 12-1 to 12-4 (for example, the disk adapter unit 12-4) that the data has been written. This allows the disk adapter section 12-4
Writes the above data to the disk array 3-2.

[0006] When a read request is issued from the host computer 2-1, the host adapter unit 11-1 checks whether data to be read exists in the cache memory unit 13-1 or 13-2. If it exists, the data to be read is read from the cache memory unit 13-1 or 13-2 via the shared bus 14 and sent to the requesting host computer 2-1. On the other hand, when the data to be read does not exist, the host adapter unit 11-1
It requests one of the disk adapter units 12-1 to 12-4 (for example, the disk adapter unit 12-1) to store the data to be read. As a result, the disk adapter 12-1
Reads the data to be read from the disk array 3-1 and writes it to the cache memory unit 13-1 or 13-2.
After that, the host adapter unit 11-1
The data to be read is read from 13-1 or 13-2 and sent to the requesting host computer 2-1.

[0007]

The above-mentioned prior art has the following problems.

The first problem is that since data is written in a single cache memory unit, it is extremely difficult to recover data when a failure occurs in the cache memory unit.

A second problem is that a plurality of adapter units and the cache memory unit are connected by a shared bus.
When one adapter unit accesses the cache memory unit, another adapter unit cannot access the cache memory unit, and the access efficiency is poor.

SUMMARY OF THE INVENTION It is an object of the present invention to facilitate recovery of damaged data due to a hardware failure in a cache memory unit and to improve access efficiency to the cache memory unit.

[0011]

In order to achieve the above object, a disk array control device according to the present invention is connected to a disk array composed of a plurality of data disk devices and one parity disk device. And a data cache memory unit for each data disk device, a parity cache memory unit corresponding to the parity disk device, and a write operation from the host computer. At the time of request, while writing the logical parity of the write data to the parity cache memory unit,
The write data is divided into divided data for each of the data cache memory units and written to the corresponding data cache memory unit. When a data read request is issued from the host computer, the data to be read is stored in each of the data cache memory units. If so, the read target data divided and stored in each of the data cache memory units is combined and transmitted to the host computer. And after the read target data is stored in each of the data cache memory units in response to the storage request, the read target data divided and stored in each of the data cache memory units is combined to form the host A host adapter for sending to a computer; When the partition unit writes the divided data and the logical parity in the data cache memory unit and the parity cache memory unit, the divided data and the logical parity are stored in the corresponding data disk device and parity disk device. When the host adapter unit issues a storage request, reads the data to be read requested to be stored from each of the data disk devices, and stores the logical parity of the read data in the parity cache memory unit; A disk adapter unit for dividing the read data into divided data for each data cache memory unit and writing the divided data to the corresponding data cache memory unit.

According to this configuration, the data is divided and stored in the plurality of data cache memory units, and the logical parity is stored in the parity cache memory unit. Even if data is destroyed due to a hardware failure, it can be easily recovered.

Further, in the disk array control device according to the present invention, in order to improve access efficiency to the data cache memory unit, each of the data cache memory units may
When each of the plurality of memory units, the host adapter unit and the disk adapter unit is disposed between the plurality of memory units, and the access destination memory units of the host adapter unit and the disk adapter unit are different, And a cross bus switch unit that enables simultaneous access.

According to this configuration, when the access destination memory section of the host adapter section is different from the access destination memory section of the disk adapter section, the host adapter section and the disk adapter section can access simultaneously, thereby improving the access efficiency.

Further, in the disk array control device of the present invention, in order to improve memory throughput, the cross bus switch unit includes a plurality of buffers for holding an access request from the host adapter unit, and a buffer from the disk adapter unit. A plurality of buffers for holding access requests.

According to this configuration, a plurality of access requests from the same host adapter unit or disk adapter unit can be processed in parallel, so that memory throughput can be improved.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

[0018]

FIG. 1 shows an embodiment of the present invention. A plurality of host computers 101-1 and 101-2 and a plurality of disk arrays 102-1 and 102-2 are connected to the disk array control device 100 according to the present embodiment. Each of the disk arrays 102-1 and 102-2 includes three data magnetic disk devices D1 to D3 and one parity magnetic disk device P.

The disk array controller 100 includes a host adapter section 103-1, connected to a host computer 101-1.
103-2, the host adapter units 103-3 and 103-4 connected to the host computer 101-2, the disk adapter units 104-1 and 104-2 connected to the disk array 102-1, and the disk array 102-2. Disk adapter part 104-3,
104-4 and data magnetic disk devices D1, D2, D3
Data cache memory units 105-1,105-2,105- corresponding to
3 and a parity cache memory unit 106 corresponding to the parity magnetic disk device P.

(Configuration of Data Cache Memory Unit) The data cache memory unit 105-1 includes a plurality of memory units 152-1.
To 152-4 and cross bus switch sections 151-1 and 151-2.

The memory sections 152-1 to 152-4 form an address space of addresses 0 to An as shown in FIG. 0
Address to (A1-1) is the directory area 21, Address A1 to (A2-1) is the control information area 22, Address A2 to
The address (A3-1) is used as the write area 23, and the addresses A3 to An are used as the read area 24.

The directory area 21 has a read area 24
Directory information indicating the correspondence between the address of each data stored in the memory unit on the memory unit and the address on the disk array (data magnetic disk device D1).

The control information area 22 includes the adapter sections 103-1 to 103-1.
It is divided into areas of 103-4, 104-1 to 104-4. When a certain adapter unit instructs an operation to another adapter unit, the certain adapter unit writes control information indicating the content of the instruction in an area corresponding to the other adapter unit.

The write area 23 is provided for each host adapter unit 10
Each of the host adapter sections 103-1 to 103-4 is divided into host computers 101-1 to 10-4.
According to the write request from 1-2, the data is stored in the area corresponding to the local adapter.

In the read area 24, the disk array 102-
A copy of a part of the data stored in the data magnetic disk drive D1 of 1,102-2 is stored.

The cross bus switch section 151-1 includes a host adapter section 103-1, 103-2, a disk adapter section 104-1, 104-
When the access destination of 2 is a different memory section, it has a configuration that allows simultaneous access. The cross bus bus switch section 151-2 has the same configuration as the cross bus switch section 151-1.

FIG. 3 is a block diagram showing a configuration example of the cross bus switch section 151-1. As shown in the figure, the cross bus switch unit 151-1 includes the host adapter units 103-1, 103-
2 and the input / output switching units 520-520-3 connected to the disk adapter units 104-1 and 104-2.
2,520-4 and an access request from the host adapter unit or the disk adapter unit via the input / output switching units 520-1 to 520-4 (in the case of a data write request, it indicates the write data, write address, and write command. Request input buffer group 502-1 to 502- which includes a plurality of request input buffers for storing information, and in the case of a data read request, a read address, a read command, and information indicating an adapter unit of an access request source.
4, an input / output switching unit 521-1 to 521-4 connected to the memory units 152-1 to 152-4, and a request output buffer 505 for holding an access request to be output to the memory units 152-1 to 152-4. -
1 to 505-4 and a read data input buffer group 508-1 to 508-4 including a plurality of read data input buffers for temporarily holding read data from the memory units 152-1 to 152-4.
And read data output buffers 511-1 to 511-4 for outputting read data to the host adapter unit and the disk adapter unit via the input / output switching units 520-1 to 520-4.

Further, the cross bus switch section 151-1 includes a request cross bus switch section 503, a read data cross bus switch section 509, a request cross bus arbitration / control section 504, and a read data cross bus arbitration / control section.
510.

The request cross bus switch unit 503 includes:
The request output buffer 505- is output from each of the plurality of buffers constituting the request input buffer groups 502-1 to 502-4.
1 to 505-4 Each has an access route. If the access source and access destination buffers are different, a plurality of access routes can be set at the same time.
FIG. 4 is a block diagram showing a configuration example of the request cross bus switch unit 503.
1 to 502-4, the signal lines from each request input buffer to each of the request output buffers 505-1 to 505-4, and the control signals from the request cross bus arbitration / control unit 504. Request output buffer 505-1 to 50 to select one of the signal lines
Each of the selectors 52-1 to 522-4 is provided for every 5-4.

Read data cross bus switch unit 509
Has an access path from each of the plurality of buffers constituting the read data input buffer groups 508-1 to 508-4 to each of the read data output buffers 511-1 to 511-4. If the access source and access destination buffers are different, a plurality of access routes can be set at the same time.
FIG. 5 is a block diagram showing an example of the configuration of the read data cross bus switch unit 509.
Each signal line group from each read data input buffer constituting each of 508-1 to 508-4 to each read data output buffer 511-1 to 511-4 and a control signal from the read data cross bus arbitration / control unit 510 It comprises selectors 523-1 to 523-4 for each of the read data output buffers 511-1 to 511-4 for selecting one of the signal lines from the read data input buffer.

Request cross bus arbitration / control unit 504
Sends an access request to the same memory unit based on a connection request (including information indicating a memory unit to be accessed) from each request input buffer constituting the request input buffer groups 502-1 to 502-4. A function for determining whether or not a plurality of held request input buffers exist, a function for performing arbitration when it is determined that a plurality of request input buffers exist and selecting one of the plurality of request input buffers, a request cross It has a function of connecting the selected request input buffer controlling the bus switch unit 503 to the request output buffer corresponding to the memory unit.

Read data cross bus arbitration / control section 510
Is the read data output buffer 511-i of the connection destination (read data output buffer corresponding to the adapter unit of the access request source) added from the request output buffers 505-1 to 505-4, and the read data input of the connection source Buffer group
Based on the connection request including the buffer in 508-j, a function to determine whether there are multiple request output buffers holding access (read) requests from the same adapter unit, In this case, arbitration is performed to select one of the connection requests from the plurality of request output buffers, or the read data cross bus switch unit 509 is controlled according to the selected connection request and included in the connection request. It has a function of connecting the buffer in the read data input buffer group 508-j of the connection source to the read data output buffer 511-i of the connection destination.

FIG. 6 is a block diagram showing an example of the configuration of the memory section 152-1.
2 and a plurality of memory modules 513 connected to the memory controller 512.
It is composed of The memory controller 512 has a function of writing data to the memory module 513 and reading data from the memory module 513 in accordance with an access request from the cross bus switch units 151-1 and 151-2. Note that the other data cache memory units 105-2, 10
5-3 and the parity cache memory unit 106 have the same configuration as the data cache memory unit 105-1.

(Configuration of Host Adapter Unit) The host adapter unit 103-1 has a host interface unit (host I / F).
Unit) 131, microprocessor 132, parity generation /
A check circuit 133 and a memory access control unit 134 are provided.

The host I / F section 131 has a function of controlling an interface with the host computer 101-1.

The parity generation / check circuit 133 has a function of generating a logical parity for the write data when data is written to the data cache memory units 105-1 to 105-3, and a data cache memory unit 105-1 to 105-. It has a function to check errors and recover damaged data according to logical parity when reading data from 3.

The memory access control section 134 stores write data and control information in each data cache memory section 105-1.
Function to create an access request for each of the data cache memory units 105-1 to 105-3 including the divided data, the write address, and the write command, and a function for creating each access request. The function of transmitting data to the corresponding data cache memory units 105-1 to 105-3, the logical parity generated by the parity generation / check circuit 133,
It has a function of transmitting an access request including a write address and a write command to the parity cache memory unit 106, a function of combining divided data read from each of the data cache memory units 105-1 to 105-3, and the like.

The microprocessor 132 uses the memory access control section 134 to store control information (data in the write area 23) in the control information area 22 in the disk arrays 102-1 and 102-2.
Control information to instruct writing to the
Read data stored in 102-1, 102-2 and read area 24
A function of writing an interrupt signal to a microprocessor in another adapter unit after writing the control information,
When an interrupt is issued from a microprocessor in another adapter unit, the own adapter unit 103-
1 has a function of performing processing according to the control information written in the area corresponding to 1. The other host adapter unit 10
3-2 to 103-4 have the same configuration as the host adapter unit 103-1.

The disk adapter section 104-1 includes a disk interface section (disk I / F section) 141, a microprocessor 142, and a parity generation / check circuit 143.
And a memory access control unit 144.

The disk I / F unit 141 includes a disk array
It has a function to control the interface with 102-1.

The parity generation / check circuit 143 has a function of generating a logical parity for the write data at the time of writing data to the data cache memory units 105-1 to 105-3, and a data cache memory unit 105-1 to 105-. It has a function to check errors and recover damaged data according to logical parity when reading data from 3.

The memory access control section 144 stores write data and control information in each data cache memory section 105-1.
Function to create an access request for each of the data cache memory units 105-1 to 105-3 including the divided data, the write address, and the write command, and a function for creating each access request. The function of transmitting to the corresponding data cache memory units 105-1 to 105-3, the logical parity generated by the parity generation / check circuit 143,
It has a function of transmitting an access request including a write address and a write command to the parity cache memory unit 106.

When an interrupt is issued from a microprocessor in another adapter section, the microprocessor 142 performs processing according to the control information written in the area corresponding to the own adapter section 104-1 in the control information area 22. And a function of generating an interrupt signal to a microprocessor in another adapter unit.

[0044]

[Explanation of operation] (Operation at the time of data writing) First, the operation at the time when the host computer 101-1 writes data to the disk array 102-1 will be described.

When writing data, the host computer 101-1 sends a write request including write data, a write command, and a write address to one of the host adapter units 103-1 and 103-2 connected to the host computer. One (for example, the host adapter unit 103-1) is output (FIG. 7, A1). At this time, the write address is an address of an area allocated to the host adapter unit 103-1 in the write area 23.

The parity generation / check circuit 133 in the host adapter unit 103-1 generates a logical parity for the write data in the write request passed from the host computer 101-1 and passes it to the memory access control unit 134 (A2). ). Accordingly, the memory access control unit 134
The above write data is stored in each data cache memory unit 105-
1 to 105-3, and creates an access request for each of the data cache memory units 105-1 to 105-3 including the divided data, the write address, and the write command, and creates a corresponding data cache memory unit 105. -1 to 105-3 and an access request including the logical parity, the write command, and the write address passed from the parity generation / check circuit 133 to the parity cache memory unit 106 (A3).

Each of the data cache memory units 105-1 to 105-
3 and the parity cache memory unit 106 perform write processing according to the access request sent from the host adapter unit 103-1 (A4).

The process of step A4 will be described in detail by taking a write process in the data cache memory unit 105-1 as an example.

The access request including the divided data, the write address, and the write command from the host adapter unit 103-1 is transmitted to the request input buffer group 502- via the input / output switching unit 520-1 in the cross bus switch unit 151-1. 1 and held in one of the request input buffers (the request input buffer is referred to as a request input buffer RI in the following description). The request input buffer RI holding the access request is stored in an access destination memory unit (memory unit 152-1) based on the write address.
1), and outputs a connection request to the request cross bus arbitration / control unit 504 with the access destination memory unit 152-1 as a connection destination. The request input buffer group 50
Since 2-1 is composed of a plurality of request input buffers, the next access request from the host adapter unit 103-1 can be held in an empty request input buffer. Request input buffer group 50
The access request held in 2-1 is not related to the input order,
A connection request can be issued to the request cross bus arbitration / control unit 504.

Request cross bus arbitration / control unit 504
When a connection request is added from the request input buffer RI, it is checked whether or not a connection request with the memory unit 152-1 as a connection destination is also added from another request input buffer. By controlling the request cross bus switch unit 503, the request input buffer RI is connected to the request output buffer 505-1 corresponding to the memory unit 152-1 to request the access request held in the request input buffer RI. Set in output buffer 505-1. On the other hand, the memory unit 15
If there are multiple connection requests with 2-1 as the connection destination, arbitration is performed. As a result of the arbitration, if it is determined that the connection right is given to the request input buffer RI, the request cross bus arbitration / control unit 504 controls the request cross bus switch unit 503 to request the request input buffer RI.
Is connected to the request output buffer 505-1, and the access request held in the request input buffer RI is set in the request output buffer 505-1.

The access request set in the request output buffer 505-1 is applied to the memory controller 512 in the memory section 152-1 via the input / output switching section 521-1 (see FIG. 6). This allows the memory controller 512
Writes the divided data included in the access request into the memory module 513 according to the write address included in the access request. The above is the details of the processing performed in the data cache memory unit 105-1 in step A4. The other data cache memory units 105-2 and 105-3 and the parity cache memory unit 106
However, a similar writing process is performed.

The data cache memory units 105-1 to 105-3,
When the write processing to the parity cache memory unit 106 is completed, the following processing for writing the data written to the data cache memory units 105-1 to 105-3 to the disk array 102-1 as the final write destination is performed. Will be

First, the microprocessor 132 passes control information including the following information to the memory access control unit 134 (A5).

The address Aa of the data written in step A4 on the data cache memory units 105-1 to 105-3. The write address Ab on the disk array 102-1. The data stored in the address Aa of the data cache memory units 105-1 to 105-3 is transferred to the disk array 102-1.
Instruction information for instructing writing to the above address Ab ・ Write address Ac of control information (address of area allocated to disk adapter unit 104-1 corresponding to disk array 102-1 in control information area 22)

When the control information is passed, the memory access control unit 134 divides the address Aa, the address Ab, and the instruction information into divided data for each of the data cache memory units 105-1 to 105-3. An access request for each of the data cache memories 105-1 to 105-3 including the divided data, the write command, and the write address Ac is created and transmitted to the corresponding data cache memory units 105-1 to 105-3. Thereby, the data cache memory unit 105-
Control information is written to addresses Ac of 1 to 105-3.

Thereafter, the microprocessor 132 sends the disk adapter unit via an interrupt signal line (not shown).
The microprocessor 142 in 104-1 is interrupted (A6).

As a result, the microprocessor 142
The address Ac assigned to the own disk adapter unit 104-1 in the control information area 22 of the data cache memory units 105-1 to 105-3 for the memory access control unit 144.
(A7). According to this instruction, the memory access control unit 14
4 reads the control information divided and stored in each of the data cache memory units 105-1 to 105-3 and combines them (A8).

The microprocessor 142 sends the data from the address Aa of the data cache memory units 105-1 to 105-3 and the parity cache memory unit 106 to the memory access control unit 144 based on the combined control information.
It instructs to read the logical parity (A9).

In response to this instruction, the memory access control unit 144 controls the data cache memory units 105-1 to 105-3.
The data read and stored at the address Aa of the parity cache memory unit 10 are read and combined.
The logical parity is read from the address Aa of No. 6 (A1
0). Thereafter, the parity generation / check circuit 143 performs a data check according to the logical parity (if there is a damage, also recovers it) (A11). When the check by the parity generation / check circuit 143 is completed, the data that has been checked and the write address Ab are transmitted to the disk array 102-1 (A12). As a result, data and logical parity are written to the addresses Ab of the data magnetic disk devices D1 to D3 and the parity magnetic disk device P.

(Operation at the time of reading data) Next, the operation at the time when the host computer 101-1 reads data from the disk array 102-1 will be described.

At the time of reading data, the host computer 101-1 reads the read address Ad (the disk array 102-
1, a read request including a read command is output to one of the host adapter units 103-1 and 103-2 (in this example, the host adapter unit 103-1) (FIG. 8, FIG. B1).

When the read request is added, the microprocessor 132 in the host adapter unit 101-1 determines whether the data to be read indicated by the read address Ad is stored in the data cache memory units 105-1 to 105-3. Whether or not the data cache memory units 105-1 to 10
The determination is made based on the directory information stored in the directory area 21 of 5-3 (B2).

When it is determined that the data to be read exists in the data cache memory units 105-1 to 105-3 (B2: YES), each data cache memory unit 105-1 is transmitted via the memory access control unit 134. The access request including the read address Aca, the read command, and the request source information indicating that the access request source is the host adapter unit 103-1 is transmitted to the parity cache memory unit 106 and the read address Aca (B3). The read address Aca is the read address A on the disk array 102-1.
Data cache memory units 105-1 to 105-3 corresponding to d
The above address, which can be obtained from directory information.

Each of the data cache memory units 105-1 to 105-
3 and the parity cache memory unit 106 perform data read processing in accordance with the access request sent from the host computer 101-1 (B4).

The process of step B4 will be described in detail by taking a read process in the data cache memory unit 105-1 as an example.

The access request including the read address Aca, the read command, and the request source information from the host adapter section 103-1 is transmitted to the request input buffer group via the input / output switching section 520-1 in the cross bus switch section 151-1. 502-1
And one of the request input buffers R
I is held. The request input buffer RI holding the access request obtains a memory unit to be accessed (referred to as a memory unit 152-1) based on the read address Aca.
The connection request with the access destination memory unit 152-1 as a connection destination is output to the request cross bus arbitration / control unit 504.

Thus, the request cross bus arbitration /
The control unit 504 performs arbitration, and the request input buffer R
If I can be given the right to connect to the memory unit 152-1, it controls the read cross bus switch unit 503 to control the request input buffer RI and the request output buffer 505-
1 and connects the access request held in the request input buffer RI to the request output buffer 505-.
Set to 1.

When the access request is set, the request output buffer 505-1 determines whether or not the data of the read address Aca (data to be read) included in the access request exists in the read data input buffer group 508-1. Find out what. As described later, read data input buffer group
Since each buffer in 508-1 stores data and the address of the data, it is necessary to determine whether data to be read is stored based on whether or not data at address Aca exists. Can be.

If there is, the read data input buffer group 508-
The connection request with the read data input buffer DI in 1 as the connection source and the read data output buffer 511-1 corresponding to the host adapter unit 103-1 as the request source of the access request as the connection destination is read data cross bus arbitration / control. Output to section 510. As a result, the read data cross bus arbitration / control unit 510 performs arbitration and sets the read data input buffer DI.
When the right to connect to the read data output buffer 511-1 can be given to the read data output buffer 511-1, the read data cross buffer switch unit 509 is controlled to connect the read data input buffer DI and the read data output buffer 511-1. As a result, the data to be read is changed from the read data input buffer DI to the read data output buffer
It is sent to the host adapter unit 103-1 via 520-1.

On the other hand, if the data to be read does not exist in the read data input buffer group 508-1,
The request output buffer 505-1 sends a read address A to the memory controller 512 in the memory unit 152-1.
ca, output access request including read command.
As a result, the memory controller 512 reads the data to be read from the corresponding address Aca of the memory module 513, and stores the data to be read and the address Aca in one of the buffers in the read data input buffer group 508-1.
And are stored. Further, the request output buffer 505-1
Prompts the requesting host adapter unit 103-1 to retry. When the host adapter unit 103-1 that has been prompted to retry outputs the access request again, the data to be read is stored in one of the buffers in the read data input buffer group 508-1. Is performed, and the data to be read is sent to the host adapter unit 103-1 via the read data cross bus switch unit 509, the read data output buffer 511-1, and the input / output switching unit 520-1. The above is the details of the processing performed in the data cache memory unit 105-1 in step B4. The same read processing is performed in the other data cache memory units 105-2 and 105-3 and the parity cache memory unit 106.

The memory access control section 134 in the host adapter section 103-1 includes the respective data cache memory sections 105-1 to 105-1.
The data to be read from 105-3 are combined, and the parity generation / check circuit 133 checks the data to be read according to the logical parity from the parity cache memory unit 106 (recovers the damaged data if it is corrupted) (B5). B6). The data to be read after the check is
The read request is sent to the host computer 101-1 via the host I / F unit 131 (B7).

Data cache memory units 105-1 to 105-3
When the data to be read exists above (YES in B2)
In the case of (2), the above-described processing is performed. However, when the processing does not exist (B2 is NO), the following processing is performed.

If it is determined in step B2 that the data to be read does not exist in the data cache memory units 105-1 to 105-3, the microprocessor 132 in the host adapter unit 103-1 includes the following information. The control information is passed to the memory access control unit 134 (B8).

The address Ad of the data to be read on the disk adapter unit 102-1. The instruction information for instructing the data of the address Ad to be written to the data cache memory units 105-1 to 105-3. The write address of the control information. Ac (the address of the area allocated to the disk adapter unit 104-1 corresponding to the disk array 102-1 in the control information area 22)

When the above-mentioned control information is passed, the memory access control unit 134 divides the address Ad and the instruction information into divided data for each of the data cache memory units 105-1 to 105-3. , A write command, and a write address Ac.
An access request for each of 5-1 to 105-3 is created and transmitted to the corresponding data cache memory units 105-1 to 105-3. As a result, the control information is written to the address Ac of the data cache memory units 105-1 to 105-3.

Thereafter, the microprocessor 132 in the host adapter unit 103-1 interrupts the microprocessor 142 in the disk adapter unit 104-1 via an interrupt signal line (not shown) (B9).

As a result, the microprocessor 142 in the disk adapter unit 104-1 can operate the memory access control unit 14
4 for reading control information stored in the control information area 22 of the data cache memory units 105-1 to 105-3 divided into addresses Ac assigned to the own disk adapter unit 104-1. (B10). In accordance with this instruction, the memory access control unit 144 reads and combines the control information divided and stored in each of the data cache memory units 105-1 to 105-3 (B11).

The microprocessor 142 determines the address A of the disk array 102-1 based on the combined control information.
Data to be read is read from d (B12). The parity generation / check circuit 143 generates a logical parity for the data to be read (B13). The memory access control unit 144 divides the data to be read into divided data for each of the data cache memory units 105-1 to 105-3, and stores the divided data, the write address, and the write command in each of the data cache memory units 105-1. ~ 105-
3 and sends the access request to the corresponding data cache memory units 105-1 to 105-3. The access request including the logical parity, the write command, and the write address generated by the parity generation / check circuit 143 is used as a parity. Transmission to the cache memory unit 106 (B1
4). Note that the write address can be an address determined by the microprocessor 142 by the LRU method or the like. The data cache memory units 105-1 to 105-3 and the parity cache memory unit 106
In accordance with the access request from 04-1, write processing of read target data is performed (B15). Thereafter, the microprocessor 142 in the disk adapter unit 104-1 updates the directory information stored in each of the data cache memory units 105-1 to 105-3 and the parity cache memory unit 106 (B16). Then, the above-described step B3
To B7.

[0079]

As described above, according to the present invention, since data is stored by being divided into a plurality of data cache memories and the logical parity thereof is stored in the parity cache memory, a hardware failure occurs. Can easily recover from data corruption, and the reliability of the disk array control device can be improved.

Further, according to the present invention, the cross bus switch section is provided, and the access destination memory section can process different access requests in parallel, so that the access efficiency can be improved.

Further, according to the present invention, the cross bus switch unit includes a plurality of buffers for holding a plurality of access requests, and simultaneously receives a plurality of access requests from the same host adapter unit or disk adapter unit. Therefore, memory throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an embodiment of the present invention.

FIG. 2 is a diagram showing an address space of a data cache memory units 105-1 to 105-3 and a parity cache memory unit 106.

FIG. 3 is a diagram illustrating a configuration example of a cross bus switch unit 151-1.

FIG. 4 is a block diagram illustrating a configuration example of a request cross bus switch unit 503;

FIG. 5 is a block diagram showing a configuration example of a read data cross bus switch unit 509;

FIG. 6 is a block diagram illustrating a configuration example of a memory unit 152-1.

FIG. 7 is a flowchart showing a processing example at the time of data writing.

FIG. 8 is a flowchart showing a processing example at the time of data reading.

FIG. 9 is a block diagram of a conventional example.

[Explanation of symbols]

 100 Disk array control device 101-1, 101-2 Host computer 102-1, 102-2 Disk array D1 to D3 Data magnetic disk device P1 Parity magnetic disk device 103-1 to 103-4 Host adapter unit 131 ... Host I / F section 132 ... Microprocessor 133 ... Parity generation / check circuit 134 ... Memory access control section 104-1 to 104-4 ... Disk adapter section 141 ... Disk I / F section 142 ... Microprocessor 143 ... Parity generation / Check circuit 144 Memory access control unit 105-1 to 105-3 Data cache memory unit 151-1, 151-2 Cross bus switch unit 502-1 to 502-4 Request input buffer group 503 Request cross bus switch unit 504 … Request cross bus arbitration / control unit 505-1 to 505-4… Request output buffer 508-1 to 508-4… Read data input buffer group 509… Re Read data cross bus arbitration / control unit 511-1 to 511-4 ... read data output buffer 152-1 to 152-4 ... memory unit 512 ... memory controller 513 ... memory module 522-1 522522-4, 523-1〜523-4 セ レ ク タ Selector 106 パ リ テ ィ Parity cache memory unit 1 デ ィ ス ク Disk array controller 11-1〜11-4 ホ ス ト Host adapter unit 12-1〜12-4 デ ィ ス ク Disk adapter unit 13- 1, 13-2: Cache memory unit 14: Shared bus 2-1, 2-2: Host computer 3-1, 3-2: Disk array

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G06F 12/08 541 G06F 12/08 541Z 557 557 12/16 320 12/16 320L

Claims (7)

[Claims] 1. A disk array control device connected to a disk array comprising a plurality of data disk devices and one parity disk device and connected to a host computer, wherein each of the data A data cache memory unit for each disk device, a parity cache memory unit corresponding to the parity disk device, and when a write request is issued from the host computer, a logical parity of write data is written to the parity cache memory unit and the write operation is performed. The data is divided into divided data for each of the data cache memory units and written into the corresponding data cache memory unit. When a data read request is issued from the host computer, data to be read is stored in each of the data cache memory units. Where you are In this case, the data to be read which is divided and stored in each of the data cache memory units is combined and sent to the host computer, and if not stored, a storage request for the data to be read is made. After the read target data is stored in each of the data cache memories in response to the storage request, the read target data divided and stored in each of the data cache memories is combined and transmitted to the host computer. A host adapter unit that writes the divided data and the logical parity into the data cache memory unit and the parity cache memory unit when the host adapter unit writes the divided data and the logical parity into the data disk device. , Stored in a parity disk device, and When a storage request is made, the read target data requested to be stored from each of the data disk devices is read,
A disk adapter unit for storing the logical parity of the read data in the parity cache memory unit, dividing the read data into divided data for each of the data cache memory units, and writing the divided data to the corresponding data cache memory unit. A disk array control device, comprising: 2. The disk array control device according to claim 1, wherein the host adapter unit and the disk adapter unit include:
When reading data from the data cache memory unit, the disk array control device has a configuration in which data check and recovery of damaged data are performed using logical parity stored in the parity cache memory unit. 3. The disk array control device according to claim 2, wherein each of the data cache memory units includes a plurality of memory units, the host adapter unit and the disk adapter unit,
A cross bus switch unit that is arranged between the plurality of memory units and that enables simultaneous access when the host adapter unit and the disk adapter unit access different memory units. Disk array controller. 4. The disk array controller according to claim 3, wherein the cross bus switch unit includes an access path from the host adapter unit to each of the memory units, and the disk adapter different from the access path. A disk array control device comprising: an access path from a unit to each of the memory units; and an arbitration control unit that arbitrates between an access request from the host adapter unit and an access request from the disk adapter unit. 5. The disk array control device according to claim 4, wherein said cross bus switch unit includes a plurality of buffers for holding access requests from said host adapter unit and an access request from said disk adapter unit. A disk array control device comprising: a plurality of buffers to be held. 6. A disk array comprising a plurality of data disk units and one parity disk unit and connected to a host computer,
Disk array control in a disk array control device including a data cache memory unit for each data disk device, a parity cache memory unit corresponding to the parity disk device, a host adapter unit, and a disk adapter unit In a method, at the time of a write request from the host computer, the host adapter unit writes logical parity of write data into the parity cache memory unit, and divides the write data into divided data for each data cache memory unit. The disk adapter unit writes the divided data and logical parity written in the data cache memory unit and the parity cache memory unit by the host adapter unit. The host adapter unit stores the data to be read in the data cache memory unit when the data to be read is stored in the data cache memory unit. The data to be read which is divided and stored in the unit is combined and sent to the host computer. If the data to be read is not stored, a request for storing the data to be read is made. pls respond,
The data to be read which is requested to be stored is read from each of the data disk devices, the logical parity of the read data is stored in the parity cache memory unit, and the read data is divided into divided data for each of the data cache memory units. The host adapter unit combines the read target data divided and stored in the data cache memory units by the disk adapter unit and transmits the read target data to the host computer. A disk array control method. 7. The disk array control method according to claim 6, wherein the host adapter unit and the disk adapter unit
A disk array control method, wherein when reading data from the data cache memory unit, data check and recovery of damaged data are performed using logical parity stored in the parity cache memory unit.