JP2002140199A - Information processing device and method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save only an effective resource corresponding to an instruction for permitting interruption, and improve the overhead, in an information processing device. SOLUTION: An instruction generation device 101 determines whether a register 102d of a CPU 102 is effective or not from a source file 101a described by a user by a compiler 101b, and reports information acquired by determination including an object file 101c to the CPU. The CPU temporarily holds the reported information in a state register 102e, saves the held information in a stack memory 104, and saves selectively the effective content in the register in the stack memory by referring the information held in the state register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for improving the performance of a CPU. The present invention relates to an information processing apparatus and method for avoiding performance degradation due to evacuation.

[0002]

2. Description of the Related Art Interrupt technology is used for various purposes such as requests from input / output devices and interval timer interrupts in order to respond in real time to events.

[0003] Basic interrupt control in the CPU includes:
There are states where interrupts are accepted and states where interrupts are not accepted. Normally, even when interrupts are accepted,
For each interrupt, it is possible not to permit the interrupt by a mask bit set in the status register in advance. Also, when the CPU selects the state of accepting the interrupt or the state of prohibiting the interrupt, the control is performed via the writing of the state register.

Therefore, when an interrupt request is issued during the execution of a certain process, the interrupt occurs when the process is ready to accept an interrupt and the interrupt request signal is not masked. If an interrupt occurs,
Normally, branch to the appropriate interrupt handler, but if resources such as registers and status registers used by the user program are destroyed during processing in the interrupt handler at this time, after returning from the interrupt handler, ,
Normal execution of the original user program cannot be resumed.

Therefore, when an interrupt occurs, it is necessary to save resources. However, since it is not possible to distinguish whether the resource is valid or invalid, virtually all resources including the invalid resource are saved every time an interrupt is received.

[0006] In view of the fact that an interrupt that occurs substantially on the order of several microseconds or more can be answered by a user without necessarily receiving an interrupt for all instructions, a specific instruction is decoded. A control method has been devised in which an interrupt is permitted in the event that the operation is performed.

[0007]

However, even if an interrupt is accepted only by an instruction for permitting an interrupt, a considerable amount of resources may have to be saved in some cases. In addition, since it is not possible to distinguish whether a resource is valid or invalid, there is a problem that overhead is generated because the saving and restoring processes are performed for all resources including the invalid resource.

The present invention has been made in view of such a problem, and an object of the present invention is to save overhead and improve system performance by saving only valid resources in accordance with an instruction that permits an interrupt. To provide an information processing apparatus and method.

[0009]

In order to achieve the above object, a first information processing apparatus according to the present invention comprises an instruction generation apparatus,
And an information processing device including a CPU having at least one register and performing processing in accordance with an instruction generated by the instruction generation device, wherein the instruction generation device determines whether or not the register of the CPU is valid. Notification means for notifying the CPU of the information as to whether the register is valid or not obtained by the determination means, wherein the CPU temporarily stores the notified information and a temporary storage means. A first saving means for saving the held information, and a second saving means for selectively saving the contents of the valid register with reference to the information held in the temporary holding means. .

In the first information processing apparatus, the CPU refers to first return means for restoring the saved information and the effective information saved by the second save means with reference to the information restored by the first return means. A second restoring means for selectively restoring the contents of the register. in this case,
The second return means refers to a bit corresponding to the register one by one from a status register holding the information restored from the stack memory by the first return means, and the referenced one-bit information is a predetermined bit. It is preferable to restore the contents of the corresponding register from the stack memory only when it is a logical value.

It is preferable that the notifying unit notifies the CPU of information by the generated instruction.

Preferably, the temporary holding means allocates a bit corresponding to the register to the status register, and holds a predetermined logical value in a bit corresponding to a valid register.

The second saving means refers to a bit corresponding to the register from the status register holding the information one bit at a time, and only when the referenced one bit information has a predetermined logical value, It is preferable to save the contents of the register to be stored in the stack memory.

In order to achieve the above object, a second information processing apparatus according to the present invention is an information processing apparatus including a CPU having at least one register and receiving an interrupt only when a specific instruction is executed. Means for determining whether the register of the CPU is valid, and information obtained by the determination means for determining whether the register is valid.
Notification means for notifying by means of an instruction, means for permitting an interrupt by executing the instruction while the information notified by the notification means is valid, and setting the instruction in the least effective position of the register. Means for arranging.

The second information processing apparatus includes means for temporarily holding information on whether or not the register is valid only when the instruction accepts an interrupt, and a first means for saving the information held in the temporary holding means. The information processing apparatus is characterized by comprising a saving means and a second saving means for selectively saving the contents of the valid register with reference to the information held in the temporary holding means.

In order to achieve the above object, a first information processing method according to the present invention is an information processing method for performing processing using a CPU having at least one register in accordance with a generated instruction. Determining whether the register is valid, notifying the CPU of the information as to whether the register is valid or not obtained by the determination, and temporarily storing the notified information in the CPU; Is saved, and the contents of valid registers are selectively saved by referring to the temporarily held information.

Further, the first information processing method is characterized in that the saved information is restored, and the contents of the valid register are selectively restored by referring to the restored information.
In this case, the selective restoration of the valid register contents refers to the bit corresponding to the register one bit at a time from the status register holding the restored information, and the referenced one-bit information is a predetermined logical value. Only in such a case, it is preferable to restore the contents of the corresponding register from the stack memory.

It is preferable that the notification of the information is performed by a generated instruction.

Preferably, the information is temporarily stored by allocating a bit corresponding to the register to the status register, and storing a predetermined logical value in the bit corresponding to the valid register.

Further, in the selective saving of the valid register contents, a bit corresponding to the register is referred one bit at a time from a state register holding information, and the referenced one bit information is a predetermined logical value. Only in this case, it is preferable to save the contents of the corresponding register in the stack memory.

In order to achieve the above object, a second information processing method according to the present invention has at least one register and performs processing using a CPU that receives an interrupt only when a specific instruction is executed. The method comprises: CP
The CPU determines whether or not the register of U is valid, and outputs information obtained by the determination whether or not the register is valid to the CPU.
And an interrupt is permitted by executing the instruction while the notified information is valid in the CPU, and the instruction is arranged at a position where the number of valid registers is the least. .

This second information processing method further holds information temporarily, saves the temporarily held information only when an interrupt is received, and selectively refers to the temporarily held information to select valid register contents. It is characterized by being evacuated to.

In order to achieve the above object, a recording medium according to the present invention is characterized by storing an instruction sequence generated by an instruction generation device in a first information processing device.

According to the above configuration and method, at a certain point, information as to whether or not a register is valid is represented by C
By notifying the PU and accepting an interrupt at a point where the resource is saved the least, it is possible to reduce the resource saving penalty and improve the system performance.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a diagram showing a schematic configuration of an information processing apparatus according to one embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes an instruction generation device, which is a source file 101a described by a user.
And a compiler 90 for translating the source file 101a
1b and an object file 101c created by compilation by the compiler 101b.

The object file 101c is loaded into the instruction memory 103 and executed by the CPU 102.

The CPU 102 decodes an instruction from the instruction memory 103, an instruction decoding unit 102a, a control unit 102c that performs control based on information decoded by the instruction decoding unit 102a, and a control unit 102c that controls the control unit 102c. Execution unit 102b and registers (d0, d0
1, d2, d3, a0, a1, a2, and a3) 10
2d, a processor status register (PSW) 102f indicating the status of the CPU 102, a program counter (PC) 102g indicating the address of the instruction currently being executed on the instruction memory 103, and whether the register 102d is valid. Status register (RVSR) 10 indicating the status
2e. Note that, in FIG.
Devices other than the CPU 102 have a general configuration.

In the following, first, the instruction generator 101 determines whether or not the register 102d is valid, and determines whether the register 102d is valid.
A method of notifying the U102 will be described, and subsequently, the behavior of the CPU 102 when the interrupt permission instruction is decoded will be described.

FIG. 2 is a diagram schematically showing the contents of the source file 101a of FIG. Here, the meanings of the machine language instructions used in FIG. 2 are as follows.

ADD OP1, OP2: transfer the contents of OP1 + OP2 to OP2 ADD OP1, OP2, OP3: transfer the contents of OP1 + OP2 to OP3 CLR OP: set the contents of OP to "0" MOV OP1, OP2: change the contents of OP1 Transfer to OP2 MOV OP, (addr): Transfer the contents of OP to the address indicated by addr INC4 OP: Add 4 to the contents of OP NOP: No Operation For the machine language instruction sequence in FIG. It has means for determining information, and the determination procedure is shown in FIG. First, the machine language instruction sequence in FIG. 2 is grouped for every 100 instructions, and is set as a processing unit in FIG. Note that the grouping number of 100 is an example, and the same applies to other numbers. In addition, as a grouping method, it is also possible to divide into basic blocks in addition to the number of instructions.

In FIG. 3, first, attention is paid to a certain register (step S301), and it is searched whether or not there is an instruction in which this register is a destination (dst) register in a group of instructions. (Step S302). If there is no instruction that is the destination register (No in S302), the register of interest for all instructions in this group is valid (step S303).

On the other hand, when there is an instruction to be a destination register (Yes in S302), the register focused on before this reference is set based on this instruction.
It is searched whether there is an instruction used as a source (src) register (step S304). When there is no instruction used as a source register (S30
(No in 4), the register of interest is invalid for all instructions from the reference set in the previous step to the reference in this step (step S305).

On the other hand, if there is an instruction to be used as the source register (Yes in S304), the register of interest becomes invalid from the instruction following the instruction to the search start point instruction (step S306). .

In this way, if there is an instruction used as the destination register among the remaining instruction strings in the group, the same steps are performed based on the instruction. The other registers are similarly searched for validity of each instruction.

The compiler 101b obtains the "valid register information table" shown in FIG. 4 as a result of performing the above operation on the machine language instruction sequence shown in FIG. In FIG.
U102 is a register d0, d1, d2, d3, a0, a
1, a2, and a3. In the table, “」 ”indicates that the register is valid, and“ × ”indicates that the register is invalid.

Based on this information, the compiler 101b
The interrupt enable instruction (INT_P
ERMIT), the location and the information of the effective register are determined as follows. Here, the interrupt permission instruction is an instruction for performing a control of permitting an interrupt only when this instruction is decoded.

The compiler 101b uses the “valid register information table” of FIG. 4 to arrange an interrupt permitting instruction at a point where the resources to be saved when an interrupt occurs are the least. First, an instruction having the smallest effective number is selected from the "effective register information table". Here, when the effective numbers are the same, the instruction having the smallest address is selected. Next, an interrupt permission instruction INT_PERMIT is inserted at a position immediately before the selected instruction. Further, the interrupt enable instruction is specified as follows using a valid register name at this position as an operand based on the “valid register information table” of FIG.

INT_PERMIT [regs]:
The valid register information indicated by [regs] is set in the status register 902e, and the interrupt is permitted by this instruction. Thus, as shown in FIG.
b, an object file 101c in which INT_PERMIT is arranged is created.

Here, as shown in FIG. 6, VALID_STORE is always arranged at the head of the interrupt handler, and VALID_LOAD and RTI are always arranged at the exit of the interrupt handler. The meaning of these instructions is as follows.

VALID_STORE: status register 1
In accordance with the information of the valid registers stored in 02e, only valid registers are saved in the stack memory 104, and finally the status register 102e is saved in the stack memory 104. VALID_LOAD: first the stack memory 104
From the status register 102e.
Only the valid registers are restored from the stack memory 104 according to the information of the valid registers stored in 2e. RTI: The processor status register PSW is restored from the interrupt handler and branched to the return address. Next, these instructions are executed by the CPU 102. The behavior at the time of this will be described with reference to FIG.

FIG. 7 shows a part of the pipeline configuration of the CPU 102, and the other configuration is the same as that of a normal pipeline.

In FIG. 7, reference numeral 701 denotes an instruction memory 10.
Instruction fetch unit 702 for reading instructions from 3
Is a decode unit representing the instruction decode unit 102a in smaller functional block units, and 703 is an execution unit 1
02b is an execution unit that expresses the function block 02b in smaller functional block units.

The decode unit 702 includes a normal instruction decode unit 702a and an interrupt enable instruction (INT_PERM).
IT) decode unit 702b, valid register decode unit 702c, and valid register store instruction (VALID_S
(TORE) decoding unit 702d and a valid register load instruction (VALID_LOAD) decoding unit 702e.

The execution unit 703 includes the normal instruction execution unit 7
03a, a valid register information holding unit 703b, a valid register information acquiring unit 703c, a valid register contents saving unit 704d, and a valid register contents returning unit 703e.

Next, the operation of the CPU 102 having such a pipeline configuration will be described.

First, when the CPU 102 decodes the interrupt permission instruction INT_PERMIT in the course of the pipeline operation for executing the object file 101c as shown in FIG. 5 and the control unit 102c receives the interrupt, the interrupt permission instruction The effective register name specified by the operand is decoded by the effective register decoding unit 702c,
The valid register information obtained by the decryption is stored in the valid register information holding unit 703b by the status register (RVSR) 102e.
To hold.

The status register (RVSR) 102e
In the valid register information held in the register, for example, a register name is stored in a format shown in FIG.
That is, the register name is represented by 8 bits, and the register corresponding to the bit in which the logical value “1” is set is a valid register. Here, “0x5E” is set to the status register (RVSR) 10 as valid register information.
2e.

Subsequently, the control unit 102c includes a program counter (PC) 102g and a processor status register (P
SW) 102f is saved to the deepest position of the stack memory 104 as shown in FIG.

At the beginning of the interrupt handler, the valid register information shown in FIG. 6 is obtained from the status register 102e and the instruction VALID_ for storing the contents of the valid register is obtained.
STORE is executed. Next, VALID_STOR
When E is decoded by the valid register store instruction decoding unit 702d, the valid register information acquiring unit 703c acquires valid register information from the status register (RVSR) 102e. Here, the status register (RVSR) 102
e, the content of the register corresponding to the acquired bit is stored in the stack memory 104 by the valid register content saving unit 703d when the logical value “1” is set by acquiring the content of the bit from the lower bit one by one. Store.

The order of storing the register contents is d0, d
Assuming that 1, 2, d3, a0, a1, a2, and a3, all the registers 102d are saved in the stack memory 104, and eight cycles are required. If the acquired bit has the logical value "0", no cycle occurs in which a series of these save operations are performed.

In this embodiment, as shown in FIG. 8, only the contents of the registers d1, d2, d3, a0, and a2 are saved in the stack memory 104, so that five cycles are required. The processing speed is increased by three cycles as compared with the evacuation.

Valid register store instruction VALID_ST
The ORE causes the valid register to be
8, the contents of the status register (RVSR) 102e are finally stored in the stack memory 104, as shown in FIG.
Evacuated to Note that an interrupt enable instruction (INT_PER
Even if the MIT) is decoded, if the control unit 102c does not recognize the interrupt, the operation of holding the valid register information is not performed.

Next, at the exit of the interrupt handler, that is, immediately before the interrupt return instruction (RTI), as shown in FIG. 6, the valid register information is obtained from the status register (RVSR) 102e, and the contents of the valid register are obtained from the stack memory 104.
Valid register load instruction VALID_LO returning from
AD is executed.

Valid register load instruction VALID_LO
When the AD is decoded by the valid register load instruction decoding unit 702e, the valid register information is obtained by the valid register information acquiring unit 703c in the state register (RVSR) 1.
02e. Here, the status register (RVS
R) The content of the register 102e is obtained one bit at a time from the upper bits, and if the logical value "1" is set, the contents of the register corresponding to the obtained bit are stored in the stack memory in the valid register content return unit 703e. Return from step 904. The order of return from the stack memory 104 is as follows.
It is the opposite of the evacuation. If the acquired bit has the logical value "0", no cycle for performing these series of return operations occurs.

Therefore, in this embodiment, a
The registers are restored in the order of 2, a0, d3, d2, and d1, and an effective register can be restored in only five cycles, compared with eight cycles required to restore all the registers 102d.

The contents of processing performed by the valid register store instruction (VALID_STORE) and the valid register load instruction (VALID_LOAD) used in the present embodiment are provided in an interrupt processing instruction (INT_PERMIT) and an interrupt return instruction (RTI), respectively. It is possible that The operation in this case will be described with reference to FIG.

FIG. 10 shows a part of the pipeline configuration of the CPU 102, and the other configuration is the same as that of a normal pipeline.

In FIG. 10, 1001 is an instruction fetch unit, 1002 is a decode unit, and 1003 is an execution unit.

The decode unit 802 includes a normal instruction decode unit 1002a and an interrupt enable instruction (INT_PER).
It comprises an MIT) decoding unit 1002b, a valid register decoding unit 1002c, and an interrupt return instruction (RTI) decoding unit 1002d.

The execution unit 803 includes the normal instruction execution unit 1
003a, a valid register information saving unit 1003b, a valid register information acquiring unit 1003c, a valid register contents saving unit 1003d, and a valid register contents restoring unit 1003.
e.

Next, the operation of the CPU 102 having such a pipeline configuration will be described.

First, an interrupt permission instruction INT_PERMIT
Is decoded by the interrupt enable instruction decoding unit 1002b, and when the control unit 102c recognizes that there is an interrupt, the valid register information is obtained by the valid register decoding unit 1002c and the valid register information is saved by the valid register information saving unit 1003b. Register (RVSR) 1
Save to 02e. Next, the valid register contents saving unit 10
According to 03d, the contents of the valid registers are saved in the stack memory 1004 based on the valid register information, and the process branches to the handler. Note that the interrupt enable instruction INT_PERM
The IT does not save or branch if there is no interrupt.

When the interrupt return instruction (RTI) is decoded by the interrupt return instruction decoding unit 1002d,
The valid register information acquisition unit 1003c reads the valid register information set in the status register (RVSR) 102e, and acquires the valid register information. Subsequently, the contents of the valid registers are returned from the stack memory 1004 by the valid register contents return unit 1003e, and the handler branches to the return address.

[0066]

As described above, according to the present invention,
Using the information on whether the register is valid or not, decode the instruction with the information on whether to enable the interrupt at the point where the register to be saved is the least, and perform the interrupt processing faster. This has the effect that it can be performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an information processing apparatus according to an embodiment of the present invention;

FIG. 2 is a diagram schematically showing the contents of a source file 101a in FIG. 1 in a machine language instruction sequence.

FIG. 3 is a flowchart showing a procedure of determining valid register information by a compiler 101b in FIG. 1;

FIG. 4 is a view showing an effective register information table obtained as a result of the determination procedure of FIG. 3;

FIG. 5 is a view showing the contents of an object file 101c created by a compiler 101b based on the valid register information table of FIG.

FIG. 6 is a diagram showing a part of instruction contents of an interrupt handler.

FIG. 7 is a diagram showing a part of a pipeline configuration example in the CPU 102 of FIG. 1;

FIG. 8 is a diagram illustrating a method of storing valid register information in the status register 102e of FIG. 1;

9 is a diagram schematically showing the contents saved in the stack memory 104 in FIG. 1;

FIG. 10 is a diagram showing a part of another example of a pipeline configuration in the CPU 102 of FIG. 1;

[Explanation of symbols]

101 Instruction Generator 101a Source File 101b Compiler 101c Object File 102 CPU 102a Instruction Decoding Unit 102b Execution Unit 102c Control Unit 102d Register 102e Status Register (RVSR) 102f Processor Status Register (PSW) 102g Program Counter (PC) 103 Instruction Memory 104 Stack Memory 701, 1001 Instruction fetch unit 702, 1002 Decoder unit 702a, 1002a Normal instruction decode unit 702b, 1002b Interrupt enable instruction (INT_PE
RMIT) decoding unit 702c, 1002c valid register decoding unit 702d valid register store instruction (VALID_ST)
ORE) Decode section 702e Valid register load instruction (VALID_LO)
AD) decoding unit 703, 1003 execution unit 703a, 1003a normal instruction execution unit 703b effective register information holding unit 703c, 1003c effective register information acquisition unit 703d, 1003d effective register contents saving unit 703e, 1003e effective register contents restoration unit

Claims (17)

[Claims] 1. An information processing apparatus, comprising: an instruction generation device; and a CPU having at least one register and performing processing according to an instruction generated by the instruction generation device, wherein the instruction generation device includes: Means for determining whether or not the register is valid; and notifying means for notifying the CPU of information on whether or not the register is valid, obtained by the determining means, wherein the CPU Means for temporarily holding the notified information, first evacuation means for evacuation of the information held in the temporary holding means, and the effective information with reference to the information held in the temporary holding means. An information processing apparatus comprising: a second save unit for selectively saving the contents of a register. 2. The information processing apparatus according to claim 1, wherein the CPU refers to the first return unit that restores the information that has been saved, and refers to the information that has been restored by the first return unit, and refers to the valid information that has been saved by the second save unit. 2. The information processing apparatus according to claim 1, further comprising a second restoration unit that selectively restores the contents of the register. 3. The information processing apparatus according to claim 1, wherein the notifying unit notifies the CPU of the information by the generated command. 4. The temporary storage unit according to claim 1, wherein the temporary storage unit allocates a bit corresponding to the register to a status register, and stores a predetermined logical value in the bit corresponding to the valid register. Information processing device. 5. The second evacuation unit refers to a bit corresponding to the register from a status register holding the information one bit at a time, and when the referenced one-bit information is a predetermined logical value. 2. The information processing apparatus according to claim 1, wherein the contents of the corresponding register are saved only in the stack memory. 6. The second return means refers to a bit corresponding to the register from the status register holding the information restored from the stack memory by the first return means one bit at a time, and 3. The information processing apparatus according to claim 2, wherein the content of the corresponding register is restored from the stack memory only when the bit information has a predetermined logical value. 7. An information processing apparatus including a CPU having at least one register and accepting an interrupt only when a specific instruction is executed, and determining whether or not the register of the CPU is valid. Notification means for notifying the CPU of information on whether the register is valid obtained by the determination means to the CPU by an instruction; and while the information notified by the notification means is valid. An information processing apparatus, comprising: means for permitting an interrupt by executing the instruction; and means for arranging the instruction at a position in the register where the number of effective registers is the smallest. 8. The information processing apparatus, comprising: means for temporarily holding information on whether the register is valid only when the instruction accepts an interrupt; and saving the information held by the temporary holding means. 8. A system according to claim 7, further comprising: a first shunting unit for causing the contents of the valid register to be selectively saved by referring to the information held in the temporary holding unit. An information processing apparatus according to claim 1. 9. According to the generated instructions, at least one
An information processing method for performing processing using a CPU having two registers, the method comprising: determining whether the register of the CPU is valid; and determining whether the register obtained by the determination is valid. To the CPU, the CPU temporarily holds the notified information, saves the temporarily held information, and selectively refers to the temporarily held information to select the contents of the valid register. An information processing method characterized by evacuating to a computer. 10. The information processing method according to claim 9, further comprising restoring the saved information, and selectively restoring the contents of the valid register by referring to the restored information. The information processing method described. 11. The information processing method according to claim 9, wherein the notification of the information is performed by the generated instruction. 12. The temporary holding of the information is performed by allocating a bit corresponding to the register to a status register and holding a predetermined logical value in the bit corresponding to the valid register. Item 10. The information processing method according to Item 9. 13. The method of selectively saving the contents of a valid register is performed by referring to a bit corresponding to the register from a status register holding the information one bit at a time, and
10. The information processing method according to claim 9, wherein the method is performed by saving the contents of a corresponding register to a stack memory only when the bit information has a predetermined logical value. 14. The method of selectively restoring valid register contents refers to a bit corresponding to the register from a state register in which the restored information is held, one bit at a time,
11. The information processing method according to claim 10, wherein the method is performed by restoring the contents of the corresponding register from the stack memory only when the referenced one-bit information is a predetermined logical value. 15. A CPU having at least one register and receiving an interrupt only when a specific instruction is executed.
An information processing method for performing processing by using the CPU, wherein it is determined whether the register of the CPU is valid, and the information obtained as a result of the determination whether the register is valid is used by the CPU. In the CPU, the interrupt is permitted by executing the instruction while the notified information is valid, and the instruction is arranged at a position in the register where the valid number is the smallest. An information processing method, comprising: 16. The information processing method further comprises: temporarily storing the information only when the interrupt is received; saving the temporarily stored information; and referencing the temporarily stored information to the valid register. 16. The method according to claim 15, wherein the contents of the contents are selectively saved.
The information processing method described. 17. A recording medium storing an instruction sequence generated by the instruction generation device in the information processing device according to claim 1.