JP2002134718A - Semiconductor memory device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile memory in which high integration is realized, while solving the problem of junction leakage or off-leaks of a transfer transistor. SOLUTION: A semiconductor memory device has a semiconductor substrate, a plurality of trench capacitors formed on the semiconductor substrate in a matrix form, a plurality of vertical tunnel junction layers embedded in the trench capacitors, a plurality of word line diffusion layers extending along the first direction of the substrate so as to be adjacent to the tunnel junction layers, and a plurality of bit lines, each connected to each tunnel junction layer and extending in the direction, crossing the word line diffusion layer at a right angle. Each trench capacitor is positioned at about the intersecting point of a word line and a bit line. A gate insulating film is inserted between the tunnel junction layer and the word line diffusion layer adjacent thereto, and a tunnel junction type transistor is constituted by a part of the trench capacitors, the vertical tunnel junction layers and a part of the word line diffusion layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having a vertical tunnel transistor in which a transistor on a transfer side of a DRAM is buried above a trench capacitor, and a method of manufacturing the same. About.

[0002]

2. Description of the Related Art In recent years, with the miniaturization of semiconductor integrated circuits,
In the structure of a conventional DRAM cell, problems arise in securing cell capacitance and controlling off-leakage of a transistor on the transfer side (transfer), and the process is becoming complicated.

The performance of a capacitor depends on how much electric charge can be stored and how long the electric charge can be retained. Therefore, an attempt to increase the electric storage effect by using a high dielectric film having a relatively high relative dielectric constant has been made. Has been made. However, materials such as STO (SrTiO ₃ : strontium titanate) and BST (barium strontium titanate) having a high relative dielectric constant have material instability.
Therefore, a reliable operation with a small capacitance or a nonvolatile DRAM cell is desired.

On the other hand, as for the transfer transistor, a DRAM cell which is not affected by the characteristic deterioration due to the miniaturization of the gate length (or channel length) L is desired. Therefore, a transistor having a vertical structure capable of realizing a gate length longer than the feature size has been studied. However, there are many problems such as the complexity of the structure and the controllability of the gate length, and it is desired to change the structure of the transfer transistor.

[0005]

FIG. 7 shows a conventional DRA.
It is sectional drawing which shows the structure of M trench cell. A planar transfer transistor (consisting of a diffusion layer 79 and a part of a word line 71 extending therebetween) is located adjacent to a trench capacitor formed in the trench. The gate length L of this transistor is almost the minimum processing dimension of lithography. The minimum processing size is determined by the lithography limit, and the short channel effect, in which the threshold voltage sharply decreases with miniaturization, and the deterioration of off-leak have become problems.

[0007] As shown in FIG. 7, the connection between the transfer transistor and the trench capacitor is formed by an impurity diffusion layer 7.
9, there is a problem that the accumulated charge in the storage node leaks due to the PN junction of the diffusion layer. In order to prevent this leak current (junction leak), it is necessary to relax a steep profile or lower the concentration of each impurity (particularly, p-well), which has a trade-off relationship with the off-leak characteristic of the transfer transistor.

It is an object of the present invention to provide a semiconductor memory device which solves the problem of junction leak and off-leak characteristics without increasing the cell size. Such a semiconductor memory device maintains a fine cell structure,
A short gate effect can be prevented by securing a sufficient gate length.

A second object of the present invention is to provide a manufacturing method capable of realizing such a semiconductor memory device without a large process change.

[0009]

In order to achieve the above object, in the present invention, a vertical tunnel transistor formed above a trench capacitor is used as a transfer transistor of a DRAM. As a result, almost conventional DRA
A non-volatile memory cell equivalent to 4F ² (2F × 2F; F is the minimum processing size) can be realized while ensuring the operation of the M cell and without any major process change.

More specifically, the semiconductor memory device of the present invention
A semiconductor substrate, a plurality of trench capacitors formed in a matrix on the semiconductor substrate, a plurality of vertical tunnel junction layers embedded on the trench capacitors, and a first direction on the substrate adjacent to the tunnel junction layers. A plurality of word line diffusion layers extending along the plurality of bit lines; and a plurality of bit lines connected to each of the tunnel junction layers and extending in a direction orthogonal to the word line diffusion layers.

The trench capacitors and the vertical tunnel transistors located above the trench capacitors are arranged in a matrix at substantially intersections between word lines and bit lines.

A gate insulating film is located between the tunnel junction layer and the word line diffusion layer, and a part of the trench capacitor, the tunnel junction layer, and a part of the word line diffusion layer form a tunnel junction type transistor. Is configured.

[0013] The tunnel junction layer includes one or more tunnel insulating films. More specifically, it has a laminated structure of two or more layers, for example, a thin tunnel insulating film such as SiN and a polysilicon layer. Such a tunnel junction layer is located above the trench capacitor inside the trench or on the semiconductor substrate outside the trench. As described above, by providing the vertical tunnel junction transistor above the trench capacitor, a DRAM with an improved degree of integration can be realized.

Preferably, the semiconductor memory device further includes a metal silicide covering both the tunnel junction layer and the surface of the word line diffusion layer. This metal silicide has the effect of reducing both the gate resistance above the tunnel junction layer and the source / drain resistance of the diffusion layer.

The word line diffusion layer extends adjacent to both sides or one side of the tunnel junction layer in a cross-sectional shape along the direction in which the word lines extend. When a word line extends adjacent to both sides of the tunnel junction layer, the gate length can be increased to form a wide channel.
The transistor current can be increased. Thereby, the operation speed of the device can be increased.

Still another preferable embodiment of the semiconductor memory device includes a semiconductor substrate, a plurality of trench capacitors formed at predetermined positions in the semiconductor substrate, and a plurality of trench capacitors formed on the semiconductor substrate above each trench capacitor. A gate electrode located along the first direction on the semiconductor substrate adjacent to the tunnel junction layer, and a bit line connected to the tunnel junction layer and extending in a direction orthogonal to the first direction. Having.

The distance between adjacent tunnel junction layers in the direction along the gate electrode is substantially equal to or smaller than the distance between adjacent tunnel junction layers in the direction along the bit line.

In this configuration, the tunnel junction layer is located on the trench capacitor outside the trench. Therefore, there is an advantage that the transistor is less likely to be damaged in the step of forming the tunnel junction layer and has excellent transistor characteristics.

In order to achieve the second object of the present invention, in a method of manufacturing a semiconductor memory device, first, a plurality of trench grooves having a predetermined depth are formed at predetermined positions on a semiconductor substrate in a matrix. Next, a buried diffusion plate electrode in contact with the bottom of each trench is formed in the semiconductor substrate. Next, after a capacitor insulating film is formed on the inner wall of the trench, the inside of the trench is filled with polysilicon or the like to form an electrode in the trench. A diffusion region is formed above the electrode in the trench. Then, a word line diffusion layer extending in the first direction is formed in a region adjacent to the trench on the substrate.
Thereafter, a tunnel junction layer is formed on the diffusion region in the trench. Finally, a bit line connected to the tunnel junction layer and extending in a direction orthogonal to the word line diffusion layer is formed.
According to this manufacturing method, it is possible to manufacture a semiconductor memory device having high integration and eliminating the problem of junction leak and off-leak characteristics without making a significant process change to the conventional trench DRAM manufacturing method.

[0020] The manufacturing method preferably includes, after the step of forming the tunnel junction layer, along the first direction:
The method further includes forming a plurality of element isolation insulating layers deeper than the diffusion layer electrode, and forming a metal silicide covering both the tunnel junction layer and the diffusion layer electrode in a self-aligning manner between adjacent element isolation insulating layers. By providing salicide covering the gate and the source / drain of the transistor, channel resistance can be effectively reduced.

Further, as a method of manufacturing a semiconductor memory device having a structure in which a tunnel junction layer is provided on a trench capacitor outside a trench groove, first, at a predetermined position on a semiconductor substrate,
A plurality of trench grooves having a predetermined depth are formed. A buried diffusion plate electrode in contact with the bottom of each trench is formed inside the semiconductor substrate. After forming the capacitor insulating film on the inner wall of the trench, an electrode is formed inside the trench to a height that matches the surface of the semiconductor substrate. Further, a tunnel junction layer is formed on the entire surface so as to cover the semiconductor substrate and the electrode in the trench, and the tunnel junction layer is processed so as to remain only on the electrode in the trench. A gate electrode is formed adjacent to the processed tunnel junction layer along the first direction on the semiconductor substrate. Finally, a bit line connected to the tunnel junction layer and extending in a direction orthogonal to the gate electrode is formed.

According to this manufacturing method, a predetermined pattern can be formed at a time after the tunnel junction layer is deposited, so that the manufacturing is easy and the tunnel junction layer is not affected by repeated etching and heat treatment. The characteristics of the transistor are improved.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> FIGS. 1 and 2
1 shows a semiconductor memory device according to the first embodiment of the present invention. FIG. 1 is a plan layout of the semiconductor memory device. FIG. 2A is a sectional view taken along the line AA of FIG. 1 (a sectional view taken along the word line 11), and FIG. FIG. 3 is a cross-sectional view (a cross-sectional view as viewed from a direction along a bit line 12).

As shown in FIG. 1, a word line 11 and a bit line 12 extend on a semiconductor substrate at right angles to each other, and a capacitor & formed in a trench at an intersection of the word line 11 and the bit line 12. The transistors 13 are arranged in a matrix.

The pitch of the bit lines is 2F (F is the minimum processing size), and the pitch between the centers of the word lines is 2.5F. Therefore, the occupied area per cell is 5F ² (2F × 2.
5F). The capacitor size of each cell is 1F ×
1.5F. The element isolation region STI (trench isolation film) 14 is formed in a line and space shape along the word line 11.

The semiconductor memory device according to the first embodiment includes:
As shown in FIG. 2, the semiconductor substrate 1, a trench capacitor located inside a plurality of trenches formed in an array on the semiconductor substrate 1, a tunnel junction layer 22 located above the trench capacitor inside the trench, The semiconductor device includes a plurality of diffusion layer electrodes extending in a first direction adjacent to the trench on the substrate, and a plurality of bit lines extending in a direction orthogonal to the diffusion layer.

The semiconductor memory device further includes an element isolation region (STI) 14 extending along the diffusion layer (word line) 11.
And a bit line contact 18 connecting the tunnel junction 22 and the bit line 12, and a buried diffusion plate electrode 20 in contact with a lower portion of the trench in the semiconductor substrate 1.

The trench capacitor includes a buried diffusion plate 20, a capacitor insulating film 16 formed along the inner wall of the trench, and a polysilicon diffusion electrode 21 filled in the trench via the capacitor insulating film 16. .

A part of the polysilicon diffusion electrode 21 of the trench capacitor, a part of the tunnel junction 22, and a part of the word line diffusion layer 11 adjacent to the trench form a tunnel junction transistor. In this case, for example, the word line diffusion layer 11 and the upper part of the polysilicon diffusion electrode 21 of the capacitor are formed as n + type diffusion layers. Bit line contact 1
8 is connected to the uppermost polysilicon gate electrode 23 of the tunnel junction layer.

The tunnel junction layer 22 includes one or more tunnel insulating films 24. The tunnel insulating film 24 is made of, for example, S
iN (silicon nitride). Although not shown, a thin gate oxide film is formed between tunnel junction layer 22 and word line diffusion layer 11.

In the semiconductor memory device of the first embodiment, one side of the trench is in contact with the element isolation insulating layer (STI) 14 and the other side is in contact with the word line diffusion layer 11. The lower end of the word line diffusion layer 11 is located closer to the substrate surface than the lower end of the element isolation insulating layer (STI) 14. That is, the depth of the shallow trench 14 forming the element isolation layer is deeper than the depth of the diffusion layer 11 forming the word line in order to clearly separate cells. In particular,
The thickness of the device isolation layer (STI) 14 is about 1500Å to 2
000 °, and the thickness of the word line diffusion layer 11 is smaller than that.

The semiconductor memory device having such a configuration has both a capacitor in a trench and a vertical tunnel transistor as a transfer transistor. Therefore, unlike a conventional planar transistor structure adjacent to a trench as in the related art, it has a fine structure. Can cope with the change. That is, the cell placed close to the ideal 4F ² cross-point cell located capacitor and a transistor are at a cross point between the word line 11 and bit line 12 can be achieved.

Further, since the transfer transistor is a vertical tunnel transistor, the adverse effect of the short channel effect which occurs when the gate length L is determined by the minimum processing size in the conventional transistor is prevented.

Further, since the tunnel transistor utilizes the tunnel barrier, the problem of junction leakage occurring at the PN junction of the transistor does not occur as in the related art.

As a method of manufacturing this semiconductor memory device,
First, a matrix-shaped trench is formed at a predetermined position of the semiconductor substrate 1 by, for example, gas plasma etching. Thereafter, a buried diffusion plate electrode 20 is formed in the semiconductor substrate in contact with the lower part of the trench groove by ultra-high energy ion implantation. Next, a capacitor insulating film 16 is formed on the inner wall of the trench, and thereafter, polysilicon is charged to a predetermined depth of the trench to form a cell capacitor.

Next, a trench side wall insulating (oxide) film 15 is formed to separate from the upper portion of the trench, and thereafter, an n + diffusion layer 11 extending in a predetermined direction is formed on the semiconductor substrate 1 in contact with the upper portion of the trench by solid phase diffusion. . This diffusion layer 11 becomes a word line.

Next, an n + type polysilicon layer is deposited on the polysilicon 21 deposited to a predetermined depth of the trench, and furthermore, an SiN film 24, a polysilicon film 23,
A film 24 and a polysilicon film 23 are sequentially laminated. Specifically, first, an n + type polysilicon layer is deposited so as to cover the inside of the trench and the surface of the substrate, and the surface is planarized by CMP, and then processed by RIE to a predetermined thickness inside the trench. Next, for the SiN 24 and the polysilicon layer 23, deposition, CMP polishing, and RIE are repeated for each layer,
The tunnel junction 22 is formed as a laminated structure having a predetermined thickness. This tunnel junction 22 forms a tunnel transistor by the n + diffusion layer above the trench capacitor and a part of the n + type word line diffusion 11.

Next, an element isolation insulating layer (STI) 14 which is in contact with one side of the trench and extends in the same direction as the word line diffusion layer 11 but is thicker than the word line diffusion layer 11 is formed.
Formed. Further, a thin silicon oxide film 17 is formed covering the surface of the tunnel junction and the surface of the semiconductor substrate, and an interlayer insulating film is further deposited.

Via holes are formed at predetermined positions of the interlayer insulating film and penetrate through the interlayer insulating film and the silicon oxide film 17 to reach the uppermost portion of the tunnel junction, and are filled with, for example, tungsten to form bit line contacts 18. .

Finally, a bit line 12 connected to the bit line contact 18 and extending in a direction orthogonal to the word line diffusion layer 11 is formed.

As described above, a semiconductor memory device having a vertical tunnel transistor can realize a cross-point type cell structure without a large change from the conventional trench DRAM manufacturing process.

<Second Embodiment> FIGS. 3 and 4 are views of a semiconductor memory device according to a second embodiment of the present invention.
As shown in the plan layout of FIG. 3 and the cross-sectional view of FIG. 4, in the semiconductor memory device of the second embodiment, the word line diffusion layer 31 Stretches. That is, as is apparent from the cross-sectional view taken along the line CC of FIG.
When viewed from the direction along the line, the word line diffusion layer 31 extends on both sides of the trench, and the element isolation layer (STI) 34
Extend a certain distance from the trench. Other configurations are the same as in the first embodiment.

That is, in the second embodiment, the buried diffusion plate 40 and the capacitor insulating film 3 on the inner wall of the trench are formed.
6 and a polysilicon electrode 41 filled in the trench
Thus, a trench capacitor is formed. On the other hand, a tunnel junction 42 formed by laminating a polysilicon film 43 and a tunnel insulating film 24 such as SiN, a word line diffusion layer 31 surrounding the tunnel junction 42, and a diffusion region above the polysilicon electrode 41 form a vertical tunnel transistor. Is configured. Although not shown, a thin gate insulating film is inserted between the tunnel junction layer 42 and the word line diffusion layer 31 as in the first embodiment. Both the capacitor and the transistor are located inside the trench.

In the second embodiment, compared to the first embodiment,
The diffusion layers 31 are evenly located on both sides of the tunnel junction layer 42 when viewed from the direction along the word line. Therefore, the gate potential of the vertical tunnel junction transistor is applied to the diffusion layers 31 on both sides of the trench. As a result, the channel of the tunnel transistor is formed wider, and the amount of current flowing through the channel increases. There is an advantage that the operation speed of the device is improved by increasing the current of the tunnel transistor.

Further, in the present invention, the word line diffusion layer is formed as n +
Although it is a concern that the wiring resistance may be slightly increased due to the use of the type diffusion layer, this problem can also be reduced by forming the word line diffusion layers 31 on both sides of the trench as in the second embodiment. .

<Third Embodiment> FIG. 5 is a sectional view of a semiconductor memory device according to a third embodiment. A feature of the semiconductor memory device of the third embodiment is that a tunnel junction 4 in a trench is formed.
2 and a salicide 59 covering the upper part of the word line diffusion layer 51 of the semiconductor substrate. The reason for providing the salicide 59 is to reduce the wiring resistance when the word line diffusion layer is an n + type diffusion layer, as described in relation to the second embodiment.

The salicide 59 is provided on the polysilicon 43 serving as a gate electrode of a tunnel junction and on the surface of the diffusion layer 51 serving as a source / drain by forming metal silicide simultaneously and in a self-aligned manner. By providing the salicide 59, the channel resistance can be reduced and the channel current required for high-speed operation can be secured. That is, the channel resistance is effectively reduced by lowering the source / drain resistance at the same time as lowering the resistance of the gate electrode.

The salicide 59 is made of titanium silicide (T
In addition to iSi ₂ ), finely-designed devices include cobalt silicide (CoSi ₂ ) and nickel silicide (Ni
Si) or the like. Such a metal silicide forms a metal thin film on the entire surface of the substrate and is relatively high in temperature (500 ° C. to
(50 ° C.). As a result of the heat treatment, silicon (polysilicon) in the gate and source / drain portions reacts with the metal to form metal silicide only in those portions. In the third embodiment, the element isolation layer (STI) 54 functions as a side wall spacer, and metal silicide is formed between the element isolation layer (STI) 54 in a self-aligned manner. After the heat treatment, the unreacted portion of the metal thin film is removed by, for example, chemical etching.

With such a salicide structure, a metal silicide film can be formed in a single process on the gate and on the source / drain in a self-aligned manner, so that the load on the manufacturing process is small.

The semiconductor memory device of the third embodiment can increase the degree of integration to achieve a cell structure close to an ideal cross-point type cell, while further reducing the channel resistance. In addition, by using a tunnel junction transistor, junction leak can be prevented.

<Fourth Embodiment> FIG. 6 is a diagram showing a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 6 (a)
FIG. 6B is a cross-sectional view in the bit line direction (that is, as viewed from the direction along the word line). FIG. 6B is a cross-sectional view in the gate wiring (word line) direction (that is, as viewed from the direction along the bit line). FIG.

The semiconductor memory device according to the fourth embodiment is
The tunnel junction layer 63 is not located inside the trench 65,
It is provided on the trench capacitor outside the trench groove 65.
This semiconductor memory device includes a semiconductor substrate 1 and a semiconductor substrate 1.
A plurality of trench capacitors formed at predetermined positions in the semiconductor substrate 1, a tunnel junction layer 63 formed on the semiconductor substrate 1 above each trench capacitor, and a tunnel junction adjacent to the semiconductor substrate 1 in a predetermined direction. The semiconductor device includes a gate wiring 61 extending between the layers 63 and a bit line 62 connected to the tunnel junction layer 63 and extending in a direction perpendicular to the gate wiring 61. The distance between the tunnel junction layers 63 adjacent in the direction along the gate line 61 is smaller than the distance between the tunnel junction layers 63 adjacent in the direction along the bit line 62. This is because the gate wiring (for example, polysilicon gate wiring) 61 constituting the tunnel junction transistor together with the tunnel junction layer 63 and the diffusion electrode 66 in the trench capacitor functions as a word line.

The structure of the fourth embodiment has an advantage that the tunnel junction can be easily manufactured, as compared with the structure having the tunnel junction inside the trench groove as in the first to third embodiments. In order to provide a laminated structure of thin films inside the trench, after depositing a film covering the trench and the substrate, first, planarization by CMP is performed to remove a step generated on the film surface corresponding to the depression of the trench, and thereafter, , It is necessary to perform a process of processing to a desired thickness inside the trench by RIE for each layer.

On the other hand, when a stacked structure of a tunnel junction is formed on the trench capacitor outside the trench groove 65 as in the fourth embodiment, the height of the inside of the trench is set to match the surface of the semiconductor substrate 1. Is filled with a capacitor electrode (for example, polysilicon), and SiN (tunnel insulating film) and polysilicon are sequentially deposited on the entire surface of the flattened substrate. Thereafter, the transfer transistor can be formed by processing the transistor in a batch. The batch processing after the lamination not only simplifies the manufacturing in each step, but also has the advantage that the characteristics of the transistor are stabilized because there is no influence of repeated etching or chemical mechanical polishing.

As a specific manufacturing method, first, a trench 65 having a predetermined depth is formed at a predetermined position on the semiconductor substrate 1.
Are formed. The trenches 65 are arranged and formed in a matrix on the semiconductor substrate, and the interval between adjacent trenches is such that the interval along the first direction on the semiconductor substrate 1 is the second direction orthogonal to the first direction. Is formed so as to be substantially equal to or smaller than the interval along.

Next, a buried diffusion plate electrode 60 that contacts the bottom of each trench is formed inside the semiconductor conductor substrate 1. After forming a capacitor insulating film (not shown) on the inner wall of the trench groove 65, the inside of the trench groove is filled with, for example, polysilicon to a height corresponding to the surface of the semiconductor substrate to form a capacitor electrode 66.

Next, as described above, SiN and a polysilicon layer are sequentially deposited to cover the semiconductor substrate 1 and the in-trench electrode 66, thereby forming a tunnel junction layer 63 on the entire surface.
After that, the tunnel junction layer 63 is etched so as to remain only on the in-trench electrode 66. A gate wiring (electrode) 61 along the first direction on the semiconductor substrate is formed in self-alignment with, for example, polysilicon, adjacent to the processed tunnel junction layer.

In this case, the gate wiring 61 is as shown in FIG.
As shown in FIG. 5, the semiconductor device 1 is formed so as to fill the space between the tunnel junction layers 63 located on the semiconductor substrate 1 along the first direction. In the case of using this method, the interval between the trenches along the first direction is made smaller than the interval along the direction orthogonal to the first direction, and the gate wiring is formed between the tunnel junction layers 63 along the first direction. 61 is embedded in a self-aligned manner.
Alternatively, after the trench junction layer 63 is buried so as to surround it, processing is performed by isotropic etching so that the interval between the gate wirings 61 is increased along the second direction as shown in FIG.

When the gate wiring 61 is formed by, for example, lithography, the interval between adjacent tunnel junction layers can be made substantially equal in the first and second directions.

Finally, it is connected to the tunnel junction layer 63,
A bit line 62 extending in a second direction orthogonal to the gate wiring 61 is formed.

According to such a manufacturing method, a semiconductor memory device having stable characteristics of a tunnel junction transistor can be manufactured by a relatively easy manufacturing process.

As for the degree of integration, the first to third embodiments will be described.
Like the third embodiment, Ki can achieve cell placement close to 4F ² cross-point cell, it is possible to prevent deterioration of the junction leakage and off-leak.

[0064]

According to the semiconductor memory device of the present invention, by providing a tunnel junction transistor in a trench or on an upper portion of a trench, a cell arrangement close to an ideal cross-point type cell structure is obtained and a highly integrated nonvolatile memory is provided. Memory can be achieved.

The problem of junction leak and off-leak caused by the PN junction can be solved by the tunnel junction transistor.

The method of manufacturing a semiconductor memory device according to the present invention can achieve a highly integrated cell configuration without significantly changing the conventional trench DRAM process.

Further, when a tunnel junction layer is provided on a trench capacitor outside a trench groove, a semiconductor memory device having stable transistor performance can be manufactured by a relatively easy manufacturing process.

[Brief description of the drawings]

FIG. 1 is a plan layout view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor memory device shown in FIG. 1 as viewed from a direction along word lines and bit lines.

FIG. 3 is a plan layout diagram of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a cross-sectional view of the semiconductor memory device shown in FIG. 3 as viewed from a direction along word lines and bit lines.

FIG. 5 is a cross-sectional view of a semiconductor memory device according to a third embodiment of the present invention as viewed from a direction along a word line.

FIG. 6 is a cross-sectional view of a semiconductor memory device according to a fourth embodiment of the present invention as viewed from a direction along word lines and bit lines.

FIG. 7 is a sectional view of a conventional DRAM cell in a bit line direction.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 11, 31, 51 word line diffusion layer (diffusion layer electrode) 12, 32, 52, 62 bit line 14, 34, 54, 64 element isolation insulating layer (STI) 16, 36, 56, 66 capacitor insulating film 17, 37, 57, 67 Silicon oxide film 18, 38, 58, 68 Bit line contact 20, 40, 50, 60 Buried diffusion plate electrode 21, 41 Polysilicon in trench (polysilicon electrode) 22, 42, 63 Tunnel junction Layer 61 Gate wiring

Claims (19)

[Claims] A semiconductor substrate; a capacitor formed at a predetermined position in the semiconductor substrate; a tunnel junction layer located on the capacitor; a diffusion layer electrode located adjacent to the tunnel junction layer; And a bit line connected to the tunnel junction. 2. The semiconductor device further comprises an insulating film located between the tunnel junction layer and the diffusion layer electrode, wherein the capacitor, the tunnel junction layer, and the diffusion layer electrode form a tunnel junction transistor. 2. The semiconductor memory device according to claim 1, wherein: 3. A semiconductor substrate; a plurality of trench capacitors formed in a matrix on the semiconductor substrate; a plurality of vertical tunnel junction layers located on the trench capacitors; A semiconductor memory device comprising: a plurality of diffusion layer electrodes extending along a first direction of the substrate; and a plurality of bit lines connected to each of the tunnel junction layers and extending in a direction orthogonal to the diffusion layer electrodes. 4. The semiconductor device according to claim 1, further comprising an insulating film located between said tunnel junction layer and said diffusion layer electrode, wherein said trench capacitor, said vertical tunnel junction layer, and said diffusion layer electrode comprise a tunnel junction transistor. 4. The semiconductor memory device according to claim 3, wherein: 5. The semiconductor memory device according to claim 1, wherein said tunnel junction layer includes at least one tunnel insulating film. 6. The semiconductor memory device according to claim 1, further comprising an element isolation insulating layer extending in parallel with said diffusion layer electrode and having a thickness greater than a thickness of said diffusion layer electrode. 7. The device according to claim 1, further comprising an element isolation insulating layer formed between the adjacent vertical tunnel junction layers, wherein a bottom surface of the element isolation insulating layer is located deeper than a bottom surface of the diffusion electrode. 5. The semiconductor memory device according to claim 3, wherein: 8. The semiconductor memory device according to claim 3, wherein said plurality of trench capacitors are located at substantially intersections between said diffusion layer electrodes and said bit lines. 9. The semiconductor memory device according to claim 3, wherein said vertical tunnel junction layer is located on a trench capacitor inside the trench. 10. The semiconductor memory device according to claim 9, further comprising a metal silicide covering upper portions of said tunnel junction layer and said diffusion layer electrode. 11. The device according to claim 1, wherein the diffusion layer electrode is located adjacent to both sides of the tunnel junction layer in a cross-sectional shape viewed from a direction in which the diffusion layer electrode extends. Semiconductor storage device. 12. The device according to claim 1, wherein the diffusion layer electrode extends adjacent to one side of the tunnel junction layer in a cross-sectional shape viewed from a direction in which the diffusion layer electrode extends.
Or the semiconductor memory device according to 3. 13. A semiconductor substrate; a plurality of trench capacitors formed at predetermined positions in the semiconductor substrate; a plurality of tunnel junction layers formed above the trench capacitors on the semiconductor substrate; A gate electrode located adjacent to the tunnel junction layer along the first direction on the semiconductor substrate; and a bit line connected to the tunnel junction layer and extending in a direction orthogonal to the first direction. Semiconductor storage device. 14. The semiconductor memory device according to claim 13, wherein the tunnel junction layer, the trench capacitor, and the gate electrode form a tunnel junction transistor. 15. The device according to claim 13, wherein the tunnel junction layer includes at least one tunnel insulating film.
3. The semiconductor memory device according to claim 1. 16. A step of forming a plurality of trench grooves having a predetermined depth at predetermined positions on a semiconductor substrate, and a step of forming a buried diffusion plate electrode in contact with the bottom of each of the trench grooves inside the semiconductor substrate. Forming a capacitor insulating film on the inner wall of the trench groove, forming an electrode inside the trench groove, forming a diffusion region above the electrode in the trench, and adjoining the trench groove on the substrate. Forming a diffusion layer electrode extending in a first direction in a region to be formed; forming a tunnel junction layer on the diffusion region in the trench; being connected to the tunnel junction layer and orthogonal to the diffusion layer electrode Forming a bit line extending in the direction. 17. A step of forming a plurality of element isolation insulating layers deeper than the diffusion layer electrode along the first direction after the step of forming the tunnel junction layer; 17. The method according to claim 16, further comprising: forming a metal silicide covering the tunnel junction layer and the diffusion layer electrode in a self-aligning manner. 18. A step of forming a plurality of trench grooves having a predetermined depth at predetermined positions on a semiconductor substrate, and a step of forming a buried diffusion plate electrode in contact with the bottom of each of the trench grooves inside the semiconductor substrate. Forming a capacitor insulating film on the inner wall of the trench, and then forming an electrode in the trench to a height corresponding to the surface of the semiconductor substrate; and forming a tunnel junction covering the semiconductor substrate and the electrode in the trench. Forming a layer over the entire surface; processing the tunnel junction layer so as to remain only on the electrode in the trench; and adjoining the tunnel junction layer along a first direction on the semiconductor substrate. Forming a gate electrode; forming a bit line connected to the tunnel junction layer and extending in a direction orthogonal to the gate electrode And a method of manufacturing a semiconductor memory device. 19. The method according to claim 18, wherein the step of forming a gate electrode includes the step of forming a gate electrode between adjacent tunnel junction layers in a self-aligned manner.