JP2002134483A - Etching liquid, method for etching, method for manufacturing capacitor and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove a surface layer by selectively etching the lower electrode made of an amorphous silicon, while preventing etching of a contact electrode made of a crystalline silicon in a stacked capacitor of cylindrical structure. SOLUTION: A method for manufacturing the capacitor comprises the steps of forming the lower electrode 20 made of an amorphous silicon on the contact electrode 17 made of a polycrystalline silicon and a sidewall film 15, then etching the electrode 20 through wet etching, by using an aqueous solution containing NH4OH and H2O2 as an etching liquid, and removing the surface layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an etching solution,
The present invention relates to an etching method, a method for manufacturing a capacitor, and a method for manufacturing a semiconductor device, and is suitable for, for example, manufacturing a semiconductor memory.

[0002]

2. Description of the Related Art In a semiconductor device, especially a semiconductor memory, a capacitor is used as information holding means. In recent years, the area occupied by a capacitor in a memory cell has been reduced with the increase in integration of a semiconductor memory. This results in a reduction in the capacitance of the capacitor. However, a certain capacitance should be secured in order to sufficiently fulfill the function of the memory cell, and in order to secure a sufficient margin against soft errors and noise caused by α rays, the capacitance must be increased. No.

In order to increase the capacitance of a capacitor, a method using a ferroelectric film having a high dielectric constant, a method for increasing the electrode area of the capacitor, and the like have been proposed. Among them, as a method of increasing the electrode area, a method using a hemispherical grain (HSG) film (for example,
JP-A-8-306646). In this method, first, a nucleus is formed by irradiating silane (SiH ₄ ) to the surface of an amorphous silicon film containing impurities, and then annealing is continuously performed. Hemispherical grains (HSG) are formed by migration so as to gather at the center.

[0004]

However, when an HSG is formed by this method, if a natural oxide film, an organic substance, silicon microcrystals, etc. are present on the surface of the amorphous silicon film, these suppress the migration of silicon atoms. Therefore, HSG cannot be formed. Therefore, cleaning with HF is performed immediately before HSG formation. However, organic substances or silicon microcrystals present in the initial layer of the amorphous silicon film serving as a lower electrode in a capacitor having a cylindrical structure can be subjected to HF treatment. Since it cannot be removed, growth on the outer wall of the cylinder is hindered. Therefore, in order to remove the initial layer, conventionally, a mixed liquid of NH ₄ F and HF, for example, a chemical liquid mixing ratio of NH ₄ F: HF = 20
The layer containing the organic substance or the silicon microcrystal was etched by a ratio of 0: 1.
Since the etching selectivity of amorphous silicon to polycrystalline silicon is as low as about 0.5, in the case of a cylinder having a PSC (Poly Shrink Contact) which is a contact electrode made of crystallized silicon, as shown in FIG. At the same time, they are etched, causing problems such as poor contact.

SUMMARY OF THE INVENTION Therefore, the problem to be solved by the present invention is to selectively etch a lower electrode made of an amorphous silicon film while preventing a contact electrode made of crystalline silicon from being etched in a stacked capacitor having a cylinder structure. An object of the present invention is to provide an etching method capable of removing a surface layer by etching.

[0006] The problem to be solved by the present invention is, more generally, to prevent the etching of crystalline silicon when etching a substrate having crystalline silicon and amorphous silicon exposed on the surface. It is another object of the present invention to provide an etching method capable of selectively etching amorphous silicon to remove a surface layer and a method of manufacturing a semiconductor device having such an etching step.

Another problem to be solved by the present invention is that
When etching is performed on a substrate having crystalline silicon and amorphous silicon exposed on the surface, amorphous silicon is selectively etched to remove a surface layer while preventing etching of crystalline silicon. It is to provide an etching solution that can be used.

[0008]

In order to solve the above-mentioned problems of the prior art, the present inventor conducted various experiments and conducted intensive studies, and as a result, selected amorphous silicon over crystalline silicon. A new etching technique that can be etched efficiently has been found. This etching technique will be described below. As described above, a mixed solution of NH ₄ F and HF (NH ₄ F: HF = 200: 1), which has been conventionally used as an etching solution for amorphous silicon, is obtained by etching amorphous silicon with respect to crystalline silicon. Considering that the etching selectivity is about 0.5, which is considerably smaller than 1, here, "the amorphous silicon can be selectively etched with respect to the crystalline silicon" means that the amorphous silicon can be selectively etched with respect to the crystalline silicon. It means that the etching selectivity of amorphous silicon (the etching rate of amorphous silicon / the etching rate of crystalline silicon) is 1 or more.

Accordingly, the present inventor has conducted a search for an etchant capable of selectively etching the amorphous silicon with respect to crystalline silicon, NH ₄
An aqueous solution containing OH and H ₂ O ₂ has been found to be an etchant suitable for this purpose. And then,
The mixing ratio of the etching solution optimal for etching and the liquid temperature during etching were also studied. Some of the results are shown in FIGS.

FIG. 1 shows a chemical mixture ratio of an etching solution of NH _4.
OH: H ₂ O ₂ : H ₂ O = 1: 1: y, and the change of the etching selectivity when y is changed is shown. However, the liquid temperature was 80 ° C. FIG. 1 shows that the etching selectivity tends to slightly decrease as y increases, but the etching selectivity is 1 or more.

FIG. 2 shows a chemical mixture ratio of the etching solution to NH _4.
OH: H ₂ O ₂ : H ₂ O = 1: x: 20, and the change of the etching selectivity when x is changed is shown. However,
The liquid temperature was 60 ° C. FIG. 2 shows that the etching selectivity tends to increase as x increases, and that the etching selectivity is 1 or more.

FIG. 3 shows that the chemical mixture ratio of the etching solution is NH _4.
OH: H ₂ O ₂ : H ₂ O = 1: x: 150, and the change of the etching selectivity when x is changed is shown. However, the liquid temperature was 80 ° C. FIG. 3 shows that the etching selectivity is 1.

FIG. 4 shows that the chemical mixture ratio of the etching solution is NH _4.
OH: H ₂ O ₂ : H ₂ O = 1: 1: 20, and shows the change of the etching selectivity when the liquid temperature is changed. From FIG. 3, the etching selectivity is 1 or more within the range of the measured liquid temperature.

FIG. 5 shows the mixing ratio of the etching solution to NH _4.
OH: H ₂ O ₂ : H ₂ O = 1: 1: 150, and shows the change of the etching selectivity when the liquid temperature is changed. FIG.
The etching selectivity is 1 within the range of the measured liquid temperature.

From the results of experiments conducted by the present inventor, generally speaking, the temperature of an etching solution composed of an aqueous solution containing NH ₄ OH and H ₂ O ₂ is required to obtain an etching selectivity of at least one. In this case, the temperature is preferably higher than room temperature, more specifically, 30 ° C. or higher. Further, the smaller the ratio of H ₂ O, the higher the etching selectivity tends to be. Further, the ratio between NH ₄ OH and H ₂ O ₂ may be the same or more. More specifically, the chemical mixture ratio of the etching solution is NH ₄ OH: H ₂ O ₂ : H ₂ O = 1: (1 to 10
0 or less): (greater than 0 and less than or equal to 150), and the liquid temperature is 3
0 ° C. or higher, preferably NH ₄ OH: H ₂
O ₂ : H ₂ O = 1: (1 or more and 5 or less) :( more than 0 and 50 or less), and it was concluded that the liquid temperature should be 60-80 ° C.

On the other hand, the above-mentioned etching technique is wet etching, but dry etching is also available as an etching technique for selectively etching amorphous silicon with respect to crystalline silicon. Specifically, for example, amorphous silicon can be selectively etched with respect to crystalline silicon by dry etching using a fluorine-based gas.

According to the present invention, as a result of further intensive studies from various viewpoints based on the above-mentioned studies by the present inventors,
It was devised. That is, in order to solve the above-mentioned problems, the first invention of the present invention is directed to NH ₄ OH and H ₂ O
_2. An etching solution comprising an aqueous solution containing

This etching solution is more specifically
For example, if the chemical mixture ratio is NH_FourOH: H _TwoO_Two: H_TwoO =
1: x: y, 1 ≦ x ≦ 100, 0 <y ≦ 15
0, and the liquid temperature during etching is 30 ° C. or higher and the boiling point or lower.
I do. Amorphous silicon etch over crystalline silicon.
In order to increase the etching selectivity, this etching
The liquid preferably has a chemical mixture ratio of NH_FourOH: H_TwoO_Two:
H_TwoWhen O = 1: x: y, 1 ≦ x ≦ 5, 0 <y ≦
50 and the liquid temperature during etching is 60 ° C or higher and 80 ° C or lower
And An example of a typical chemical mixture ratio of this etchant
For example, NH_FourOH: H_TwoO_Two: H_TwoO = 1: 1: 1
0.

According to a second aspect of the present invention, an amorphous silicon is selectively etched with respect to crystalline silicon by etching a substrate having crystalline silicon and amorphous silicon exposed on the surface. An etching method characterized in that the etching method is performed.

According to a third aspect of the present invention, an electrode made of amorphous silicon and a portion made of crystalline silicon are etched on a substrate whose surface is exposed, whereby a portion made of crystalline silicon is etched. A method for manufacturing a capacitor, comprising a step of selectively etching an electrode made of amorphous silicon.

According to a fourth aspect of the present invention, an amorphous silicon is selectively etched with respect to crystalline silicon by etching a substrate having crystalline silicon and amorphous silicon exposed on the surface. A method of manufacturing a semiconductor device, comprising the steps of:

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a capacitor, comprising etching a substrate having a capacitor electrode made of amorphous silicon and a portion made of crystalline silicon exposed on the surface. A step of selectively etching a capacitor electrode made of amorphous silicon with respect to a portion made of crystalline silicon by performing the method.

In the second to fifth aspects of the present invention,
Typically, an amorphous silicon or an electrode made of amorphous silicon (or an electrode for a capacitor) is selectively etched with respect to crystalline silicon or a part made of crystalline silicon by a wet etching method. In this wet etching method, an etching solution according to the first invention of the present invention, that is, an aqueous solution containing NH ₄ OH and H ₂ O ₂ can be used. If necessary, amorphous silicon may be selectively etched with respect to crystalline silicon by a dry etching method.

In the third and fifth aspects of the present invention, typically, the electrode made of amorphous silicon is a lower electrode in a stacked capacitor having a cylindrical structure, and the portion made of crystalline silicon is a contact electrode. is there. In the present invention, crystalline silicon includes monocrystalline silicon in addition to polycrystalline silicon.

According to the present invention configured as described above, it has been difficult to selectively etch amorphous silicon with respect to crystalline silicon by the conventional etching technique. By being able to selectively etch amorphous silicon, while preventing the etching of crystalline silicon,
The surface layer can be removed by etching the amorphous silicon.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the following embodiments, the same or corresponding parts are denoted by the same reference numerals. 6 to 14 show a method of manufacturing a semiconductor memory according to one embodiment of the present invention.

In this embodiment, first, as shown in FIG. 6, a field oxide film 12 made of silicon dioxide is formed on a semiconductor substrate 11 such as a silicon substrate.
The semiconductor substrate 11 is separated into an active region and a field region. Next, after an interlayer insulating film 13 is formed on the entire surface of the semiconductor substrate 11, an etching stopper layer 14 for removing a later-described cylinder core layer 18 by etching is formed on the entire surface. As the etching stopper layer 14, for example, a silicon nitride film having a thickness of 100 nm formed by a low pressure CVD method is used. Thereafter, an antireflection film 15 is formed on the etching stopper layer 14. As the antireflection film 15, a silicon nitride film having a thickness of 200 nm formed by a plasma CVD method is used.

Next, as shown in FIG. 7, after a resist pattern (not shown) having a predetermined shape is formed on the antireflection film 15 by lithography, the resist pattern is used as a mask to form, for example, reactive ion etching (RIE). Anti-reflection film 15 and etching stopper layer 1
4 is anisotropically etched to form a contact hole reaching the interlayer insulating film 13. Next, an amorphous silicon film or a polycrystalline silicon film is formed on the entire surface, and anisotropic etching is performed to form a sidewall film 16 on the side wall of the contact hole.

Next, as shown in FIG. 8, a contact hole C reaching the semiconductor substrate 11 is formed by anisotropically etching the interlayer insulating film 13 using the sidewall film 16 as a mask.

Next, as shown in FIG. 9, after a conductive film is embedded in the contact hole C, a chemical mechanical polishing (C
By performing MP) or isotropic etching, a contact electrode 17 connected to a diffusion layer (not shown) formed in the semiconductor substrate 11 is formed. This contact electrode 17 is made of, for example, amorphous silicon or polycrystalline silicon containing phosphorus (P).

Next, as shown in FIG. 10, the antireflection film 15 made of a silicon nitride film is selectively removed by wet etching using diluted hydrofluoric acid as an etchant.

Next, as shown in FIG. 11, a cylinder core layer 18 made of, for example, a silicon oxide-based material is
It is formed with a thickness of about m. The silicon oxide-based material forming the cylinder core layer 18 is, for example, borophosphosilicate glass (BPS).
G), and after forming this BPSG, reflow is performed at 700 ° C. for 20 minutes to form the cylinder core layer 18. When the sidewall film 16 and the contact electrode 17 are formed of an amorphous silicon film, the amorphous silicon film is crystallized by annealing at the time of the reflow, and becomes polycrystalline silicon.

Next, a resist pattern (not shown) having a predetermined shape is formed on the cylinder core layer 18 by lithography, and the cylinder core layer 18 is etched using the resist pattern as a mask, as shown in FIG. Then, the upper portions of the contact electrodes 7 and the sidewall films 16 are exposed. Next, an amorphous silicon film 19 is formed on the entire surface so as to cover the inner wall of the core pattern.

Next, as shown in FIG.
The portion of the amorphous silicon film 19 on the cylinder core layer 18 is removed by polishing. Thereafter, the cylinder core layer 18 made of a silicon oxide-based material is selectively removed by wet etching using dilute hydrofluoric acid as an etchant. At this time, since the interlayer insulating film 13 is covered with the etching stopper layer 14, it is not affected by the etching.

Thus, as shown in FIG. 14, a cylindrical lower electrode 20 made of the amorphous silicon film 19 left only on the inner wall of the core pattern is formed.

Next, by performing wet etching using a mixed aqueous solution of NH ₄ OH and H ₂ O ₂ as an etching solution, the surface layer of the lower electrode 20 containing an organic substance or silicon microcrystals is, for example, about 5 to 10 nm. Remove by etching. The chemical mixture ratio of the mixed aqueous solution of NH ₄ OH and H ₂ O ₂ is, for example, NH ₄ OH: H ₂ O ₂ : H ₂ O =
The liquid temperature is set to 60 ° C. using a material having a ratio of 1: 1: 10.

Here, as described above, conventionally, N
A mixed solution of H ₄ F and HF, specifically, NH ₄ F: HF =
The layer containing the organic substance or the silicon microcrystal of the lower electrode 20 was etched away by 200: 1. However, in the case of a mixed solution of NH ₄ F and HF, the lower electrode 2
0 than the amorphous silicon forming the side wall film 1
6 and the crystallized silicon forming the contact electrode 17 have a higher etching rate.
m of the side wall film 16
And the problem that the contact electrode 17 is eroded. This erosion causes a contact failure, and even when the contact failure does not occur, a short-circuit failure between cylinders has occurred.

On the other hand, when the chemical mixture ratio is, for example, NH ₄ O
In the wet etching using the etching according to the present invention in which H: H ₂ O ₂ : H ₂ O = 1: 1: 10, as shown in FIG. 15, the etching selectivity of amorphous silicon to crystalline silicon (=) (Etching rate of amorphous silicon / etching rate of crystalline silicon) is extremely large, 3 or more, so that only the surface layer of the lower electrode 20 containing organic matter or silicon microcrystals is isotropically etched and removed without causing contact failure. be able to.

Next, silane (SiH ₄ ) or disilane (Si ₂ H ₆ ) gas is supplied into the reaction chamber of the CVD apparatus to selectively form silicon nuclei on the surface of the lower electrode 20 made of an amorphous silicon film. Form. Thereafter, the supply gas is stopped, and annealing is performed under an ultra-high vacuum or an inert gas, whereby the silicon HSG 21
To form At this time, since the lower electrode 20 of the cylinder is formed of a clean amorphous silicon film containing no organic substance or silicon microcrystal on the surface, a uniform silicon HSG 21 is formed on the inner wall and the outer wall, and the abnormal HSG growth occurs. Did not occur. Also, the side wall film 16
And the etching amount of the contact electrode 17 is lower electrode 2
By being much less than 0, no contact failure or the like occurred. FIG. 16 shows a state after the silicon HSG 21 is grown.

Thereafter, a dielectric film and an upper electrode (not shown) are formed to form a stacked capacitor having a cylinder structure, and necessary steps are executed to complete a target semiconductor memory.

As described above, according to this embodiment,
The lower electrode 20 made of amorphous silicon film, NH ₄ OH
And H ₂ O ₂ mixed aqueous solution of, for example, chemical-liquid mixing ratio is NH ₄
OH: H ₂ O ₂ : H ₂ O = 1: 1: 10 is etched by wet etching using an etchant, so that the sidewall film 16 and the contact electrode 17 are prevented from being etched while the lower portion is etched. Electrode 20
The surface layer containing organic substances or silicon microcrystals can be removed by etching. Therefore, it is possible to form a highly reliable stacked capacitor having a cylinder structure while preventing a contact failure and abnormal HSG growth of the lower electrode 20.

Next, a method of manufacturing a semiconductor memory according to another embodiment of the present invention will be described. In the other embodiment, the structure of the capacitor of the memory cell is different from that of the above-described embodiment. Specifically, the capacitor has a simple stack structure instead of a cylinder structure.

That is, in this other embodiment,
As shown in FIG. 17, a flat lower electrode 20 is formed by patterning an amorphous silicon film by etching.
Is formed so as to be connected to the contact electrode 17 made of polycrystalline silicon, and then the silicon HSG 21 is formed on the surface of the lower electrode 20. Before that, as in the above-described embodiment, A mixed aqueous solution of NH ₄ OH and H ₂ O ₂ , for example, a chemical solution having a mixing ratio of NH ₄ OH: H
_The lower electrode 20 is etched by wet etching using a mixture of 2O ₂ : H ₂ O = 1: 1: 10 as an etchant.

According to this embodiment, similarly to the above-described embodiment, the surface layer of the lower electrode 20 containing the organic substance or the silicon microcrystal is removed by etching while preventing the contact electrode 17 from being etched. it can. Therefore, a highly reliable stacked capacitor can be formed while preventing the lower electrode 20 from contact failure and abnormal HSG growth.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical concept of the present invention are possible.

For example, the numerical values, structures, shapes, materials, processes, and the like described in the above embodiments are merely examples, and different numerical values, structures, shapes, materials, processes, and the like may be used as necessary. it can.

[0047]

As described above, according to the present invention, amorphous silicon and crystalline silicon are formed by wet etching using an aqueous solution containing NH ₄ OH and H ₂ O ₂ as an etching solution. By performing etching on the substrate exposed on the surface, amorphous silicon can be selectively etched with respect to crystalline silicon, whereby, for example, in a stacked capacitor having a cylinder structure, the amorphous silicon is formed of crystalline silicon. The surface layer can be removed by selectively etching the lower electrode made of the amorphous silicon film while preventing the contact electrode from being etched.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining an etching solution according to the present invention.

FIG. 2 is a schematic diagram for explaining an etching solution according to the present invention.

FIG. 3 is a schematic diagram for explaining an etching solution according to the present invention.

FIG. 4 is a schematic diagram for explaining an etching solution according to the present invention.

FIG. 5 is a schematic diagram for explaining an etching solution according to the present invention.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to one embodiment of the present invention;

FIG. 8 is a sectional view for explaining the method for manufacturing the semiconductor memory according to the embodiment of the present invention;

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to the embodiment of the present invention;

FIG. 10 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to one embodiment of the present invention;

FIG. 11 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to one embodiment of the present invention;

FIG. 12 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to one embodiment of the present invention;

FIG. 13 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to the embodiment of the present invention;

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the semiconductor memory according to the embodiment of the present invention;

FIG. 15 is a schematic diagram comparing the etching selectivity of a mixed solution of NH ₄ OH, H ₂ O ₂ and H ₂ O and a mixed solution of NH ₄ and HF.

FIG. 16 is a schematic diagram showing a state after forming a silicon HSG of the semiconductor memory according to the embodiment of the present invention;

FIG. 17 is a sectional view illustrating the method of manufacturing the semiconductor memory according to another embodiment of the present invention;

FIG. 18 is a schematic diagram for explaining a problem of the related art.

[Explanation of symbols]

11 ··· semiconductor substrate, 13 ··· interlayer insulating film, 14 ·
..Etching stopper layer, 15... Antireflection film,
16 sidewall film, 17 contact electrode, 18 cylinder core layer, 19 amorphous silicon film, 20 lower electrode, 21 HS
G

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomoyuki Hirano 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hayato Iwamoto 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Masaki Kuramae 2-844-2 Kozoji-cho, Kasugai-shi, Aichi F-term in Fujitsu VSI Ltd. (reference) 5F043 AA10 AA11 BB03 BB04 DD02 GG04 5F083 AD24 AD62 JA56 MA01 MA06 MA17 PR05 PR33 PR40

Claims (24)

[Claims] 1. An etching solution comprising an aqueous solution containing NH ₄ OH and H ₂ O ₂ . 2. The chemical liquid mixture ratio is NH ₄ OH: H ₂ O ₂ : H
₂ O = 1: x: y, 1 ≦ x ≦ 100, 0 <y
The etching solution according to claim 1, wherein ≤ 150. 3. The etching solution according to claim 2, wherein the solution temperature is not lower than 30 ° C. and not higher than the boiling point. 4. The chemical solution mixing ratio is NH ₄ OH: H ₂ O ₂ : H
_{When 2} O = 1: x: y, 1 ≦ x ≦ 5, 0 <y ≦ 5
2. The etching solution according to claim 1, wherein the value is 0. 5. The etching solution according to claim 4, wherein the solution temperature is 60 ° C. or more and 80 ° C. or less. 6. The chemical liquid mixture ratio is NH ₄ OH: H ₂ O ₂ : H
_2. The etching solution according to claim 1, wherein ₂ O = 1: 1: 10. 7. The method according to claim 7, wherein the amorphous silicon is selectively etched with respect to the crystalline silicon by performing etching on a base having the crystalline silicon and the amorphous silicon exposed on the surface. An etching method characterized by the above-mentioned. 8. The etching method according to claim 7, wherein the amorphous silicon is selectively etched with respect to the crystalline silicon by a wet etching method. 9. The method as set forth in claim 1, wherein the wet etching method comprises:
9. The etching method according to claim 8, wherein an aqueous solution containing H ₄ OH and H ₂ O ₂ is used as an etching solution. 10. The etching method according to claim 7, wherein said amorphous silicon is selectively etched with respect to said crystalline silicon by a dry etching method. 11. An etching process is performed on a substrate having an electrode made of amorphous silicon and a portion made of crystalline silicon exposed on the surface, so that the portion made of crystalline silicon is etched from the amorphous silicon. A method for manufacturing a capacitor, comprising a step of selectively etching an electrode. 12. The method for manufacturing a capacitor according to claim 11, wherein the electrode made of amorphous silicon is selectively etched by a wet etching method with respect to the portion made of crystalline silicon. . 13. The wet etching method,
NH_FourOH and H_TwoO _TwoAqueous solution containing
13. The key according to claim 12, wherein the key is used.
Manufacturing method of Japan. 14. The method of manufacturing a capacitor according to claim 11, wherein the electrode made of amorphous silicon is selectively etched by a dry etching method with respect to the portion made of crystalline silicon. . 15. The capacitor according to claim 11, wherein the electrode made of amorphous silicon is a lower electrode in a stacked capacitor having a cylindrical structure, and the portion made of crystalline silicon is a contact electrode. Production method. 16. A step of selectively etching the amorphous silicon with respect to the crystalline silicon by etching a substrate having crystalline silicon and amorphous silicon exposed on the surface. A method for manufacturing a semiconductor device, comprising: 17. The method according to claim 16, wherein said amorphous silicon is selectively etched with respect to said crystalline silicon by a wet etching method. 18. The method according to claim 18, wherein in the wet etching method,
NH_FourOH and H_TwoO _TwoAqueous solution containing
18. The half according to claim 17, wherein the half is used.
A method for manufacturing a conductor device. 19. The method of manufacturing a semiconductor device according to claim 16, wherein said amorphous silicon is selectively etched with respect to said crystalline silicon by a dry etching method. 20. A method of manufacturing a semiconductor device having a capacitor, comprising etching a substrate having a capacitor electrode made of amorphous silicon and a portion made of crystalline silicon exposed on the surface. A step of selectively etching the capacitor electrode made of amorphous silicon for a portion made of amorphous silicon. 21. The semiconductor device according to claim 20, wherein the capacitor electrode made of amorphous silicon is selectively etched by a wet etching method with respect to the portion made of crystalline silicon. Manufacturing method. 22. In the above wet etching method,
NH_FourOH and H_TwoO _TwoAqueous solution containing
22. The half according to claim 21, wherein the half is used.
A method for manufacturing a conductor device. 23. The semiconductor device according to claim 20, wherein the capacitor electrode made of amorphous silicon is selectively etched by a dry etching method with respect to the portion made of crystalline silicon. Manufacturing method. 24. The capacitor according to claim 20, wherein the capacitor electrode made of amorphous silicon is a lower electrode in a stacked capacitor having a cylinder structure, and the portion made of crystalline silicon is a contact electrode. A method for manufacturing a semiconductor device.