JP2002133897A - Semiconductor measuring device, tool for measuring semiconductor, and semiconductor measuring method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor measuring system in which the algorithm of analyzing defect can be easily changed and test efficiency is high. SOLUTION: In a semiconductor measuring system testing a semiconductor device 1 provided with a function by which self diagnosis of a built-in memory cell can be performed and having a defective cell storing means 6 storing defective cell information of a memory cell diagnosed by itself, a defect relief analyzing means 7 performing relief analysis of a memory cell based on defective cell information of the defective cell storing means 6 is provided in a probe card 2 connecting electrically semiconductor device 1 and a semiconductor measuring device 3, and this defect relief analyzing means 7 is made to be logical (e.g. FPGA) so as to be able to rewrite from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor measuring device for testing a semiconductor device having a built-in memory cell array and having a self-diagnosis function, a jig for semiconductor measurement,
The present invention relates to a semiconductor measurement method.

[0002]

2. Description of the Related Art In a conventional semiconductor measuring apparatus (ATE),
When the bus width of a semiconductor device with a built-in memory cell array, which is a device under test, becomes wider, it becomes difficult to connect all signals,
The test efficiency is reduced due to a decrease in the number of same sides and an increase in test time.

Therefore, a self-diagnosis function (Built In Self Te
st), and a semiconductor device in which a defective cell storage means and a defect remedy analysis means having the same bus width as the memory cell array are built in as a logic circuit is invented. Compared to the analysis, the speed of the semiconductor memory test has been remarkably increased.

FIG. 8 is a schematic system diagram showing a conventional semiconductor device and a semiconductor measuring device for testing the semiconductor device.

In FIG. 8, a semiconductor device 10 has a built-in memory cell array 40 and has a self-diagnosis function. In the semiconductor device 10, a logic circuit including a pattern generator 50, a defective cell storage unit 60, and a defect repair analysis unit 70 is mounted. The pattern generator 50 generates a test pattern signal for measuring the memory cell array 40.
The defective cell storage means 60 is a circuit for storing defective cell information of the memory cell array 40. The defect repair analysis means 70 is a circuit for performing a repair analysis of a memory cell based on the defective cell information stored in the defective cell storage means 60.

The probe card 20 is a semiconductor measuring jig for electrically connecting pads of the semiconductor device 10 and the semiconductor measuring device 30. Then, after the defective memory information is analyzed by the defective repair analysis means 70 in the semiconductor device 10, the repair code is output to the semiconductor measuring device 30 via the probe card 20.

[0007]

The conventional semiconductor measuring apparatus is configured as described above, and the algorithm for the defect repair analysis is built in the semiconductor device as a logic circuit and is fixed. There is a problem that it is difficult to change, and it is not possible to improve the yield of the process and to rationalize it.

Further, a wafer level burn-in (WLB)
In the defect convergence determination in the I: Wafer Level Burn In) test, since an increase in the number of defective bits cannot be detected, it is necessary to use the relief analysis function of the semiconductor measuring device (ATE) as a convergence monitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor measurement system which can easily change a failure analysis algorithm and has high test efficiency.

Also, the number of defective bits is counted and WLB is counted.
Provided is a semiconductor measurement system capable of determining convergence of I and having high test efficiency.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array. A semiconductor measuring device for testing, wherein a semiconductor measuring jig (for example, a probe card) for electrically connecting the semiconductor device and the semiconductor measuring device relieves the memory cells based on the defective cell information of the defective cell storage means. It is characterized in that a defect repair analysis means for performing analysis is provided.

According to a second aspect of the present invention, there is provided a semiconductor measuring device for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array. A jig for probe (for example, a probe card), wherein a jig for semiconductor measurement (for example, a probe card) is provided with defect repair analysis means for performing a repair analysis of a memory cell based on defective cell information of a defective cell storage means. It is characterized by.

[0013] The invention of claim 3 is claim 1 or claim 2.
In the invention, the defect remedy analyzing means is configured so that the defect remedy algorithm can be rewritten externally into logic.

According to a fourth aspect of the present invention, there is provided a semiconductor measurement method for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array. A semiconductor device and a semiconductor measurement jig (for example, a probe card) for electrically connecting the semiconductor device to the semiconductor measurement device, collecting defective cell information from the defective cell storage means, and performing error counting based on the collected information. A failure counting means for determining convergence of a failure is provided.

According to a fifth aspect of the present invention, there is provided a semiconductor measurement device for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array. A jig (for example, a probe card) for collecting defective cell information from a defective cell storage means in a jig for semiconductor measurement (for example, a probe card) and counting errors based on the collected information to determine convergence of the initial failure. It is characterized in that a defect counting means is provided.

The invention according to claim 6 is the invention according to claim 4 or claim 5.
In the invention of (1), the failure counting means is characterized in that the algorithm is formed into a logic so that the algorithm can be rewritten from the outside.

According to a seventh aspect of the present invention, there is provided the first to sixth aspects.
In the invention, the defective cell information is compressed in units of a redundant circuit.

The semiconductor measuring method according to claim 8 is a step of self-diagnosing a memory cell array built in a semiconductor device and storing defective cell information of the self-diagnosed memory cell array in defective cell storage means inside the semiconductor device. And a step of performing a repair analysis of the memory cell by the defect repair analysis means provided on the semiconductor measuring jig (for example, a probe card) based on the defective cell information of the defective cell storage means.

According to a ninth aspect of the invention, there is provided a semiconductor measuring method for self-diagnosing a memory cell array built in a semiconductor device, and storing defective cell information of the self-diagnosed memory cell array in a defective cell storage means inside the semiconductor device. And a step of collecting defective cell information from the defective cell storage means, counting the errors by a defective counting means provided on a semiconductor measuring jig (for example, a probe card), and determining the convergence of the initial failure.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a schematic system diagram showing a semiconductor device and a measuring device according to a first embodiment of the present invention.

In FIG. 1, a semiconductor device 1 has a built-in memory cell array 4 and has a self-diagnosis function.
In the semiconductor device 1, a logic circuit for a pattern generator 5 and a defective cell storage means 6 is mounted. The pattern generator 5 generates a test pattern signal for measuring the memory cell array 4. The defective cell storage means 6 is a circuit for storing defective cell information of the memory cell array 4. Here, the defective cell information is a large amount of information corresponding to all addresses and is difficult to store and transmit. Therefore, the defective cell information is compressed and stored in redundant circuits of spare rows and spare columns.

The probe card 2 is a semiconductor measuring jig for electrically connecting pads of the semiconductor device 1 and the semiconductor measuring device 3. The defect remedy analyzing means 7 is a circuit in which the defect remedy algorithm is converted into logic so as to be rewritable from the outside, for example, a FPGA (Field Programmable Logic Array), and is installed in the probe card 2.

Next, a method for measuring a semiconductor device according to the first embodiment will be described.

The pattern generator 5 generates a test pattern signal based on the test start signal of the semiconductor measuring device 3, and executes a self-diagnosis test of the memory cell array 4.
Then, the defective cell information of the memory cell array 4 is stored in the defective cell storage means 6. Here, since the defective cell information is compressed in units of redundant circuits, it can be transferred in a short bus width in a short time.

Failure repair analysis means 7 in probe card 2
Receives the signal of the start of the repair analysis from the defective cell storage means 6 and performs the repair analysis based on the signal. Then, after the defective memory information is analyzed by the defective relief analysis means 7, the repair code is output to the semiconductor measuring device 30.

Here, an example of repairing a memory cell will be described with reference to FIG. In the figure, a spare cell of a spare row and a spare column are provided in a memory block in addition to a normal storage cell (normal cell), and when a defect occurs, the defective normal cell is replaced by a fuse blow or the like, so that Perform relief. Here, 3 bits x 3
This is a state in which one spare exists in each bit memory. In this case, since there is a possibility that each spare is replaced with three addresses, six fuses are required.

In FIG. 2, when defective cells 1 to 3 occur simultaneously, defective cells 1 and 2 are repaired by spare columns because of the same column address, and defective cell 2 is repaired by spare rows. When the defective cells 1, 3 and 4 occur at the same time, the defective cells 1 and 4 are repaired by a spare row because of the same row address, and the defective cell 3 is repaired by a spare column. If the defective cells 1 to 4 occur at the same time, it cannot be repaired.

Conventionally, a fail memory having a memory capacity equivalent to the memory capacity and a memory test measuring device having a rescue analysis function are required to perform the above-described processing, which increases the cost of the device and makes it possible to store the test results of the entire space from the memory. The test time was increased to read from fewer pins during the test and to analyze after the test.

However, in the present embodiment, based on the defective memory information from the defective cell storage means 6, repair analysis is performed during the test by the defect repair analysis means 7 provided in the probe card 2, and the address to be replaced is tested. Since only reading is necessary later, the test time can be significantly reduced.

FIG. 3 shows a configuration example 1 of the memory, which is composed of eight memory blocks shown in FIG. in this case,
Since the spare for rescue is independent, each memory block can be analyzed independently. However, 48 fuses are required, eight times as large. FIG. 4 is a configuration example 2 of the memory. Here, in order to reduce the area of the fuses and suppress the cost, the spares are linked to each other, and the number of fuses is reduced to 18 pieces. In this case, since repair analysis cannot be performed independently for each memory block, a complicated algorithm including selection of row priority or column priority for a defect of each memory block is required. Providing the algorithm in a fixed form in the semiconductor device in a complete manner increases the circuit scale, and tends to simplify the process by improving the quality of the optimum process. Therefore, it is necessary to take measures so that the algorithm can be changed according to the state of the process. In this regard, in the first embodiment, the probe card 2
Since the algorithm of the defect repair analysis means 7 is made into a logic so that it can be rewritten from the outside, the above-mentioned demand can be answered.

As described above, according to the first embodiment, the probe card is provided with the defect repair analysis means for performing the repair analysis of the memory cell based on the defective cell information of the defective cell storage means. This has the effect that defect repair analysis can be performed. In addition, since the defect rescue algorithm is implemented as logic so that it can be rewritten from the outside, the defect rescue algorithm can be easily changed, and a semiconductor measuring device with high test efficiency can be obtained.

Embodiment 2 FIG. FIG. 5 is a diagram showing a semiconductor device and a measuring device according to a second embodiment of the present invention.

In FIG. 5, the semiconductor device 1 has a memory cell array 4 and a self-diagnosis function. In the semiconductor device 1, a logic circuit for a pattern generator 5 and a defective cell storage means 6 is mounted. The pattern generator 5 generates a test pattern signal for measuring the memory cell array 4. The defective cell storage means 6 is a memory cell array 4
Is a circuit for storing defective cell information. Here, the defective cell information is a large amount of information corresponding to all addresses and is difficult to store and transmit. Therefore, the defective cell information is compressed and stored in redundant circuits of spare rows and spare columns.

The probe card 2 is a jig for electrically connecting the pads of the semiconductor device 1 and the semiconductor measuring device 3. The failure counting means 7 has a function of periodically collecting the failure cell information from the failure cell storage means 6, counting the errors based on the information, and determining the convergence of the initial failure.
Externally rewritable logic circuit, for example, FPGA
(Field Programmable Logic Array) is installed in the probe card 2.

Next, a method for measuring a semiconductor device according to the second embodiment will be described.

The pattern generator 5 generates a test pattern signal based on the test start signal of the semiconductor measuring device 3, and executes a self-diagnosis test of the memory cell array 4.
Then, the defective cell information of the memory cell array 4 is stored in the defective cell storage means 6. Here, since the defective cell information is compressed in units of redundant circuits, it can be transferred in a short bus width in a short time.

Defect counting means 8 in probe card 2
Receives a WLBI test start or end signal from the defective cell storage means 6, periodically collects defective cell information and counts errors, calculates a count increment by a timer at regular intervals, and converges the initial failure. Make a decision.

FIG. 6 is a diagram showing the transition of the memory cell defect rate in the WLBI test. The WLBI is applied to repeat the test by applying a temperature or a voltage stress to remove an initial failure. The cumulative failure rate is saturated by the burn-in (BI) time, and the test failure rate converges. Some particularly bad semiconductor devices do not converge even with the longest burn-in time, and this is determined to be unusable.

FIG. 7 is a flowchart showing an example of the WLBI test according to the embodiment. As described above, by providing the function of counting the number of defective bits by the defective counting means 8 provided on the probe card 2 and confirming whether or not the number of defective bits has increased, it is possible to determine the convergence of the defective rate only by monitoring the defective rate. Becomes

As described above, according to the second embodiment, the probe card is provided with the defect counting means for collecting the defective cell information from the defective cell storage means and counting the errors based on the collected error cell information. Therefore, the convergence of WLBI can be determined without using a CPU or the like of an expensive semiconductor measuring device.
A large number of semiconductor devices can be processed simultaneously at high speed. In addition, since the algorithm is converted into logic so that it can be rewritten from the outside, the algorithm can be easily changed, and a semiconductor measuring device with high test efficiency can be obtained.

[0041]

According to the first to third aspects of the present invention,
Since the semiconductor repair jig is provided with the defect repair analysis means for performing the repair analysis of the memory cell based on the defective cell information of the defective cell storage means, there is an effect that the test and the defect relief analysis can be performed in a short time. In addition, since the defect rescue algorithm is implemented as logic so that it can be rewritten from the outside, the defect rescue algorithm can be easily changed, and a semiconductor measuring device with high test efficiency can be obtained.

According to the fourth to sixth aspects of the present invention, there is provided a failure counting means for collecting defective cell information from a defective cell storage means in a probe card, counting errors based on the information, and determining convergence of an initial failure. With the provision, the convergence of the WLBI can be determined without using a CPU or the like of an expensive semiconductor measuring device, and a large number of semiconductor devices can be simultaneously processed at high speed. In addition, since the algorithm is converted into logic so that it can be rewritten from the outside, the algorithm can be easily changed, and a semiconductor measuring device with high test efficiency can be obtained.

According to the seventh aspect of the present invention, since defective cell information is compressed in units of redundant circuits, there is an effect that transfer can be performed in a short bus width in a short time.

According to the eighth aspect of the present invention, the repair analysis of the memory cell is performed by the repair analysis means of the semiconductor measuring jig based on the defective cell information of the defective cell storage means. Test and defect relief analysis can be performed.

According to the ninth aspect of the present invention, the defective cell information is collected from the defective cell storage means, the error is counted by the defect counting means of the jig for semiconductor measurement, and the convergence of the initial failure is determined. The convergence can be determined without using a CPU or the like of an expensive semiconductor measuring device, and a large number of semiconductor devices can be simultaneously processed at high speed.

[Brief description of the drawings]

FIG. 1 is a schematic system diagram showing a semiconductor device and a measuring device according to a first embodiment of the present invention;

FIG. 2 is a diagram for explaining a repair analysis of a memory cell;

FIG. 3 is a diagram illustrating a configuration example 1 of a memory;

FIG. 4 is a diagram illustrating a configuration example 2 of a memory;

FIG. 5 is a schematic system diagram showing a semiconductor device and a measuring device according to a second embodiment of the present invention;

FIG. 6 is a diagram showing a transition of a memory cell defect rate in a WLBI test.

FIG. 7 is a flowchart illustrating an example of a WLBI test.

FIG. 8 is a schematic system diagram showing a conventional semiconductor device and its measuring device.

[Explanation of symbols]

Reference Signs List 1 semiconductor device, 2 probe card, 3 semiconductor measuring device, 4 memory cell array, 5 pattern generator, 6
Defective cell storage means, 7 defect repair analysis means, 8 error count means.

Claims (9)

[Claims] 1. A semiconductor measuring device for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array, A semiconductor measurement jig for electrically connecting a semiconductor device and a semiconductor measurement device is provided with a defect repair analysis means for performing a repair analysis of a memory cell based on the defective cell information of the defective cell storage means. Semiconductor measuring equipment. 2. A semiconductor measuring jig for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array. A semiconductor measurement jig, wherein the semiconductor measurement jig is provided with a defect relief analysis means for performing a relief analysis of a memory cell based on the defective cell information of the defective cell storage means. 3. The semiconductor measuring device according to claim 1, wherein the defect repair analysis means is implemented as a logic so that a defect repair algorithm can be rewritten from the outside. jig. 4. A semiconductor measuring device for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array, A semiconductor measuring jig for electrically connecting a semiconductor device and a semiconductor measuring device includes a defective counting unit that collects defective cell information from the defective cell storage unit, counts errors based on the collected information, and determines convergence of an initial failure. A semiconductor measuring device provided. 5. A semiconductor measurement jig for testing a semiconductor device having a function of self-diagnosing a built-in memory cell array and a defective cell storage means for storing defective cell information of the self-diagnosed memory cell array. A semiconductor measuring jig provided with a failure counting means for collecting defective cell information from the defective cell storage means and counting errors based on the collected error cell information to determine convergence of an initial failure; Jig. 6. The semiconductor measuring apparatus according to claim 4, wherein the defect counting means is implemented by logic so that an algorithm can be rewritten from the outside. 7. The semiconductor measuring device or the semiconductor measuring jig according to claim 1, wherein said defective cell information is compressed in units of a redundant circuit. 8. A step of self-diagnosing a memory cell array built in the semiconductor device and storing defective cell information of the self-diagnosed memory cell array in a defective cell storage means inside the semiconductor device; A semiconductor measuring method comprising a step of performing a repair analysis of a memory cell by a defect repair analysis means provided on a semiconductor measuring jig based on cell information. 9. A step of self-diagnosing a memory cell array built in a semiconductor device and storing defective cell information of the self-diagnosed memory cell array in a defective cell storage means inside the semiconductor device; A semiconductor measuring method comprising the steps of collecting cell information, counting errors by a fault counting means provided on a semiconductor measuring jig, and determining convergence of an initial failure.