JP2002133879A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent unnecessary stress from being applied to a memory cell in a previously verify-passed chip in a program/program-verify cycle, and a erase/erase-verify cycle in a simultaneous test of plural chips of a non-volatile semiconductor memory. SOLUTION: In a program/program-verify cycle and a erase/erase-verify cycle, a non-volatile storage element over-writen preventing circuit masks a mode enable-mask internal signal line 111 by a pass signal outputted by a memory control circuit 103 through a verify-pass signal line 110. Therefore, even if an active signal is inputted from a mode enable-mask signal line 118, since the mode enable-mask internal signal line 111 is masked, the program mode/ erase mode inputted from a mode selecting signal line 114 cannot be made active, unncessary stress for a memory cell array 104 can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device provided with an overwrite protection circuit in a test.

[0002]

2. Description of the Related Art Conventionally, in testing a nonvolatile memory which is a nonvolatile storage element, one socket is arranged on one tester board serving as a device interface using a tester, and one chip is tested. However, there is a method of using a tester board for simultaneous inspection in order to increase the inspection time due to the subdivision of the inspection items and to improve the throughput from the viewpoint of tester cost.

In a tester which is designed to test one chip, the same voltage and the same signal are supplied from the tester to a plurality of chips on a test board for simultaneous testing. Data writing and erasing of the nonvolatile memory cell are performed by changing the threshold value of the transistor by injecting and extracting electric charge to and from the gate, but the degree of the transition when the same signal is applied differs for each chip.

In a memory cell inspection, in a program / program verify cycle, a program for writing data and a program verify for confirming writing are performed, and in an erase / erase verify cycle, an erase for erasing data and an erase verify for confirming erasure are performed. Do. As described above, since the degree of transition when the same signal is applied differs for each chip, the writing operation or the erasing operation is repeated, and the number of repetitions differs for each chip.

For example, when two chips are simultaneously tested by a tester, the chip 1 becomes a verify pass at the 50th program / program verify cycle, and the chip 1 becomes unnecessary if the chip 2 passes the verify pass at the 55th cycle. Five program / program verify cycles are performed.

[0006]

Performing an unnecessary write or erase operation on a memory cell in a chip that has passed the verify operation is called an over-program or over-erase state. There is a problem that the convergence distribution of the threshold is deteriorated.

An object of the present invention is to solve such a problem, and an object of the present invention is to provide a nonvolatile memory device in which unnecessary stress is not applied to a memory cell of a chip that has passed verification.

[0008]

According to the first aspect of the present invention, there is provided a nonvolatile memory device, which is used for verifying whether or not data has been written to a memory cell array and a memory cell. And a memory control circuit for outputting a verify pass signal when the writing to the memory cell or the erasure to the memory cell is completed during the erase verify, and the verify pass signal is output from the memory control circuit. And a mode enable signal for permitting or disallowing writing and erasing to and from the memory cell array.

According to a second aspect of the present invention, in the nonvolatile memory device, when the verify pass signal is input, the mode enable signal is disabled and output or the verify pass signal is output. The selection is made by a write protection enable signal.

With the above configuration, even when the convergence degree of the threshold value of the memory cell differs for each of the plurality of memory cell arrays, unnecessary stress is not applied to the memory cells in the chip that have been verified and passed first.

[0011]

FIG. 1 is a block diagram showing a nonvolatile memory device according to a first embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a nonvolatile memory, 10
2 is a non-volatile memory block, 104 is a memory cell array capable of program erase and read in the non-volatile memory 101, 103 is a memory control circuit for controlling program erase and read from the outside of the non-volatile memory 101 to the memory cell array 104, Reference numeral 105 denotes a power supply circuit which is controlled by the memory control circuit 103 and outputs a predetermined voltage to the memory cell array 104; 114, a mode selection signal line for inputting a mode such as program erase / read from outside the nonvolatile memory 101; Signal lines input from outside the non-volatile memory 101, 11
Reference numeral 6 denotes a data signal line for inputting / outputting data to / from the outside of the nonvolatile memory 101; 110, a verify pass signal line from which a pass signal or a fail signal is output from the memory control circuit 103 during program / program verify, erase / erase verify; Is the mode selection signal line 11
A mode enable signal line for setting the mode input from 4 to standby or active, and 111 is a mode enable mask internal signal line. Reference numeral 119 denotes a nonvolatile memory element overwrite prevention enable signal line input from outside the nonvolatile memory 101, 117 denotes a mode enable mask external signal line output to the outside of the nonvolatile memory 101, and 121 denotes a nonvolatile memory element overwrite This is a write protection circuit.

In the nonvolatile memory device according to the first embodiment configured as described above, first, the memory block 1 does not include the operation of the nonvolatile memory element overwrite prevention circuit 121.
The operation in the program / program verify cycle for the memory cell array 104 in the memory 02 will be described.
The erase / erase verify cycle performs the same operation as the program / program verify cycle except that data to be programmed is stored in the memory control circuit 103 and the voltage of the power supply circuit 105 is set.

The mode enable signal line 118 is set to the standby mode, the mode selection signal line 114 is set to the program mode, and the address signal line 115 is set to select the non-volatile memory block 102. The information is stored through a line 116. Programming to the memory cell array 104 is performed by activating the mode enable signal line 118. Subsequently, the mode enable signal line 118 is set to the standby mode, and the mode selection signal line 114 is set to the program verify mode.
Is activated to perform program verification. The memory control circuit 103 outputs a pass signal or a fail signal to the verify pass signal line 110 as a result of the program verify. Thus, the memory control circuit 1
The program / program verify cycle is repeated until 03 outputs a pass signal to the verify pass signal line 110.

Next, the nonvolatile memory element overwriting prevention circuit 12
1 will be described. The nonvolatile memory element overwrite prevention enable signal line 119 is a mode enable signal line 1
It is selected whether to mask the signal No. 18 with the signal of the verify pass signal line 110. When the signal on the nonvolatile memory element overwrite prevention enable signal line 119 is disabled, the signal on the verify pass signal line 110 is output to the mode enable mask external signal line 117 as it is, and the signal on the mode enable signal line 118 is mode enabled. Output to the mask internal signal line 111. When the signal on the nonvolatile memory element overwrite protection enable signal line 119 is enabled, the mode enable mask internal signal line 111 and the mode enable mask external signal line 117 are masked by the signal on the verify pass signal line 110, and the verify pass signal line When the signal 110 passes, the mode enable mask external signal line 117 and the mode enable mask internal signal line 111 are set to standby, and when the signal fails, the mode enable mask external signal line 117 and the mode enable mask internal signal line 111 are activated.

As described above, according to the non-volatile memory device of the present embodiment, the non-volatile memory is provided with a means for prohibiting program / erase at the stage when the result of program verify / erase verify has passed. By adopting, even if the same voltage and the same signal are given from the tester to multiple chips on the tester board, unnecessary write or erase operations are not performed on the memory block of the chip that has passed the verify pass, and the memory cell Of the oxide film and deterioration of the convergence distribution of the threshold value of the memory cell can be prevented.

FIG. 2 is a block diagram showing a nonvolatile memory device according to a second embodiment of the present invention. FIG.
In the figure, 1 is a nonvolatile memory, 2 and 6 are nonvolatile memory blocks forming a bank configuration, 4 and 8 are memory cell arrays in the nonvolatile memory blocks 2 and 6 which can be programmed, erased and read, respectively, and 3 and 7 are respectively Memory cell arrays 4 and 8 from outside the nonvolatile memory 1
Memory control circuits for controlling a program erase read corresponding to the memory control circuits 3 and 7 respectively.
A predetermined voltage controlled by the memory cell array 4
And 8, a power supply circuit for outputting a mode selection signal line for inputting a mode such as program erase / read from the outside of the nonvolatile memory 1, an address signal line 15 for inputting a mode outside the nonvolatile memory 1, and 16 Are data signal lines for inputting and outputting data to and from the outside of the nonvolatile memory 1;
Reference numeral 3 denotes a verify pass signal line output from the memory control circuits 3 and 7 at the time of program / program verify and erase / erase verify, respectively. Reference numeral 18 denotes a mode enable signal line for setting the mode input from the mode selection signal line 14 to standby or active. And 11
And 12 are mode enable mask internal signal lines corresponding to the memory control circuits 3 and 7, respectively. Reference numeral 19 denotes a non-volatile memory element overwrite prevention enable signal line inputted from outside the non-volatile memory 1, and 17 and 20 denote non-volatile memory 1
Mode enable mask external signal lines 21 and 22 which are output to the outside of the nonvolatile memory element.

In the second embodiment configured as described above, the mode enable signal line 18 and the nonvolatile memory element overwrite prevention enable signal line 19 are commonly input to the nonvolatile memory blocks 2 and 6. The other configuration is the same as that of the first embodiment, and performs the same operation as that of the first embodiment. When the bank 2 and the bank 6 are simultaneously selected by the address signal line 15, since the nonvolatile memory element overwrite protection circuit is provided for each bank, it can operate independently, and each mode enable mask internal signal line 11
And 12 can be masked by verify pass signal lines 10 and 13.

As described above, according to the nonvolatile memory device of the present embodiment, the nonvolatile memory is provided with a means for inhibiting the program / erase at the stage when the program verify / erase verify has passed as a result. By employing this, it is possible to prevent deterioration of the oxide film quality of the memory cell and deterioration of the convergence distribution of the threshold value of the memory cell in the inspection of the memory blocks of a plurality of banks.

[0019]

According to the present invention, as a result of the program verify / erase verify, a signal for enabling the mode is masked in the nonvolatile memory by the pass signal output from the memory control circuit. Program / erase cannot be performed even if an input is made to enable the mode from the outside, and unnecessary stress on the memory cell can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a nonvolatile storage device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a nonvolatile memory device according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Non-volatile memory 102 Non-volatile memory block 103 Memory control circuit 104 Memory cell array 105 Power supply circuit 110 Verify pass signal line 111 Mode enable mask internal signal line 114 Mode selection signal line 115 Address signal line 116 Data signal line 117 Mode enable mask external signal Line 118 Mode enable signal line 119 Non-volatile memory element overwrite prevention enable signal line

Claims (2)

[Claims] 1. A memory cell array and a memory cell are written to or erased from a memory cell at the time of program verify for verifying whether or not the memory cell has been erased or at the time of erase verify for verifying whether or not an erase has been performed on the memory cell. And a memory control circuit for outputting a pass signal when erasing of the memory cell is completed. A mode enable for permitting or disabling writing and erasing to and from a memory cell array when a pass signal is output from the memory control circuit. A non-volatile memory device further comprising a non-volatile memory element overwrite prevention circuit, wherein a signal is rejected. 2. The nonvolatile memory element overwrite protection circuit determines whether the mode enable signal is disabled when the verify pass signal is input, or whether the verify pass signal is output. 2. The nonvolatile memory device according to claim 1, wherein the nonvolatile memory device is selected by an element overwrite prevention enable signal.