JP2002133875A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which blunting of a waveform caused by long wiring load is suppressed by arranging a circuit generating an output latch control signal near a sense amplifier, a signal having a desired pulse width can surely be formed without requiring to have excessive margin. SOLUTION: This memory is provided with plural memory cells, a pre-charge circuit, a sense amplifier 13 detecting stored data of a memory cell and amplifying it with a sense amplifier control signal 15, an output latch circuit 14 latching an output of the sense amplifier, and a detecting circuit 21 positioned near the sense amplifier, detecting the decision of an output of the sense amplifier, and generating a control signal 18 of the output latch circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to an internal timing control technique in a memory operation of a semiconductor integrated circuit, for example, a static random access memory (hereinafter referred to as an SRAM (SRAM)).
static Random AccessMemor
y), which is an effective technique applied to the timing control of the output latch circuit.

[0002]

2. Description of the Related Art FIG. 1 shows a block 1 of a semiconductor memory device, which comprises a memory cell array unit 2, a data I / O unit 3, a decoder unit 4, and a control circuit unit 5. FIG. 8 shows a part of a block diagram of a conventional SRAM. 8, a large number of memory cells 6 (only one is shown in FIG. 8) are arranged in a row and column direction in a memory cell array 2, and complementary bit lines provided corresponding to respective memory cell columns are provided. The storage data is read from the memory cell 6 by the pairs 7 and 8. 9 is a bit line pair 7,
The precharge circuit is connected between the power supply voltages 8 and controls the operation of the bit line pair 7 and 8 to the potential of the power supply voltage. Numerals 11 and 12 denote data line pairs for reading the data on the bit line pairs 7 and 8 amplified by the sense amplifier 13 to the output latch circuit 14, and 13 includes a complementary input node and a complementary data line pair 11 , 12 are sense amplifiers for detecting and amplifying the potential difference between them,
That is, it is an output latch circuit that takes in the data on the data line pairs 11 and 12, latches the data, and outputs the latched data to the outside. Further, the precharge signal 10 and the sense amplifier control signal 15 are generated by the control circuit unit 5, and control the precharge operation and the sense amplifier operation of the selected column, respectively.

The operation of reading data from the memory cell 6 will be described with reference to the timing chart of FIG. As shown in FIG.
Now, it is assumed that the memory cell 6 is selected by the word line 16 from a large number of memory cells in the memory array 2. Sense amplifier control signal 1 output from control circuit unit 5
When the word line 16 rises to the "H" level in the state where the sense amplifier 5 is set to the "L" level and the sense amplifier is inactive, the memory cell 6 is activated and the data held in the memory cell 6 becomes The potential of one of the complementary bit line pairs 7 and 8 (data line pair 11 and 12) which has been at the power supply potential due to the charge drops, and the potential difference between the two opens. At time t1 when the potentials of the bit line pairs 7 and 8 (data line pairs 11 and 12) are opened to some extent, the control circuit unit 5 sets the sense amplifier control signal 15 to the "H" level,
Activate the sense amplifier 13. Further, at this time, the sense amplifier control signal 15
In response, one-shot pulse generation circuit 17 generates output latch control signal 18. This signal causes the output latch circuit 14 to enter a through state, and the activated sense amplifier 13 amplifies and outputs the potential difference between the pair of bit lines 7 and 8, and outputs data from the output latch circuit 14 to the outside. Thereafter, the time t2 when the sense amplifier control signal 15 is dropped to the "L" level and the sense amplifier operation ends.
Then, the output data is latched in the output latch circuit 14, and the precharge signal 10 is lowered to the "L" level in the control circuit section, thereby starting the precharge in the next read cycle. That is, as shown in FIG. 8, the sense amplifier 13 and the output latch circuit 14 are controlled by a signal generated from the sense amplifier control signal 15 generated by the control circuit unit 5, and during the period when the sense amplifier 13 is activated. The output latch circuit 14 is set to the through state, and the timing (t
After holding the output data in 2), the data is read at the operation timing of starting the precharge of the next cycle.

[0004]

However, in the conventional circuit configuration described above, since the sense amplifier control signal 15 is generated in the control circuit section 5, the signal waveform rises and falls due to the wiring load of the long signal wiring. Due to the slowness of the slope, the substantial pulse width of the output latch control signal is narrowed or the pulse is crushed, so that the output latch circuit 14 cannot latch correct output data. Therefore, the pulse width generated by the one-shot pulse generation circuit 17 is generated with a sufficient margin, but on the contrary, the access speed is reduced.

The present invention solves the above-mentioned conventional problems. By arranging a circuit for generating an output latch control signal near a sense amplifier, it is possible to suppress waveform dulling due to a long wiring load and to reduce an excessive margin. It is an object of the present invention to provide a semiconductor memory device capable of reliably forming a signal having a desired pulse width without having to provide the signal.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells arranged in a row and a column direction; a word line provided corresponding to each memory cell row; A complementary bit line pair provided corresponding to the cell column, a precharge circuit for charging the bit line pair to a predetermined potential before data reading, and a complementary input node pair, A sense amplifier that detects stored data and amplifies the sensed data with a sense amplifier control signal;
An output latch circuit for latching the output of the sense amplifier, and a one-shot pulse signal generation circuit located near the sense amplifier and generating a control signal for the output latch circuit from a sense amplifier control signal are provided. Things.

According to the semiconductor memory device of the first aspect,
Since the one-shot pulse generation circuit for generating the output latch control signal is arranged in the vicinity of each sense amplifier, the dull signal due to the long wiring load of the output latch control signal in the conventional configuration can be avoided. Further, since a pulse having a minimum width required for the output data to reach the output latch circuit can be reliably generated, accurate data reading can be performed.

According to a second aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells arranged in a row and a column direction; a word line provided corresponding to each memory cell row; A complementary bit line pair provided, a precharge circuit for charging the bit line pair to a predetermined potential before reading data, and a complementary input node pair for detecting and sensing storage data of a selected memory cell A sense amplifier that amplifies with an amplifier control signal, an output latch circuit that latches the output of the sense amplifier, and a control signal for the output latch circuit that is located near the sense amplifier and detects that the output of the sense amplifier has been determined. And a detecting means for performing the detection.

According to the semiconductor memory device of the second aspect,
Since the sense amplifier output voltage detecting means for detecting that the complementary output of the sense amplifier is determined is arranged near each of the sense amplifiers, and the output latch circuit is controlled by the output signal of the detecting means. The output latch control signal is not generated from the sense amplifier activation signal in the control circuit section as in the conventional configuration, but is generated in the vicinity of each sense amplifier in response to the determination of the complementary output of the sense amplifier. . Therefore, since it is not affected by a long signal load as in the conventional technique, the pulse waveform of the output latch control signal can be reliably obtained without expecting an excessive margin, so that an accurate output data latch operation can be performed. .

According to a third aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of memory cells arranged in a row and a column direction; a word line provided corresponding to each memory cell row; A complementary bit line pair provided, a precharge circuit for charging the bit line pair to a predetermined potential before reading data, and a complementary input node pair for detecting and sensing storage data of a selected memory cell A sense amplifier that amplifies by an amplifier control signal, an output latch circuit that latches the output of the sense amplifier, and a control signal for the output latch circuit that is located near the sense amplifier and detects that the output of the sense amplifier has been determined. A detection means to be generated, a sense amplifier control signal as an input signal, an output of the detection means as a reset signal, and a latch for outputting a sense amplifier activation signal to the sense amplifier. It is obtained by a circuit.

According to the semiconductor memory device of the third aspect,
In addition to the same effects as those of the second aspect, since the configuration is such that the sense amplifier is deactivated in response to the determination of the output of the sense amplifier, power consumption can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram of a semiconductor memory device according to a first embodiment of the present invention, and a semiconductor device having a conventional configuration shown in the block diagram of FIG. The parts different from the storage device are mainly shown. In the conventional configuration, the one-shot pulse generation circuit 17 for generating the output latch control signal 18 is provided in the control circuit section 5, whereas in the present embodiment, the one-shot pulse generation circuit 17 for generating the output latch control signal 18 is provided. A pulse generation circuit 17 is arranged near each of the sense amplifiers 13 and controls output data latch timing in the output latch circuit 14. As the one-shot pulse generating circuit 17, a two-input NAND circuit 28 is used as in the conventional configuration, and the sense amplifier control signal 15 is applied to the two input terminals 19 and 36 at the terminal 36, and the sense amplifier control signal 15 is applied to the terminal 19. A one-shot pulse signal 20 is generated by inputting a signal obtained by delaying and inverting the control signal 15 by a delay element 29 and an inverter 30.
The latch timing of the output latch circuit 14 is controlled by using a signal obtained by inverting the one-shot pulse signal 20 by the inverter 31 as the output latch control signal 18.

The operation of the semiconductor memory device configured as described above at the time of reading will be described below with reference to FIG.
This will be described with reference to FIG. In the present embodiment, as in the above-described conventional configuration, at the time (t1) when the data of the selected memory cell 6 appears on the pair of bit lines 7 and 8 after the end of the precharge period and the potential difference between the two has opened to some extent.
When the sense amplifier control signal 15 rises to the “H” level in the control circuit unit 5, the sense amplifier 13 is activated. The potential difference between the bit line pair 7 and 8 is amplified by the activated sense amplifier 13 and transmitted to the output latch circuit 14. On the other hand, the sense amplifier control signal 15
Rises from "L" level to "H" level (t1)
As a result, the one-shot pulse signal 20 is generated. The inverted signal of the one-shot pulse signal 20 becomes the output latch control signal 18, and the output latch control signal 18 is output during the period (T) during which the one-shot pulse signal 20 is generated. In the circuit 14, the data appearing on the data line pair 11, 12 is latched and output to the outside.

In the conventional configuration, as shown in FIG. 8, the output latch control signal 18 is generated by the one-shot pulse generation circuit 17 arranged in the control circuit section 5. That is, since the control signal is transmitted from the control circuit unit 5 to all of the output latch circuits 14, the rise and fall of the signal waveform are caused by the wiring load associated with the long signal wiring. However, according to the present embodiment as described above, the output latch control signal 1
By arranging the one-shot pulse generation circuit 17 for generating the signal 8 in the vicinity of each of the sense amplifiers 13, it is possible to shorten the wiring length through which the output latch control signal 18 propagates as compared with the conventional configuration. Therefore, the wiring load is reduced, and the waveform of the output latch control signal 18 can be suppressed from becoming dull. As a result, the output latch control signal 18 having the pulse width necessary for latching the output data can be reliably generated without expecting an excessive margin, and mislatch as in the conventional configuration can be prevented. Become.

As described above, according to the present invention, by forming a circuit configuration for generating an output latch control signal near the sense amplifier, waveform dulling due to wiring load can be avoided, so that an excessive margin is not expected. A signal waveform can be reliably obtained. Therefore, data can be read without causing mislatch in the output latch circuit.

[Second Embodiment] FIG. 3 is a block diagram showing a circuit configuration of an SRAM according to a second embodiment of the present invention. In the figure, the same reference numerals are given to the same or equivalent parts as described above. This SRAM is shown in FIG.
The difference from the conventional configuration shown in FIG. 1 and the configuration of the semiconductor memory device in the first embodiment is that the sense amplifier 13
Output voltage detecting circuit 21 for detecting that the voltage on the pair of output terminals to complementary data line pair 11 and 12 in FIG.
Is provided in the vicinity of each sense amplifier 13, and the output latch control signal 18 is generated using the detection signal 22 output at the stage of detecting that the output voltage of the data line pair 11 and 12 of the sense amplifier 13 has been determined. It is the point that is occurring. Specifically, an AND circuit 33 having the data line pairs 11 and 12 connected to the complementary output terminals of the sense amplifier 13 as inputs is provided as the sense amplifier output voltage detection circuit 21, and the output (detection) signal 22 and the sense amplifier The output latch control signal 18 of the output latch circuit 14 is generated as an inverted signal 18 of the output signal 23 of the NAND gate to which the control signal 15 is input.

The operation of the semiconductor memory device configured as described above at the time of reading will be described below with reference to the timing chart of FIG. Similarly to the semiconductor memory device according to the first embodiment, the data read from the memory cell 6 after the end of the precharge is used for the bit line pair 7,.
At a point in time t1 when the potential of the gate 8 has opened to some extent, the sense amplifier control signal 15 is raised to “H” level,
Activate 3 By the sense amplifier 13 in the activated state, one of the potentials of the outputs of the data line pair 11 and 12 of the sense amplifier 13 sharply drops, and the potential difference opens. At this time, the AND of the sense amplifier output voltage detecting circuit 21 is determined.
The D gate 33 is connected to the data line pair 11, 1 of the sense amplifier 13.
The sense amplifier output voltage detection circuit 21 outputs an "H" level at time t3 when the level mismatch of the output pair 2 is detected, that is, when the output of the sense amplifier 13 is determined. The inverted signal 18 of the output signal 23 of the NAND circuit 34 to which the detection signal 22 and the sense amplifier control signal 15 are input is used as the output latch control signal 18.

As described above, according to the present embodiment, the sense amplifier output voltage detecting circuit 21 for detecting that the voltage on the output terminal pair to the complementary data line pair 11 and 12 of the sense amplifier 13 has been determined is individually provided. , The wiring length through which the output latch control signal 18 propagates can be reduced and the wiring load can be reduced as compared with the conventional configuration, as in the first embodiment. Therefore, the waveform of the output latch control signal 18 can be suppressed from becoming blunt. As a result, the output latch control signal 1 having a pulse width long enough to latch the output data is output.
8 can be reliably generated without expecting an excessive margin, and mislatch as in the conventional configuration can be prevented.

On the other hand, when using a compilable memory whose memory capacity can be arbitrarily changed, the number of bits and the number of word lines of the memory cell array 2 change.
In other words, since the size in the column direction changes, the load capacitance of the sense amplifier control signal 15 line changes accordingly, and the time from when the sense amplifier activation signal 15 is input to when the output data of the sense amplifier 13 is determined is also determined. Change.
For this reason, in the conventional configuration and the circuit configuration according to the first embodiment of the present invention, the one-shot pulse width is two inputs N
Since the fixed value is determined by the delay inverter and the buffer at one input terminal of the AND circuit, when applied to a compilable memory in which the number of bits / word of the memory cell 6 is variable, the output data is held. Time had to be adjusted to the longest configuration. However, if the time until the output data is held is long as described above, the time until the output data is held is short, and if the capacity is small, a temporally redundant period occurs, and the access time is originally reduced. Had become slower than the performance of. Therefore, in the present embodiment, a circuit configuration for detecting that the outputs of the data line pairs 11 and 12 of the sense amplifier 13 are determined has a large memory capacity, and the outputs of the data line pairs 11 and 12 of the sense amplifier 13 are large. If the time until the determination is long, the time until the output latch circuit 14 starts holding the output data can be long, and the memory capacity is small, and the data line pair 1 of the sense amplifier 13 is small.
If the time until the outputs 1 and 12 are determined is short, the time until the output latch circuit 14 starts holding the output data can be shortened. Therefore, a compilable memory that can be accessed at an operation timing according to the memory capacity is used. Can be realized.

In this embodiment, the AND gate 33 is provided as the sense amplifier output voltage detecting circuit 21.
A similar function can be achieved by using an XNOR circuit.

[Third Embodiment] FIG. 5 is a block diagram showing a circuit configuration of an SRAM according to a third embodiment of the present invention. In the figure, the same reference numerals are given to the same or equivalent parts as described above. The configuration of the SRAM according to the present embodiment is different from the configuration of the semiconductor memory device according to the second embodiment shown in FIG. 3 in that a new latch circuit, for example, an RS latch circuit 24 is newly provided and the vicinity of each sense amplifier 13 is provided. The sense amplifier activation signal 25 is reset by a detection signal 22 generated when the output of the sense amplifier 13 is determined by the sense amplifier output voltage detection circuit 21 provided in the circuit, and the sense amplifier operation is terminated (inactive state). To). Specifically, RS
The sense amplifier control signal 15 generated by the control circuit unit 5 is input to a set terminal of the latch circuit 24, and a one-shot pulse 26 is generated in the RS latch circuit 24.
Similarly to the second embodiment, an AND having an output terminal to the complementary data line pair 11 and 12 of the sense amplifier 13 as an input is provided.
The circuit 33 is provided as a sense amplifier output voltage detection circuit 21, and the detection signal 22 is input to a reset terminal R of the RS latch circuit 24. The Q output of the RS latch circuit 24 is used as a sense amplifier activating signal 25, and the output latch control signal 18 is connected to the output (detection) signal 22 of the sense amplifier output voltage detection circuit 21 and the sense signal 22 as in the second embodiment. NAND circuit 3 receiving amplifier control signal 15 as input
4 is generated as an inverted signal 18 of the output signal 23 of FIG.

The operation of the semiconductor memory device configured as described above at the time of reading will be described below with reference to the timing chart of FIG. As in the semiconductor memory device according to the first or second embodiment, at the time t1 when the potential of the bit line pair 7, 8 is opened to some extent by the data of the memory cell 6 after the end of the precharge, RS
The sense amplifier control signal 15 input to the set terminal S of the latch circuit 24 rises to “H” level, the RS latch circuit 24 is set and the sense amplifier activation signal 25 output from the Q output terminal changes to “H” level. stand up.
As a result, the sense amplifier 13 is activated, and one of the potentials of the outputs of the data line pair 11 and 12 of the sense amplifier 13 drops sharply and the potential difference opens. Then AND gate 3
Reference numeral 3 indicates that the detection circuit 21 outputs the "H" level at a time t3 when the output level of the data line pair 11 and 12 of the sense amplifier 13 is detected as a mismatch, that is, when the output voltage of the sense amplifier 13 is determined. The output latch control signal 18 is generated as an inverted signal of the output signal 23 of the NAND circuit 34 having the detection signal (22) and the sense amplifier control signal 15 as input signals, and the output latch timing is controlled. Further, in the present embodiment, the configuration is such that the output node 22 of the detection circuit 21 is input to the reset terminal R of the RS latch circuit 24, and by detecting that the output voltage of the sense amplifier has been determined, the At time t3, the output node 22 of the detection circuit 21 rises to “H” level, the RS latch circuit 24 is reset, and the Q output terminal (2
5) can be lowered to the “L” level, and the sense amplifier 13 can be made inactive.

As described above, according to the present embodiment, the detection circuits 21 simulating the output data on the complementary data line pairs 11 and 12 in the sense amplifier 13 are arranged near the individual sense amplifiers 13. Therefore, similarly to the second embodiment, the output latch control signal 18
Can be shortened and the wiring load can be lightened, so that the waveform of the output latch control signal 18 can be suppressed from becoming dull. As a result, it is possible to reliably generate the output latch control signal 18 having a pulse width of a length necessary to latch the output data without expecting an excessive margin. Can be. The detection signal 22 output in response to the determination of the output of the sense amplifier 13 is RS
The sense amplifier activation signal 25 is immediately reset (dropped to "L" level) by being input to the reset terminal R of the latch circuit 24, and the sense amplifier 13 is inactivated. As a result, the period during which the sense amplifier 13 is in the active state is shorter than in the case of the second embodiment, so that power consumption can be reduced.

[0025]

According to the semiconductor memory device of the present invention, the one-shot pulse generating circuit for generating the output latch control signal is arranged near each sense amplifier, so that the output seen in the conventional configuration is obtained. Since the signal dulling due to the long wiring load of the latch control signal can be avoided and a pulse having a minimum width required for the output data to reach the output latch circuit can be reliably generated, accurate Data can be read.

According to the semiconductor memory device of the second aspect,
Since the sense amplifier output voltage detecting means for detecting that the complementary output of the sense amplifier is determined is arranged near each of the sense amplifiers, and the output latch circuit is controlled by the output signal of the detecting means. The output latch control signal is not generated from the sense amplifier activation signal in the control circuit section as in the conventional configuration, but is generated in the vicinity of each sense amplifier in response to the determination of the complementary output of the sense amplifier. . Therefore, since it is not affected by a long signal load as in the conventional technique, the pulse waveform of the output latch control signal can be reliably obtained without expecting an excessive margin, so that an accurate output data latch operation can be performed. .

According to the semiconductor memory device of the third aspect,
In addition to the same effects as those of the second aspect, since the configuration is such that the sense amplifier is deactivated in response to the determination of the output of the sense amplifier, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a part of a configuration of an SRAM according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a data read operation of the SRAM shown in FIG. 2;

FIG. 3 is a block diagram illustrating a part of a configuration of an SRAM according to a second embodiment of the present invention;

FIG. 4 is a timing chart showing a data read operation of the SRAM shown in FIG. 3;

FIG. 5 is a block diagram showing a part of the configuration of an SRAM according to a third embodiment of the present invention;

FIG. 6 is a timing chart showing a data read operation of the SRAM shown in FIG. 5;

FIG. 7 is a block diagram of a semiconductor memory device.

FIG. 8 is a block diagram showing a configuration of a conventional SRAM.

9 is a timing chart showing a data read operation of the SRAM shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Block of semiconductor memory device 6 Memory cell 7, 8 Bit line pair 9 Precharge circuit 10 Precharge signal 11, 12 Data line pair 13 Sense amplifier 14 Output latch circuit 15 Sense amplifier control signal 16 Word line 17 One shot pulse generation circuit 18 output latch control signal 21 detection circuit 24 RS latch circuit 25 sense amplifier activation signal

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshinobu Yamagami 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F term (reference) 5B015 JJ11 KB23 KB35 KB92 QQ18

Claims (3)

[Claims] 1. A plurality of memory cells arranged in the row and column directions, a word line provided corresponding to each memory cell row, and a complementary bit line pair provided corresponding to each memory cell column. And a precharge circuit for charging the bit line pair to a predetermined potential before reading data, and a complementary input node pair, and detects storage data of the selected memory cell and amplifies it by a sense amplifier control signal. A sense amplifier, an output latch circuit that latches the output of the sense amplifier, and a one-shot pulse signal generation circuit that is located near the sense amplifier and generates a control signal for the output latch circuit from the sense amplifier control signal. Semiconductor memory device provided. 2. A plurality of memory cells arranged in a row and column direction, a word line provided corresponding to each memory cell row, and a complementary bit line pair provided corresponding to each memory cell column. And a precharge circuit for charging the bit line pair to a predetermined potential before reading data, and a complementary input node pair, and detects storage data of the selected memory cell and amplifies it by a sense amplifier control signal. A sense amplifier, an output latch circuit that latches the output of the sense amplifier, and a detection circuit that is located near the sense amplifier and detects that the output of the sense amplifier is determined and generates a control signal for the output latch circuit. Semiconductor memory device comprising: 3. A plurality of memory cells arranged in a row and column direction, a word line provided corresponding to each memory cell row, and a complementary bit line pair provided corresponding to each memory cell column. And a precharge circuit for charging the bit line pair to a predetermined potential before reading data, and a complementary input node pair, and detects storage data of the selected memory cell and amplifies it by a sense amplifier control signal. A sense amplifier; an output latch circuit for latching the output of the sense amplifier; and a detection circuit located near the sense amplifier for detecting that the output of the sense amplifier has been determined and generating a control signal for the output latch circuit. Means for receiving the sense amplifier control signal as an input signal, the output of the detecting means as a reset signal, and outputting a sense amplifier activation signal to the sense amplifier. And a semiconductor memory device having a switch circuit.