JP2002132849A - Logic simulation system and input/output controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a user to easily and efficiently perform logic simulation and analysis without paying any attention to a troublesome procedure nor operation. SOLUTION: This logic simulation system which displays the result of logic simulation on a screen is equipped with a result display control means which displays on the screen logic simulation result information in free-format display form displaying signal values of signal terminals only at specified time and logic simulation result information in stream display format as the time-series display format of signal values of the signal terminals including the specified time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for simulating a logic circuit, and more particularly, to a technique for performing a logic simulation by interacting with a user via a display screen and displaying the result on a display screen. The present invention relates to a logic simulation system and an input / output control device.

In recent years, logic circuits implemented in computer systems and the like have been increasingly integrated, and accordingly, the time required for simulation for confirming the operation of the designed logic circuit and analyzing malfunctions is enormous. It has become something. In the process of designing a large-scale circuit by dividing it hierarchically, in order to perform a logic simulation for each hierarchical unit and verify it, as in the work of simulating a large-scale circuit in the upper hierarchy, It is required that the work of simulating a small circuit is easy and easy to understand.

[0003]

2. Description of the Related Art In a conventional logic simulation system, a "free format display format" method in which logic simulation result information at a specified time is displayed according to a user-defined display format, or logic simulation result information of a specified signal terminal is displayed. A "stream display format" method is used in which a display is made in a form following the flow of time according to a display format defined by the system.

The free format display format has the advantage that a large number of signal values of signal terminals serving as logic simulation result information can be displayed on one screen. On the other hand, however, the temporal flow of signal values cannot be grasped. There is a problem that when an error is found, it takes time to analyze the cause. On the other hand, in the stream display format, the time series data of the signal value of the signal terminal is displayed, so that when a logic circuit error is found, there is an advantage that the cause analysis becomes easy, but on the other hand, Since the time-series data is displayed, the number of signal terminals that can be displayed on one screen is reduced, so that a separate screen is frequently displayed, and a long time is required for a simulation operation. As described above, both display formats have advantages and disadvantages.

In the conventional logic simulation method, a procedure of the logic simulation (for example, a circuit operation pattern) is described in advance using a dedicated control language, and the written control language is translated, and then the simulation is performed. Is executed, and the operation result of the logic circuit is analyzed by analyzing the execution result, that is, the logic simulation result information.

In this case, since there are relatively many design errors in the initial stage of the logic circuit design, rather than a method of describing various circuit operation patterns in advance, the logic circuit designer interacts with the display screen rather than writing it. It is considered that a method of thinking the operation of the next simulation while watching the operation state of the circuit little by little through is more suitable.

[0007]

As described above, in the prior art, a description of a simulation procedure in a control language is used.
A logic simulation has been performed based on a technique such as translation of a control language → simulation execution → result analysis and operation check. For this reason, there has been a problem that a great deal of labor and time are required from the start of the simulation immediately after the design of the logic circuit is completed until the operation is confirmed.

[0008] Further, after the result analysis and the operation confirmation, the following simulation procedure is further described, which is not always a convenient method for a logic circuit designer. The present invention has been made in view of the problems in the related art, and enables a user to easily and efficiently execute and analyze a simulation without being conscious of troublesome procedures and operations related to a logic simulation. It is another object of the present invention to provide a logic simulation system and an input / output control device capable of providing good operability by reducing the interruption of the thinking when considering the next simulation procedure.

[0009]

In order to solve the above problems, a logic simulation system according to the present invention performs a logic simulation by interacting with a user via a display screen, and displays the result on the display screen. Setting means for setting at least one display format of the logic simulation result information in the form of a window defined by an arbitrary display range by interacting with the user via the display screen, assuming that the configuration is adopted; A first management table that manages a display mode of a free format display format set by the setting unit; and a second management table that manages a display mode of a stream display format that is a time-series display format of logic simulation result information. And the signal for each signal terminal that Third to manage time-series data values
Of the logic simulation result information using the management data of the first, second, and third management tables, and processing for displaying the specified logic simulation result information on the display screen. A display control unit, for displaying the logic simulation result information in a free format display format at a specified time and the logic simulation result information in a stream display format of a specified signal terminal, respectively, in a set window on the display screen. Are displayed simultaneously.

Further, in the logic simulation system according to the present invention, in the logic simulation system for displaying the result of the logic simulation on a screen, the logic simulation result information in a free format display format for displaying a signal value of a signal terminal only at a designated time is provided. A result display control unit for displaying on the screen logical simulation result information in a stream display format that is a time-series display format of the signal values of the signal terminals including the designated time, and executing the logic simulation at the designated time Execution means.

In the input / output control device according to the present invention, the input / output control device for controlling the logic simulation device and displaying the result of the logic simulation device on a screen displays the signal value of the signal terminal only at the designated time. A result display control unit for displaying on the screen the logic simulation result information in a stream display format that is a time-series display format of the signal value of the signal terminal including the specified time and the logic simulation result information in a free format display format, Execution means for causing the logic simulation apparatus to execute a logic simulation at a designated time.

In a preferred embodiment of the present invention, the apparatus further comprises a memory management table for managing data defining a logical address space for specifying a plurality of memory cells in a circuit to be subjected to a logic simulation, With reference to the table, processing is performed to display the memory contents on the display screen in a memory virtual space image defined by the logical address space.

[0013]

According to the configuration of the present invention described above, it is possible to grasp the logic simulation result information in a free format display format enabling display of the signal values of a large number of signal terminals and the temporal flow of the signal values of the signal terminals. The basic configuration is to simultaneously display the logic simulation result information in the stream display format and the multi-window form on the same display screen, and to display the memory contents on the display screen in a memory virtual space image. The configuration makes it unnecessary to input instructions or the like by selecting menus, sets state values by directly writing on the free format display, executes simulation by directly instructing the time portion on the stream display, or executes memory. Rewrite memory contents by writing directly on the contents display It adopts a configuration.

Therefore, the user can easily and efficiently execute the logic simulation and analyze the logic simulation without being conscious of complicated procedures and operations concerning the logic simulation. Also, when thinking about the next stage of the simulation procedure, reduce the interruption of that thinking,
An efficient simulation can be performed. In addition,
For details of other structural features and operations of the present invention,
A description will be given using embodiments described below with reference to the accompanying drawings.

[0015]

FIG. 1 shows the configuration of an embodiment of a logic simulation system according to the present invention. In the figure, 1 is a logic simulation system according to the present invention,
Reference numeral 2 denotes a terminal included in the logic simulation system 1, and the terminal includes a display 3 for displaying logic simulation result information and the like, and an input device 4 such as a keyboard or a mouse operated by a user or an operator.

The logic simulation system 1 according to the present embodiment includes an input / output (I / O) control means 10, a logic circuit data (LD) information management means 11, a logic simulation means 12, a result display control means 13, Command analysis means 14, function key control means 15, window management table 16, signal value management table 17
A free format window (FW) management table 18, a stream window (SW) management table 19, a time management table 20, a memory management table 21, a function management table 22, a log output unit 23, and a window setting unit. 24, state value selecting means 25, signal value setting means 26, attribute changing means 27
And memory contents display means 28 and memory contents setting means 2
9, a simulation executing unit 30, a time setting unit 31, and a memory content selecting unit 32. Hereinafter, each component will be described.

The input / output (I / O) control means 10
Execute the interface processing between The logic circuit data (LD) information management unit 11 manages logic circuit data information to be subjected to a logic simulation. However, since the logic circuit data information is actually described by the signal terminal number, the LD information management means 11 manages the correspondence between the signal terminal number and the user-defined signal terminal name. The logic simulation means 12
Executes a logic simulation process of a logic circuit managed by the LD information management unit 11, registers the logic simulation result information in the signal value management table 17, and stores the simulation time in the time management table 20.
Register with.

The result display control means 13 uses the management data of the window management table 16, the signal value management table 17, the free format window management table 18, the stream window management table 19, and the time management table 20 to generate logical simulation result information. Is displayed on the display 3 of the terminal 2. The command analyzing unit 14 interacts with the user to analyze a command given by the user, creates an instruction management table, and transfers control to the instructed instruction. The function key control unit 15 transfers the command set to the function key specified by the user via the input device 4 of the terminal 2 to the command analysis unit 14 by interacting with the user.

The window management table 16 manages one or more windows to be displayed on the display 3 of the terminal 2. In addition, the signal value management table 17
Manages time-series data of signal values for each signal terminal, which constitutes logic simulation result information. The free format window (FW) management table 18 manages a display mode of a user-defined free format display format. The stream window (SW) management table 19 manages a display mode of a system-defined stream display format that is a time-series display format of the logic simulation result information. The time management table 20 manages the logic simulation time to be displayed and the current display time. The memory management table 21 manages definition data of a logical address space as described later.
Further, the function management table 22 manages command data set in a function key provided in the input device 4 of the terminal 2.

The log output means 23 is a command analysis means 1
Based on the analysis result of No. 4, the one without error is output as a “log”. The window setting unit 24 sets one or more windows (free format window and stream window) to be displayed on the display 3 of the terminal 2 based on the analysis result of the command analysis unit 14 through dialogue with the user. I do. Specifically, for example, when the user desires to display two types of free format windows, in addition to displaying the stream window, a window frame for two free format windows prepared as defaults And through user interaction,
A free format display format desired by the user is assigned to each of these two window frames. This process is the same when displaying two or more types of free format windows. Further, the window setting means 24 has a function of changing the size and arrangement of the window frame for the free format window through a dialog with the user.

The state value selecting means 25 selects a state value in the free format display format displayed on the display 3 of the terminal 2 by interacting with the user. Also,
When the signal value setting means 26 determines that the command is a signal value setting command based on the analysis result of the command analysis means 14, it sets a value to a signal terminal obtained from the analysis result. When the attribute change unit 27 determines that the command is an attribute change command based on the analysis result of the command analysis unit 14, the attribute change unit 27 changes the attribute of the signal terminal obtained from the analysis result. Do not evaluate the corresponding element or circuit.

When the command is determined to be a memory content display command based on the analysis result of the command analysis means 14, the memory content display means 28 refers to the memory management table 21 and displays the corresponding memory content in the terminal. The control is performed so as to be displayed on the display 3 of the second computer. When the command is determined to be a memory content setting command based on the analysis result of the command analysis unit 14, the memory content setting unit 29 rewrites the memory content in the circuit to be simulated.

The simulation executing means 30 transfers control to the logic simulation means 12 when it is determined that the command is a command for executing a simulation based on the analysis result of the command analyzing means 14, and at a specified time. Perform a logic simulation.
Also, the time setting means 31 interacts with the user,
An arbitrary simulation time in the stream display format displayed on the display 3 of the terminal 2 is set, the control is transferred to the logic simulation means 12 via the simulation execution means 30, and the logic simulation is executed until the set simulation time. . If the set simulation time is earlier than the current time, processing is performed to display the simulation result at the set past time in a free format display format.

The memory content selecting means 32 selects a memory content specified by the user from among the memory contents displayed on the display 3 of the terminal 2 by interacting with the user, and sets the selected memory content to the memory content setting. Means 29
Transfer to Then, when the value of the selected memory content is different from the original display value, the memory content setting means 29 performs processing to rewrite the selected memory content.

Hereinafter, various management tables used for the display processing of the logic simulation result information will be described with reference to FIGS.
This will be described in detail with reference to FIG. FIG. 2 is a diagram for explaining the window management table and each table related thereto. In the figure, a window management table 16 shown in (a) manages attribute information of a window displayed on the display 3 of the terminal 2. Specifically, the window set by the window setting means 24 is A window type entry that manages whether the window is a free format window or a stream window, a display position entry that manages a display position of a set window, and a management table position that manages a development position of the display mode data of the set window An entry and a display content entry for managing a development position of the display content data of the previously specified free format window are provided.

The free format window (FW) management table 18 shown in (b) manages the display mode data in the user-defined free format display format as described above. It manages display mode data such as which signal terminal has a signal value displayed at a position. When the free format window type is managed by the window type entry, the window management table 16 manages the development position of the free format window management table 18 that manages the set free format display mode data.

The stream window (SW) management table 19 shown in (c) manages the display mode data of the stream display format defined by the system as described above. Manages display mode data such as which signal terminal signal value is displayed and which signal terminal signal value is displayed in the second row. The window management table 16 described above indicates that when the stream window type is managed by the window type entry,
The expansion position of the stream window management table 19 for managing the set stream display mode data is managed.

The signal value management table 1 shown in FIG.
7 manages the logic simulation result information as described above, and specifically, manages the time-series data of the signal value for each signal terminal for each signal terminal. (E)
The time management table 20 shown in FIG. 1 manages the display time of the target logic simulation and the logic simulation display time indicating the current display time. Further, (f) shows a display content table, which is managed for reuse of the display content data of the previously specified free format window. The above-described window management table 16 manages the development position of the display content table by the display content entry.

As described above, the window management table 16 manages the display mode of one or a plurality of windows to be displayed on the display 3 of the terminal 2, but the display in each set window is free. Free format window (FW) for format display format
This is performed by referring to the management table 18 and the signal value management table 17, and in the case of the stream display format, by referring to the stream window (SW) management table 19 and the signal value management table 17. When the simulation time has elapsed or a time earlier than the current time has been specified, the display simulation time of all windows is synchronized by managing the time using the time management table 20.

When an arbitrary status value displayed in the window of the free format display format is designated, the free format window (FW) management table 18
, The signal terminal corresponding to the instructed state value can be known. Therefore, when the status value on the window is rewritten, the status value is replaced with the circuit information of the designated signal terminal (that is, the logic circuit data information management means 1).
1, the signal value can be set by rewriting the free format display format window.

FIG. 3 is a diagram for explaining the memory management table. In the figure, (a) shows a memory virtual space image defining an address space for specifying a plurality of memory cells (RAM) in a logic circuit to be subjected to a logic simulation, and (b) manages the memory virtual space image. 2 shows a configuration of a memory management table 21 to be executed.

This memory virtual space image is, for example,
It is defined by the memory definition example described below. Memory definition example MEMORY MEMORY01 (('/ RAM SIG11 ',' / RAM SIG1
2 ', …………,' / RAM SIG18 '), (' / RAM SIG21 ',' / R
AM SIG22 ', …………,' / RAM SIG28 '), …………
…, ('/RAM SIG81 ',' / RAM SIG82 ', …………,' / RAM
SIG88 ')) SIZE (512K, 8); In this memory definition example,' / RAM SIG11 ',' / RAM SIG12 ', …… etc.
The figure shows the signal names for the model of each memory cell (RAM).
Eight bits are used to define an 8-bit wide 512K address space.

FIG. 4 is a diagram for explaining memory interleaving. When the addresses are discontinuous due to interleaving or the like, the number of ways is defined, for example, as in the following interleave designation definition example. Interleave specification definition example MEMORY MEMORY01 (('/ RAM SIG11 ',' / RAM SIG1
2 ', …………,' / RAM SIG18 '), (' / RAM SIG21 ',' / R
AM SIG22 ', …………,' / RAM SIG28 '), …………
…, ('/RAM SIG81 ',' / RAM SIG82 ', …………,' / RAM
SIG88 ')) SIZE (512K, 8) INTERLEAVE (8); When the number of ways is 8 as in this example, the lower 3 bits (0 to 18) of 19 bits (0 to 18) as shown in FIG.
2) Move to the higher position and calculate the address. FIG.
, M = 19 means log (number of addresses) = log
(512K), where n = 3 is lo
It is obtained by calculating g (the number of ways) = log (8).

The number of ways, number of addresses, signal names, and the like defined in this way are managed by a memory declaration management table shown in FIG. Then, by accessing the storage area via the auxiliary table expanded by the auxiliary table position entry in the memory declaration management table, the above-mentioned memory virtual space can be created, and the memory contents can be displayed.

Further, even when addresses are discontinuous according to a certain conversion rule, a memory virtual space can be created by performing the above-described interleaving address calculation from the number of ways in the memory declaration management table. Further, in the case of writing to the memory, the memory content can be rewritten by accessing the storage area in the same manner as displaying the memory content.

FIG. 5 is a diagram for explaining the function management table 22. When a function key is operated from the input device 4 of the terminal 2 through dialogue with the user, a command sequence to be executed can be obtained by referring to the illustrated function management table. In FIG.
When the command starts with a command (in the illustrated example, a command for executing a simulation; SIML) as in the command character string of (1), the command is a command analysis unit 1
4 to process the immediate execution of the instruction. In addition, when the command character string has "D" at the beginning like the command character string in (2), the command character string is displayed in a command input area (an area (7) in FIG. 7 described later).

As described above, in the logic simulation system according to the present invention, the logic simulation result information represented in the free format display format and the logic simulation result information represented in the stream display format are multiply displayed on the same display screen. The basic configuration is to display them simultaneously using a window. Of these, the display mode of the stream display format is prepared in advance by the system side, but the display mode of the free format display format is freely defined by the user.

The setting process of the display mode of the free format display format is mainly performed by the window management table 1
6 (Free format window management table 18)
And the window setting means 24. In other words, by allowing the user to specify a display mode such as which signal terminal should display a signal value at which display position with a screen image, and converting this into an internal data format of the logic simulation system 1, One or more free format display formats (for example, windows a and b shown in FIGS. 6 to 10 described later) are set.

Here, both the stream display format and the free format display format allow a plurality of signal terminals to be defined as one group.
GROUP # GRP1 ('DATA0', 'DATA1', 'DATA2', 'DATA
3 ′) ;, the four signal terminals DATAi (i = 0, 1, 2, 3) are defined by a group name “# GRP1”, and this group name is used to define the four signal terminals DATAi. It is also possible to specify that the signal value is displayed in binary or hexadecimal. In accordance with this designation, the display of the signal values of the four signal terminals DATAi is realized by a binary number, for example, "0011".
The display of the signal values of these four signal terminals DATAi is realized by the hexadecimal numbers.

Next, an example of display processing of logic simulation result information by the system according to the present embodiment will be described with reference to FIG.
This will be described with reference to FIGS. FIG. 6 shows a display example in which two windows a and b in the free format display format and a window c in the one stream display format are displayed on the screen of the display 3.

In the figure, (1) shows characters that can be freely set by the user, and (2) shows the state values of the signal terminals set by the user. As described above, this state value can be indicated by one character for one signal terminal or one character (that is, hexadecimal display) for four signal terminals collectively. Also,
(3) is the simulation time, (4) is the signal terminal name,
(5) shows the state value for the signal terminal of (4) along with the simulation time. Also, (6)
Indicates the current simulation time.

FIG. 7 shows the three windows a, b, and c.
And a display example showing a command input area. In the figure,
The part indicated by (7) indicates a command input area for displaying a command (character string) input based on a user's input operation. In the illustrated example, SETS (command for setting a value to a signal terminal) is displayed in the command input area (7), and an instruction to set "1" to a signal terminal "SIG1" is displayed.

FIG. 8 shows a display example in which the state value is directly rewritten by designating the portion (8) in the window a in the display example of FIG. 7 with a pointing device or the like.
This is the same function as the above-described SETS (command for setting a value to a signal terminal), but easily sets a signal value without inputting a long character string in the command input area (7) as shown in FIG. Here are some examples that you can do.

FIG. 9 shows that the command input area (7) has a SIML
7 shows a display example in which (an instruction to execute a simulation) is displayed. In the illustrated example, an instruction to advance the simulation time to t1 is displayed. FIG.
A display example is shown in which the simulation time is advanced to t1 by instructing the portion (9) in the window c in the display example of FIG. 9 with a pointing device or the like. This has the same function as the above-mentioned SIML (simulation execution instruction), but as shown in FIG.
2 shows an example in which a simulation can be easily executed without inputting a character string.

FIG. 11 shows an example of the content display of the memory virtual space image described with reference to FIGS. In the illustrated example, the contents of a virtual space image having a word length of 16K and a bit length of 72 bits are displayed. In the figure,
* 1, * 2, ..., * 16 represent a message display field or a data input field, respectively. That is, * 1 is a memory name display field, * 2 is a word length display field, * 3 is a bit length display field, * 4 is an interleave way number display field, * 5 is a base address display / input field, and * 6 is a display. Head address displacement display / input field, * 7 is the mode of address expression (HEX
/ DEC) display / input field, * 8 indicates vertical scroll amount
Input field, * 9 is horizontal scroll amount display / input field, * 10 is top display column position display / input field, * 11 is template name input field, * 12 is comment display / input field, * 13 is format display / input Column, * 14 is an address display column,
* 15 indicates a data display / input field, and * 16 indicates a command input field.

FIG. 12 shows an example of rewriting the contents of the memory. In the illustrated example, the command input area (7) on the display screen has a SETM (command for rewriting the contents of the memory) in the command input area (7).
Is displayed, whereby '0' is written in the 0th word of the memory space defined as MEMORY01. FIG. 13 shows another example of rewriting the contents of the memory.

The illustrated example shows a display example in which data corresponding to the address "0" in the address display column * 14 in the display example of FIG. 11 is directly specified and rewritten. In this example, rewriting is performed by designating only one location. Of course, it is also possible to designate a plurality of locations and write simultaneously. This is the same function as the above-mentioned SETM (instruction for rewriting the contents of the memory).
2 shows an example in which the memory content can be easily rewritten without inputting a character string in the command input area (7).

FIG. 14 shows an example of a program configuration of the result display control means 13. As shown in the figure, the result display control means 13 includes a window manager 80, an event processing process 81 controlled by the window manager, and a stream window display process 8 started by the event processing process 81, respectively.
2. Free format window display process 83,
A time change process 84, a command processing process 85, a state value change process 86, a memory display process 87, a memory write process 88, and a function key processing process 89 are provided.

FIGS. 15 to 25 show the result display control means 13.
2 shows a flowchart that defines each process included in the process. Hereinafter, the logic simulation processing according to the present embodiment will be described in detail with reference to these flowcharts. <Event processing process 81... See FIG. 15> When an event is input from the terminal 2, first, step 1 is executed.
In step 01, the input event is accepted. In the next step 102, it is determined whether the input event is an event instructing activation of the stream window (SW) display process 82 (Y) or not (N).
Is started, the stream window display process 82 is started, and if the determination result indicates N, the process proceeds to step 103. In step 103, the input event is a free format window (FW) display process 8
3 is determined (Y) or not (N), and if the determination result indicates Y, the free format window display process 83 is activated, and if the determination result indicates N, Go to step 104.

In step 104, it is determined whether the input event is an event for instructing activation of the time change process 84 (Y) or not (N). If the determination result indicates Y, the time change process 84 is executed. Start up and the judgment result is N
When the instruction is given, the process proceeds to step 105. Step 1
In step 05, it is determined whether or not the input event is an event instructing activation of the command processing process 85 (Y) or not (N). If the determination result indicates Y, the command processing process 85 is activated and If the result indicates N, go to step 106. In step 106, it is determined whether or not the input event is an event for instructing activation of the state value change process 86 (Y) or not (N). If the determination result indicates Y, the state value change process 86 is activated. If the determination result indicates N, the process proceeds to step 107.

In step 107, it is determined whether or not the input event is an event for instructing the activation of the memory display process 87 (Y) or not (N). It starts up and proceeds to step 108 when the determination result indicates N. In step 108, the input event is sent to the memory write process 8
It is determined whether the event is an event instructing activation of (8) (Y) or not (N). If the determination result indicates Y, the memory writing process 88 is activated, and if the determination result indicates N, Proceed to step 109.

In step 109, it is determined whether the input event is an event instructing activation of the function key processing process 89 (Y) or not (N).
To indicate the function key processing process 8
9 is started, and if the determination result indicates N, the process proceeds to step 110. In step 110, whether the input event is an end event for instructing the end of the process (Y) or not (N)
If the determination result indicates “Y”, this flow is “end”. If the determination result indicates “N”, the flow returns to step 101 to repeat the above processing.

Thus, the event processing process 8
1 executes the processing flow of FIG. 15 so as to start the process instructed by the input event.
<Stream Window Display Process 82... See FIG. 16> When activated from the event processing process 81, first, in step 201, the logic simulation display time indicating the current display time is read from the time management table 20.
In the next step 202, stream window display data is created using the read logic simulation display time as the standard time. In other words, stream window display data is created by applying the read signal value time-series data of the signal value management table 17 near the logic simulation display time to the display format of the stream window designated by the stream window management table 19. .

In the next step 203, the created stream window display data is displayed in the stream window set by the window setting means 24 (for example, the stream display format window c shown in FIGS. 6 to 10). At this time, the stream window display process 8
2 is the current simulation display time portion ((6) in FIG. 6)
Is changed and the signal value portion (portion (5) in FIG. 6) associated with the simulation display time is displayed in different colors, so that the effect is displayed.

<Free Format Window Display Process 83... See FIG. 17> When started from the event processing process 81, first, at step 301, the logic simulation display time indicating the current display time is read from the time management table 20. In the next step 302, free format window display data is created using the read logic simulation display time as the standard time. That is, by applying the read signal value data of the signal value table 17 of the logic simulation display time to the display format of the free format window designated by the free format window management table 18, the free format window display data is created.

In the next step 303, the created free format window display data is displayed in a free format window set by the window setting means 24 (for example, windows a and b of the free format display format shown in FIGS. 6 to 10). To go. As described above, according to the processes of the stream window display process 82 and the free format window display process 83, the logic simulation result information according to the stream display format and the logic simulation result information according to the free format display format are simultaneously displayed on the display 3 of the terminal 2. Will be.

<Time change process 84: see FIG. 18>
When started from the event processing process 81, first, in step 401, a designated time after the change, which is a new logic simulation display time, is acquired. In the next step 402, it is determined whether or not the designated time is before the current time (Y) or not (N). If the determination result indicates Y, the process proceeds to step 403, where the determination result is N When the instruction is given, the process proceeds to step 404. Step 404
Then, a process of advancing the logic simulation until the designated time is performed, and thereafter, the process proceeds to step 403.

In step 403, the time management table 2
While updating the logic simulation display time of 0,
The window to be processed (ie, the window being displayed)
Is a stream display format (Y) or not (N). If the determination result indicates Y, the process proceeds to step 405. If the determination result indicates N (that is, the window to be processed is free). Format display format)
Go to step 406. In step 406, the signal value of the designated new logic simulation display time is acquired from the signal value management table 17, and the next step 40
In step 7, the acquired signal value is compared with the signal value currently being displayed, and only the difference is changed and displayed in the free format window. Thereafter, this flow is “end”.

On the other hand, in step 405, it is determined whether the designated time is before the current time (Y) or not (N). If the determination result indicates Y, the process proceeds to step 408, where Indicates N, step 409
Proceed to. In step 409, the signal values from the logical simulation display time before the update to the new logical simulation display time specified are read out from the signal value management table 17 and displayed, and then the process proceeds to step 408.
In step 408, the color of the display portion of the designated new logic simulation display time is changed and displayed. Thereafter, this flow is “end”.

In this way, according to the processing of the time change process 84, the logical simulation display time is updated to the one designated by the user, and the display portion of the current simulation display time in the stream window is displayed in a different color. At the same time, the signal value portion that changes due to the update of the logic simulation display time in the signal value display in the free format window is displayed in a different color.

<Command processing process 85... FIG.
When the process is started from the event processing process 81, first, in step 501, it is determined whether the command is input from a file (Y) or not (N), that is, whether the command is input through a dialog with the user. If the determination result indicates Y, the process proceeds to step 502,
If the determination result indicates N, the process proceeds to step 504. In step 502, it is determined whether the command input from the file has not been completed (Y) or not (N). If the determination result indicates Y, the process proceeds to step 503. If the determination result indicates N, the process proceeds to step 503. Indicates that this flow is "end". In step 503, one command character string is input from a file.

In the next step 504, the input command character string is analyzed. In step 505, it is determined whether there is a grammatical error (Y) or not (N) based on the analysis result. If the determination result indicates Y, the process proceeds to step 506, and the determination result indicates N. If so, the process proceeds to step 507. In step 506, an error message is output, and thereafter, the flow ends.

On the other hand, in step 507, it is determined whether or not the input command is SETS (instruction for setting a value to a signal terminal) (Y) or not (N). If the determination result indicates Y, Proceed to step 508, and if the determination result indicates N, proceed to step 509. In step 508, a value is set to the designated signal terminal, and thereafter, the process proceeds to step 515.

On the other hand, in step 509, it is determined whether the input command is SETM (instruction for rewriting the contents of the memory) (Y) or not (N). If the result of the determination indicates Y, step 510 is executed. If the determination result indicates N, the process proceeds to step 511. Step 510
Then, a value is set in the specified memory virtual space, and thereafter, the process proceeds to step 515.

On the other hand, in step 511, it is determined whether or not the input command is CHGV (instruction for changing the attribute of the signal terminal) (Y) or not (N), and if the determination result indicates Y, The process proceeds to step 512, and if the determination result indicates N, the process proceeds to step 513. Step 512
Then, the attribute of the designated signal terminal is changed, and thereafter, the process proceeds to step 515.

On the other hand, in step 513, the inputted command is a SIML (a command for executing a simulation).
Is determined (Y) or not (N). If the determination result indicates Y, the process proceeds to step 514. If the determination result indicates N, the process proceeds to step 515. Step 51
At 4, the logic simulation is executed until the designated time, and thereafter, the process proceeds to step 515.

In step 515, it is determined whether a command is being input from the file (Y) or not (N). If the determination result indicates Y, the process returns to step 502 and the above processing is repeated. Indicates N, the flow ends. In this way, according to the processing of the command processing process 85, the time at which the specified condition of the command is satisfied is set as the logic simulation display time.
The display data in the window in the free format display format, the display data in the window in the stream display format, and the content display data of the memory virtual space image are updated.

<State Value Change Process 86... FIG. 21> When activated from the event processing process 81, first, in step 601, the display position of the designated state value in the window of the free format display format and the rewritten value Window management table 16, free format window management table 18, and signal value management table 17.
To get from. In the next step 602, it is determined whether or not the designated display position allows the setting of the state value (Y) or not (N). If the determination result indicates Y, the process proceeds to step 603, where the determination is made. If the result indicates N, go to step 605.

In step 603, the signal terminal corresponding to the designated display position is obtained from the free format window management table 18, and in the next step 604,
The state value is set to the obtained signal terminal. As a result, the state value at the designated display position in the free format window is changed and displayed. Thereafter, this flow is “end”.

On the other hand, in step 605, an error message is output, and thereafter, this flow ends.
In this way, the signal terminal corresponding to the display position is specified from the designation of the display position on the free format window and the designation of the state value to be rewritten according to the processing of the state value change process 86, and the state value of the signal terminal Will be changed and displayed.

<Memory Display Process 87... FIG. 22> When started from the event processing process 81, first, in step 701, the virtual process is performed by referring to the memory management table 21 as described with reference to FIGS. Generate a spatial image. In the next step 702, the generated virtual space image is displayed on the display 3 of the terminal 2 (for example, see FIGS. 11 and 13). After this, the flow is "finished"
Becomes

<Memory Write Process 88... FIG.
3, FIG. 24> (1) First Example See FIG. 23 When activated from the event processing process 81, first, in step 801, the position and the state value specified directly on the display screen through the dialogue with the user are displayed. get. In the next step 802, an area to be accessed in the storage area of the memory management table 21 (that is, a storage area specified by an address indicating the obtained position) is obtained based on the obtained position. Next step 803
Then, the designated state value is set in the obtained area. As a result, the memory content corresponding to the position directly specified on the display screen is rewritten. Thereafter, this flow is “end”.

(2) Second Example: Refer to FIG. 24 When activated from the event processing process 81, first, step 85
In step 1, when it is determined that the input command is an instruction (SETM) for rewriting the memory contents, an area to be accessed is obtained from the memory management table 21. In the next step 852, the above-mentioned SETM is stored in the obtained area.
Set the state value indicated by. by this,
The contents of the memory corresponding to the position specified on the display screen are rewritten based on the SETM. Thereafter, this flow is “end”.

<Function key processing process 89 ...
... FIG. 25> When activated from the event processing process 81, first, in step 901, information indicating the number of the function key operated by the user is acquired from the function management table 22. In the next step 902, based on the acquired number information, it is determined whether a specific command is set to the operated function key (Y) or not (N), and the determination result indicates Y. In this case, the process proceeds to step 903, and if the determination result indicates N, the flow ends.

In step 903, it is determined whether the command is an instruction to be executed immediately (Y) or not (N). If the determination result indicates Y, the process proceeds to step 904, where the determination result is N Step 905 when instructing
Proceed to. In step 905, the designated command character string is entered in the command input area ((7) on the display screen shown in FIG. 19).
Part), and thereafter, this flow is “end”.

On the other hand, in step 904, the designated command character string is stored in the command processing process (FIG. 19, FIG. 19).
(See FIG. 20) to execute immediately. Thereafter, this flow is “end”. As described above, in the logic simulation system according to the present embodiment, the result display control unit 13 refers to the management data of the window management table 16 (free format window management table 18) and the signal value management table 17 and By setting the signal value of the current display time of the signal terminal of the free format display format, the logic simulation result information in the free format display format at the current display time is specified, and the window management table 16 (stream window management table 19) ) And the management data of the signal value management table 17 to identify the time-series data of the signal value including the current display time of the signal terminal having the stream display format, thereby enabling the display in the stream display format including the current display time. Logic simulation result information A constant. Then, the specified logic simulation result information in the free format display format and the logic simulation result information in the stream display format are simultaneously displayed in the set windows on the display screen.

Then, the command analysis means 14 analyzes the command input through the input / output control means 10 by interacting with the user through the display 3, and as a result, the command is transmitted to the signal terminal. If the command is a value setting command, the control is passed to the signal value setting means 26. The signal value setting means 26 changes the state of the signal value by notifying the logic circuit data information management means 11 of the change. When setting the signal value, the signal value may be collectively set to a plurality of signal terminals by binary display or hexadecimal display.

The state value selecting means 25 selects a state value in the free format display format by interacting with the user via the display screen. Then, when it is determined that the selected state value is different from the original display value, the signal terminal corresponding to the selected state value is referred to the window management table 16 and the input value is changed. At the same time, the signal is passed to the signal value setting means 26. In response to this, the signal value setting means 26 directly changes the designated state value in the free format display format.

The time setting means 31 selects the simulation time in the stream display format by interacting with the user via the display screen. If it is determined that the selected simulation time is earlier than the current time, the simulation execution means 30
The simulation is advanced to the selected simulation time.

On the other hand, the memory contents selecting means 32 selects the memory contents designated by the user from the memory contents displayed on the display screen by interacting with the user via the display screen. Then, when it is determined that the value of the specified memory content is different from the original display value, the control is referred to the memory management table 21 and the control is transferred to the memory content setting means 29, so that the specified memory content is set. Rewrite the contents of the stored memory.

As described above, according to the logic simulation system of the present embodiment, the logic simulation result information in the free format display format enabling display of the signal values of a large number of signal terminals, and the temporal analysis of the signal values of the signal terminals. The basic configuration is to simultaneously display the logic simulation result information in the stream display format that can grasp the flow in a multi-window format on the same display screen, and to display the contents of the memory virtual space image on the display screen This eliminates the need for input instructions, etc., by selecting menus, setting status values by writing directly on the free format display, executing simulations by directly indicating the time portion on the stream display, and executing memory contents. Write memory contents by writing directly on the display It adopts a configuration or replaced.

Therefore, the user can easily and efficiently execute the logic simulation and analyze the logic simulation without being conscious of complicated procedures and operations concerning the logic simulation. Also, when thinking about the next stage of the simulation procedure, reduce the interruption of that thinking,
An efficient simulation can be performed.

In the above-described embodiment, the configuration in which the color of the display portion on the display screen is changed to draw the user's attention has been described. However, the present invention is not limited to this. Other configurations, such as changing or flickering, are also possible.

The present invention further includes the following embodiments. (Supplementary Note 1) Interaction with a user via the display screen in an interactive logic simulation system having a configuration in which a logic simulation is performed by interacting with the user via the display screen and the result is displayed on the display screen. A setting unit (24) for setting at least one display format of the logic simulation result information in a window defined by an arbitrary display range, and a display mode of a free format display format set by the setting unit. A first management table (16, 18), a second management table (16, 19) for managing a display mode of a stream display format that is a time-series display format of the logic simulation result information, and a logic simulation result information. Manages time-series data of signal values for each signal terminal Third management table to be executed (17)
Result display control means for specifying logic simulation result information using the management data of the first, second, and third management tables, and performing processing to display the specified logic simulation result information on the display screen. (1
3) the logic simulation result information in a free format display format at a specified time and the logic simulation result information in a stream display format of a specified signal terminal are respectively set in a set window on the display screen. An interactive logic simulation system characterized by being displayed simultaneously.

(Supplementary Note 2) In the interactive logic simulation system according to Supplementary Note 1, means (11) for managing logic circuit data information associated with signal terminals of a logic circuit to be subjected to logic simulation, and the display Means (14) for analyzing a command given by a user through interaction with a screen; and, when the command is a command (SETS) for instructing a signal value setting to a signal terminal based on the analysis result, Means (26) for setting a signal value by changing information of a signal value corresponding to a designated signal terminal among circuit data information.

(Supplementary Note 3) In the interactive logic simulation system according to Supplementary Note 2, the means for setting a signal value may be a signal based on a command by designating a single signal terminal name or a group name in which a plurality of signal terminals are put together. An interactive logic simulation system characterized by setting signal values to terminals.

(Supplementary Note 4) In the interactive logic simulation system according to Supplementary Note 3, when the signal value setting to the signal terminal is performed by designating a group name, the result display control unit may output the logic simulation result information. An interactive logic simulation system, wherein a signal value is displayed in a hexadecimal number or a binary number to perform processing to collectively display signal values of a plurality of signal terminals.

(Supplementary Note 5) In the interactive logic simulation system according to Supplementary Note 1, means (11) for managing logic circuit data information associated with signal terminals of a logic circuit to be subjected to logic simulation, and the display Means (25) for selecting a state value designated by the user from the state values displayed in the free format display format window by interacting with the user via the screen; If the displayed value is different from the displayed value, the signal terminal corresponding to the selected state value is specified by referring to the first management table, and the specified signal terminal of the logic circuit data information is specified. Means (25, 2) for changing the state value information at the corresponding current time
6) An interactive logic simulation system comprising:

(Supplementary Note 6) In the interactive logic simulation system according to Supplementary Note 1, means (11) for managing logic circuit data information associated with signal terminals of a logic circuit to be subjected to logic simulation, and the display Means (14) for analyzing a command given by a user through interaction with a screen; and, when the command is a command for instructing an attribute change based on the result of the analysis, the command is specified in the logic circuit data information. Means (27) for performing processing so as not to evaluate a corresponding element or circuit in the circuit to be simulated by changing attribute information of a signal terminal.

(Supplementary Note 7) In the interactive logic simulation system according to Supplementary Note 1, means (14) for analyzing a command given by a user through a dialog with the display screen, and the command is generated based on the analysis result. Means (30, 12) for executing a logic simulation at a time specified by the instruction when the instruction is a simulation execution instruction (SIML).

(Supplementary Note 8) In the interactive logic simulation system according to supplementary note 1, by interacting with the user via the display screen, an arbitrary simulation time in a stream display format window displayed on the display screen is displayed. Means (31) for setting
Means (30, 12) for executing a logic simulation until the set simulation time.

(Supplementary Note 9) In the interactive logical simulation system according to supplementary note 8, when the set simulation time is a time earlier than the current time, the result display control means may set the past time. An interactive logic simulation system characterized by performing a process of displaying logic simulation result information at a time of a time in a free format display format.

(Supplementary Note 10) In the interactive logic simulation system described in Supplementary Note 1, a function management table (management) for managing command data set in a function key provided in an input device (4) operated by a user. 22) identifying a command set in a function key designated by a user through interaction with the display screen from the fact management table, and immediately executing a defined command according to the content of the identified command. Means (15, 14) for controlling execution processing or display processing of the command in a specific display area in the display screen.

(Supplementary Note 11) In the interactive logic simulation system according to supplementary note 1, means (14) for analyzing a command given by a user through a dialog with the display screen, and an error based on an analysis result of the command. Means (23) for outputting, as a log, those which did not have an error.

(Supplementary Note 12) In the interactive logic simulation system described in Supplementary Note 1, a memory management table for managing data defining a logical address space for specifying a plurality of memory cells (RAM) in a circuit to be subjected to a logic simulation ( 21) further comprising a step of displaying the memory contents on the display screen in a memory virtual space image defined by the logical address space with reference to the memory management table. Simulation system.

(Supplementary Note 13) In the interactive logic simulation system according to supplementary note 12, means (14) for analyzing a command given by a user through a dialog with the display screen, and the command is generated based on the analysis result. Means (28, 13) for performing processing to display the corresponding memory content on the display screen by referring to the memory management table when the command is an instruction to display the memory content. Interactive logic simulation system.

(Supplementary Note 14) In the interactive logic simulation system according to supplementary note 12, means (14) for analyzing a command given by a user through a dialog with the display screen, and the command is generated based on the analysis result. Means (29) for performing processing to rewrite the memory contents of the memory cell in the circuit to be simulated in the case of a memory content setting instruction (SETM).

(Supplementary Note 15) In the interactive logic simulation system according to supplementary note 12, by interacting with the user via the display screen, the memory contents specified by the user among the memory contents displayed on the display screen Means for selecting (32), and when the value of the selected memory content is different from the original display value, performing a process of rewriting the selected memory content with reference to the memory management table. Means (32, 2)
9) An interactive logic simulation system comprising:

(Supplementary Note 16) In the interactive logic simulation system according to Supplementary Note 12, addresses specifying a plurality of memory cells in the circuit to be simulated are set discontinuously according to a predetermined conversion rule for interleaving or the like. In the case, when displaying the memory contents on the display screen in the memory virtual space image corresponding to the address space, the data is continuously displayed on the memory virtual space by rearranging the data according to the predetermined conversion rule. An interactive logic simulation system characterized by performing processing to perform.

(Supplementary Note 17) In the interactive logic simulation system according to Supplementary Note 16, when an arbitrary address and a bit value in the memory cell virtual space displayed on the display screen are rewritten, the address conversion of Supplementary Note 16 is reversed. An interactive logic simulation system, wherein an address for a memory cell in a circuit to be simulated is calculated by conversion, and data is rearranged to rewrite the contents of the memory cell.

[0101]

As described above, according to the present invention, a state value is set by directly writing on a free format display, a simulation is executed by designating a time portion on a stream display, Since the contents of the memory can be rewritten by directly writing on the memory contents display, the user can easily and efficiently execute and analyze the simulation without being conscious of troublesome procedures and operations related to the simulation. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of an interactive logic simulation system according to the present invention.

FIG. 2 is an explanatory diagram of a window management table in FIG. 1 and tables related thereto.

FIG. 3 is an explanatory diagram of a memory management table in FIG. 1;

FIG. 4 is an explanatory diagram of memory interleaving.

FIG. 5 is an explanatory diagram of a function management table in FIG. 1;

FIG. 6 is a diagram showing a first example of a process of displaying logic simulation result information by the system of FIG. 1;

FIG. 7 is a diagram showing a second example of the display processing of the logic simulation result information by the system of FIG. 1;

FIG. 8 is a diagram showing a third example of the display processing of the logic simulation result information by the system of FIG. 1;

FIG. 9 is a diagram showing a fourth example of the display processing of the logic simulation result information by the system of FIG. 1;

FIG. 10 is a diagram showing a fifth example of the display processing of the logic simulation result information by the system of FIG. 1;

11 is a diagram showing an example of a content display of a memory virtual space image by the system of FIG. 1;

FIG. 12 is a diagram illustrating an example of rewriting the contents of a memory.

FIG. 13 is a diagram showing another example of rewriting the contents of a memory.

FIG. 14 is a block diagram illustrating an example of a program configuration of a result display control unit in FIG. 1;

FIG. 15 is a flowchart illustrating an example of the event processing process illustrated in FIG. 14;

FIG. 16 is a flowchart showing an example of the stream window display process shown in FIG.

FIG. 17 is a flowchart showing an example of a free format window display process shown in FIG.

FIG. 18 is a flowchart illustrating an example of a time change process illustrated in FIG. 14;

FIG. 19 is a flowchart illustrating an example (part 1) of the command processing process illustrated in FIG. 14;

FIG. 20 is a flowchart illustrating an example (part 2) of the command processing process illustrated in FIG. 14;

FIG. 21 is a flowchart illustrating an example of a state value changing process illustrated in FIG. 14;

FIG. 22 is a flowchart illustrating an example of a memory display process illustrated in FIG. 14;

FIG. 23 shows a first example of the memory writing process shown in FIG. 14;
6 is a flowchart showing an example of the above.

FIG. 24 shows a second example of the memory writing process shown in FIG.
6 is a flowchart showing an example of the above.

FIG. 25 is a flowchart illustrating an example of a function key processing process illustrated in FIG. 14;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Interactive logic simulation system 2 ... Terminal 3 ... Display 4 ... Input device (keyboard, mouse, etc.) 10 ... Input / output (I / O) control means 11 ... Logic circuit data (LD) information management means 12 ... Logic simulation means Reference Signs List 13 Result display control means 14 Command analysis means 15 Function key control means 16 Window management table 17 Signal value management table 18 Free format window (FW) management table 19 Stream window (SW) management table 20 Time management table 21 Memory management table 22 Function management table 23 Log output means 24 Window setting means 25 State value selecting means 26 Signal value setting means 27 Attribute changing means 28 Memory contents displaying means 29 Memory contents Setting means 0 ... simulation execution means 31 ... time setting means 32 ... memory content selection means

Claims (8)

[Claims] 1. A logic simulation system for displaying a result of a logic simulation on a screen, comprising: a logic simulation result information in a free format display format for displaying a signal value of a signal terminal only at a designated time; A display unit for displaying on the screen logical simulation result information in a stream display format that is a time-series display format of signal values; and an execution unit for executing a logic simulation at a specified time. Features a logic simulation system. 2. The logic simulation system according to claim 1, further comprising setting means for setting display of each of said logic simulation result information in a corresponding window. 3. The logic simulation system according to claim 1, further comprising setting means for setting a display form of the logic simulation result information based on a user's instruction. 4. The logic simulation system according to claim 1, further comprising the execution unit that executes a logic simulation until a time designated by the user according to a command input by the user. 5. An input / output control device for controlling a logic simulation device and displaying a result of the logic simulation device on a screen, wherein a logic simulation result in a free format display format for displaying a signal value of a signal terminal only at a specified time. Result display control means for displaying, on a screen, logic simulation result information in a stream display format that is a time-series display format of the signal value of the signal terminal including the information and the designated time, An execution means for executing a logic simulation at a time when the input / output control is performed. 6. The input / output control device according to claim 5, further comprising setting means for setting display of each of said logic simulation result information in a corresponding window. 7. The input / output control device according to claim 5, further comprising setting means for setting a display form of the logic simulation result information based on a user's instruction. 8. The logic simulation apparatus according to claim 5, wherein the execution means causes the logic simulation apparatus to execute a logic simulation up to a time designated by a command input by a user. Input / output control unit.