JP2002132747A - Fft arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make compatible both efficient processing and the expansion of available target data while effectively utilizing a circuit area when the number of sample data is large. SOLUTION: In this FFT arithmetic circuit, a crossing processing part 14 for outputting the data of the butterfly arithmetic result of a radix 8 from a first signal line group is provided with second and third signal line groups for extracting intermediate data in the middle of the relevant butterfly arithmetic. Then, the intermediate data corresponding to the butterfly arithmetic result of a radix 2 are outputted from the first signal line group, and the intermediate data corresponding to the butterfly arithmetic result corresponding to a radix 4 are outputted from the second signal line group.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FFT (Fast Fourier Transform) operation circuit used for digital signal processing. In this specification, for example, “2 * 8 ^ n” means “2 × (8 n)”
Shall mean.

[0002]

2. Description of the Related Art FFT is a technique used for extracting a frequency component hidden in a series of sample data in a time domain, and has an excellent feature that a large number of data can be processed in a short time. Further, when the FFT is implemented by hardware, a circuit having a small area is required.

When an FFT operation is performed on an object having the same number of data, the higher the value of the radix of the butterfly operation, the higher the processing speed. Assuming that the number of data to be subjected to FFT is N, the number of butterfly operations until the end of the FFT operation is (N / 2) log2N in radix 2, (N / 4) log 4 N in radix 4,
In radix 8, it becomes (N / 8) log8N. The number of multiplications per butterfly is 4 for radix 2, 12 for radix 4, and 3 for radix 8.
It becomes 2. Therefore, the number of multiplications is 4 * (N / 2) log in base 2
2N, radix 4 is 12 * (N / 4) log4N, radix 8 is 32 * (N / 8) log8N, and the number of multiplications for radix 2 and radix 4 is 1.5 times and 1.125, respectively, for simple calculations. Double.

On the other hand, the number of data to be processed in the FFT is a power of the radix. Therefore, the radix-2 butterfly operation can handle the number of data of 256, 512, 1024, 2048, 4096,. On the other hand, in the radix-8 butterfly operation, only the number of powers of 8, that is, 512, 4096,...

[0005]

Since this problem is the same for the radix-4 butterfly operation, the radix-4 FF is used.
In T, the target data is limited to a power of four. In Japanese Patent Application Laid-Open No. 10-307811, this problem is solved by incorporating a circuit for processing a radix-2 butterfly operation in a radix-4 butterfly operation circuit. However, even when the number of data is large, the calculation is limited to the radix-4 butterfly operation, and the operation efficiency is lower than that of the radix-8 butterfly operation.

[0006] A method of connecting a butterfly operation having a small radix to a butterfly operation having a large radix is conceivable.
For example, a radix-2 butterfly operation is connected to a radix-8 butterfly operation to process the data number 2 * 8 ^ n. However, by performing a radix-2 butterfly operation on one stage after performing a radix-8 butterfly operation on N stages, the radix-2 butterfly operation circuit is not utilized while the radix-8 butterfly operation is being processed. The circuit area cannot be used effectively.

[0007]

As described above, the radix-8 butterfly operation realizes efficient processing when the number of sample data is large, but has a problem that the number of available sample data is limited. Therefore, an object of the present invention is to
An object of the present invention is to provide an FFT operation circuit capable of achieving both efficient processing when the number of sample data is large and expansion of the number of available sample data while effectively utilizing the circuit area.

[0008]

According to the FFT operation circuit of the present invention, if a single integer equal to or greater than 2 is α, and at least one integer from 1 to α−1 is β, a radix-2 raised to the power of α. The present invention is characterized in that a radix-2 .beta.-th power butterfly operation is performed using a part of a butterfly operation circuit (claim 1). More specifically, the crossing processing unit that outputs data of the butterfly operation result of the radix-2 α power from the αth signal line group includes a βth signal line group that extracts intermediate data in the middle of the butterfly operation. The intermediate data corresponding to a result of a butterfly operation of a radix-2 raised to the power of β is output from the β-th signal line group (claim 2).

For example, the α is 3 and the β is 1 and 2 (claims 3 and 4). At this time, the crossing processing unit includes a first adder / subtractor group for performing addition / subtraction of input data, a second adder / subtractor group for performing addition / subtraction for output data of the first adder / subtractor group, and a second adder / subtractor group. A third adder / subtractor group for performing addition / subtraction on output data of the adder / subtractor group,
A multiplier group for performing multiplication on a part of the output data of the third adder / subtractor group, and a fourth adder / subtractor for performing addition / subtraction on the output data of the multiplier group and a part of the output data of the adder / subtractor group A group, the first signal line group for extracting output data of the first adder / subtractor group, the second signal line group for extracting output data of the second adder / subtractor group, the third and the And a third signal line group for extracting output data of a fourth adder / subtractor group.

At this time, the first and second adder / subtractor groups each include eight 2-input / one-output adders and eight 2-input / one-output subtractors, and the third adder-subtractor group includes The fourth adder / subtractor group comprises six 2-input 1-output adders and 6 2-input 1-output subtractors, and the 4-adder-subtracter group comprises four 2-input 1-adders.
It may be composed of an output adder and four two-input one-output subtractors (claim 6).

Hereinafter, the case where α is 3 and β is 1 and 2 will be described as an example. The radix-8 butterfly operation realizes efficient processing when the number of sample data is large, but has a problem that the number of available sample data is limited. The present invention is intended to solve this problem by processing radix-2 and radix-4 butterfly operations in a radix-8 butterfly operation circuit. In the FFT operation circuit according to the present invention,
8 ^ n (= 2 ^ (3n)), 2 * 8 ^ n (= 2 ^ (3n + 1)), 4 * 8 ^
Since n (= 2 ^ (3n + 2)) can be targeted, all targets that can be handled by the radix-2 butterfly operation circuit can be covered. In addition, since radix-2 and radix-4 butterfly computations are performed using a radix-8 butterfly computation circuit,
The circuit area can be used effectively.

[0012]

FIG. 1 is a block diagram showing one embodiment of an FFT operation circuit according to the present invention. FIG. 2 is a block diagram showing an internal configuration of the crossing processing unit and a connection relationship between the crossing processing unit and the selector in the FFT operation circuit of FIG. Hereinafter, description will be made based on these drawings.

The FFT operation circuit according to the present embodiment uses a part of a radix-8 butterfly operation circuit to form a radix-2 and a radix-4.
Of the data storage unit 1.
1, a twist coefficient storage unit 12, a twist coefficient multiplying unit 13, a crossing processing unit 14, a selector 15, a control unit 16, and the like. The feature of the present embodiment is that the crossing processing unit 14, the selector 15, and the control unit 1 which form the core of the butterfly operation
At 6.

The radix-8 butterfly operation result data is output from the signal line group sig3 of the crossing processor 14. In addition, a signal line group sig1 and a signal line group sig2 are set, and intermediate data is extracted therefrom to obtain data corresponding to a processing result of a radix-2 butterfly operation from the signal line group sig1 and a radix from the signal line group sig2. Data corresponding to the processing result of the butterfly operation of No. 4 is obtained. Therefore, the radix-8 butterfly operation circuit also performs radix-2 and radix-4 butterfly operations, so that 2 *
It is possible to process 8 ^ n or 4 * 8 ^ n data.

The data storage unit 11 stores initial data before starting the FFT operation. The intermediate data is stored during the FFT processing, and the processing result data is stored at the end of the FFT operation. The twist coefficient storage unit 12 stores a twist coefficient. When the number of data to be subjected to the FFT is N, the stored twist coefficients are k, 0, 1, 2,.
Then, sin (2πk / N) and cos (2πk / N) are obtained. The twist coefficient multiplying unit 13 multiplies the data output from the data storage unit 11 by the twist coefficient output from the twist coefficient storage unit 12. The crossing processing unit 14 performs a crossing process on the data output from the twist coefficient storage unit 12, and from the signal line group sig1, the data corresponding to the processing result of the radix-2 butterfly operation, and the signal line group sig2. Represents data and signal lines corresponding to the processing result of the radix-4 butterfly operation
The radix-8 butterfly operation processing result data is output from sig3. The selector 15 controls the signal line groups sig1, sig1
2. The data output from sig3 is selected and output to the data storage unit 11.

The crossing processing unit 14 includes an adder / subtracter group as1 for performing addition / subtraction of input data, an adder / subtractor group as2 for performing addition / subtraction for output data of the adder / subtractor group as1, and an adder / subtractor for performing addition / subtraction for output data of the adder / subtractor group as2. Group as3, multiplier group mul1, which performs multiplication on a part of the output data of adder / subtractor group as3, output data of multiplier group mul1, and adder / subtractor group as3
Adder / subtracter group that performs addition and subtraction with a part of the output data of
as4, signal line group si for extracting output data of adder / subtractor group as1
g1, signal line group sig for extracting output data of adder / subtractor group as2
2. A signal line group sig3 for extracting output data from the adder / subtracter groups as3 and as4 is provided.

Each of the adder / subtractor groups as1 and as2 is composed of eight two-input / one-output adders and eight two-input / one-output subtractors. The adder / subtractor group as3 is composed of six two-input / one-output adders and six.
The two-input one-output subtractor, and the adder-subtractor group as4 has four
It consists of two 2-input 1-output adders and 4 2-input 1-output subtractors. The selector 15 selects one of the signal line groups sig1, sig2, and sig3 of the crossing processing unit 14 according to a control signal from the control unit 16, and outputs respective data.

Next, the operation of the FFT operation circuit of this embodiment will be described in detail. First, the radix-8 butterfly operation will be described, and then the radix-2 and radix-4 butterfly operations will be described. Then, a method of realizing the radix-2 butterfly operation and the radix-4 butterfly operation in the radix-8 butterfly operation will be described.

In the radix-8 butterfly operation, discrete Fourier transform of eight points is performed. The eight-point butterfly operation is represented by equation (1). Xn = Σ ⁷ _{k = 0} x_k * W ^ (n * k) ---- (1) n = 0,1,2, ..., 7 where W is the rotator represented by equation (2) . j is an imaginary unit hereinafter. W = exp (-2πj / 8) ---- (2)

When Expression (1) is expanded, Expressions (3) to (10) are expressed. X0 = x0 + x1 + x2 + x3 + x4 + x5 + x6 + x7 ---- (3) X1 = x0 + t (1-j) * x1-j * x2 + t (-1-j) * x3 -x4-t (1-j) * x5 + j * x6-t (-1-j) * x7 ---- (4) X2 = x0-j * x1-x2 + j * x3 + x4-j * x5-x6 + j * x7 ---- (5) X3 = x0 + t (-1-j) * x1 + j * x2 + t (1-j) * x3-x4-t (-1-j) * x5-j * x6-t (1-j) * x7 ---- (6) X4 = x0-x1 + x2-x3 + x4-x5 + x6-x7 ---- (7) X5 = x0 + t (-1 + j) * x1-j * x2 + t (1 + j) * x3-x4 + t (-1 + j) * x5 + j * x6-t (1 + j) * x7 --- -(8) X6 = x0 + j * x1-x2-j * x3 + x4 + j * x5-x6-j * x7 ---- (9) X7 = x0 + t (1 + j) * x1 + j * x2 + t (-1 + j) * x3-x4-t (1 + j) * x5-j * x6-t (-1 + j) * x7 ---- (10) where t is a constant 1. / √2.

The data handled here is complex data. Therefore, the real part of the butterfly operation input data xi is a
i, imaginary part bi, real part of output data Xi Ai, imaginary part B
Let i be the formula (9) from the formulas (2).
It is expressed as 6). Also, as shown in equation (26) from equation (11),
a0, a1, ..., a7, b0, b1, ..., b7 to A0, A1, ..., A7,
FIG. 3 illustrates a process of calculating B0, B1,..., B7. A0 = a0 + a4 + (a1 + a5) + (a2 + a6) + (a3 + a7) ---- (11) A2 = a0 + a4 + (b1 + b5)-(a2 + a6)-(b3 + b7 ) ---- (12) A4 = a0 + a4- (a1 + a5) + (a2 + a6)-(a3 + a7) ---- (13) A6 = a0 + a4- (b1 + b5)- (a2 + a6) + (b3 + b7) ---- (14) A1 = a0-a4 + t (a1-a5) + t (b1-b5) + (b2-b6) -t (a3-a7) + t (b3-b7) ---- (15) A3 = a0-a4-t (a1-a5) + t (b1-b5)-(b2-b6) + t (a3-a7) + t (b3 -b7) ---- (16) A5 = a0-a4-t (a1-a5) -t (b1-b5) + (b2-b6) + t (a3-a7) -t (b3-b7)- --- (17) A7 = a0-a4 + t (a1-a5) -t (b1-b5)-(b2-b6) -t (a3-a7) -t (b3-b7) ---- ( 18) B0 = b0 + b4 + (b1 + b5) + (b2 + b6) + (b3 + b7) ---- (19) B2 = b0 + b4- (a1 + a5)-(b2 + b6) + ( a3 + a7) ---- (20) B4 = b0 + b4- (b1 + b5) + (b2 + b6)-(b3 + b7) ---- (21) B6 = b0 + b4 + (a1 + a5 )-(b2 + b6)-(a3 + a7) ---- (22) B1 = b0-b4 + t (b1-b5) -t (a1-a5)-(a2-a6) -t (b3- b7) -t (a3-a7) ---- (23) B3 = b0-b4-t (b1-b5) -t (a1-a5) + (a2-a6) + t (b3-b7) -t (a3-a7) ---- (24) B5 = b0-b4-t (b1-b5) + t (a1-a5)-(a2-a6) + t (b3-b7) + t (a3-a7 ) ---- (25) B7 = b0-b4 + t (b1-b5) + t (a1-a5) + (a2-a6) -t (b3-b7) + t (a3-a7) --- -(26)

Here, the variable ap is calculated as shown in equations (27) to (42).
0, am0, ap1, am1, ap3, am2, ap3, am3, bp0, bm0, bp
Set 1, bm1, bp2, bm2, bp3, bm3. This corresponds to the output of the adder / subtractor group as1 in FIG. ap0 = a0 + a4 ---- (27) am0 = a0-a4 ---- (28) ap1 = a1 + a5 ---- (29) am1 = a1-a5 ---- (30) ap2 = a2 + a6 ---- (31) am2 = a2-a6 ---- (32) ap3 = a3 + a7 ---- (33) am3 = a3-a7 ---- (34) bp0 = b0 + b4 ---- (35) bm0 = b0-b4 ---- (36) bp1 = b1 + b5 ---- (37) bm1 = b1-b5 ---- (38) bp2 = b2 + b6- --- (39) bm2 = b2-b6 ---- (40) bp3 = b3 + b7 ---- (41) bm3 = b3-b7 ---- (42)

Further, the variable aap is calculated as shown in equations (43) to (58).
0, apm0, app1, apm1, amp0, amm0, amp1, amm1, bpp
0, bpm0, bpp1, bpm1, bmp0, bmm0, bmp1, bmm1 are set. This corresponds to the output of the adder / subtractor group as2 in FIG. app0 = ap0 + ap2 ---- (43) apm0 = ap0-ap2 ---- (44) app1 = ap1 + ap3 ---- (45) apm1 = ap1-ap3 ---- (46) amp0 = am0 + bm2 ---- (47) amm0 = am0-bm2 ---- (48) amp1 = am1 + bm3 ---- (49) amm1 = am1-bm3 ---- (50) bpp0 = bp0 + bp2 ---- (51) bpm0 = bp0-bp2 ---- (52) bpp1 = bp1 + bp3 ---- (53) bpm1 = bp1-bp3 ---- (54) bmp0 = bm0 + am2- --- (55) bmm0 = bm0-am2 ---- (56) bmp1 = bm1 + am3 ---- (57) bmm1 = bm1-am3 ---- (58)

When these are used to express equations (11) to (26), equations (59) to (74) are obtained. This corresponds to the operation of the addition / subtraction group as3, the addition / subtraction group as4, and the multiplier group mul1 in FIG. A0 = app0 + app1 ---- (59) A4 = app0-app1 ---- (60) A2 = apm0 + bpm1 ---- (61) A6 = apm0-bpm1 ---- (62) A1 = amp0 + t * (amp1 + bmm1) ---- (63) A5 = amp0-t * (amp1 + bmm1) ---- (64) A3 = amm0-t * (amm1-bmp1) ---- ( 65) A7 = amm0 + t * (amm1-bmp1) ---- (66) B0 = bpp0 + bpp1 ---- (67) B4 = bpp0-bpp1 ---- (68) B2 = bpm0-apm1- --- (69) B6 = bpm0 + apm1 ---- (70) B1 = bmm0-t * (amp1-bmm1) ---- (71) B5 = bmm0 + t * (amp1-bmm1) --- -(73) B3 = bmp0-t * (amm1 + bmp1) ---- (72) B7 = bmp0 + t * (amm1 + bmp1) ---- (74)

Next, the radix-2 butterfly operation will be described, and a method of implementing the radix-2 butterfly operation in the above-described radix-8 butterfly operation will be described.

The radix-2 butterfly operation is represented by equation (75). Xn = Σ ¹ _{k = 0} x_k * W ^ (n * k)-(75) n = 0,1 where W is represented by the equation (76). W = exp (-2πj / 2) ---- (76)

Therefore, the radix-2 butterfly operation is performed using the radix-8
Expressions (11) to (26) in the butterfly operation of (7) result in expressions (77) to (80). A0 = a0 + a1 ---- (77) A1 = a0-a1 ---- (78) B0 = b0 + b1 ---- (79) B1 = b0-b1 ---- (80)

The four-term set of equations (77), (78), (79), and (80) is a four-term set of equations (27), (28), (35), and (36), and equation (29) ), (3
0), (37), (38), Eqs. (31), (32), (39), (40), Eqs. (33), (34), (41), ( Correspondence can be obtained with the four-item set in 42). Therefore, two data 4 inputs for performing a radix-2 butterfly operation are input to (a0, a4, b0, b4) or (a2, a6, b2, b6), (a
1, a5, b1, b5), corresponding to (a3, a7, b3, b7), the result of addition and subtraction (ap0, am0, bp0, bm0) or (ap2, am2, b
(p2, bm2), (ap1, am1, bp1, bm1), (ap3, am3, bp3, bm
By obtaining 3), a radix-2 butterfly operation result can be output.

That is, in the radix-8 butterfly operation as shown in FIG. 3, a0, a1,..., A7, b0, b1,.
Input in consideration of the above combination, and adder / subtracter group as
By extracting the result of 1 into the signal line group sig1, four sets of radix-2 butterfly operations can be output in parallel.

Next, the radix-4 butterfly operation will be described, and a method of implementing the radix-4 butterfly operation in the radix-8 butterfly operation described above will be described.

The radix-4 butterfly operation is represented by equation (81). Xn = Σ ³ _{k = 0} x_k * W ^ (n * k)-(81) n = 0,1,2,3 where W is represented by the equation (82). W = exp (-2πj / 4) ---- (82)

Therefore, the radix-4 butterfly operation is performed using the radix-8
Expression (26) from Expression (11) in the butterfly operation of Expression (23) gives Expression (90) from Expression (83). A0 = a0 + a2 + (a1 + a3) ---- (83) A2 = a0 + a2- (a1 + a3) ---- (84) A1 = a0-a2 + (b1-b3) ---- ( 85) A3 = a0-a2- (b1-b3) ---- (86) B0 = b0 + b2 + (b1 + b3) ---- (87) B2 = b0 + b2- (b1 + b3)- -(88) B1 = b0-b2- (a1-a3) ---- (89) B3 = b0-b2 + (a1-a3) ---- (90)

This equation (83), (84), (85), (86), (87), (8
8), (89) and (90) are represented by equations (43), (44), (47), (48),
(51), (52), (56), (55) 8-tuple, Equations (45), (46), (4
9), (50), (53), (54), (58), and (57) can be associated with the eight-item set. Therefore, four data 8 inputs for performing a radix-4 butterfly operation are input to (a0, a4, a2, a6, b0, b4, b2, b6) or (a1, a
5, a3, a7, b1, b5, b3, b7), and the result of addition and subtraction (app0, apm0, amp0, amm0, bpp0, bpm0, bmm
0, bmp0) or (app1, apm1, amp1, amm1, bpp1, bpm1, b
By obtaining mm1 and bmp1), a radix-4 butterfly operation result can be output.

That is, as shown in FIG. 3, in the radix-8 butterfly operation, a0, a1,..., A7, b0, b1,.
Input in consideration of the above combination, and adder / subtracter group as
By taking out the result of No. 2 to the signal line group sig2, it is possible to output a result obtained by processing two sets of radix-4 butterfly operations in parallel.

Here, as an example, a description will be given of a process for performing an FFT on an object having a data number of 2 * 8 ^ n. However, it is assumed that each storage unit is realized by a memory.

The control unit 16 sends a control signal to the data storage unit 11 so as to output data at an address in accordance with the radix-8 butterfly computation algorithm. A control signal is sent to the twist coefficient storage unit 12 so as to output a twist coefficient according to an algorithm of a radix-8 butterfly operation. Also, for the twist coefficient multiplication unit 13,
The multiplication of the data output from the data storage unit 11 and the twist coefficient output from the twist coefficient storage unit 12 is performed in radix 8
Is transmitted in accordance with the butterfly calculation algorithm. The multiplied data is crossed by the crossing processing unit 14.
, Where the crossing process is performed. continue,
The control unit 16 sends a control signal to the selector 15 to select a radix-8 butterfly operation result. The selector 15 selects a signal line group sig3 that is a radix-8 butterfly operation result from the signal line group of the crossing processing unit 14, and outputs the data to the data storage unit 11. This loop is executed n times.

Then, the control unit 16 sends a control signal to the data storage unit to output data at an address in accordance with the radix-2 butterfly computation algorithm.
A control signal is sent to the twist coefficient storage unit 12 so as to output a twist coefficient in accordance with the algorithm of the radix-2 butterfly operation. The twist coefficient multiplying unit 13 multiplies the data output from the data storage unit 11 by the twist coefficient output from the twist coefficient storage unit 12 in accordance with the radix-2 butterfly computation algorithm. Send control signal. The multiplied data is sent to the crossing processing section 14, where crossing processing is performed. Subsequently, the control unit 16 sends a control signal to the selector 15 so as to select a radix-2 butterfly operation result. The selector 1 selects a signal line group sig1 that is a radix-2 butterfly operation result from the signal line group of the crossing processing unit 14, and outputs the data to the data storage unit 11. This loop is executed once.

As a result of the above processing, the data storage unit 11
The result of 2 * 8 ^ n FFT operation is stored.

It should be noted that the present invention is developed from the above embodiment by, for example, "performing radix-2, 4-, and 8-butterfly computations using a part of the radix-16 butterfly computation circuit". The radix-8 part in the form is 16, 3
2, etc. As an example, base 16
The case will be described.

When the radix-16 butterfly operation is performed, X_n = Σ ¹⁵ _{k = 0} x_k * W ^ (n * k) n = 0,..., 15 ---- (91) where W = exp (-2πj / 16) : J operates on the basis of the imaginary unit as in the case of bases 2, 4, and 8.

Expanding equation (91), if n = 2m, X_n = {(x_0 + x_8) + (x_4 + x_12) * w4 ^ n} + {(x_1 + x_9) + (x_5 + x_13) * w4 ^ n} * W ^ n + {(x_2 + x_10) + (x_6 + x_14) * w4 ^ n} * W ^ (2 * n) + {(x_3 + x_11) + (x_7 + x_15) * w4 ^ n} * W ^ (3 * n) ---- (92) When n = 2m + 1 X_n = {(x_0-x_8) + (x_4-x_12) * w4 ^ n} + {(x_1-x_9) + (x_5 -x_13) * w4 ^ n} * W ^ n + {(x_2- x_10) + (x_6-x_14) * w4 ^ n} * W ^ (2 * n) + {(x_3-x_11) + (x_7-x_15) * w4 ^ n} * W ^ (3 * n) ---- (93) However, w4 = exp (2πj / 4).

The expression (92) is expressed as follows: * n)} + {(x_1 + x_9) + (x_3 + x_11) * w8 ^ n + (x_5 + x_13) * w8 ^ (2 * n) + (x_7 + x_15) * w8 ^ (3 * n)} * W ^ n- --- (94) (93) Formula X_n = {(x_0-x_8) + (x_2-x_10) * w8 ^ n + (x_4-x_12) * w8 ^ (2 * n) + (x_6- x_14) * w8 ^ (3 * n)} + {(x_1-x_9) + (x_3-x_11) * w8 ^ n + (x_5-x_13) * w8 ^ (2 * n) + (x_7-x_15) * w8 ^ (3 * n)} * W ^ n ---- (95) However, w8 = exp (2πj / 8).

The brackets {} in the equations (92) and (93) correspond to a radix-4 butterfly operation, and the brackets {} in the equations (94) and (95) correspond to a radix-8 butterfly operation. The radix 2 can be similarly shown. This is true even if the value of the radix is further increased.

[0044]

According to the FFT operation circuit according to the present invention,
Assuming that a single integer equal to or greater than 2 is α and at least one integer from 1 to α−1 is β, a radix (2 to the power of β) is used by utilizing a part of a butterfly operation circuit of a radix (2 to the power of α). ), The number of data becomes (2 α)
FFT can be performed not only for the power of 2) (n) but also for 2 * (2 to the power of α) ^ n, without increasing the circuit scale. The reason is that by performing the butterfly operation of the radix (2 to the power of β) using part of the butterfly operation circuit of the radix (2 to the power of α) as it is, 2 * (2 to the power of α) ^ n,. This is because a radix (2 to the power of β) butterfly operation circuit that handles the number of data becomes unnecessary. Therefore, while effectively utilizing the circuit area, efficient processing when the number of sample data is large,
The expansion of the number of available sample data can be compatible.

In particular, according to the FFT operation circuit according to the third or fourth aspect, not only the number of data is 8 ^ n but also 2 * 8 ^ n and 4 * 8 ^ n, the FFT can be performed without increasing the circuit scale. I can do it.
The reason is that a radix-2 butterfly operation and a radix-4 butterfly operation can be performed by using a part of the radix-8 butterfly operation circuit as it is, so that the radix handling the data number of 2 * 8 ^ n or 4 * 8 ^ n This is because a butterfly arithmetic circuit of 2 or radix 4 becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an FFT operation circuit according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of a crossing processing unit and a connection relationship between the crossing processing unit and a selector in the FFT operation circuit of FIG. 1;

FIG. 3 is a flowchart showing an operation of the FFT operation circuit of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Data storage unit 12 Twist coefficient storage unit 13 Twist coefficient multiplication unit 14 Crossing processing unit 15 Selector 16 Control unit sig1 First signal line group sig2 Second signal line group sig3 Third signal line group

Claims (6)

[Claims] 1. The method of claim 1, wherein a single integer equal to or greater than 2 is α, 1 to α
Assuming that at least one integer up to −1 is β, radix (2 to the power of β) butterfly operation is performed using a part of a radix (2 to the power of α) butterfly operation circuit. Arithmetic circuit. 2. A crossing processing section for outputting data of a butterfly operation result of a radix (2 to the power of α) from an αth signal line group includes a βth signal line group for extracting intermediate data in the middle of the butterfly operation. 2. The FFT operation circuit according to claim 1, wherein the intermediate data corresponding to a butterfly operation result of a radix (2 to the power of β) is output from the βth signal line group. 3. The FFT operation circuit according to claim 1, wherein said α is 3, and said β is 1 and 2. 4. The FFT operation circuit according to claim 2, wherein said α is 3 and said β is 1 and 2. 5. A cross processing unit comprising: a first adder / subtractor group for performing addition / subtraction of input data; a second adder / subtractor group for performing addition / subtraction for output data of the first adder / subtractor group; A third adder / subtracter group that performs addition / subtraction on output data of the second adder / subtractor group, a multiplier group that performs multiplication on a part of output data of the third adder / subtractor group, and output data of the multiplier group. A fourth adder / subtractor group for performing addition / subtraction on a part of output data of the adder / subtractor group, the first signal line group for extracting output data of the first adder / subtractor group, and the second adder / subtractor 5. The FFT operation according to claim 4, comprising: the second signal line group for extracting output data of a group; and the third signal line group for extracting output data of the third and fourth adder / subtractor groups. circuit. 6. The first and second adder / subtractor groups each include eight 2-input / one-output adders and eight 2-input / one-output subtractors, and the third adder-subtractor group includes six. Wherein the fourth adder / subtractor group comprises four 2-input / one-output adders and four 2-input / one-output subtractors. The FFT operation circuit according to claim 5.