JP2002124656A - Image sensor ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS image sensor which can prevent reduction in characteristic caused by manufacturing fluctuations of junction leak current in a diffusion part of a MOS transistor as a switching element of by an increase in the entire capacity of wiring for storing a photoelectric charge. SOLUTION: A drain or source diffusion layer of a MOS transistor wired to a node for holding and storing a signal charge is arranged so as not to be contacted with an inversion blocking diffusion layer of element isolation. Consequently, the concentration of a junction can be reduced, variations in junction leakage and a capacity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a CMOS image sensor IC suitable for facsimile, image scanner, and electronic camera for reading and transmitting image information.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional image sensor. In a sensor circuit 10 of a CMOS image sensor, a photodiode 12 using a PN junction
A reset MOS 11 which is a switching element for resetting the photodiode 12 to an appropriate voltage;
An amplifier circuit 13 for amplifying the photoelectric charge accumulated in the photodiode 12 is connected. Reset MO
S11 is turned on to reset the photodiode 12 to a sufficient reset voltage.
F, the optical information is continuously read by a storage operation of accumulating the photoelectric charge in the photodiode 12 for a certain period of time and a read operation of turning on the amplifier circuit 13 to amplify and read the optical charge accumulated in the photodiode 12. It is configured to be able to. In addition, the signal amplified after the read operation can be temporarily stored using the holding circuit 20 including a capacitor and two switching MOS transistors. Switching MO during read operation
The S transistor A22A is turned ON, the signal is stored as charge in the storage capacitor 21 by the amplifier circuit 13, and the switching M
After the OS transistor A22A is turned off, the switching MOS transistor B22B is turned off after an arbitrary holding time.
N and can be read from the storage capacitor 21. A series of operations of reset, accumulation, and reading can be collectively processed for a plurality of photodiodes, and can be arbitrarily read individually from the holding circuit.

FIG. 4 is a cross-sectional view of a drain or source region of a reset MOS transistor connected to a photodiode and a switching MOS transistor connected to a storage capacitor of a conventional image sensor.
P-type channel stop layer 2 on P-type silicon substrate 1
And a LOCOS oxide film 3 are formed so as to overlap with each other, and an N-type drain or source diffusion layer 4 is provided in contact therewith. Below the end of the LOCOS oxide film 3, the P-type channel stop layer 2 and the N-type drain or source diffusion layer 4 are in contact. Generally, this P-type channel stop layer 2
And N-type drain or source diffusion layer 4 are formed in self-alignment with LOCOS oxide film 3.

[0004]

However, such CO2
In the MS image sensor, the N-type drain or source diffusion layer 4, which is a relatively high-concentration diffusion layer, and the P-type channel stop layer 2 are in contact with each other under the end portion of the LOCOS oxide film 3, so that the P-type channel stop layer 2 is in contact with the diffusion layer. Is liable to vary in the amount of junction leak current in manufacturing. Signal charges stored in the photodiode during the storage time or the capacitor during the holding time gradually leak from the junction of the drain or source of the MOS transistor, which is a connected switching element, causing loss of optical signals and There has been a problem that fixed noise is generated due to variations in leakage between sensors.

In addition, a junction having a relatively high impurity concentration between the N-type drain or source diffusion layer and the P-type channel stop layer is formed, the capacitance of the entire diode wiring for storing the amount of photocharge increases, and the sensitivity decreases. was there.

[0006]

In order to solve the above problems, the present invention has a CMOS image sensor constructed as follows. (1) M connected to a node that holds and stores signal charges
A CM characterized in that a drain or source diffusion layer of an OS transistor is separated from an inversion blocking diffusion layer for element isolation.
An OS image sensor IC was used. (2) In the CMOS image sensor manufacturing process of (1), the reverse blocking diffusion layer is formed so as to be separated from the drain or source diffusion layer by 0.5 μm or more by using pattern formation using a photoresist and an ion implantation technique. I made it. (3) In the manufacturing process of the CMOS image sensor of (1), a polysilicon wiring having a substrate potential covering 0.5 μm or more from the edge portion of the LOCOS oxide film in a region serving as a drain or a source is formed. The drain or source diffusion layer is formed in a self-aligned manner with respect to a silicon wiring by an ion implantation technique.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a first embodiment of a diffusion region of a drain or source portion of a MOS transistor which is a switching element connected to a photodiode and a storage capacitor of a CMOS image sensor according to the present invention. P
A LOCOS oxide film 3 is provided on a type silicon substrate 1, and an N-type drain or source diffusion layer 4 is provided in contact with the LOCOS oxide film 3. The N-type drain or source diffusion layer 4A on one side is connected to a photodiode or a storage capacitor, and the other N-type drain or source diffusion layer 4B is not connected to a photodiode or a storage capacitor. The P-type channel stop layer 2 on the N-type drain or source diffusion layer 4B side is in contact with the N-type drain or source diffusion layer 4B at the end of the LOCOS oxide film 3, and the P-type channel on the N-type drain or source diffusion layer 4A side. Stop layer 2 is L
At least 0.5 μm from the contact point between the OCOS oxide film 3 and the N-type drain or source diffusion layer 4
It is formed on the S oxide film 3 side.

In general, when LOCOS oxidation is formed on a P-type layer having a relatively high impurity concentration, silicon lattice defects such as oxide stacking faults are likely to be formed in the vicinity of the edge of the LOCOS oxide film where stress is highly concentrated. The presence of these lattice defects serves as a carrier generation and extinction center, causing a leakage current. As in the first embodiment, the P-type channel stop layer 2 having a high impurity concentration is separated from the end portion of the LOCOS oxide film by 0.5 μm or more, thereby suppressing the formation of silicon lattice defects in the LOCOS oxidation step. Junction leakage current of the N-type drain or source diffusion layer 4A can be reduced, and fixed noise due to loss of an optical signal and variation in leakage among a plurality of sensors can be suppressed.

The N-type drain or source diffusion layer 4
The junction capacitance of A also decreases by separating from the P-type channel stop layer 2, and the sensitivity to light increases.

Further, as a method of manufacturing the present structure, a step of introducing a P-type impurity in the P-type channel stop layer 2 includes:
By forming a resist in a portion other than the mold channel stop layer 2 and injecting a P-type impurity using an ion implantation technique, the structure of FIG. 1 can be easily formed.

FIG. 2 is a cross-sectional view of a second embodiment of a diffusion region of a drain or source portion of a MOS transistor which is a switching element connected to a photodiode and a storage capacitor of a CMOS image sensor according to the present invention. A LOCOS oxide film 3 is formed on a P-type silicon substrate 1,
The P-type channel stop layer 2 exists below the OCOS oxide film 3. N-type drain or source diffusion layer 4A on one side
Is connected to the photodiode or storage capacitor,
The other N-type drain or source diffusion layer 4B is not connected to the photodiode or the storage capacitor. The N-type drain or source diffusion layer 4B is a LOCOS oxide film 3
Is in contact with the P-type channel stop layer 2 on the side of
The N-type drain or source diffusion layer 4A has a structure separated from the P-type channel stop layer 2 by the presence of the shield polysilicon wiring 5 having a width of 0.5 μm or more and grounded to the same potential as the P-type silicon substrate 1. Has become. In this structure, since the junction between the N-type drain or source diffusion layer 4A and the P-type silicon substrate 1 is far from the vicinity of the end of the LOCOS oxide film 3 where the stress is highly concentrated, the leakage current is more effective than in the first embodiment. Can be suppressed. However,
Since the capacitance with the shield polysilicon wiring 5 increases,
The increase in sensitivity to light is smaller than in the first embodiment.

As a manufacturing method of the second embodiment, the shield polysilicon wiring 5 is formed simultaneously with the polysilicon gate 6, and N-type impurities are ion-implanted in a self-aligned manner using these polysilicon layers as a mask. By forming the mold drain or source diffusion layer 4, the structure of FIG. 2 can be easily formed.

[0014]

As described above, according to the present invention, regardless of the accumulation time and the holding time, the noise is small and the sensitivity is high.
A MOS image sensor can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a switching element connected to a photodiode and a storage capacitor of an image sensor according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a first embodiment of a diffusion region of a drain or source portion of an S transistor.

FIG. 2 is a diagram illustrating a switching element connected to a photodiode and a storage capacitor of an image sensor according to an embodiment of the present invention;
FIG. 9 is a cross-sectional view of a second embodiment of a diffusion region of a drain or source portion of an S transistor.

FIG. 3 is a circuit diagram illustrating an example of a conventional image sensor.

FIG. 4 is a MOS diagram showing a switching element connected to a photodiode and a storage capacitor of a conventional image sensor.
FIG. 4 is a cross-sectional view illustrating an example of a PN junction pixel in a diffusion region of a drain or source portion of a transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 P-type silicon substrate 2 P-type channel stop layer 3 LOCOS oxide film 4, 4 A, 4 B N-type drain or source diffusion layer 5 shield polysilicon wiring 6 polysilicon gate wiring 10 sensor circuit 11 reset MOS 12 photodiode 13 amplifier circuit 20 Holding circuit 21 Holding capacitance 22A, 22B Switch MOS

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 4M118 AA05 AB01 BA06 CA03 FA26 FA29 FA33 5C051 AA01 BA03 DA02 DB01 DB04 DB06 DB08 DC03 DC07 5F032 AA13 AC01 BA01 BA05 BB01 BB06 CA07 CA17 CA21 DA43 DA53 5F040 DA00 DC01 EA00 EK01 EF01

Claims (3)

[Claims] In a CMOS image sensor IC having a photodiode and a CMOS element on the same substrate, a drain or source diffusion layer of a MOS transistor connected to a node for holding and accumulating signal charges has an inversion blocking diffusion layer for element isolation. And a CMOS image sensor IC separated from the CMOS image sensor IC. 2. The CMOS image sensor I according to claim 1, wherein said inversion preventing diffusion layer is formed so as to be separated from said drain or source diffusion layer by 0.5 μm or more by using a patterning and ion implantation technique using a photoresist.
C 3. A polysilicon wiring having a substrate potential covering an inner portion of 0.5 μm or more from an edge portion of the LOCOS oxide film in a region serving as the drain or the source is formed, and the polysilicon wiring is self-aligned with the polysilicon wiring. 2. The drain or source diffusion layer is formed by an ion implantation technique.
CMOS image sensor IC as described