JP2002124092A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a processing time for writing and reading only control data, consequently, to shorten a time required for writing and erasing data, in a flash memory in which memory cells of two or more are correspondent to one data line in one sector. SOLUTION: In a non-volatile semiconductor memory in which memory cells of '0' and '1' are connected respectively to each data line through a selecting means in one sector, any one memory cell out of memory cells of phase '0' and '1' is constituted so as to be able to conduct for each data line selectively and simultaneously by the selecting means, the sector comprises memory cells corresponding to normal bit addresses (Y=0-2047) in which arbitrary data is stored and memory cells corresponding to control bit addresses (Y=2048-2111) in which control data about the sector is stored, memory cells corresponding to the control bit addresses are allotted to only memory cells of phase '0'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for speeding up data erasing and data writing in a nonvolatile semiconductor memory, and more particularly to a technique useful when applied to a flash memory capable of collectively erasing data.

[0002]

2. Description of the Related Art In a flash memory as a nonvolatile semiconductor memory, for example, as shown in FIG. 2, a plurality of memory cells MC composed of MOSFETs having a control gate and a floating gate are arranged in a matrix, A memory cell column MCC connected in common with a source and a drain is formed between the line and the local source line. Further, a plurality of such memory cell columns MCC are provided in the word line direction to form a memory array. It is configured.

In the memory array configured as described above, different word lines are respectively connected to control gates of the memory cells MC forming the same memory cell column MCC, and a common drain is connected to the selection MOSF.
Are connected to data lines (also referred to as bit lines) via ETs Qs10, Qs11,..., While connected to a common source via selection MOSFETs Qs2, Qs2 to, for example, ground.

In recent semiconductor technology, while the technology for reducing the scale of elements such as memory cells has been advanced, the technology for reducing the width of wiring has not advanced much. Therefore, if one data line is provided for one memory cell column MCC, it is difficult to efficiently form the memory cell column MCC so as to reduce the gap due to the interval between the data lines as a bottleneck. Become. Then, as shown in FIG. 2, two memory cell columns MCC, MCC of the first system and the second system are made to correspond to one data line DL, and each drain side of the two memory cell columns MCC, MCC is selected. MOSFET
In recent years, a flash memory that is connected to data lines via Qs10 and Qs11 has been developed, thereby reducing the density of data lines DL0.

Hereinafter, a flash memory having such a configuration is called a two-phase flash memory, and a first-system memory cell column is a memory cell having a phase “0”.
The memory cell row of the second system is referred to as a memory cell of phase “1”. The selection MOSFETs Qs10..., Qs11 that make the data lines and the drains of the memory cells MC.
Are configured to selectively and simultaneously simultaneously conduct all phase “0” memory cells MC or all phase “1” memory cells MC in the memory array to the data lines. .

According to such a two-phase flash memory, when data is read or written, two-system selection MOSFETs of a phase "0" system and a phase "1" system connected to the drain side are sequentially arranged. By being turned on, 2 connected to the same word line and the same data line
Reading and writing of data from and to one memory cell are performed with a time lag.

On the other hand, data erasure in the two-phase flash memory is performed simultaneously in all memory cells sharing a word line. That is, data erasure is performed simultaneously for the phase "0" memory cells and the phase "1" memory cells that share a word line. In response to a desire to make the unit of data erasing and writing the same, the unit of data writing is set so that the word line is common and the sector including both the first and second system memory cells is one unit. It is often the case.

By the way, in a flash memory,
Generally, management data such as the state of the memory cell is stored in management bits provided for each sector, and management processing is performed for each sector. For example, after erasing data in a certain sector, if the memory cell in the sector is normal, a process of writing normal management data to the management bits is performed. When writing data to a certain sector,
First, a management process of reading the management data of the sector and confirming that the memory cells of the sector are normal and then writing the data is performed.

In a conventional two-phase flash memory, the management bits are allocated to both memory cells of phase "0" and phase "1". For example, the address arrangement of memory cells in the Y direction is based on general bit addresses (Y = 0 to 2) in which arbitrary data is stored along the arrangement order of the memory cells on the circuit.
047) are successively assigned, a management bit address (Y = 2048 to 2111) is successively assigned, and thereafter, a redundant bit address for replacement of a defective cell (Y = 2112 to 2127) is assigned. The configuration is such that the memory cells to which the management bit address is assigned include both the phase “0” and the phase “1” memory cells.

[0010]

However, if the management data is stored so as to span the memory cells of the phase "0" and the phase "1" as described above, the management data must be stored after the erasing process or before the writing process. Even when writing or reading only the management data to be performed, two writing operations and reading operations are required, and the data erasing time and the data writing time are lengthened by an extra amount. There has been a problem that the first access time from the command to the reading of data is lengthened.

An object of the present invention is to provide a non-volatile semiconductor memory in a so-called two-phase flash memory, which can reduce the time required to read and write management data and, as a result, the time required to erase and write data. To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, there are provided a plurality of memory cells composed of MOSFETs for storing data at high and low threshold values, and among these memory cells, a plurality of memory cells connected to the same word line constitute one sector. The one sector is connected to a plurality of systems (for example, a first system and a second system) of memory cells via a selection means for each data line. In the nonvolatile semiconductor memory in which any one of the memory cells is selectively made conductive to a corresponding data line, the sector is usually assigned a bit address, Is stored in a memory cell, and a management bit address is assigned to the memory cell to manage the sector (e.g. And the memory cells to which the management bit address is assigned are included in the memory cells of the plurality of systems (the number is not limited to one if less than all the systems, and may be two or three). Out of any one of the memory cells.

According to such a configuration, when the management data is read / written only to the management bit, conventionally, for example, the first
While it was necessary to perform two or more sets of reading and writing of the memory cell of the system and reading and writing of the memory cell of the second system,
For example, it can be completed only by a write operation or a read operation of either the first system or the second system. Therefore,
For example, when reading and writing management data only to management bits, such as writing management data after data erasure or reading management data before data writing, the access time can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of a flash memory according to a preferred embodiment of the present invention.

The flash memory 1 of this embodiment is a nonvolatile semiconductor memory capable of electrically writing and erasing data, and has an external connection terminal to which an input / output buffer 2 and a control signal input / output buffer 3 are connected. I have.

The input / output buffer 2 is connected to eight I / O (Input / Output) terminals that are also used for inputting addresses and data, and is a logic interface for distributing input I / O data and address data. It is carried out. Further, the address input to the input / output buffer 2 is input twice (A0 to A7, A8 to A13). The control signal input / output buffer 3 is an input buffer for a control signal input from the outside. The input / output buffer 2
The controller 4 is connected to the main amplifier 5 and the X address buffer 6.

The controller 4 performs write, read, and write based on the control signal input to the control signal input buffer 3.
A mode such as erasing is determined, and control of the entire flash memory 1 is performed in accordance with the designated mode.

The main amplifier 5 is connected to a Y gate 7, and the Y gate 7 is connected to a data register 8. The main amplifier 5 has a data register 8
The data input / output via the gate 7 is amplified, and X
The address buffer 6 stores the X address input from the input / output buffer 2.

The X address buffer 6 has an X decoder 9
The Y gate 7 is connected to a Y decoder, and the Y decoder 10 is connected to a Y address counter 11. The X decoder 9 and the data register 8 are connected to a memory mat 12, in which memory cells, which are the minimum units of storage, are regularly arranged in a matrix.

X decoder 9 applies a predetermined voltage to a word line in memory mat 12 corresponding to the X address output from X address buffer 6. Here, the voltage applied by the X decoder 9 is, for example, about 16 V during erasing,
The voltage is about -13 V at the time of writing, and about 2 V to 3.3 V at the time of reading.

The Y decoder 10 has a Y address counter 7
The Y gate 7 corresponding to the Y address in the operation is operated. Y
The gate 7 connects between the data register 8 corresponding to the Y address selected by the Y decoder 10 and the main amplifier 5.

The data register 8 stores data to be input / output via the Y gate 7, and the Y address counter 11 stores data to be input to the data register 8 or data to be output. When outputting from the register 8, the Y address is incremented in order to serially access the Y gate 7 along the Y-system address (Y = 0 to 511).

The X decoder 9 is connected to an internal power supply circuit 13. The internal power supply circuit 13 has a voltage for applying a voltage other than the power supply voltage Vcc of, for example, about 3.3 V to the word line. Generate Internal power supply circuit 13
Is composed of, for example, a step-down power supply circuit that generates a voltage of about 2.0 V and a step-up power supply circuit that generates a negative voltage of about -13.0 V.

A clock generation circuit (clock generation means) 14 is connected to the controller 4. The clock generation circuit 14 is based on a start signal output from the controller 4 when data is read / written, for example. Thus, for example, a clock signal CLK having a constant period of about 10 MHz and about 20 MHz is generated.

FIG. 2 shows a configuration diagram of a part of a memory array provided in the flash memory of the embodiment.

The memory array of this embodiment has a control gate and a floating gate. By applying a positive or negative high voltage between the control gate and the drain, a charge is injected or released into the floating gate to store data. The memory cells MC made of nonvolatile MOSFETs are arranged in a matrix. Then, a plurality of (for example, 128) memory cells MC arranged in one row in a direction along the data lines DL0.
Are commonly used to form one block of memory cell column MCC, and a plurality of (for example, 85) memory cell columns MCC are arranged in the direction along the word line.
12) to form an AND-type memory array.

The control gates of the memory cells MC are connected to corresponding word lines WL0 to WL127, respectively. A plurality of memory cells M sharing a word line
A sector SEC, which is a unit of data erasure or data writing, is constituted by C. In addition, the memory cell column MCC
Are connected to the ground potential via selection MOSFETs Qs2, and the drain side of the memory cell column MCC is connected to corresponding data lines DL0,... Via selection MOSFETs Qs10, Qs11.

The word line WL0 is connected to the memory cell column MCC.
WL127 are provided, and each memory cell MC is associated with a different word line WL0. On the other hand, one data line is associated with two adjacent memory cell columns MCC for data lines DL0. Selection MOSFETs Qs10 ..., Q connecting the memory cell columns MCC ... to the data lines DL0 ...
s11 ... are select signals SiD0 of the phase "0".
"0" selection MOSF in which is input to the gate
ET Qs10... And a phase "1" selection MOSFET Qs11... For inputting a phase "1" selection signal SiD1 to the gate.

One of the two memory cell columns MCC and MCC associated with one data line is connected to the data line via a phase “0” -system selection MOSFET Qs10, and the other is connected to the phase “0”. MO for 1 "system
It is connected to the data line via SFET Qs11. As a result, the memory cell column MCC connected to the data line via the selection MOSFET Qs10 becomes the memory cell column MCC of the phase “0”, and the selection MOSFET
The memory cell column MCC connected to the data line via T Qs11 becomes the phase “1” system memory cell column MCC.

According to such a memory array configuration, data erasing processing is performed in units of memory cells (sectors) having a common word line. That is, the source side of all the memory cell columns is set to 0 V and the drain side is set to the open state, and the erase voltage (for example, 16 V) is applied to one word line.
, Negative charges are released from the floating gate of each memory cell of one sector corresponding to the word line, and the threshold value of all memory cells of the sector becomes a high value, for example, the logical value “1”. Is stored.

In this embodiment, data writing is performed in the same unit as data erasing, that is, in a unit of a sector having a common word line. However, in this embodiment, the selection M
Since two memory cell columns are connected to one data line via the OSFETs Qs10 and Qs11, it is not possible to simultaneously perform a write operation on all memory cells in a sector. Therefore, the data writing process firstly
The phase “0” -system selection MOSFET Qs10 is turned on, and the phase “1” -system selection MOSFET Qs11 is turned on.
Is turned off, and data is written into the memory cells of phase "0" in the sector. Then, conversely, the selection MOSFET Qs10 of phase "0" is turned off, and the phase "1" is selected. The MOSFET Qs11 is turned on, and data is written to the memory cell MC in phase "1" in the sector.

Data reading is also usually performed in sector units using a common word line. That is, in the same manner as the above-described write operation, two sets of read operations of a memory cell of phase “0” and a memory cell of phase “1” are performed to store one sector of data in the data register 8, and then the Y address is designated. The data of a predetermined number of bits (for example, 8 bits) selected by the Y decoder 10 is output via the main amplifier 5 and the input / output buffer 2. However,
If it is known that the read data is present only in the memory cell of the phase “0” or the memory cell of the phase “1”, only the data read operation of the memory cell in the corresponding phase is performed by the control of the controller 4 or the like. The setting is performed, and the data register 8 is controlled so that only the data of the corresponding phase is read out.

In the flash memory of this embodiment, the contents of each bit provided in each sector are the same as in the prior art.
It looks like this: That is, in each sector, a normal bit that can store arbitrary data, a management bit that stores management data related to the quality of the sector, and a normal data bit or a management bit that is defective when a cell unit failure occurs. And a redundant bit as a substitute for the memory cell. Of these, the bits that can be freely accessed by the user from outside are usually bits. As in the prior art, the normal bit memory cell has the normal bit address (Y = 0 to 2047), the management bit memory cell has the management bit address (Y = 2048 to 2111), and the redundant bit memory cell. Has a redundant bit address (Y = 2
112 to 2127) are respectively assigned. The assignment between the Y address and each memory cell is determined by the Y decoder 10.
A desired assignment is possible by the logical design of.

FIG. 3 is a diagram showing the arrangement of Y addresses in the flash memory of the embodiment. In the figure, the column of “array” indicates the physical arrangement order of each memory cell in one sector, the column of “Phase” indicates the phase (“0” or “1”) of each memory cell, In the column of “Y address”, the value of the Y address assigned to each memory cell is set to “I /
The column of "O" indicates the number of the corresponding I / O terminal.

In FIG. 3, if the value of the Y address is the same and I
The reason why there are four memory cells having different values of / O is that the configuration is such that by specifying an X address and a Y address, memory cells having the same number of bits as the number of I / O terminals are selected. is there. Here, the number of I / O terminals is treated as, for example, 8 bits.

In the flash memory of this embodiment, two-bit data can be stored in one memory cell by distributing the threshold values of the memory cells in four separated ranges. . Therefore, two I / Os correspond to one memory cell.

In the flash memory of this embodiment, as shown in FIG. 3, the management bit address (Y = 2048 to 2111) is limited to only the memory cells in phase "0" in a part of the memory cell array. Assigned to. Then, a normal bit address is assigned to the memory cells in phase "1" in this range.

The management bit addresses may be assigned in any arrangement as long as they are assigned only to the memory cells in one phase. For example, as shown in FIG. It is not necessary to assign all management bit addresses to memory cells in phase “0”,
For example, a management bit address may be divided and assigned to a plurality of dispersed ranges in a sector, and as shown in FIG. 3, it is not necessary to assign management bit addresses in order, and May be assigned in any order.

By setting the management bit address in this way, when only the management bit is written or when only the management bit is read, only the writing operation and the reading operation of the phase “0” are sufficient. Compared with the case where two sets of write operation and read operation are required between "0" and phase "1", the write time and read time of the management data can be halved.

Next, the procedure of the data erasing process and the data writing process in the flash memory configured as described above will be described.

FIG. 4 is a flowchart showing the procedure of the data erasing process.

When the mode shifts to the data erasing mode, first, each data line is precharged to a predetermined voltage, and then an erasing determination voltage Vev is applied to the word line to detect an erasure determination by detecting the potential of the data line. Then, two sets of memory cells of phase "0" and memory cells of phase "1" are performed (steps S1 and S2). Then, it is determined whether there is an unerased (Fail) memory cell whose threshold value has not reached the predetermined value (step S3). If there is an unerased memory cell, the process proceeds to steps S4 and S5.

In steps S4 and S5, the erasing operation for increasing the threshold value of the memory cell by applying the erasing voltage to the word line is performed two times for the memory cell of phase "0" and the memory cell of phase "1". Do the set. Then, the erase determination in steps S1 to S3 is performed again, and the erase operation and the erase determination processing in steps S1 to S5 are repeated until there is no unerased memory cell.

As a result, when it is determined that there is no unerased memory cell, the flow shifts to step S6, and in this step, a process of writing a "non-defective sector code" to the management bit of the sector is performed. And in this data writing,
Only the phase "0" write operation is performed, and the phase "1" write operation is not performed. Then, the data erasing process for one sector is completed.

FIG. 5 is a flowchart showing a processing procedure of the data writing processing.

When the mode is shifted to the data write mode,
First, the management data of the write destination sector is read (step S11). In this management data read processing, only the read operation of phase “0” is executed, and the read operation of phase “1” is not executed. Next, it is determined whether or not the management data is a "non-defective sector code" indicating that the state of the sector is good (step S12). If the management data is "non-defective sector code", the next steps S14 and S15 are performed.
Then, if it is not "non-defective sector code", the process proceeds to error processing (step S13).

After proceeding to steps S14 and S15, the write judgment performed by precharging each data line to a predetermined voltage and then applying the write judgment voltage Vwv to the word line to detect the potential of the data line is determined in a phase " Two sets of memory cells of "0" and memory cells of phase "1" are performed (steps S14 and S15). Then, unwritten (Fa
il) is determined (step S1).
6) If there is an unwritten memory cell, step S17,
Move to S18.

In steps S17 and S18, a write operation for lowering the threshold value of the memory cell by applying a write voltage to the word line and the data line is performed between the memory cell of phase "0" and the memory cell of phase "1". Perform two sets. Then, the write determination in steps S14 to S16 is performed again,
Steps S14 to S14 until there are no unwritten memory cells
The write operation of S18 and the write determination process are repeated.

As a result, when there are no unwritten memory cells and data has been written to all the bits in the sector, the data writing process ends.

As described above, according to the flash memory of this embodiment, in the two-phase flash memory, the management bit address is assigned only to the memory cells in the phase "0". There is no need to perform two sets of reading and writing of management data, such as writing of a code and reading of management data in a data writing process, in phase “0” and phase “1”. You can do it. Therefore, the write time of the management data is halved, and when only the management data is read, the first access time from the input of the read command to the output of the management data is halved.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, in one sector, one data line
Although a configuration in which three memory cells are associated is shown, the present invention can be similarly applied to a configuration in which three or more systems of memory cells corresponding to one data line are provided. In the case of such a configuration, the management data address is not limited to the configuration in which the memory cell is allocated to only one system of memory cells. The same effect that the time required for reading and writing only data can be reduced is obtained.

The non-defective sector code indicating the good or bad of the state of the sector is shown as the management data. However, the present invention is not limited to this. Various data stored in the sector and used for the management of the sector can be used. Contains data.

In the above description, the invention made mainly by the present inventor is based on the field of application AND
The present invention is not limited to this type of flash memory, but the present invention is not limited thereto. In one sector composed of a plurality of memory cells having a common word line, two memory cells correspond to one data line. Widely used for non-volatile semiconductor memories.

[0058]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, the processing time required for reading and writing only the management data is reduced, and the time required for normal data erasing processing and data writing processing can be reduced. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a flash memory according to a preferred embodiment of the present invention.

FIG. 2 is a circuit diagram showing a part of a memory array configuration.

FIG. 3 is a diagram showing an array of Y-system addresses.

FIG. 4 is a flowchart illustrating a processing procedure of a data erasing process.

FIG. 5 is a flowchart illustrating a processing procedure of a data writing process.

[Explanation of symbols]

 Reference Signs List 1 flash memory 2 memory mat 4 controller 8 data register 9 X decoder 10 Y decoder MC memory cell MCC memory cell column DL0, DL1. Selection MOSFET (selection means) SiD0 Select signal on first system side SiD1 Select signal on second system side Qs2 Selection MOSFET on source side

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B025 AA03 AB01 AC01 AD04 AD05 AD08 AE05

Claims (1)

[Claims] 1. An MO for storing data according to a threshold value
A plurality of memory cells made up of SFETs are provided, and among these memory cells, a plurality of memory cells connected to the same word line constitute memory cells constituting one sector. A plurality of memory cells are respectively connected to the data lines via selection means, and the selection means enables any one of the plurality of memory cells to selectively conduct to the corresponding data line. In the nonvolatile semiconductor memory configured, a memory cell in which a normal bit address is assigned to store any data and a management bit address is allocated to the sector and management data related to the sector is stored in the sector. And the memory cell to which the management bit address is assigned is one of the memory cells of the plurality of systems. A non-volatile semiconductor memory comprising only memory cells of any system.