JP2002112258A - Noise reduction device and its method, and image recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise reduction device and its method that can reduce mosquito noises caused in characters of a flip and at the surrounding of a telop while suppressing occurrence of blurs in an image in the case of decoding and reproducing image data and to provide an image recording and reproducing device. SOLUTION: The image recording and reproducing device 1 that is provided with: a recording system 4 having an MPEG encoder 43 that generates image data compressed and coded in compliance with the MPEG system and recording the compressed image data to an optical disk 2 as a prescribed bit stream and; a reproduction system 5 having an MPEG decoder 54 that decodes the compressed data recorded in the optical disk 2 in compliance with the MPEG system, is further provided with the noise reduction device 55 that receives a decoded signal from the MPEG decoder 54, uses a two-dimensional high pass filter and a prescribed threshold value to detect an edge of the image, and outputs the median of data of e.g., nine pixels consisting of pixels adjacent to the target pixel with respect to an area of the image not discriminated to be the edge as the result of detection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise reduction apparatus and method for reducing mosquito (ringing) noise generated when decoding encoded image data.
And an image recording / reproducing apparatus.

[0002]

2. Description of the Related Art Video tape recorders, such as VHS, have been widely used.
-Optical disk media such as RAM and DVD-RW,
Devices capable of recording on a hard disk are in practical use.

[0003] However, since these have a small recording capacity for recording image data, they need to be compressed and stored in real time at a low rate for long-time recording.

For example, in a video CD or the like,
MPEG (Movin) established by SO (International Organization for Standardization)
g Picture Coding Expert Group), a highly efficient coding method for image information proposed as a result of international standardization work,
That is, based on the MPEG1 system and the MPEG2 system,
When performing low-rate compression and decoding and reproducing the compressed data in real time, mosquito noise is generated around flip characters and telops, and the image quality is significantly reduced.

[0005]

However, conventionally, DV
An image recording / reproducing apparatus using a D-RAM, a DVD-RW, or a hard disk does not have a circuit for reducing mosquito noise and outputs the signal as it is. Also, when processing including filtering in the vertical direction is performed on an interlaced image, a line may appear to be split into two lines.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to reduce mosquito noise generated around flip characters and telops when decoding and reproducing image data. It is an object of the present invention to provide a noise reduction device and method capable of reducing blur while suppressing blurring, and an image recording / reproducing device.

[0007]

According to the present invention, there is provided a noise reducing apparatus for performing a process for reducing mosquito noise of data obtained by decoding image data encoded by a predetermined method. Upon receiving the decoded image data, an edge of the image is detected, and as a result of the detection, a median of data of a plurality of pixels including a pixel adjacent to the pixel of interest is obtained for a region not determined as an edge, and the median is calculated as It has processing means for outputting as decoded image data.

Further, in the present invention, there is further provided a frame memory, wherein the processing means stores the image data for which the median is obtained for a plurality of frames in the frame memory, and further stores the image data for which the median is obtained. The median value of the pixel data at the same position for each of a plurality of frames is output.

In the present invention, the processing means has a SIMD control processor in which element processors are one-dimensionally and multi-parallel.

In the present invention, the SIMD control processor in which the element processors are one-dimensionally and multi-parallel is bit processing.

Further, the present invention is a noise reduction method for performing processing for reducing mosquito noise of data obtained by decoding image data encoded by a predetermined method. Detect, the result of the detection,
A median value of data of a plurality of pixels including a pixel adjacent to the target pixel is output as decoded image data for a region not determined as an edge.

Further, in the present invention, the image data for which the median is obtained is stored in a frame memory for a plurality of two frames,
Further, the median value of the pixel data at the same position for each of a plurality of frames including the image data for which the median value is obtained is output.

[0013] Also, an image recording / reproducing apparatus according to the present invention comprises: an encoding circuit for encoding input image data according to a predetermined method; a recording medium on which the image data encoded by the encoding circuit is recorded; A decoding circuit for decoding the image data reproduced from the recording medium in accordance with a predetermined method, and detecting the edge of the image by receiving the decoded image data by the decoding circuit; A noise reduction device that obtains a median value of data of a plurality of pixels including a pixel adjacent to the pixel of interest and outputs the median value as decoded image data.

Further, in the present invention, the noise reduction device has a frame memory, stores the image data for which the median is obtained for a plurality of frames in the frame memory, and further stores the image data for which the median is obtained. The median value of the pixel data at the same position for each of a plurality of frames is output.

Further, in the present invention, the noise reduction device is a SIMD in which element processors are one-dimensionally and multi-parallel.
It has a control processor.

Further, according to the present invention, the SIMD control processor in which the above-mentioned element processors are multi-paralleled one-dimensionally is bit processing.

According to the present invention, for example, the processing means receives the decoded image data and detects the edge of the image. As a result of the detection, a median value of data of a plurality of pixels including a pixel adjacent to the pixel of interest, for example, 9 pixels is obtained for an area not determined as an edge, and the median value is output as decoded image data. You. This allows
Low rate e.g. MPEG, e.g. video CD
When decoding and reproducing encoded data by performing compression in real time according to the method, mosquito noise generated around flip characters and around telops can be reduced without blurring the image. Further, even if the processing is performed with the interlace, the line does not break into two.

[0018]

FIG. 1 is a block diagram showing an embodiment of an image recording / reproducing apparatus employing a noise reduction device according to the present invention.

As shown in FIG. 1, the image recording / reproducing apparatus 1 includes an optical disk 2 as a recording medium, a pickup 3 for accessing the optical disk 2 for recording and reproducing data, a recording system 4 for image data, and It has a reproduction system 5 for image data as a main component.

The recording system 4 has an analog / digital (A /
D) Conversion circuit 41, NTSC (National Television Sys
tem Committe) Decoder 42, MPEG encoder 4
3. ECC (Error Correction Codes) encoder 44,
An ETF (Eigth To Fourteen; 8-14) modulation circuit 45 and an RF amplifier 46 are provided.

The A / D conversion circuit 41 converts, for example, an analog image signal of the NTSC system, which is input from the input terminal TIN, into a digital signal and outputs the digital signal to the NTSC decoder 42.

The NTSC decoder 42 separates the NTSC digital image signal input from the A / D conversion circuit 41 into a luminance signal and a chroma signal, performs expansion processing on the image data, and outputs the resulting data to the MPEG encoder 43.

The MPEG encoder 43 applies DCT (Discrete Coding) to the image data from the NTSC decoder 42.
(Sine Transform) Encoding processing is performed to generate MPEG image data and output to the ECC encoder 44.
At this time, the MPEG encoder 43 adds encoding information such as a quantization scale to the image data to form a bit stream.

The ECC encoder 44 adds an error correction code to the bit stream from the MPEG encoder 43 and outputs it to the 8-14 modulation circuit 45.

The 8-14 modulation circuit 45 performs processing such as 8-14 modulation on the bit stream from the ECC encoder 44 and outputs the result to the RF amplifier 45.

The RF amplifier 46 includes an 8-14 modulation circuit 45.
, And outputs the amplified bit stream to the optical pickup 3.

The recording system 4 of the image recording / reproducing apparatus 1
Records a bit stream indicating an image on the optical disk 2 via the optical pickup 3.

The reproduction system 5 includes RF amplifiers 51 and 8-
14 demodulation circuit 52, ECC decoder 53, MPEG decoder 54, noise reduction device 55, image quality correction circuit 56, N
TSC encoder 57, digital / analog (D /
A) It is composed of a conversion circuit 58.

The RF amplifier 51 amplifies the image data from the optical disk 2 detected by the optical pickup 3, and
14 to the demodulation circuit 52.

The 8-14 demodulation circuit 52 includes an RF amplifier 51
Performs an 8-14 demodulation process on the image data from
Output to the ECC decoder 53.

The ECC decoder 53 performs a predetermined decoding process on the image data from the 8-14 demodulation circuit 52, performs an error correction process using the error correction code added by the ECC encoder 44,
Output to the EG decoder 54.

The MPEG decoder 54 performs a predetermined decoding process on the image data of the MPEG system from the ECC decoder 53 and outputs the decoded data to the noise reduction device 55.

The noise reduction device 55 performs a mosquito noise reduction process on the decoded image data from the MPEG decoder 54 by performing a filtering process. As will be described in detail later, the noise reduction device 55 detects an edge of the image based on, for example, a two-dimensional high-pass filter and a predetermined threshold. And outputs the median value of data of a plurality of pixels (9 in this embodiment) including adjacent pixels as decoded image data. In this case, the noise reduction device 55
As will be described later, for example, two frames are stored in the frame memory, and the median value of the pixel data at the same position for each of three frames including the image extracted by this processing is output. The noise reduction device 55 outputs the image data subjected to such noise reduction processing to the image quality correction circuit 56.

The image quality correction circuit 56 includes a noise reduction device 55
The image data is subjected to an image quality correction process, such as an outline correction process, for example, and output to the NTSC encoder 57.

The NTSC encoder 57 performs a predetermined encoding process on the image data from the image quality correction circuit 56 to obtain image data conforming to the NTSC system.
Output to the A conversion circuit 58.

The D / A conversion circuit 58 converts the NTSC image data from the NTSC encoder 57 from a digital signal to an analog signal and outputs it to an output terminal TOUT.

Next, a specific configuration example and function of the noise reduction device 55 will be described with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of the noise reduction device 55 of FIG.

As shown in FIG. 2, the noise reduction device 55 includes a digital signal processor (DSP) 551 as processing means for performing mosquito noise reduction processing, and one frame of image data for storage and delay. Memory (MEM1) 552, Memory (MEM2) 55
3 as a main component.

An input line for image data is connected to a first input terminal (I1) of the DSP 551. Memory (ME
M1) The input terminal of 552 is connected to the second output terminal (O2) of the DSP 551, and the output terminal of the memory 552 is connected to the DSP
11, a third input terminal (I3) and a memory (MEM)
2) It is connected to the input terminal of 553. Memory 553
Is connected to the second input terminal (I2) of the DSP 551. Then, the DSP 551 outputs the data after the mosquito noise reduction processing to the first output terminal (O
Output from 1).

The DSP 551 stores data for the input terminal I1 for three lines in an internal memory. Also, DS
The P551 stores data for the input terminals I2 and I3 in an internal memory.

The DSP 551 is a linear array (linear array) type DSP, for example, a SIMD (Single Instruction Stream Mult) in which element processors are one-dimensionally and multi-parallel.
iple Data stream) It is composed of a control type parallel processor.

Hereinafter, the specific configuration of the SIMD control processor and the specific contents of the mosquito noise reduction processing in the DSP 551 will be sequentially described with reference to the drawings.

Basic Configuration of SIMD Control Processor Hereinafter, the configuration of the SIMD control processor will be described with reference to FIG. This SIMD control processor 100
As shown in FIG. 3, an input pointer (input skip register) 101, an input SAM (serial access memory) unit (input register) 102, a data memory unit (local memory) 103, and an ALU (Arithmetic and)
Logic Unit) Array unit 104, output SAM
It comprises a unit (output register) 105, an output pointer (output skip register) 106, and a program control unit 107.

Of these components, the input SAM unit 1
02, data memory unit 103 and output SAM unit 105
Is mainly composed of a memory. Input SAM unit 102,
The data memory unit 103, the ALU array unit 104, and the output SAM unit 105 constitute a plurality of (more than the number of pixels H for one horizontal scanning period of the original image) element processors 110 parallelized in a linear array (linear array) format. I do. Each of the element processors 110 (single element) has a component part of an independent processor, and corresponds to a hatched part in FIG. The plurality of element processors 110 are arranged in parallel in the horizontal direction in FIG.
Construct an element processor group.

Input pointer (input skip register) 1
Reference numeral 01 denotes a 1-bit shift register. Each time pixel data for one pixel of an original image is input from an external image processing device (not shown) or the like, a 1-bit signal of logical value 1 (H) is input. Pointer signal (SIP)] to designate the element processor 110 that is in charge of the input pixel data of one pixel, and
The pixel data of the corresponding original image is written to the input SAM unit 102 (input SAM cell) of 0.

That is, the input pointer 101 sets the logical value of the input pointer signal to the element processor 110 at the left end of FIG. 3 to 1 at every horizontal scanning period of the original image in accordance with the clock signal synchronized with the pixel data. The pixel data of the first input original image is converted to the SIM data shown in FIG.
The leftmost element processor 100 of the D control processor 100
Then, every time the clock signal changes by one cycle, the input pointer signal of the logical value 1 to the element processor 110 on the right is sequentially shifted rightward, and each of the element processors 110 , The image data of the original image is written one pixel at a time into the input SAM unit 102.

The input SAM unit (input register) 102
As described above, when the input pointer signal input from the input pointer 101 becomes a logical value 1, pixel data (input data) for one pixel input to the input terminal DIN from an external image processing device or the like is stored. I do. That is, the input SAM unit 102 of the element processor 110 stores pixel data for one horizontal scanning period of the original image as a whole for each horizontal scanning period. Further, the input SAM unit 102 stores the pixel data (input data) of the stored original image for one horizontal scanning period in a data memory as needed in the next horizontal scanning retrace period according to the control of the program control unit 107. Transfer to the unit 103.

Data memory unit (local memory) 103
Under the control of the program control unit 107, pixel data of the original image input to the input SAM unit 102, data in the middle of calculation, and data corresponding to the logical value of the input pointer signal (SIP) input from the input pointer 101 , Constant data, etc., and output them to the ALU array unit 104.

Under control of the program control unit 107, the ALU array unit 104 performs arithmetic operation processing and logical operation on pixel data of the original image, data in the middle of operation, constant data, and the like input from the data memory unit 103. Processing is performed and stored at a predetermined address in the data memory unit 103. The ALU array unit 104 performs all the arithmetic processing on the pixel data of the original image in bit units,
The arithmetic processing is performed on data of one bit every one cycle.

The output SAM unit (output register) 105
Under the control of the program control unit 107, when the processing assigned to one horizontal scanning period is completed, the processing result is transferred from the data memory unit 103 and stored. The output SAM unit 105 outputs the stored data to the outside according to an output pointer signal (SOP) input from the output pointer 106.

Output pointer (output skip register) 1
Reference numeral 06 denotes a 1-bit shift register that selectively activates an output pointer signal (SOP) to the output SAM unit 105 and controls output of a processing result (output data).

The program control unit 107 includes a program memory, a sequence control circuit for controlling the progress of a program stored in the program memory, the input SAM unit 102, the data memory unit 103, and the output SAM unit 10.
5 is composed of "ROW" address code data (both not shown) for the memory and the like. The program control unit 107 stores a single program by these components, generates various control signals based on the stored single program for each horizontal scanning period of the original image,
All the element processors 1 through the generated various control signals
The image data is processed by interlocking and controlling the image data 10. Controlling a plurality of element processors based on a single program in this manner is referred to as SIMD control.

Each element processor (processor element) 110 is a 1-bit processor, and performs a logical operation process and an arithmetic operation process on pixel data of an original image input from an external image processing device or a preceding circuit. Then, as a whole, the element processor 110 realizes a filtering process in a horizontal direction and a vertical direction using an FIR digital filter. The program control unit 1
07 is performed with the horizontal scanning period as a cycle. Therefore, each element processor 110 divides the program of the maximum number of steps obtained by dividing the horizontal scanning period by the cycle of the instruction cycle of the element processor 110 into each horizontal line. It can be performed every scan period.

The element processor 110 is connected to the adjacent element processor 110 and has a function of performing inter-processor communication with the adjacent element processor 110 as necessary. That is, each element processor 110
According to the SIMD control of the program control unit 107,
For example, the processing can be performed by accessing the data memory unit 103 and the like of the element processor 110 on the right or left side, and by repeating the access to the element processor 110 on the right side, the element processor 110 The data memory unit 103 of the element processor 110 that is not connected can be accessed and data can be read. The element processor 110 realizes a horizontal filtering process as a whole by using a communication function between adjacent processors.

Here, for example, in the case where arithmetic processing between pixel data separated by about 10 pixels in the horizontal direction is required, the number of program steps becomes extremely large when inter-processor communication is performed. The FIR filter processing hardly includes arithmetic processing between pixel data separated by as much as 10 pixels, and mostly includes arithmetic processing on continuous pixel data. Therefore, FI for performing inter-processor communication
It is very unlikely that the number of program steps of the R filter processing increases and becomes inefficient.

Each of the element processors 110 always processes the pixel data at the same position in the horizontal scanning direction exclusively. Therefore, the write address of the data memory unit 103 to which the pixel data (input data) of the original image is transferred from the input SAM unit 102 is changed at each initial stage of the horizontal scanning period to retain the input data of the past horizontal scanning period. The element processor 110
Can also filter pixel data of the original image in the vertical direction.

The input processing (first processing) for writing the pixel data (input data) of the original image into the input SAM unit 102 in each of the element processors 110 and stored in the input SAM unit 102 under the control of the program control unit 107. Transfer processing of input data to the data memory unit 103, arithmetic processing by the ALU array unit 104, output SAM
Transfer process (output data) to the processing unit 105 (second
) And the process of outputting output data from the output SAM unit 105 (third process) are executed in a pipeline format with a processing cycle of one horizontal scanning period. Therefore, when focusing on the input data, each of the first to third processes for the same input data requires a processing time for one horizontal scanning period. Processing time for a period is required. However, since these three processes are executed in parallel in a pipeline format, on average, processing of input data for one horizontal scanning period requires only a processing time for one horizontal scanning period.

Hereinafter, the basic operation of the linear array type SIMD control processor for image processing shown in FIG. 3 will be described.

In the input pointer 101, in the first horizontal scanning period (first horizontal scanning period), the logical value 1 (H) for each element processor 110 according to the clock synchronized with the input pixel data of the original image. Are sequentially shifted, and the element processor 110 that performs arithmetic processing on each pixel data of the original image is designated.

The pixel data of the original image is input to the input SAM unit 102 via the input terminal DIN. In the input SAM unit 102, each element processor 110 stores pixel data of one pixel of the original image according to the logical value of the input pointer signal. In all input SAM units 102 of the element processor 110 corresponding to each pixel included in one horizontal scanning period, pixel data of an original image is stored. When the pixel data for one horizontal scanning period is stored as a whole, the input process (first process) ends.

When the input processing (first processing) is completed, the input SAM section 102, the data memory section 103, the ALU array section 104, and the output SAM section of each element processor 110 according to a single program for each horizontal scanning period. 1
05 is subjected to SIMD control by the program control unit 107 to execute processing on pixel data of the original image.

That is, in the next horizontal scanning retrace period (second horizontal scanning period), each input SAM unit 102
Each pixel data (input data) of the original image stored in the first horizontal scanning period is transferred to the data memory unit 103.

In this data transfer process, the program control unit 107 activates the input SAM read signal (SIR) [to a logical value 1 (H)] to activate a predetermined row (ROW) of the input SAM unit 102. Data is selected and accessed, and further, a memory access signal (SWA) is activated, and the input SA is written so that the accessed data is written to a memory cell (described later) of a predetermined row of the data memory unit 103.
It is realized by controlling the M unit 102 and the data memory unit 103.

Next, during the horizontal scanning period, the program control unit 1
07, each element processor 1 based on the program
10 is controlled, and the data is
Output to the LU array unit 104. In the ALU array unit 104, arithmetic operation processing and logical operation processing are performed, and the processing result is written to a predetermined address of the data memory unit 103. When the arithmetic operation processing and the logical operation processing according to the program are completed, the program control unit 107
Then, the control of the data memory unit 103 is performed, and the processing result is further output to the output SAM unit 105 in the next horizontal scanning retrace period.
(This is the second processing). Further, in the next horizontal scanning period (third horizontal scanning period), the output S
The AM unit 105 is controlled, and the processing result (output data) is output to the outside (third processing).

That is, the input data for one horizontal scanning period stored in the input SAM unit 102 is transferred to the data memory unit 103 as required in the next horizontal scanning period, stored and stored in the subsequent horizontal scanning period. Used for processing in the period.

Next, specific processing of mosquito noise reduction in the DSP 11 having the basic configuration as shown in FIG. 3 will be described with reference to FIGS.

As described above, the DSP 551 stores data for the input terminal I1 for three lines in the internal memory. These data are stored in DAT0, DAT1, DAT
Let it be 2. The DSP 551 stores data for the input terminals I2 and I3 in an internal memory. These data are referred to as DAT1FD and DAT2FD.

In the horizontal retrace period of the input data (ST10
1) First, the following transfer and substitution processing is performed. First, the following transfer processing is performed in step ST102. DS
The value of the variable RES on the data memory unit 103 inside the P551 is transferred to the output SAM unit 105 (first output terminal) O1. The value of the variable MRES on the data memory unit 103 inside the DSP 551 is output to the output SAM unit 105 (second output terminal O).
Transfer to 2).

Next, the following substitution processing is performed in step ST103. Input SAM unit 102 (first input terminal I
The value of the data from 1) is assigned to a variable DAT0 on the data memory unit 103 inside the DSP 551. Input SAM
The value of the data from the unit 102 (second input terminal) I2 is
Variable DAT on Data Memory Unit 103 Inside SP551
Substitute for 1FD. The value of the data from the input SAM unit 102 (third input terminal I3) is assigned to a variable DAT2FD on the data memory unit 103 inside the DSP 551.

Next, the value of the variable DAT0 on the data memory unit 103 inside the DSP 551 and the value of the variable DAT2 on the data memory unit 103 inside the DSP 551 are added, and DS
It is assigned to a variable T0 on the data memory unit 103 inside P551 (ST104).

Data memory section 103 inside DSP 511
Is shifted right by one bit (ST1).
05). Next, DAT1 of the one left processor element 110 and DA of the one right processor element 110
The data of T1 is added and assigned to a variable T1 in the data memory unit 103 inside the DSP 551 (ST106). D
The contents of variable T1 in data memory unit 103 inside SP551 are shifted right by one bit (ST107). Then, the data of T0 of the one left processor element 110 and the data of T0 of the one right processor element 110 are added and assigned to a variable T2 in the data memory unit 103 inside the DSP 551 (ST108). Next, the contents of the variable T2 in the data memory unit 103 inside the DSP 551 are shifted right by one bit (ST109). Next, the process proceeds to step ST110 in FIG.

In step ST110, T0 and T
The data of 1 is added and assigned to a variable T0 in the data memory unit 103 inside the DSP 551. Next, the DSP 551
The contents of the variable T0 in the internal data memory unit 103 are shifted right by one bit (ST111). The data of T0 and T2 are added, and the data memory unit 103 in the DSP 551 is added.
(ST112). Next, the DSP
The contents of variable T0 in data memory unit 103 inside 551 are shifted right by one bit (ST113). The data of T0 is subtracted from DAT1 and assigned to the variable T0 in the data memory unit 103 inside the DSP 551 (ST114).
Then, the absolute value of T0 is obtained and assigned to the variable T0 in the data memory unit 103 inside the DSP 551 (ST115).
To ST117). Next, the value of the data of T0 is compared with a predetermined threshold value (ST118).
Is larger than the threshold, 1 is substituted for a variable F in the data memory unit 103 inside the DSP 551 (ST
119). On the other hand, if the data of T0 is not larger than the threshold value (ST118), 0 is substituted for the variable F in the data memory unit 103 inside the DSP 551 (ST120). Next, the process proceeds to step ST121 in FIG.

In step ST121, the following processing is performed. The data of DAT0 is substituted for the variable T0 in the data memory unit 103 inside the DSP 551. DSP55
1 in the variable T1 in the data memory unit 103 inside DAT1.
Substitute the data of The data of DAT2 is substituted for the variable T2 in the data memory unit 103 inside the DSP 551.
The variable T3 in the data memory unit 103 inside the DSP 551
To the data of DAT0 of the processor element 110 on the left. Data memory unit 1 inside DSP 551
Processor element 11 left one to variable T4
The data of DAT1 of 0 is substituted. The data of DAT2 of the one left processor element 110 is substituted for the variable T5 in the data memory unit 103 inside the DSP 551. D
The data of DAT0 of the next right processor element 110 is substituted for the variable T6 in the data memory unit 103 inside SP551. Data memory unit 10 inside DSP 551
Processor element 110 one to the right of variable T7 in
Of DAT1 is substituted. The data of DAT2 of the next right processor element 110 is substituted for a variable T8 in the data memory unit 103 inside the DSP 551.

Next, the data of the variables T0 to T8 in the data memory unit 103 inside the DSP 551 are sorted in ascending or descending order and assigned to the variables T0 to T8 in the data memory unit 103 inside the DSP 551 (ST122).
If the variable F in the data memory unit 103 inside the DSP 551 is 1 (ST123), the data of DAT1 is assigned to the variable MRES in the data memory unit 103 inside the DSP 551 (ST124). On the other hand, if the variable F in the data memory unit 103 inside the DSP 551 is not 1 (ST123), the data memory unit 1 inside the DSP 551
03 to the variable MRES in ST3 (ST1
25). Next, the data memory unit 10 inside the DSP 551
3, the data of the variables MRES, DAT1FD, and DAT2FD are rearranged in descending order, and the middle value is substituted for the variable RES in the data memory unit 103 inside the DSP 551 (ST126). Then, the value of DAT1 is substituted for DAT2. Further, the value of DAT0 is substituted for DAT1 (S
T127). Return to START (FIG. 4) and repeat every line.

Next, the operation of the image recording / reproducing apparatus shown in FIG. 1 will be described.

First, in the recording system 4, the input terminal TIN
For example, an analog image signal of the NTSC system is converted into a digital signal by the A / D conversion circuit 41 and output to the NTSC decoder 42. In the NTSC decoder 42, the NTSC input from the A / D conversion circuit 41
The digital image signal of the system is separated into a luminance signal and a chroma signal. Then, the image data is subjected to decompression processing and output to the MPEG encoder 43. MPE
In the G encoder 43, DCT coding processing is performed on the image data from the NTSC decoder 42.
Based on this processing, MPEG image data is generated. At this time, in the MPEG encoder 43, encoding information such as a quantization scale is added to the image data and output to the ECC decoder 44 as a bit stream. In the ECC encoder 44, an error correction code is added to the bit stream from the MPEG encoder 43 and output to the 8-14 modulation circuit 45. In the 8-14 modulation circuit 45, the bit stream from the ECC encoder 44 is subjected to processing such as 8-14 modulation and output to the RF amplifier 45, where the bit stream is subjected to an amplification operation and further passed through the optical pickup 3. Thus, a bit stream indicating an image is recorded in a desired recording area of the optical disc.

In the reproducing process in the reproducing system 5, the image data from the optical disk 2 detected by the optical pickup 3 is amplified by the RF amplifier 51 and is subjected to the 8-14 demodulation circuit 52.
Supplied to In the 8-14 demodulation circuit 52, the image data from the RF amplifier 51 is subjected to 8-14 demodulation processing and output to the ECC decoder 53. The ECC decoder 53 performs a predetermined decoding process on the image data from the 8-14 demodulation circuit 52, performs an error correction process using the error correction code added by the ECC encoder 44 of the recording system 4, and performs an MPEG decoder process. It is output to 54. In the MPEG decoder 54, EC
MPEG image data from the C decoder 53 is subjected to a predetermined decoding process and output to the noise reduction device 55. In the noise reduction device 55, edges of the image are detected using a two-dimensional high-pass filter and a predetermined threshold. Then, as a result of the detection, a median value of data of, for example, nine pixels including a pixel adjacent to the target pixel is output to a region not determined as an edge. In this case, for example, two frames are stored in the frame memory, and the central value of the pixel data at the same position for each of three frames including the image extracted by this process is output.

The decoded image data subjected to the mosquito noise reduction processing by the noise reduction device 55
In, for example, image quality correction processing such as contour correction processing is performed, and the resultant is supplied to the NTSC encoder 57. NTS
The C encoder 57 performs a predetermined encoding process on the image data from the image quality correction circuit 56 and
Image data conforming to the system is generated and output to the D / A conversion circuit 58. Then, in the D / A conversion circuit 58, the NTSC image data from the NTSC encoder 57 is converted from a digital signal to an analog signal,
Output to the output terminal TOUT.

As described above, according to the present embodiment, the MPEG encoder 43 for generating image data compressed and encoded based on the MPEG system is provided, and the compressed image data is converted into a predetermined bit stream on the optical disc 2. An MPEG system having a recording system 4 for recording and decoding compressed data recorded on the optical disc 2 in accordance with the MPEG system.
In the image recording / reproducing apparatus 1 having the reproducing system 5 having the decoder 54, the edge of the image is detected by using the two-dimensional high-pass filter and the predetermined threshold in response to the decoded signal of the MPEG decoder 54, Since the noise reduction device 55 that outputs the median value of data of, for example, 9 pixels including the pixel adjacent to the pixel of interest with respect to the area not determined as an edge is provided, the noise reduction device 55 follows the low-rate MPEG method such as a video CD. When decoding and reproducing encoded data by performing compression in real time, mosquito noise generated around flip characters and telops can be reduced without blurring the image. Further, there is an advantage that the line is not broken into two even if the processing is performed with the interlace signal as it is.

In the above-described embodiment, an example has been described in which the noise reduction device is configured by a DSP and a frame memory. However, no frame memory is provided, and mosquito noise is reduced only by the DSP 551 as shown in FIG. It is also possible to configure to reduce. In this case, the DSP 551A inputs the input image data to the first input terminal (I1), and outputs the image data after the mosquito noise reduction processing is performed from the output terminal (O1) of the DSP 551A.

The specific processing flow is shown in FIGS.
Is performed in substantially the same manner as that described with reference to FIG. 6, but in the processing shown in FIG. 6, after the rearrangement processing is performed in step ST122, steps ST123 to ST12 are performed.
The same processing as in step 5 is performed as shown in FIG. That is, as shown in FIG. 8, if the variable F in the data memory unit 103 inside the DSP 551A is 1 (ST131), the DSP 5
The data of DAT1 is assigned to the variable MRES in the data memory unit 103 inside 51A (ST132). On the other hand, D
If the variable F in the data memory unit 103 inside the SP 551A is not 1 (ST131), the contents of T4 are assigned to the variable MRES in the data memory unit 103 inside the DSP 551A (ST133). And then the variable MRES,
The data of DAT1FD and DAT2FD are rearranged in descending order, and the process of substituting the middle value for the variable RES is not performed.
Substitute the value of DAT1 for DAT2 and the value of DAT0 for DA
Substitute into T1 (ST134).

By performing the above processing, the same effects as those described above can be obtained.

In the above-described embodiment, the case where the processing means according to the present invention is constituted by a DSP has been described as an example. However, the present invention is not limited to this, and is constituted by combining logic circuits. It is also possible.

[0085]

According to the present invention, it is possible to reduce mosquito noise generated around flip characters and telops without blurring the image. Further, even if the processing is performed with the interlace, the line does not break into two.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an image recording / reproducing device employing a noise reduction device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration example of the noise reduction device of FIG. 1;

FIG. 3 is a block diagram showing a basic configuration of a SIMD control processor constituting a DSP according to the present invention.

FIG. 4 is a flowchart illustrating a mosquito noise reduction process according to the embodiment.

FIG. 5 is a flowchart illustrating a mosquito noise reduction process according to the embodiment.

FIG. 6 is a flowchart illustrating a mosquito noise reduction process according to the embodiment.

FIG. 7 is a block diagram showing another example of the configuration of the noise reduction device of FIG. 1;

FIG. 8 is a flowchart illustrating a mosquito noise reduction process in the case of the noise reduction device of FIG. 7;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Image recording / reproducing apparatus, 2 ... Optical disk, 3 ... Optical pickup, 4 ... Recording system, 41 ... A / D conversion circuit, 42 ... N
TSC decoder, 43 ... MPEG decoder, 44 ... EC
C decoder, 45 ... 8-14 modulation circuit, 46 ... RF amplifier, 5 ... reproduction system, 51 ... RF amplifier, 52 ... 8-14 demodulation circuit, 53 ... ECC decoder, 54 ... MPEG decoder, 55 ... Noise reduction device, 551,551A ... DS
P, 552, 553: memory, 56: image quality correction circuit, 5
7 ... NTSC encoder, 58 ... D / A conversion circuit, 10
0: SIMD control processor, 101: input pointer (input skip register), 102: input SAM unit (input register), 103: data memory unit (local memory), 104: ALU array unit, 105: output SAM unit (output register) ), 106... Output pointer (output skip register).

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C021 PA33 PA40 PA42 PA62 PA79 PA85 PA86 RA02 RB08 SA24 XB03 YA01 YC03 YC07 YC08 5C053 FA23 FA25 GB06 GB15 GB22 GB32 GB37 GB38 HA06 HA33 JA30 KA01 KA03 KA08 KA11 KA13 KA21 LA05 LB15 MA00 MA23 MC11 PP14 PP22 PP24 SS13 UA05 UA11 UA14 UA31

Claims (14)

[Claims] 1. A noise reduction device for performing a process of reducing mosquito noise of data obtained by decoding image data encoded by a predetermined method, comprising: receiving decoded image data; detecting an edge of the image; As a result, a noise reduction device including a processing unit that obtains a median value of data of a plurality of pixels including a pixel adjacent to a pixel of interest in an area not determined as an edge, and outputs the median value as decoded image data. 2. The image processing apparatus according to claim 1, further comprising a frame memory, wherein the processing unit stores the image data for which the median is obtained for a plurality of frames in the frame memory, and further stores a plurality of frames including the image data for which the median is obtained. 2. The noise reduction device according to claim 1, wherein a central value of the pixel data at the same position in each of the minutes is output. 3. The noise reduction device according to claim 1, wherein said processing means includes a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 4. The noise reduction apparatus according to claim 2, wherein said processing means has a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 5. The noise reduction device according to claim 3, wherein said SIMD control processor in which said element processors are multi-parallel one-dimensionally performs bit processing. 6. The noise reduction device according to claim 4, wherein the SIMD control processor in which the element processors are multi-parallel one-dimensionally performs bit processing. 7. A noise reduction method for performing processing for reducing mosquito noise of data obtained by decoding image data encoded by a predetermined method, the method comprising the steps of: receiving decoded image data, detecting an edge of the image; And outputting a median value of data of a plurality of pixels including a pixel adjacent to the pixel of interest in a region not determined as an edge as decoded image data. 8. The image data for which the median has been obtained is stored in a frame memory for a plurality of frames, and the median of pixel data at the same position for a plurality of frames including the image data for which the median has been obtained is output. The noise reduction method according to claim 7, wherein 9. An encoding circuit for encoding input image data according to a predetermined method, a recording medium on which the image data encoded by the encoding circuit is recorded, and a recording medium reproduced from the recording medium. A decoding circuit that decodes the image data according to a predetermined method, and receives the decoded image data from the decoding circuit, detects an edge of the image, and, as a result of the detection, adjoins the pixel of interest to a region that is not determined to be an edge An image recording / reproducing apparatus comprising: a noise reduction device that obtains a median value of data of a plurality of pixels including pixels and outputs the median value as decoded image data. 10. The noise reduction device has a frame memory, stores a plurality of frames of image data for which the median is obtained in the frame memory, and further stores a plurality of frames of image data including the image data for which the median is obtained. 10. The image recording / reproducing apparatus according to claim 9, wherein a median value of pixel data at the same position in each of the minutes is output. 11. The image recording / reproducing apparatus according to claim 9, wherein said noise reduction apparatus has a SIMD control processor in which element processors are multidimensionally arranged in one dimension. 12. The image recording / reproducing apparatus according to claim 10, wherein said noise reduction apparatus includes a SIMD control processor in which element processors are one-dimensionally and multi-parallel. 13. The image recording / reproducing apparatus according to claim 9, wherein the SIMD control processor in which the element processors are one-dimensionally multi-parallel is bit processing. 14. The image recording / reproducing apparatus according to claim 10, wherein the SIMD control processor in which the element processors are one-dimensionally and multi-parallel is bit processing.