JP2002111474A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving an output buffer circuit enabling to suppress a reduction of a output current due to a parasitic resistance of an output signal line, and in a programmable impedance output buffer system, capable of reducing errors of impedance matching of the buffer circuit due to the resistance. SOLUTION: In the device comprising the buffer circuit composed of a parallel connections of a plurality of transistors with different sizes between the output signal line connected an output terminal and a power source line and an impedance control circuit to control on/off of each transistor to adjust impedances of the buffer circuit, in each transistor of the buffer circuit, transistors in large size are arranged close to the terminal, transistors in small size are arranged away from the terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device having a function of an impedance output buffer method.

[0002]

2. Description of the Related Art Conventionally, in a general output buffer circuit, noise (di / d) generated when a buffer is turned on.
Increasing the buffer size within a range where t) does not matter has been considered as a high-speed data transfer technique. Simply control a large buffer with one gate control,
The method that turns on all at once is the most common.

As a technique taking the above noise into consideration, it is known to divide a large buffer into a plurality of buffers and gradually turn them on with a time difference.

[0004] In either method, there is no need to particularly consider the parasitic resistance in the layout configuration of the output buffer circuit.

[0005] However, as speeding up has progressed, recently,
If the impedance of the system bus line and the impedance of the output buffer circuit of the device connected to the bus line do not match, high-speed data transfer cannot be performed due to reflected waves. There has been proposed a specification called a programmable impedance output buffer method in which a value set to a pin is adjusted with high precision. This is one of the important circuit technologies in the high-speed interface specification.

FIG. 5 is a circuit diagram of a main part of a conventional semiconductor device using the above-mentioned programmable impedance output buffer system.

This semiconductor device has an output buffer circuit 200 for driving output data and outputting it to output pad 210.
And a programmable impedance control circuit 100 for controlling the impedance of the output buffer circuit 200.
And

The output buffer circuit 200 includes an output pad 2
10, five (5 bits) pull-up PMOS transistors P1 to P5 having different gate widths between the output signal line 21 and the VDD line and the GND line. P0 and pull-down NMOS transistors N1 to N5, N0 are connected in parallel.

The arrangement of these transistors is such that pull-up PMOS transistors P1, P2, P3, P4, P5, and P0 are arranged in this order from the side closer to the output pad 210, and pull-down NMOS transistors N1 and N1
N2, N3, N4, N5, and N0 are arranged.

For example, in the case of 5 bits, pull-up PMOS transistors P0, P1, P2, P3, P
4, P5 transistor sizes WP0, WP1, WP
2, WP3, WP4, and WP5 use WP0 as an offset, and WP1: WP2: WP3: WP4: W5 = 1: 2: 4:
8:16, from WP0 to WP0 + 31 * WP1,
The step interval can be changed in 32 steps in WP1.

Similarly, the transistor sizes WN0, WN1, WN2, WN3, WN4, WN of the NMOS transistors N0, N1, N2, N3, N4, N5 for pull-down.
N5 uses N0 as an offset, and WN1: WN2: WN3: WN4: W5 = 1: 2: 4:
8:16, from WN0 to WN0 + 31 * WN1,
The step interval can be changed in 32 steps in WN1.

The programmable impedance control circuit 100 has a pull-up P for pulling up the output buffer circuit 200.
MOS transistors P1, P2, P3, P4, P5, P
0 control signals PG1 and PG
2, PG3, PG4, PG5, PG0 and NMOS transistors N1, N2 for pull-down.
Gate control signals NG1, NG2, NG3, NG4, NG are respectively applied to the gates of N3, N4, N5, N0.
5, NG0, and by controlling the on / off of each of these transistors, the impedance of the output buffer circuit 200 can be adjusted.

[0013]

However, when the programmable impedance output circuit is to be realized by the above-mentioned conventional semiconductor device, there are the following problems.

FIG. 6 is a diagram showing the parasitic resistance of the circuit of FIG. In the conventional method, the relationship between the distance from the pad (pad) and the transistor size has been arranged without having to worry about anything. For example, as shown in FIG. 5, consider the case where the transistor size is P5>P4>P3>P2> P1. As shown in the figure, when a large-sized transistor is far from the output pad 210, the reduction in current is increased by the parasitic resistances r0 to r5 of the output signal line 21. For example, the PMOS with the largest current
The parasitic resistance when the transistor P5 is turned on is r1
+ R2 + r3 + r4 + r5, and the decrease in the output current IOH at the time of “H” level output to the output pad 210 increases.

Similarly, when the NMOS transistor N5 having the largest current is turned on, the parasitic resistance is r1 + r2
+ R3 + r4 + r5, and the decrease in the output current IOL at the time of the “L” level drawn from the output pad 210 increases.

Therefore, a predetermined output current IOH / IOL
Cannot be obtained, and the matching of the impedance of the output buffer circuit 200 causes a large error, which is a problem.

The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an output buffer capable of suppressing a decrease in output current due to a parasitic resistance of an output signal line. It is an object of the present invention to provide a semiconductor device which realizes a circuit and can reduce an impedance matching error of an output buffer circuit due to a parasitic resistance in a programmable impedance output buffer system.

[0018]

In order to achieve the above object, in a semiconductor device according to the present invention, a plurality of power supply lines having different sizes are provided between an output signal line to which an output terminal is connected and a power supply line. A semiconductor device comprising: an output buffer circuit formed by connecting transistors in parallel; and an impedance control circuit that controls on / off of each of the transistors in order to adjust the impedance of the output buffer circuit. The transistor is characterized in that a large-sized transistor is arranged closer to the output terminal, and a small-sized transistor is arranged farther from the output terminal.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, each of the transistors of the output buffer circuit is sequentially arranged in ascending order of size from the output terminal. It is characterized by.

According to a third aspect of the present invention, in the semiconductor device, an output buffer circuit comprising a plurality of transistors having different sizes connected in parallel between an output signal line to which an output terminal is connected and a power supply line; A semiconductor device comprising: an impedance control circuit that controls on / off of each of the transistors in order to adjust the impedance of the buffer circuit; dividing each of the transistors of the output buffer circuit into an arbitrary number; The obtained transistor group is connected in parallel, and is configured to be turned on / off by the same control signal from the impedance control circuit in units of division. From the larger transistor to the smaller transistor. And characterized by being arranged.

According to a fourth aspect of the present invention, in the semiconductor device, an output buffer circuit comprising a plurality of transistors having different sizes connected in parallel between an output signal line to which an output terminal is connected and a power supply line; A semiconductor device comprising: an impedance control circuit that controls on / off of each of the transistors in order to adjust the impedance of the buffer circuit; dividing each of the transistors of the output buffer circuit into an arbitrary number; The obtained transistor group is configured to be connected in parallel and to be turned on / off by the same control signal from the impedance control circuit in units of division, and the arrangement of all transistors after division is arranged in an arbitrary order. It is characterized by having done.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 is a circuit diagram of a main part of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing the parasitic resistance of the circuit of FIG.

In the semiconductor device of this embodiment, an output buffer circuit 20 having a different configuration is provided in place of the conventional output buffer circuit 200 in the configuration shown in FIG. That is, in the output buffer circuit 20, for example, in a transistor arrangement of a 5-bit configuration, a large-sized transistor is arranged closer to the output pad 210, and a small-sized transistor is arranged farther from the output pad 210. It is different from the circuit.

That is, the output buffer circuit 20 sequentially includes pull-up PMOS transistors P5, P4, P3, P2, P
1, P0, and N for pull-down
MOS transistors N5, N4, N3, N2, N1, N
0, and the PMOS transistors P0 to P5 are connected to VDD.
NMOS transistors N0 to N5 are connected in parallel between the output signal line 21 and the GND line. The transistor size of the pull-up PMOS transistors P5, P4, P3, P2, and P1 is P5>P4>P3>P2> P1, and the pull-down NMOS transistors N5, N4, N3
The transistor size of N2 and N1 is N5>N4> N3
>N2> N1.

Here, the transistor sizes WP0-WP5 of the pull-up PMOS transistors P0-P5
Is, as in the conventional case, WP0 is the offset, and WP1: WP2: WP3: WP4: W5 = 1: 2: 4:
8:16, the on / off control of the programmable impedance control circuit 100 causes WP0 to WP0 +
Up to 31 * WP1, the step interval can be changed by 32 steps in WP1. Similarly, an NMOS for pull-down
The transistor size WN0 of the transistors N0 to N5
WN5 uses WN0 as an offset, and WN1: WN2: WN3: WN4: W5 = 1: 2: 4:
8:16, from WN0 to WN0 + 31 * WN1,
The step interval can be changed in 32 steps in WN1.

As described above, by arranging a large-sized transistor near the output pad 210 and a small-sized transistor far from the output pad 210, as shown in FIG. When the large PMOS transistor P5 is turned on, the parasitic resistance is only r5, and the decrease in current is eased as compared with the conventional circuit.

Although the buffer current is the sum of WP0 to WP5, according to this embodiment, even if the current reduction due to the parasitic resistance is large in the small-sized transistor (the driving current is small), the large-sized transistor (the driving current Is large), the reduction in the current due to the parasitic resistance can be reduced, so that the reduction in the total drive current can be reduced.

As a result, in the programmable impedance output buffer system, it is possible to reduce the impedance matching error.

A circuit protection function (ESD) for protecting an internal circuit against a high voltage applied to the output pad 210
In the above, according to the configuration of the present embodiment, a current can easily flow through a large-sized transistor disposed near the output pad 210, and the ESD strength can be increased.

[Second Embodiment] FIG. 3 is a circuit diagram of a main part of a semiconductor device using a programmable impedance output buffer system according to a second embodiment of the present invention.

Output buffer circuit 30 of this semiconductor device
Are the transistors P connected in parallel as shown in FIG.
0 to P5 and N0 to N5 are arbitrary numbers (in this embodiment, 2
), And the transistor groups P0a to P5a and P0b to P5 obtained by the respective divisions.
b, N0a to N5a and N0b to N5b are similarly connected in parallel. Further, on / off control is performed in units of division by the same control signal from the impedance control circuit 100.

That is, the pull-up PMOS transistors P0a and P0b are controlled by the control signals PG0 and PM
The OS transistors P1a and P1b output the control signal P
G1 and the PMOS transistors P2a and P2b are controlled by the control signal PG2 and the PMOS transistors P3a and P3b.
Is a control signal PG3, a PMOS transistor P4
a and P4b are controlled by the control signal PG4, and the PMOS transistors P5a and P5b are controlled by the control signal PG5.

Similarly, pull-down NMOS transistors N0a and N0b control signals NG0 and NMO, respectively.
The S transistors N1a and N1b output a control signal NG
1, NMOS transistors N2a and N2b have control signal NG2, NMOS transistors N3a and N3b have control signal NG3 and NMOS transistor N4
a and N4b are controlled by a control signal NG4, and the NMOS transistors N5a and N5b are controlled by a control signal NG5.

The arrangement of all the transistors after the division is such that the transistors having the larger size and the transistors having the smaller size are repeatedly arranged from the output pad 210 side. In the present embodiment, the arrangement on the pull-up side is as follows: the PMOS transistors P5a, P4a, P3a, P2a, P1a, P0a
This is repeated, and PMOS transistors P5b, P4b, P3b, P2b, P1b, and P0b are sequentially arranged. Similarly, the arrangement on the pull-down side is such that the NMOS transistors N5a, N4a, N3a, N2a, N1a, N
0a, and this is repeated to sequentially arrange the NMOS transistors N5b, N4b, N3b, N2b, N1b, and N0b.

According to the layout method of the present embodiment, the transistor size dependence of current reduction due to parasitic resistance can be reduced as compared with the layout method of the first embodiment. PMOS is a large buffer
Even when the transistors P5a and P5b (or the NMOS transistors N5a and N5b) are turned on, and even when the PMOS transistors P1a and P1b (or the NMOS transistors N1a and N1b), which are small buffers, are turned on, the current loss is smoothed. . This is because, in the case of the programmable impedance, it is necessary to match with a similar degree of error regardless of whether IOH / IOL is large or small.

As is apparent from FIG.
OS transistor P1 (or NMOS transistor N)
The parasitic resistance of 1) is r1 + r2 + r3 + r4 + r5, and the large-sized PMOS transistor P5 (or NM)
The parasitic resistance of the OS transistor N5) is r5, and the current reduction smoothing effect of the small-sized transistor due to the division of the present embodiment is larger than that of the large-sized transistor.

From the viewpoint of matching the impedance of the output buffer circuit, if the impedance to be matched is large, the transistors P1a,
Turn on P1b or the like and fit. When the impedance to be adjusted is small, the large-sized transistors P5a, P5b and the like are turned on and adjusted. In either case, in order to reduce the alignment error similarly, it is necessary to reduce the transistor size dependency of the current reduction due to the parasitic resistance, and the layout method of the present embodiment is superior to the first embodiment.

Third Embodiment FIG. 4 is a circuit diagram of a main part of a semiconductor device using a programmable impedance output buffer system according to a third embodiment of the present invention.

The output buffer circuit 40 of the present embodiment is obtained by arranging all the divided transistors in an arbitrary order in the layout method of the second embodiment.

That is, as shown in FIG. 4, in the present embodiment, the arrangement on the pull-up side is such that the PMOS transistors P5a, P5a
4a, P3a, P2a, P1a, P0a;
PMOS transistors P1b, P2b, P3b, P4
b, P5b, P0b. Similarly, the arrangement on the pull-down side is such that the NMOS transistors N5a, N4a, N3
a, N2a, N1a, N0a, and NMOS transistors N1b, N2b, N3b, N4b, N5b, N
0b.

In this embodiment, as in the second embodiment, the dependence of the current reduction due to the parasitic resistance on the buffer size can be reduced.
In view of the impedance matching, it is possible to reduce the impedance dependency of the matching accuracy.

[0043]

As described above in detail, according to the present invention, it is possible to suppress a decrease in the output current due to the parasitic resistance of the output signal line. , The error in matching the impedance of the output buffer circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a programmable memory according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram of a main part of a semiconductor device using an impedance output buffer method.

FIG. 2 is a diagram illustrating a parasitic resistance of the circuit of FIG. 1;

FIG. 3 shows a programmable memory according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram of a main part of a semiconductor device using an impedance output buffer method.

FIG. 4 is a diagram illustrating a programmable memory according to a third embodiment of the present invention.
FIG. 3 is a circuit diagram of a main part of a semiconductor device using an impedance output buffer method.

FIG. 5 is a main part circuit configuration diagram of a conventional semiconductor device using the above-described programmable impedance output buffer system.

FIG. 6 is a diagram illustrating a parasitic resistance of the circuit of FIG. 5;

[Explanation of symbols]

 20, 30, 40 Output buffer circuit 21 Output signal line 100 Programmable impedance control circuit 210 Output pad P0-P5 PMOS transistor for pull-up N0-N5 NMOS transistor for pull-down

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 (72) Inventor Osamu Hirabayashi 1 Kosuka Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation F term in Microelectronics Center (reference)

Claims (4)

[Claims] An output buffer circuit comprising a plurality of transistors having different sizes connected in parallel between an output signal line to which an output terminal is connected and a power supply line; and an output buffer circuit for adjusting an impedance of the output buffer circuit. A semiconductor device comprising an impedance control circuit for controlling on / off of each transistor, wherein each transistor of the output buffer circuit includes a transistor having a large size closer to the output terminal and a transistor having a small size being connected to the output terminal. A semiconductor device, wherein the semiconductor device is arranged far from the semiconductor device. 2. The semiconductor device according to claim 1, wherein said transistors of said output buffer circuit are sequentially arranged in the order of increasing size, in a direction closer to said output terminal. 3. An output buffer circuit in which a plurality of transistors having different sizes are connected in parallel between an output signal line to which an output terminal is connected and a power supply line, and the output buffer circuit is provided for adjusting the impedance of the output buffer circuit. In a semiconductor device having an impedance control circuit for controlling ON / OFF of each transistor, each transistor of the output buffer circuit is divided into an arbitrary number, and a transistor group obtained by each division is connected in parallel. In addition, on / off control is performed in units of division by the same control signal from the impedance control circuit, and the arrangement of all the transistors after division is smaller than that of the output terminal side, starting from the larger transistor. A semiconductor device having transistors arranged repeatedly. 4. An output buffer circuit in which a plurality of transistors having different sizes are connected in parallel between an output signal line to which an output terminal is connected and a power supply line, and the output buffer circuit is provided for adjusting an impedance of the output buffer circuit. In a semiconductor device having an impedance control circuit for controlling ON / OFF of each transistor, each transistor of the output buffer circuit is divided into an arbitrary number, and a transistor group obtained by each division is connected in parallel. In addition, the semiconductor device is configured so that on / off control is performed in units of division by the same control signal from the impedance control circuit, and all transistors after the division are arranged in an arbitrary order.