JP2002100553A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device that prevents deviation in alignment, and at the same time can reliably carry out patterning between existing patterns even in a foundation having an extremely fine step. SOLUTION: Resist is flatly applied onto the foundation having a step. After that, the resist is positively turned into a thin film to the upper section of the step. A region from the upper section to the lower one in the step is subjected to overlap exposure and is developed for forming a resist pattern merely at the lower section of the step in a self-alignment manner. The resist pattern is low, and at the same time adheres not only onto the bottom surface of the step but also onto the side wall of the step, thus preventing deformation and collapse in the resist pattern. Also, alignment margin to a foundation pattern is not required, thus fining an element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, a transistor and a portable information terminal manufactured by using the method, and a resist coating apparatus and a resist developing apparatus. Lithography technology for performing self-aligned patterning.

[0002]

2. Description of the Related Art In the process of manufacturing an LSI (Large Scale Integrated Circuit), many steps and irregularities are often found on the underlying layer for patterning. There is a need for lithographic techniques that can be performed.

Conventionally, as a method of manufacturing a semiconductor device, there is a method shown in FIG. 25 (see Japanese Patent Application Laid-Open No. 1-292829). In this method of manufacturing a semiconductor device, a resist 1703 is applied to the entire surface of a semiconductor substrate 1702 on which an existing pattern 1701 is formed so as not to be thicker than the existing pattern 1701. Then, exposure and development are performed using an exposure mask (not shown), and the resist 1703 on each existing pattern 1701 is removed from the existing pattern 1.
701 is removed to be slightly wider than 701, and the existing pattern 1701 and the resist pattern 170 are removed as shown in FIG.
5 is provided with a minute gap 1706. Then, the resist pattern 1705 is deformed by heating, and
As shown in (c), the gap 1706 is buried and the upper surface of the existing pattern 1701 is exposed.

On the other hand, a MOS type field effect transistor (M
With respect to OSFETs), the size of MOSFETs constituting LSIs has been increasingly reduced with the increase in the degree of integration of large-scale integrated circuits (LSIs). In order to further improve the degree of integration or to increase the operation speed, it is necessary to further shorten the gate length of the MOSFET. However, in the MOSFET having the conventional structure, the PN junction formed between the source / drain region and the semiconductor substrate is necessarily located at a position (deep position) apart from the main surface of the semiconductor substrate, so that the short channel effect is likely to occur. Was. The conventional MOSFET has a problem that it is difficult to shorten the gate length in order to avoid characteristic deterioration due to the short channel effect.

In order to solve this problem, a MOSFET having a structure as shown in FIG.
-196577). The MOSFET of FIG. 28 is manufactured as follows.

First, as shown in FIG. 27A, an active region and a field oxide film 1902 are formed on a main surface of a single crystal silicon substrate 1901. Although only one active region is shown in FIGS. 27A and 27B, in an actual LSI, a large number of active regions are formed on the main surface of one silicon substrate 1901. The regions are electrically separated from each other by a field oxide film 1902.
Next, the gate insulating film 190 is formed by a known manufacturing technique.
3. A gate electrode 1904 and an insulating film 1905 are formed. The insulating film 1905 covers the surface of the gate electrode 1904.

Thereafter, a semiconductor layer (silicon layer) 1906 is selectively epitaxially grown on a portion of the active region of the silicon substrate 1901 where the silicon surface is exposed, as shown in FIG. Let it. Further, impurities are doped into the epitaxially grown semiconductor layer (epitaxially grown layer) 1906 to diffuse the impurities from the epitaxially grown layer 1906 to the vicinity of the surface of the silicon substrate 1901. Thus, the silicon substrate 1901
At a relatively shallow position from the main surface of the
A PN junction is formed (at a position of about m).

Next, as shown in FIG. 28, an interlayer insulating film 1907 is deposited on the entire surface, a contact hole 1908 is opened at a desired position of the interlayer insulating film 1907, and an upper wiring 1909 is formed. Obtain a MOSFET.

The MOSFET shown in FIG. 28 is called a "stacked diffusion layer type MOSFET". This is the source
This is because a diffusion layer functioning as a drain region is formed by an epitaxially grown layer (stacked layer) 1906 in which impurities are diffused and a thin impurity diffusion layer near the surface of the silicon substrate 1901.

[0010]

By the way, with respect to the lithographic technology, as the miniaturization progresses, it is becoming difficult to perform reliable alignment control with the conventional alignment technology.

For this reason, when the conventional method for manufacturing a semiconductor device shown in FIG. 25 is carried out, if a misalignment occurs at the time of exposure, as shown in FIG. The existing pattern 1701 and the resist pattern 180
5, a large groove 1806 is generated. Therefore, even if the resist pattern 1805 is deformed by heating, as shown in FIG. 26 (b), a resist residue 1805a is generated on the existing pattern 1701, and a gap between the existing pattern 1701 and the resist pattern 1805 is formed. The large groove 1806 cannot be reliably filled. Therefore, even if etching is performed by using the resist pattern 1805 as a mask in the next step of etching, the semiconductor substrate 1702 in the bottom region of the groove 1806 that cannot be filled is etched. Occur. Further, in this method, since the heating deformation process for embedding the resist between the existing patterns 1701 and 1701 is performed, the patterned existing pattern 1701 is deformed. For this reason, miniaturization is difficult, and in particular, it is difficult to control the line width of the pattern. Further, even if the second exposure and development are performed later in the area where the resist is embedded, heating is performed until the resist is deformed, so that high-precision patterning is difficult.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a semiconductor device which does not cause misalignment and can reliably perform patterning between existing patterns even on a base having a very fine step. Is to do.

Further, the conventional MOSFET shown in FIG. 28 has the following problems.

That is, as shown in FIG. 27B, when the epitaxial growth layer 1906 is formed by using the selective epitaxial growth method, a facet is inevitably formed near the side surface of the gate electrode 1904.
In the portion where the facet is formed, the thickness of the epitaxial growth layer 1906 is smaller than in other portions. Therefore, when an impurity is doped into the epitaxial growth layer 1906 by using an impurity doping technique such as solid phase diffusion, vapor phase diffusion, or ion implantation and a heat treatment for activating the impurity is performed, the impurity is formed in the silicon substrate 1901. The impurity concentration profile of the impurity diffusion layer changes from the design value. More specifically, the PN junction formed in the silicon substrate 1901 becomes locally deep immediately below the facet (for example, 100 nm to 15 nm).
In order to reach a depth of about 0 nm), the short channel effect cannot be sufficiently suppressed.

Further, since the silicon selective epitaxial growth technique uses a large amount of hydrogen, the scale of the apparatus is large and the manufacturing cost is high. In addition, since the pre-treatment temperature (1000 ° C. or higher) of the epitaxial growth and the growth temperature (900 ° C. to 1100 ° C.) are high, impurities are easily diffused deeply,
It is difficult to control the impurity concentration profile to a desired shape. Further, since a relatively large thermal stress is generated, crystal defects are likely to occur near the gate electrode 1904 and near the edge of the field oxide film 1902, and the leak current increases.

Further, as the miniaturization of elements progresses and the distance between the element isolation region 1902 and the gate electrode 1904 decreases,
When the source / drain active region becomes smaller, it becomes difficult to form the epitaxial growth layer 1906 having a desired thickness with good controllability.

Therefore, another object of the present invention is to provide a transistor such as a MOSFET or a TFT (thin film transistor) which has a small junction leak and hardly causes a short channel effect.

[0018]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a step of flatly applying a resist to a stepped base, and a step of applying a resist to the stepped base. Forming a resist pattern below the step, including a step of positively reducing the film thickness of the resist from the film thickness immediately after the application of the resist, a step of exposing the resist, and a step of developing. Features.

According to the above-described method for manufacturing a semiconductor device, in the step of forming a resist pattern, first, a resist is applied flat to a stepped base. Specifically, for example, a low-viscosity resist having a viscosity of 5 cp or less is 3000
The coating is performed at a low rotation of not more than rpm. The low viscosity and low speed rotation can suppress striation (coating unevenness that occurs as if the comet from the center side of the wafer to the outside is trailing), and can be applied very flatly.

Next, the thickness of the resist is made positively smaller than the thickness immediately after the application of the resist. The resist is usually thinner than the film thickness immediately after the application by about 5% by baking after the application, and also in the development step, the resist is usually thinner than the film thickness immediately after the application by 5% to 10%. Are known. However, the “actively thinning step” described in the present invention is not such a film reduction,
It means that the film thickness of the resist is made thinner than the film thickness immediately after application. Preferably, after applying a resist thicker than the step, the resist is thinned to the upper part of the step. Alternatively, it may be lower than the upper surface of the step (the upper surface of the convex portion). However, the point is not to remove all the resist but to leave at least a film thickness that can withstand etching. Since the surface of the resist is flat, even if the resist is thinned to the upper part of the step, the resist having a sufficient film thickness can be left under the step (the bottom of the concave portion). Note that the resist pattern may be formed even in a large area under the step.

In this way, since the resist can be left only below the step, the resist pattern can be securely formed only under the step in a self-aligned manner without considering the influence of misalignment in the exposure step. be able to.

Further, by including a step of positively reducing the thickness of the resist immediately after the application, unnecessary resist on the upper part of the step is removed. Therefore, the resist can be patterned in a self-alignment manner only with respect to the step side wall only at the lower portion (recess) of the step. At that time, the height of the resist pattern is low, and the resist pattern is in close contact with not only the bottom surface but also the side surface of the step (recess) of the base, so that deformation and collapse of the resist pattern can be prevented. . Further, since there is no need to provide an alignment margin for the underlying pattern, the element can be miniaturized.

In one embodiment of the present invention, the step of positively making the film thickness of the resist smaller than the film thickness immediately after the application of the resist includes the step of flatly applying the resist on a base and the step of This is performed between the step of exposing the resist.

This makes it possible to positively reduce the thickness of the resist immediately after coating with good controllability.
Further, since the step of thinning the resist is performed before the step of developing, the resist can be developed with good controllability.
Residual development can be suppressed.

In one embodiment of the present invention, the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist includes the step of exposing the resist and the step of developing. Performed between the steps.

In this manner, exposure can be performed with good controllability, similarly to ordinary photolithography, and the line width of the pattern can be stabilized. Further, since the step of positively thinning the resist is performed before the step of developing, the resist can be developed with good controllability, and the undeveloped residue can be suppressed.

In one embodiment of the present invention, the step of positively reducing the film thickness of the resist from the film thickness immediately after the application of the resist is performed after the developing step.

By doing so, exposure can be performed with good controllability. Further, after the formation of the resist pattern is confirmed, the resist is thinned, so that an abnormality of the resist pattern can be found at an early stage.

In one embodiment of the present invention, a region where the thickness of the resist is to be reduced is exposed to light and developed.
The thickness of the resist in the above region is reduced.

In this way, it is possible to use a device used in the developing step without using another new device in order to make the resist thinner, so that no new capital investment is required. This embodiment can be realized. Further, since the processing is limited to the processing in the area where the photolithography process is performed, the problem of dust due to transportation or the like is eliminated. Furthermore, since the developing step can use a commonly used developer,
There is no need to use a new developer, and no additional costs are incurred for implementing this embodiment.

In one embodiment of the present invention, the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist is a wet etching step.

This makes it possible to make the resist less damaged and to positively reduce the thickness of the resist immediately after coating. Further, it is possible to easily control the etching rate for making the resist thinner than the film thickness immediately after the application of the resist, depending on the concentration or the temperature of the chemical solution used for the wet etching.

In one embodiment of the present invention, the wet etching is performed using a developer.

In this case, since the apparatus used in the developing step can be used, it is not necessary to use a new apparatus. The same equipment can be used for the waste liquid line equipment. Therefore, this embodiment can be realized without making new capital investment. Further, since the processing is limited to the processing in the area where the photolithography process is performed, the problem of dust caused by transportation or the like is reduced. Further, this embodiment can be realized by adding one step to the ordinary photolithography step.

The wet etching step is not limited to a developing solution, and a mixture of isopropyl alcohol and acetone or propylene glycol monomethyl ether acetate may be used. Further, a mixture of xylene and butyl acetate or N-methylpyrrolidone may be used.

In one embodiment of the present invention, when the resist to be etched is a negative resist, the concentration of tetramethyl is less than half the standard value in the wet etching step using the developing solution. Use an ammonium hydroxide developer. In the case of a positive resist, a tetramethylammonium hydroxide developer having a concentration of at least twice the standard value is used.

This makes it possible to reduce the thickness of the resist with low damage. Further, the controllability of the etching rate when the resist is made thinner is improved.

In one embodiment of the present invention, the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist is a chemical mechanical polishing (CMP) step.

In this way, the resist surface can be made flatter in the step of positively reducing the thickness of the resist immediately after coating.

In one embodiment of the present invention, the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist is a dry etching step.

In this way, EPD (Endpoint Detection) can be used. Further, when an all-dry process that does not use a wet process is used, a cluster tool can be used. Then, after depositing the resist on the substrate by the CVD (Chemical Vapor Deposition) method, it is possible to make the resist thin by continuous processing without exposing it to the air.

In one embodiment of the present invention, in the step of exposing the resist, overlapping exposure is performed to expose a region which is larger than the resist pattern below the step to be actually left and extends to the upper part of the step. Process.

In this case, by forming the resist below the step and performing the overlap exposure, even if the alignment is misaligned, it is possible to surely expose the necessary step side wall portion. A gap can not be formed between the side wall of the step and the resist pattern, and the resist pattern can be formed accurately.

In one embodiment of the present invention, the resist is a positive resist, and the entire surface or a predetermined region of the resist is exposed to form a side wall of the resist on the side wall of the step of the base. .

Since the exposure light does not easily enter the vicinity of the side wall of the step, the positive type resist near the side wall cannot be sufficiently exposed to light required for development. Therefore, the side wall of the resist is self-aligned with the side wall of the step. Can be formed. Therefore, it is possible to use the sidewall as a mask for ion implantation. For example, when the step is a gate, a resist is formed by using the method for forming a resist pattern according to the present embodiment, and then ion implantation is performed, so that the gate is at a certain distance from the gate. Ions can be implanted in a self-aligned manner. Further, by changing the exposure amount and the temperature of PEB (post-exposure bake), a necessary ion implantation mask can be formed.

In one embodiment of the present invention, the resist is a negative type resist, and the entire surface or a predetermined region of the resist is exposed to form a gap between the side wall of the step of the base and the resist pattern. To form

Since the exposure light does not easily enter the vicinity of the step side wall, the negative resist near the side wall cannot perform sufficient exposure required for development. Therefore, the gap between the side wall of the step and the resist pattern is formed in the step. Can be formed in a self-aligned manner with respect to the side wall of the substrate. Therefore, when the underlying pattern is a gate electrode, processing of the source / drain region can be formed in a self-aligned manner with respect to the gate electrode.

In one embodiment of the present invention, a step of forming an electrode or a wiring having at least a side wall covered with an insulating film on a semiconductor substrate; a step of depositing a conductive film;
A step of applying a resist flat, a step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist, and etching the conductive film using the resist as a mask to form the electrode or the wiring. And removing the upper conductive film.

In this case, even in the wiring region formed at the minimum pitch, the wiring can be formed in a self-aligned manner with good controllability by embedding the next wiring between the wirings. For this reason, beyond the limits of lithography technology,
The density of the electrodes or wirings can be increased.

In one embodiment of the present invention, the electrode or the wiring is formed on a semiconductor substrate roughly divided into an element isolation region and an active region, and the gate electrode is formed on the active region. It is formed via a gate insulating film.

In such a case, as compared with the epitaxial growth method, the source / drain regions can be stacked in a self-aligned manner by the electrodes to form the source / drain regions having no facets. Therefore, an element having a large driving force can be obtained while suppressing the short channel effect. Also, in the conventional epitaxial growth method,
While hydrogen baking at 1000 ° C is required, CV
Method D does not require hydrogen baking and has a process temperature of 600
Since the temperature is as low as about ° C., no junction leak occurs due to thermal stress or the like. Furthermore, since the stacked source / drain regions can overlap with the element isolation region (be larger than the source / drain active regions), the degree of freedom in forming a contact on the source / drain is increased. At the same time, the distance between the gate electrode and the element isolation region can be made smaller than before, and the element can be miniaturized.

In one embodiment of the present invention, the step is an electrode or a wiring covered with an insulating film.

In this case, when the conductive film is etched, the gate electrode is not exposed to the etching atmosphere, so that deterioration of the device can be suppressed and the same material is used for the gate electrode and the conductive film. Can be.

Further, in one embodiment of the present invention, a step of positively reducing the thickness of the above-mentioned resist from the thickness immediately after application of the resist, and a step of exposing and developing the resist to form a resist pattern And etching the conductive film using the resist pattern as a mask, and forming a second wiring at a second electrode located at both sides of the electrode or the wiring or at an arbitrary position.

In this case, a desired conductive film pattern (wiring) can be obtained even in a region where the above-mentioned electrodes or wirings do not exist, and the degree of design freedom is increased. In addition, the source
In a stacked diffusion layer type MOSFET in which a drain region is formed by stacking an epitaxially grown layer in which an impurity is diffused on a thin impurity diffusion layer near the surface of a silicon substrate, a source and a drain are short-circuited through unnecessary portions of the conductive film. In order to avoid this, patterning for removing unnecessary portions can be performed in a single exposure simultaneously with patterning for other necessary portions. In other words, the removal of the conductive film on the electrode, the formation of the pattern (wiring) of the conductive film, and the formation of a resist pattern for separating the source and the drain are performed in a normal lithography step, and the resist is applied to the resist. It can be realized only by adding a step of making the film thickness smaller than the film thickness immediately after application.

In one embodiment of the present invention, the conductive film is a polycrystalline silicon film, an amorphous silicon film, a polycrystalline silicon germanium film, an amorphous silicon germanium film, a refractory metal film, or , A polycrystalline silicon film, an amorphous silicon film, a polycrystalline silicon germanium film, or a composite film of an amorphous silicon germanium film and a high melting point metal film.

In this case, when performing a heat treatment for diffusing an impurity into the source / drain region and activating the impurity, the diffusion speed is very high up to the interface between the conductive film and the semiconductor substrate, while the diffusion speed is very high. Since the diffusion speed is low, the depth of the source / drain regions located in the region below the channel region is less affected by the variation in the height of the stacked region, and a shallow junction can be formed with good controllability.

In one embodiment of the present invention, the step is an electrode or a wiring covered with a conductive film.

The transistor according to one embodiment of the present invention is manufactured by using the above-described method for manufacturing a semiconductor device.

In one embodiment of the present invention, the transistor is a stacked diffusion layer type MOSFET.

In this case, since the above-described method for manufacturing a semiconductor device is used, there is no misalignment, so that there is no need to provide an alignment margin. In particular, when manufacturing a stacked diffusion layer type MOSFET, it can be manufactured by a stable process, the short channel effect can be suppressed, the junction leakage current can be reduced, and the threshold voltage can be reduced. , Stable MOSFE
T is obtained.

A portable information terminal according to an embodiment of the present invention includes the above-described transistor.

In this case, since the portable information terminal includes the above transistor, a more stable function can be provided.

The resist coating apparatus of the present invention includes means for supplying a solvent to the resist, and can change the viscosity of the resist.

The resist coating apparatus according to one embodiment is provided with at least one of a means for changing the temperature of the resist, the wafer and the coater cup, and a means for changing the amount of the solvent of the resist to optimize the viscosity of the resist. can do.

In this case, the film thickness of the resist is controlled by controlling the number of revolutions (rpm) of the wafer after discharging the resist, and by using the above-described means, even if the resist has the same viscosity and the same viscosity, Can be controlled more widely than before.

In one embodiment of the present invention, there is provided an apparatus using a function of cooling a resist, or an apparatus having both functions of heating and cooling.

In this case, the thickness of the resist can be controlled more widely.

Further, in one embodiment of the present invention, the resist film thickness is controlled by controlling the number of rotations of the wafer after discharging the resist and changing the mixing ratio between the solute and the solvent of the resist.

In this case, even with the same resist, the resist film thickness can be arbitrarily controlled more widely than before. Also,
There is no need to connect a plurality of resist containers having different viscosities to the resist coating apparatus, and the cost can be reduced in terms of material management. Further, the amount of resist used can be reduced by adding a solvent or the like. Therefore, by preparing a high-viscosity resist in advance and suppressing the discharge amount of the resist, it is possible to significantly reduce the consumption of the resist,
Reduce costs.

The resist developing apparatus according to one embodiment of the present invention includes means for changing the concentration of the developing solution by adding pure water to the developing solution.

In one embodiment of the present invention, the developing rate of the resist is adjusted by at least one of a means for changing the temperature of the developing solution, the wafer or the developing cup, and a means for changing the concentration of the developing solution. .

In this case, by controlling the development by using the function of the above means and the time for immersing the wafer in the developing solution, various resists can be controlled more widely than before even with the same developing solution and the same concentration. .

Further, one embodiment of the present invention has a function of heating a resist or a developer, or a function of performing both heating and cooling.

In this case, the thickness of the resist can be controlled more widely.

In one embodiment, the control of the developing step can be arbitrarily controlled by changing the mixing ratio of the developer and pure water.

In this case, there is no need to connect a plurality of developer systems having different concentrations, and the cost can be reduced from the viewpoint of material management. Further, a developer usage fee can be reduced by adding pure water or the like. Therefore, not only by suppressing the discharge amount of the developing solution but also by preparing a high-concentration developing solution in advance, the consumption amount of the developing solution can be significantly reduced, and the cost can be reduced.

[0078]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First, the structure of the underlayer common to the first to sixth embodiments will be described with reference to FIGS. 1 (a) and 1 (b). 1 (a) and 1 (b) show a stepped base, FIG. 1 (a) is a cross-sectional view taken along line 108 in FIG. 1 (b), and FIG. 1 (b) is a plan view. In addition,
Here, the step is a concept including unevenness.

As shown in FIG. 1A, the silicon substrate 10
1, an insulating film 102 and a polycrystalline silicon film 105 are deposited on the order of 0.25 μm.
6 is deposited on the order of 0.20 μm. Next, the resist is patterned using a well-known lithographic technique, the silicon oxide film 106 is processed using the resist as a mask, and the resist is removed. Next, the silicon oxide film 1
After the gate electrode is formed by processing the polycrystalline silicon film 105 using the mask 06 as a mask, the silicon nitride film 104 is
Deposit about 0 nm.

The polycrystalline silicon film 105 serving as the gate electrode has a length of 0.24 μm and a width of 2.5 μm. The height of the upper surface 107 of the step is 0.4
5 μm. In the following first to sixth embodiments, a resist is patterned on the silicon nitride film 104 at the bottom 103 of the stepped recess in a self-aligned manner. Further, in FIG. 2 to FIG. 11 described below, a base having a step is shown as a whole,
The detailed structure of the base as shown in FIG. 1 is omitted. That is, the stepped bases in the upper and lower views in FIGS. 2 to 11 indicate the same as those in FIGS. 1A and 1B.

(Embodiment 1) This embodiment 1 is different from FIG.
A negative resist 201 is provided on a base 200 having a step shown in FIG.
Is applied flatly, and then the negative resist 201 is positively thinned, exposed and developed, so that the lower part of the step is formed.
This is a method in which the resist pattern 206 is formed only in the (recess). 2A to 2D are cross-sectional views, and the lower views are plan views.

First, as shown in FIG. 2A, a resist 201 is applied evenly on a base 200 having a step. At this time, a low-viscosity chemically amplified negative resist TDUR-N9 was used to apply the coating flat so as not to be affected by the step of the base.
08 4.5 cp (manufactured by Tokyo Ohka Kogyo Co., Ltd.) at 2000 rpm
The coating was performed at a low rotation of about m. Thereafter, prebaking (baking after application) was performed at 110 ° C. for 90 seconds. The film thickness of the resist 201 was about 700 nm below the step (recess), and the surface of the resist 201 was flat as shown in FIG.

At the time of this coating, the resist 201 is made of TDUR
-N908 Not limited to 4.5 CP, but any material that can withstand etching, implantation, or the like in the next step may be used. If the viscosity of the resist 201 is as low as 5 cp or less, the undercoat 20
In general, the resist 201 can be applied flat without being affected by a step (unevenness) of 0, but it is preferable that the resist 201 has a lower viscosity from the viewpoint of flattening. In addition, the lower the rotation of the spin coater (not shown), the lower the rotation of the underlayer 200, and the thicker the resist 201 is applied to the underlayer 200, the less the flatness of the resist 201 is affected by the step of the underlayer 200. For this reason, it is preferable to apply the resist 201 as thickly as possible with the lower rotation of the base 200. But,
Still, if it is difficult to flatten the surface of the resist 201 due to an excessively large step or unevenness of the surface of the resist 201, a method of forming a dummy pattern on the underlayer 200 in advance may be used. It is also an effective method to make the unevenness of the surface as uniform as possible. Prebaking is about 110 ° C., which is the optimal condition in consideration of uniformity in the next step of thinning and stability of the rate. However, it is possible to perform the prebaking at about 80 ° C. to 130 ° C. Also, when using another resist, a temperature higher than the pre-bake temperature used in ordinary photolithography is preferable.

Next, tetramethylammonium hydroxide (TMAH (SOPD-R manufactured by Sumitomo Chemical Co., Ltd.)) having a concentration lower than that used in the ordinary developing process is used.
A developer that is a 1N aqueous solution is prepared. This developer contains 1
Since the resist 201 can be made thinner by 90 ° per minute (see point B in FIG. 13), the resist 201 is immersed in this developing solution for about 240 seconds to remove the surface of the resist 201 by 350 nm (see point A in FIG. 12). Thus, as shown in FIG.
The resist 201 is positively thinned, and the upper part 20 of the step is formed.
Expose 2

Next, the base 201 coated with the thinned resist 201 is washed with pure water and spin-dried.
(After spin drying, a bake plate may be further used).

FIG. 13 shows the relationship between the concentration of the developing solution for thinning the resist 201 and the etching rate. FIG. 12 shows the relationship between the amount of etching and the etching time when the resist 201 is etched with the developing solution at point B in FIG. From this relationship, an optimum etching time (point A in FIG. 12) for exposing the upper portion 202 of the step was obtained.

In the development step after the step of thinning the resist 201, the resist pattern is reduced in film thickness by about 5% to 10%. For this reason, taking this film reduction into account,
The resist 201 may be left to some extent on the upper part 202 of the step.

The conditions for thinning the resist are as follows:
Since the etching rate of the 0.1 N developer is stable, the controllability is good. However, a developer of 0.005N to 0.26N can be used if the processing time is properly adjusted. Above all, a concentration that is less than half the concentration normally used is preferred. However, the higher the concentration, the faster the rate,
Control becomes difficult. In addition, the lower the concentration, the lower the rate, and the lower the throughput (see FIG. 13). It should be noted that since the same etching characteristics as those in FIG. 13 can be obtained with other developing solutions, this embodiment can be realized even if other developing solutions are used.

Next, as shown in FIG. 2C, using an exposure mask 204, a KrF excimer laser (248 nm) stepper was used to expose 580 J / m ² , a numerical aperture (NA) of 0.6, and
Under the condition of coherency (σ) 0.65, the area 205 of the resist 201 is overlap-exposed with the laser beam 203. That is, as shown in FIG. 2 (c), the exposed region 205 exceeds the resist pattern 206 actually left (see FIG. 2 (d)) beyond the side wall of the step where the resist pattern 206 adheres. In an extended state, it overlaps with the resist pattern 206. More specifically, the exposed region 205 shown in FIG. 2C has a smaller thickness than the resist pattern 26 actually desired to be left shown in FIG.
The resist 201 is overlap-exposed so as to be about 5 μm larger. In this way, even if the alignment shifts in the direction in which the resist pattern 206 is brought into close contact, the portion where the resist pattern 206 is brought into close contact can be reliably exposed. By doing so, the resist pattern 206 can be accurately formed at a desired position even if a misalignment occurs in the direction of contact.

In this exposure, in order to pattern the resist pattern 206 having a length of 0.24 μm into a better shape, the exposure amount is 580 J / m ² , the numerical aperture (NA) is 0.6, and the coherency (σ) is 0.65. Conditions of the degree are best, but these conditions are device dependent. Also, the overlap exposure may be about twice as high as the alignment accuracy of an apparatus in which misalignment is considered.

Next, the post-exposure bake (PEB) was performed at 130 ° C.
Immersion in a developer (2.38% TMAH aqueous solution, NMD-W manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 60 seconds, and further post-baking (baking after developing solution treatment) at 110 ° C. for 60 seconds.
Perform for seconds. When the development is performed in this manner, as shown in FIG. 2D, a resist pattern 206 that is in close contact with the side wall of the step of the base 200 and has no misalignment with respect to the contact direction can be formed. Was.

At this time, the development time can be between 30 seconds and 80 seconds because the thickness of the resist 201 is small.
PEB can be about 110 to 140 ° C., but the amount of exposure greatly depends on it. Post bake is 8
About 0 ° C to 120 ° C is possible.

As described above, the resist pattern 206 completed according to the first embodiment has a pattern height lower than that at the time of the application of the resist 201, and the resist pattern 206 is formed not only on the bottom surface of the base 200 but also on the step side surface. Therefore, the resist pattern 206 can be prevented from being deformed or collapsed.

(Embodiment 2) The second embodiment is different from the first embodiment in the order of the steps of thinning and exposing.

In the second embodiment, a negative resist 301 is applied flat to a stepped base 300 shown in FIG. 3, then exposed, and the negative resist 301 is positively thinned and developed. In this method, the resist pattern 307 is formed only in the lower part (recess) of the step. FIG.
The upper figures in (a) to (d) are cross-sectional views, and the lower figures are plan views.

First, as shown in FIG. 3A, a negative resist 301 is applied flatly on a base 300 having a step.

Next, similarly to the first embodiment, as shown in FIG.
In step 02, the region 304 of the resist 301 is exposed. This exposure is an overlap exposure in which the upper portion 306 of the step is also exposed so that the region 304 partially overlaps the upper portion 306 of the step.

At the time of this exposure, unlike the first embodiment, the surface of the resist 301 is before the thinning of the resist 301, so that the same stable exposure as in ordinary photolithography can be performed.

Next, as shown in FIG. 3C, similarly to the first embodiment, the resist 301 is positively thinned to expose the upper portion 306 of the step.

The difference from the first embodiment at the time of this thinning is that the resist 301 is exposed and then thinned. Since the reaction proceeds a little, as shown in FIG. 12, the rate of thinning of the exposed portion (exposed portion) is lower than that of the unexposed portion (unexposed portion). Instead, the film must be thinned in more time.

Next, when development is performed in the same manner as in the first embodiment,
As shown in FIG. 3D, a resist pattern 307 having no misalignment is formed in close contact with the side wall of the step.

The resist pattern 30 according to the second embodiment
7 has a pattern height lower than that at the time of application of the resist 301, and the resist pattern 307 adheres not only to the bottom surface of the base 300 but also to the side surface of the step, so that the resist pattern 307 is not deformed or collapsed. Can be prevented.

(Embodiment 3) In Embodiment 3, the negative resist of Embodiment 1 is replaced with a positive resist.

In the third embodiment, a positive resist 401 is applied flat on a stepped base 400 shown in FIG. 4A, and then the positive resist 401 is positively thinned and exposed. This is a method in which a resist pattern 406 is formed only in the lower part of the step (recess) by developing. FIG.
The upper figures in (a) to (d) are cross-sectional views, and the lower figures are plan views.

First, as in the first embodiment, as shown in FIG. 4A, a positive resist 401 is flatly applied to a base 400 having a step.

Next, a developing solution is prepared which is a 0.7N aqueous solution of TMAH (SOPD-R manufactured by Sumitomo Chemical Co., Ltd.) having a higher concentration than that used in the ordinary developing step. This developer can make the resist 401 thinner in one minute.
(See point D in FIG. 15).
After immersion for 40 seconds, the resist surface is removed by 360 nm (see point C in FIG. 14). Thus, as shown in FIG.
The resist 401 is positively thinned, and the upper part 40 of the step is formed.
Expose 2

Here, FIG. 15 shows the relationship between the concentration of the developing solution for thinning the resist 401 and the etching rate. FIG. 14 shows the resist 401 in FIG.
5 shows the relationship between the etching amount and the etching time when etching is performed with the developing solution at point D of No. 5. From this relationship, an optimal etching time for surely exposing the step upper portion 402 was obtained (see point C in FIG. 14).

At the time of this thinning, the concentration of the developing solution is 0.1.
About 7N is easy to control. However, from 0.05N to 2.6N
However, it is possible if the processing time is adjusted appropriately. Above all, a concentration that is at least twice the concentration that is usually used is preferred. However, the higher the density, the faster the rate becomes, making it difficult to control, and conversely, the lower the density, the slower the rate becomes, and the throughput becomes worse (see FIG. 15).

Next, similarly to the first embodiment, as shown in FIG.
The area other than the area 405 is overlap exposed. In this overlap exposure, an unexposed area 405 overlaps a part of the upper part 402 of the step. Furthermore, when developed,
As shown in FIG. 4D, a resist pattern 406 having no misalignment is formed in close contact with the side wall of the step.

The resist pattern 40 according to the third embodiment
In No. 6, the pattern height is lower than that when the resist 401 is applied, and the resist pattern 406 adheres not only to the bottom surface of the underlayer 400 but also to the step side surface. Can be prevented.

(Embodiment 4) Embodiment 4 is different from Embodiment 3 in the order of the steps of thinning and exposure.

In the fourth embodiment, a positive resist 501 is applied flatly to a stepped base 500 shown in FIG. 5, then exposed, and the positive resist 501 is positively thinned and developed. In this method, the resist pattern 507 is formed only in the lower part (recess) of the step. FIG.
The upper figures in (a) to (d) are cross-sectional views, and the lower figures are plan views.

First, as shown in FIG. 5A, a positive resist 501 is applied evenly to a stepped base 500.

Next, similarly to the second embodiment, as shown in FIG.
In 02, an area other than the area 504 of the resist 501 is subjected to overlap exposure. In this overlap exposure, the unexposed area 504 overlaps a part of the upper part 506 of the step.

Since the surface of the resist 501 at the time of this exposure is different from that of the third embodiment before being made thinner,
Stable exposure is possible.

Next, as in the third embodiment, the resist 501 is thinned as shown in FIG.

This thinning is different from the third embodiment in that the resist 501 is exposed and then thinned, so that the exposed portion (the region other than the region 504) is located before the PEB. Regardless of the fact, since the reaction is a little advanced, a phenomenon occurs in which the rate of thinning is higher in the exposed part than in the unexposed part.

Next, when development is performed in the same manner as in the third embodiment,
As shown in FIG. 5D, a resist pattern 507 having no misalignment is formed in close contact with the side wall of the step.

The resist pattern 50 according to the fourth embodiment
7 has a lower pattern height than when the resist 501 is applied, and the resist pattern 507 adheres not only to the bottom surface of the base 500 but also to the side surface of the step, so that the resist pattern 507 is not deformed or collapsed. Can be prevented.

(Fifth Embodiment) In the fifth embodiment, different from the fourth embodiment, after the exposure and development steps, a step of performing further exposure to positively reduce the thickness of the resist is performed.

In the fifth embodiment, a positive resist 601 is applied flatly on a stepped base 600 shown in FIG. 6, then exposed and developed, and furthermore, the formed resist pattern 601 is formed as shown in FIG. In this method, the resist pattern 606 is formed only in the lower part (recess) of the step by actively thinning as shown in FIG. 6 (a) to 7 (e)
The upper diagram is a cross-sectional view, and the lower diagram is a plan view.

First, as shown in FIG. 6A, a positive resist 601 is applied flatly on a base 600 having a step.

As for the positive resist 601, a resist having a lower transmittance has better controllability of the thinning performed later.

Next, as in the fourth embodiment, as shown in FIG. 6B, overlap exposure is performed using a laser beam 602 and an exposure mask 603, and development is performed. Then,
As in the fourth embodiment, as shown in FIG. 6C, the resist pattern 60 corresponding to the unexposed region 604 is formed.
8 surely rides on the step upper part 609.

Next, in order to reduce the thickness of the resist pattern 608, as shown in FIG. 7 (d), the entire surface of the resist pattern 608 is exposed with a small amount of light enough to expose the surface 605 of the resist pattern 608 without an exposure mask. do. It is to be noted that the exposure may be performed not on the entire surface but on only a portion to be thinned.

Next, in order to positively reduce the thickness of the resist pattern 608, a second development is performed, and only the exposed surface portion 605 is dissolved in the developing solution, as shown in FIG. Then, a resist pattern 606 is obtained. The resist pattern 606 is the same as the resist pattern 60
6 is lower than the upper portion 609 of the step and closely adheres to the side wall of the step so that there is no misalignment.

The resist pattern 60 according to the fifth embodiment
6 has a pattern height lower than that at the time of application of the resist 601, and the resist pattern 606 adheres not only to the bottom surface of the base 600 but also to the step side surface, so that the resist pattern 606 is not deformed or collapsed. Can be prevented.

At the time of the second development, the acid generated on the surface of the resist 601 due to the exposure is changed by changing the temperature and time of the PEB at the time of development, so that the acid generated on the surface of the resist 601 is removed under the resist 601. Can control the range of diffusion toward. That is, depending on the temperature and time of PEB,
The film thickness that can be made thin can be controlled. Exposure may be performed using the difference in absorbance of the resist due to the difference in wavelength. In other words, exposing the excimer resist to i-line and developing it is also a means of thinning.

(Embodiment 6) Embodiment 6 is different from Embodiment 5 in that the resist is actively thinned before patterning the resist.

In the sixth embodiment, a resist 701 having a low transmittance is applied flat on a base 700 having a step shown in FIG. 8, and the entire surface is exposed and developed to positively reduce the thickness. As shown in FIG. 7, a method of exposing, developing, and patterning the resist 701 only at the lower part of the step is used.

First, as shown in FIG. 8A, a dye-containing positive resist 701 having a low transmittance (resist film thickness of 1.0
(Transmittance of 40% at μm) is applied evenly to base 700. The transmittance of the resist is easily controlled when the exposure is about 20% to 60%.

Next, as shown in FIG. 8B, when the entire surface of the resist 701 is exposed without an exposure mask, the exposure light 7
In the area 02, the resist 701 contains a dye and is thickly applied.
Only 03 is exposed. Note that only a portion to be thinned may be exposed with a small exposure amount.

Thereafter, development is performed to obtain FIG.
As shown in (5), the resist 701 is positively thinned while leaving the resist 701 only below the step (recess).

When the resist 701 is exposed and developed, the thinning in development can be controlled by adjusting the exposure amount, the transmittance of the resist 701, and the temperature of PEB.

Next, as shown in FIG. 9D, the resist 701 left only under the step is added to the resist 701 in the same manner as in the third embodiment.
As shown in FIG. 9D, overlap exposure is performed using a laser beam 702 and an exposure mask 705. By this overlap exposure, an area other than the area 706 is exposed. Next, when development is performed, a resist pattern 707 is obtained as shown in FIG. The resist pattern 707 is such that the height of the resist pattern 707 is lower than the upper part of the step 704, and the resist pattern 707 is in close contact with the side wall of the step so that there is no misalignment.

The resist pattern 70 according to the sixth embodiment
7 has a lower pattern height than when the resist 701 is applied, and the resist pattern 707 adheres not only to the bottom surface of the base 700 but also to the side surface of the step, so that the resist pattern 707 is deformed or collapsed. Can be prevented.

It is to be noted that the resist 701 is easier to control if it has a low transmittance to some extent. However, even if the resist 701 is not a resist having a low transmittance, a portion where the surface is to be thinned with a small exposure dose, or without using an exposure mask. By exposing the entire surface of the resist 701, the resist 701 can be similarly thinned. Even when the transmittance of the resist is not low, the thinning can be controlled in the same manner by the exposure dose and the temperature of PEB.

The resists of the first to sixth embodiments may be any resists that can withstand the next step of etching. Further, the coating method that determines the flatness of the flattening of the resist is such that after the positive resist thinning step, when the patterning of the resist is completed, the thinnest part of the resist can withstand the etching in the next step. Any material can be used as long as the film thickness is stable.

The step of positively thinning the resist is not limited to a method using a developing solution or a method of developing by exposure, but may be dry etching, RIE (reactive ion etching), wet etching, polishing or polishing. Any process such as CMP (chemical mechanical polishing) may be used as long as the process can positively thin the resist. In the first to sixth embodiments, the resist is positively thinned using a developing solution. However, the present invention is not limited to the developing solution, and acetone or propylene glycol monomethyl ether acetate may be used in isopropyl alcohol for 3 to 5 times.
A mixture of 0% by weight may be used. Among the,
5% by weight is best. In addition, to xylene,
3 to 50% by weight of butyl acetate or N-methylpyrrolidone
You may use what mixed. Among them, those mixed with 5% by weight are the best.

In addition, without using a process for thinning the film, it is also possible to actively use a resist whose film thickness is significantly larger than expected with a normal resist. Includes thinning the resist. In addition, the use of a developing solution having a particularly large film reduction compared to the film reduction conceivable in a normal development step is also included in the fact that the resist is made thinner positively. Alternatively, a resist that can be applied only to the lower part of the step may be used. A resist may be applied to the upper part of the step, but it is preferable that the resist on the upper part of the step has a thickness enough to be removed in the developing step.

The exposure step is not limited to KrF excimer laser light, but may be any method that exposes a resist such as i-ray, electron beam, X-ray, ArF excimer laser light or EUV (ultra-ultraviolet) light. For development, NMD
The developer is not limited to the -W developer, but may be any organic solvent or the like that can develop the exposed resist.

As for the overlap exposure method, in addition to the method in which the exposure mask itself is enlarged in advance,
There are methods such as a method of increasing the exposure amount and a method of scanning exposure (exposure that moves the stage at the time of exposure).

In the first, third, and sixth embodiments, the resist is patterned using an exposure mask after the step of aggressively thinning the resist. The state where the resist is left, for example, FIG.
It is also possible to use the resist in the state (b) as a resist pattern for ion implantation or etching.

Further, the entire surface of the positive resist thinned by the above-described technique for positively thinning is exposed with a small exposure amount, so that the side wall of the resist is formed on the side wall of the step as shown in FIG. Can be formed.
Hereinafter, description will be made with reference to FIG. 4 of the third embodiment as necessary.

As in the process of the third embodiment, FIG.
4A, a positive resist 801 is applied evenly to the underlayer 800 having a step, and is positively thinned to surely expose the upper part of the step (see FIGS. 4A and 4B). Thereafter, the entire surface exposure without an exposure mask or the exposure of a desired region is performed with a minimum exposure amount necessary for exposing the positive resist 801 to light. Then, the positive resist 80 near the side wall of the step is formed.
No. 1 is hardly exposed because the light for exposure is absorbed by the side wall.
Next, when the positive resist is developed, a side wall 801 of a thin resist of about 0.03 μm is formed on the side wall of the step as shown in FIG.

Further, the side wall 80 of the above resist is used.
1 can be formed by adjusting the amount of exposure or the temperature and time of PEB (post-exposure bake). In addition, use an underlayer that depends on the underlayer for the resist, use a resist that is easily dependent on the underlayer, use light with a different wavelength length for exposure, or use a solution immersed in The thickness of the resist sidewall can be adjusted by changing the concentration of the solution.

Further, the entire surface of the negative resist thinned by the above-described technique for positively thinning is exposed with a small exposure amount, thereby forming the resist pattern 901 between the side wall of the step and the resist pattern 901 as shown in FIG. A gap 902 can be formed therebetween. Hereinafter, description will be made with reference to FIG. 2 of Embodiment 1 as necessary.

As in the first embodiment, FIG.
A negative resist 901 is applied flat to the underlayer 900 having a step shown in FIG. 4A, and is actively thinned to surely expose the upper portion of the step (see FIGS. 2A and 2B). Thereafter, the entire surface exposure without an exposure mask or the exposure of a desired region is performed with the minimum exposure amount necessary for exposing the negative resist 901 to light. Then, the negative resist near the side wall of the step becomes
Since the exposure light is absorbed by the side walls, it is difficult to be exposed. next,
When the negative type resist is developed, as shown in FIG.
A narrow gap 902 of about 03 μm is formed.

The gap between the side wall of the step and the resist pattern 901 can be adjusted by adjusting the exposure amount or the temperature and time of PEB (post exposure bake). In addition, use of an underlayer that is dependent on the underlayer of the resist, use of a resist that is easily subject to underlayer dependence,
To adjust the width of the gap between the side wall of the step and the resist pattern by using light with different wavelengths in the exposure, or by changing the time of immersion in the developer or the concentration of the developer. Can be.

(Embodiment 7) In this embodiment 7, a wiring pattern of a semiconductor device is formed by using the above-mentioned technique for positively reducing the thickness of a resist.

First, as shown in FIG. 16A, a silicon oxide film 1 as a first insulating film is formed on a semiconductor substrate 1401.
402 is deposited by a chemical vapor deposition method (CVD method), and aluminum serving as a first wiring is deposited by a sputtering method of about 400 nm. Next, after patterning the aluminum by a well-known lithography technique to obtain a first wiring 1403, a silicon oxide film 1404 as a second insulating film is deposited to a thickness of about 100 nm by a CVD method. Is deposited to a thickness of about 200 nm by sputtering.

In the seventh embodiment, the first wiring 140
The pattern of No. 3 is the first wiring 1403 with the minimum wiring pitch.
Are dense and the first wiring 1403 has a size of 100 μm.
There is an area that does not exist more than m at all.

Next, a low-viscosity chemically amplified negative resist TDUR-N908 4.5 cp was applied in order to apply the resist evenly without being affected by steps due to the first wiring 1403.
(Manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied at a low rotation speed of about 2000 rpm. Thereafter, the resist was prebaked (baked after coating) at 110 ° C. for 90 seconds. afterwards,
Using a developing solution, as shown in FIG.
406 was positively thinned until the upper part of the underlying step was exposed.

Next, after exposing the resist 1406 using a predetermined mask, the resist 1406 is subjected to a normal developing process, as shown in FIG.
7 was formed.

Next, the second wiring 1405 was dry-etched using the resist pattern 1407 as a mask, thereby forming a desired wiring pattern 1408 as shown in FIG. 17D.

In the seventh embodiment, in the region of the first wiring 1403 formed at the minimum wiring pitch, the first wiring
The second wiring 1408 can be formed in a self-aligned manner with good controllability between the wirings 1403. This means that the wiring density can be increased beyond the limit of the lithography technology. In addition, since a desired wiring pattern can be obtained even in a region where the first wiring 1403 does not exist, the degree of freedom in design is dramatically improved.

In the seventh embodiment, the first wiring 140
Although aluminum was used for the third and second wirings 1408, the invention is not limited to this. For example, a semiconductor material typified by silicon or silicon germanium, a metal material such as tungsten, titanium, titanium nitride, copper, gold, or aluminum may be used.
Alternatively, a composite film of a semiconductor material and a metal material may be used.

(Embodiment 8) This embodiment 8 corresponds to FIG.
As shown in FIGS. 8, 19 and 20, M having a stacked diffusion layer type source / drain region as an example of a semiconductor device
This is a method for manufacturing an OSFET.

First, as shown in FIG. 18A, an element isolation region 1502 and an active region 1503 are formed on a semiconductor substrate 1501 or a well region (not shown) provided in the semiconductor substrate 1501 by a known method. , A gate insulating film 1504 and a gate electrode 1505 are formed.
A silicon oxide film 1506 and a gate electrode side wall insulating film 1507 were formed on the substrate 05. Here, the gate electrode 1
505 is made of a polycrystalline silicon film, and the gate electrode side wall insulating film 1507 is made of a laminated film of a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 18B, after a polycrystalline silicon film 1508 is deposited on the entire surface to a thickness of about 100 nm, a resist is applied to the polycrystalline silicon film 1508 on the gate electrode 1505 as in the first embodiment. Was applied flat so as to cover completely. Thereafter, the resist was positively thinned by a development process to obtain a thin resist 1509 shown in FIG.

Next, the resist 1509 is so formed that the thin resist 1509 is left only on the source / drain regions.
After exposing using the mask 509 as a mask, the resist pattern 15 shown in FIG.
10 was obtained.

Here, the steps from FIG. 18B to FIG. 18C will be described in more detail with reference to FIGS. FIG. 21 is a plan view of the state of FIG. 18B, and FIG.
FIG. 19 is a plan view of the state shown in FIG. As shown in FIG.
Is patterned.

In this state, if the polycrystalline silicon film 15
When 08 is processed, the polycrystalline silicon film 1508 also remains on the element isolation region 1502, and the source and drain on both sides thereof are directly connected through the polycrystalline silicon film 1508. In order to avoid this, a resist pattern 1510 slightly wider than the active region 1503 is formed as shown in FIGS. 18C and 22 to form a source / drain region as shown in FIG. Only the pattern 1511 of the polycrystalline silicon film can be formed.

As shown in FIG. 19D, the gate electrode 15
After removing the polycrystalline silicon film 1508 on the upper portion of the semiconductor device 05 by dry etching, a method of applying a new resist to remove unnecessary polycrystalline silicon films other than the source / drain regions may be considered. As compared with the eighth embodiment, it is necessary to add many steps, which is not preferable. According to the eighth embodiment, a desired stacked silicon film can be formed in the source / drain region with good controllability and self-alignment by a simple process as described later.

Next, the polycrystalline silicon film 1508 is
The area other than the area covered by the resist pattern 1510 is removed by chemical dry etching, and FIG.
As shown in FIG. 19, a polycrystalline silicon film 1511 was formed only at the portions that would be the source / drain regions.

Next, as shown in FIGS. 19D and 19E, the silicon oxide film 1506 on the gate electrode 1505 is formed.
After the removal of the impurity, a blunt substance was implanted into the polycrystalline silicon film 1511 in order to form the source / drain region 1521. In the eighth embodiment, the gate electrode 150
5 and the doping of the source / drain region 1521 is performed simultaneously. Further, the thickness of the polycrystalline silicon film of gate electrode 1505 in the eighth embodiment is from 150 nm to 250 nm. For this reason, ion implantation is performed by changing phosphorus ions from 10 keV to 8 keV for n-channel transistors.
1 × 10 ¹⁵ to 1 × 10 ¹⁶ / c with energy of about 0 keV
The injection was performed at a dose of about m ² . As for the p-channel transistor, boron ions are implanted at an energy of about 10 keV to 30 keV and at a dose of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ / cm ² . Next, a heat treatment at a temperature of about 800 ° C. to 950 ° C. for about 10 to 120 minutes, or a heat treatment at a temperature of about 950 ° C. to 1100 ° C. for 10 seconds to 6 minutes
By performing a rapid heating process for about 0 seconds, the implanted impurities were activated and diffused to the silicon substrate.

Next, as shown in FIG. 19F, a refractory metal silicide film 1512 is selectively formed on the source / drain region 1521 and the gate electrode 1505 by a well-known salicide process. Membrane 15
13 were deposited. In the eighth embodiment, titanium is used as the high melting point metal. However, the present invention is not limited to this, and cobalt, nickel, platinum, or the like may be used as another high melting point metal.

Next, as shown in FIG. 20, a contact hole 1514 was opened at a desired position in the interlayer insulating film 1513, an upper wiring 1515 was formed, and a stacked diffusion type MOSFET could be formed. .

The semiconductor device formed in the eighth embodiment has a stacked source / source structure near gate electrode 1505.
No facets occur in the drain diffusion layer. Therefore,
Even if the gate length is small and the device is miniaturized, the short channel effect can be suppressed. Also, since the process temperature is lower than in the conventional example, there is no occurrence of junction leak due to thermal stress or the like. In addition, the accumulated source
Since the drain diffusion layer overlaps with the element isolation region 1502, the width of the stacked source / drain diffusion layers can be wider than the source / drain active regions. Therefore, the source
The margin and the degree of freedom in forming the contact 1514 in the drain region 1521 can be increased. Even if the contact 1514 is formed so as to partially overlap the element isolation region 1502, the contact resistance does not increase because the installation area of the contact 1514 with respect to the source / drain stacked diffusion layer does not decrease.

(Embodiment 9) This embodiment 9 is similar to FIG.
As shown in FIGS. 3 and 24, a MOSF having a stacked diffusion layer type source / drain region as an example of a semiconductor device
This is a method for manufacturing ET.

First, as shown in FIG. 23A, an element isolation region 1602 and a gate insulating film are formed on a semiconductor substrate 1601 or a well region (not shown) provided in the semiconductor substrate 1601 by a known method. 1603 and gate electrode 16
04, and a silicon oxide film 1605 and a gate electrode side wall insulating film 1606 were formed on the gate electrode 1604. Here, the gate electrode 1604 is made of a polycrystalline silicon film, and the gate electrode side wall insulating film 1606 is made of a laminated film of a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 23 (b), after depositing an amorphous silicon film 1607 on the entire surface to a thickness of about 10 nm to 50 nm, a resist pattern 1608 was formed in the same manner as in the first embodiment. Next, the amorphous silicon film 1
Regions other than the region covered by the resist pattern 1608 of FIG.
As shown in (c), an amorphous silicon film 1609 was formed only at the portions that would be the source / drain regions.

Next, after removing the silicon oxide film 1605 on the gate electrode 1604, as shown in FIG. 24D, a salicide film is formed on the source / drain region and the gate electrode 1604 by a well-known salicide process. 16
10 was formed. In this step, titanium was used as the high melting point metal material.

The film thickness of the amorphous silicon film 1609 is
The film thickness is set so that it reacts with titanium and completely disappears.
Therefore, the amorphous silicon film 1609 in the source / drain regions has completely reacted with titanium and turned into a titanium silicide film 1610.

Next, as shown in FIG. 24E, impurities (ions) were implanted into the titanium silicide film 1610 to form the source / drain regions. Also in the ninth embodiment, doping of the gate electrode 1604 and the source / drain regions is performed simultaneously. In the ninth embodiment, the titanium silicide film 1
The film thickness of 610 is 20 to 70 nm. Therefore, ion implantation, for the n-channel transistor, 1 × 10 ¹⁵ to neighboring ions from 10keV at an energy of about 50keV
The implantation was performed at a dose of about 1 × 10 ¹⁶ / cm ² . For p-channel transistors, boron ions are
From 1 × 10 ¹⁵ to 1 × 10 with energy of about 20 keV
^The implantation was performed at a dose of about ¹⁶ / cm ² . Next, 800 ° C
Heat treatment at a temperature of about 900 ° C. to about 10 minutes to 120 minutes, or a rapid heat treatment at a temperature of about 950 ° C. to 1050 ° C. for about 10 seconds to 60 seconds to activate the implanted impurities, The source / drain active region 1611 was formed by diffusing the titanium silicide film 1610 into the silicon substrate 1601. Next, an interlayer insulating film 1612 was deposited on the entire surface by a known method.

In the ninth embodiment, titanium is used as the high melting point metal material. However, the present invention is not limited to this, and other high melting point metals such as cobalt, nickel, and platinum may be used.

Next, as shown in FIG. 24F, a contact hole 1613 was opened at a desired position in the interlayer insulating film 1612, and an upper wiring 1614 was formed. Thus, a MOSFET having a desired stacked diffusion layer type source / drain region could be formed.

The MOSFE formed in the ninth embodiment
T causes no facet in the stacked source / drain diffusion layers 1610 near the gate electrode 1604. Therefore, the short channel effect can be suppressed even when the gate length is reduced and the element is miniaturized. Also, since the process temperature is lower than in the conventional example, there is no occurrence of junction leak due to thermal stress or the like. Further, the stacked source / drain diffusion layers 1610 are separated from the element isolation region 1.
602 can overlap.
That is, the stacked source / drain diffusion layers 1610 can be formed wider than the source / drain active regions 1611. Therefore, the margin and the degree of freedom when forming the contact 1613 on the source / drain region can be increased. Even if the contact 1613 is formed so as to overlap with the element isolation region 1602, the contact resistance does not increase because the installation area of the contact 1613 with respect to the source / drain stacked diffusion layer 1610 does not decrease.

Further, the M formed in Embodiment 9
The OSFET has, in addition to the effect of the eighth embodiment,
Since the titanium silicide film 1610 is formed before the impurity implantation for forming the drain diffusion layer is performed, the advantages of the titanium silicide film 1610 having low resistance and excellent heat resistance can be used. In addition, since the low-resistance titanium silicide film 1610 is very close to the channel region, a parasitic resistance is reduced and a MOSFET having high driving force can be formed.

By using the manufacturing methods of the first to sixth embodiments, not only MOSFETs but also various semiconductor devices such as TFTs and diodes can be manufactured. In this case, since there is no misalignment, it is not necessary to provide a large alignment margin, so that the semiconductor device can be miniaturized and the semiconductor device can be manufactured by a stable process.

Using this semiconductor device, a portable terminal having a stable function can be obtained.

(Embodiment 10) Embodiment 10
This is a resist coating apparatus that can be suitably used in the first to ninth embodiments.

In the conventional resist coating apparatus, the thickness of the film after the application of the resist is controlled by discharging the purchased resist as it is onto the wafer and changing the rotation speed of the subsequent wafer. I have.

However, in the above-mentioned conventional resist coating apparatus, there is a limit to increasing the number of rotations in order to apply a thinner resist film, while reducing the number of rotations of the wafer requires a film. There was a limit because the thickness could not be evenly applied. Hereinafter, the control refers to control for applying a thicker or thinner resist film.

Therefore, in the resist coating apparatus according to the tenth embodiment, means for changing the temperature of the resist, the wafer, and the coater cup and the amount of the solvent in the resist are changed in order to control the thickness of the resist. Means for optimizing the viscosity of the resist and controlling the thickness of the resist.

That is, this resist coating apparatus is provided with a means for heating the resist to increase the temperature between the resist supply source and the tip of the nozzle from which the resist is discharged. It has means for raising. In addition, this resist coating device heats or cools the wafer during the movement from the plate to the coater cup so that the wafer can be heated or cooled with a plate or the like and then moved to the coater cup while maintaining the temperature of the wafer. An air conditioner that can be used is provided so that the viscosity when the resist is applied to the wafer can be changed.

With the above configuration, the control of the film thickness after the application of the resist is performed by adjusting the number of rotations of the wafer after the discharge of the resist, and by the function of the above means, even if the same resist and the same viscosity as the conventional resist are used. The thickness of the resist can be controlled more widely than before. In addition, depending on the resist, the film thickness can be controlled more widely by applying with a means having only a function of cooling or a means having both functions of heating and cooling.

Further, in order to change the mixing ratio between the solute and the solvent in the resist solution, the resist coating apparatus adds the resist solvent to the resist solution from the source of the resist to the tip of the nozzle from which the resist is discharged. Is added to change the amount of the solvent, so that the viscosity of the resist can be changed. The means for changing the amount of the solvent discharges the resist solution after mixing the resist solution before discharge and the resist solvent in a buffer tank.

In the modified resist coating apparatus, the coater cup is provided with a nozzle for discharging a resist solution and a nozzle for discharging a resist solvent. As a result, the resist solution and the resist solvent can be mixed on the wafer, the viscosity of the resist can be arbitrarily controlled, and the thickness of the resist can be arbitrarily controlled. Furthermore, before discharging the resist solution onto the wafer, the resist solvent is discharged onto the wafer, and the entire surface of the wafer is pre-treated with the resist solvent, so that the resist coating property on the wafer (the resist is evenly spread over the wafer surface) The spread of the resist (applicability) can be improved by improving the degree of application, and the thickness of the resist can be controlled to be thin. Further, even if the discharge amount of the resist is suppressed, the resist can be uniformly applied.

According to this resist coating apparatus, the thickness of the resist is controlled by controlling the number of revolutions of the wafer after discharging the resist solution and by functioning the means for changing the mixing ratio between the solute and the solvent of the resist. As a result, the thickness of the resist can be arbitrarily controlled more widely than before even if the same resist is used and the same viscosity is used. In addition, it is not necessary to connect a plurality of systems for a plurality of resists having different viscosities to the resist coating apparatus, so that the cost can be reduced in terms of material management. Further, by adding a solvent to the resist solution, the amount of the resist solution used can be suppressed. For this reason, not only by suppressing the discharge amount of the resist solution but also by preparing a high-viscosity resist in advance, the consumption of the resist can be significantly reduced, and the cost can be reduced.

Further, the resist coating apparatus of the modified example has one or more of the resist temperature, the wafer temperature, the coater cup temperature, the mixing ratio of the solute and the solvent in the resist solution, and the rotational speed of the wafer. And change. For this reason, the control width of the resist film thickness can be made larger than before. Further, when a solvent is added to the resist solution, the consumption of the resist can be greatly reduced, and the cost can be reduced.

On the other hand, in EUV lithography, electron beam lithography, F2 laser lithography, ArF excimer laser lithography, etc.
A resist thickness of 0 nm is required. In gate processing that requires the finest processing, a resist film thickness of 50 nm to 400 nm is required. In the ion implantation, 100
A resist film thickness of 0 nm to 5000 nm is required. Therefore, the above-described resist coating apparatus is effective.

In the above resist coating apparatus, since heating or cooling can be performed even with a coater cup, the temperature of the wafer on the plate can be controlled with the coater cup. further,
By equipping the coater cup with HMDS processing and a function to return the temperature of the wafer to the temperature of the atmosphere,
It is possible to perform a series of processes of the resist coating device only with the coater cup. Furthermore, in a resist coating apparatus for mass production, by providing several such coater cups, even if one of them has a trouble, it can be processed by another coater cup, and as a whole the resist coating apparatus , Processing is not impossible.

When the resist of the first to ninth embodiments is applied using such a resist coating apparatus, better control of the film thickness can be obtained, and the surface of the resist can be made flat.
Further, by using the resist coating apparatus for applications other than the method of manufacturing a semiconductor device according to the present invention, it is possible to reduce the consumption of the resist and reduce the cost.

Further, the resist coating device is provided with a film thickness measuring means and a calculation control means.

In this case, first, after the resist is applied to the wafer by the coater cup, the wafer is transferred to a unit having a film thickness measuring means, and the resist film thickness of the wafer is measured. The film thickness measuring means measures the film thickness by an optical interference method, and does not use light having a wavelength sensitive to the resist. That is, the light used is the light from which the resist is exposed. For example, in the case of measuring the thickness of a resist for KrF excimer laser exposure, a wavelength of 350 nm or less is not used. Then, the resist is not exposed.

Next, the calculation control means comprises, for example, a microcomputer, and compares the resist film thickness value measured by the film thickness measurement means with a previously input film thickness value. If it is within the determined range, the process is continued. If it is out of the determined range, an alarm is sounded, an error is displayed, and the process is stopped. Alternatively, even if the measured resist film thickness value is out of the predetermined range, the process is continued, but a function for displaying which wafer is abnormal later may be provided.

When the measured value of the resist film thickness deviates from the set range, the calculation control means calculates the following equation (1).
The correction is performed by

The number of rotations × the square of (film thickness) = constant value (1) The above-mentioned constant value is obtained from the measured film thickness value of the resist and the number of rotations of the wafer. By applying the desired resist film thickness value to the above equation (1), calculating the wafer rotation speed from the desired resist film thickness value, and automatically changing the actual rotation speed of the wafer, The film thickness is automatically controlled. This facilitates the control of the resist film thickness, and can suppress the variation in the resist film thickness between wafers. In addition, it has a function to calculate the number of rotations of the wafer to apply the resist based on data such as the viscosity of the resist input in advance, so that the film thickness of the resist falls within a predetermined range. It also has a function to automatically enter. Therefore, the resist can always be applied with a stable film thickness. Therefore, more stable and somographic images can be obtained.

Also, the variation in the thickness of the resist in one wafer surface is determined by comparing the measured thickness of the resist with the upper and lower thresholds of the thickness previously input. If it is within the set range, the process is continued. If it is outside the set range, an alarm is sounded, an error is displayed, and the process is stopped. Or
Although the processing proceeds, a function of displaying which wafer is abnormal later may be provided. In addition, it has a function to calculate at what resist temperature coating will improve uniformity based on data such as viscosity of the resist input in advance. Is provided within a predetermined range. For this reason, it can always be applied with a stable film thickness. Therefore, a stable and uniform resist can be applied to the wafer, and more stable lithography can be performed.

Also, regarding the position of the nozzle for discharging the resist, the size of the wafer is checked with a laser, and a function is provided so that the nozzle is located at the center of the wafer, thereby improving the uniformity of the resist film thickness. Let me. This makes it possible to more stably apply a resist having a uniform thickness and to perform more stable lithography.

Further, as data, constituent films of the underlying substrate,
A function is provided for inputting a laminated film, an exposure wavelength, a refractive index, an absorbance, and the like, and calculating a film thickness and a film thickness of a resist at a certain wavelength and a certain base to obtain the sensitivity. That is, PROLITH (manufactured by Finle) or Depict
It has a function to correct simulation data obtained by using (TMA) based on actual experimental results. Further, a function for displaying a sensitivity curve of the resist is provided. Thus, by simply inputting the film thickness into the resist coating device, control can be performed instantaneously so as to obtain a desired film thickness, and the resist can be coated.

(Embodiment 11) Embodiment 11
This is a resist developing device that can be suitably used in the first to ninth embodiments.

In the conventional resist developing apparatus, the purchased developing solution is sprayed on the wafer without dilution,
The resist has been developed by changing the subsequent development time.

However, the conventional resist developing apparatus described above has a limit in developing various types of resist with good controllability. Here, the control refers to control for suppressing the occurrence of the remaining development or the reduction of the resist pattern due to insufficient development or excessive development.

Therefore, the resist developing apparatus according to the eleventh embodiment is provided with means for changing the temperature of the developing solution, the wafer and the developing cup, and means for changing the concentration of the developing solution in order to control the development. Change the rate of development. Thereby, the development rate is optimized and the development is controlled.

More specifically, this resist developing apparatus
Means are provided for cooling the developing solution to lower the temperature between the supply source of the developing solution and the tip of the nozzle from which the developing solution is discharged, and further include means for lowering the temperature inside the coater cup. In addition, this resist developing apparatus has an air conditioning means that can adjust the temperature during the movement from the plate to the developing cup so that the wafer can be cooled by a plate or the like and then moved to the developing cup while maintaining the temperature of the wafer. Is provided. Therefore, the temperature of the developer when the developer is applied to the wafer can be changed.

According to the above-described structure, the development is controlled by adjusting the time for immersing the wafer in the developing solution, and by using the function of the above-mentioned means, even if the same developing solution is used and the same concentration is obtained. It can be performed widely for resist.

Incidentally, depending on the resist or the developing solution,
The film thickness of the resist can be controlled more broadly by using a means for heating the developing solution or a means capable of performing both heating and cooling to perform the development.

Further, in order to adjust the concentration of the developing solution between the supply source of the developing solution and the tip of the nozzle, there is provided a means for adding pure water to the developing solution to change the concentration of the developing solution. ing. By this means, the developing solution before discharging is mixed with pure water in a buffer tank, and then the developing solution is discharged.

Further, the developing cup may be provided with a nozzle for discharging a developing solution and a nozzle for discharging pure water. In this case, pure water and the developer can be mixed on the wafer, and the concentration of the developer can be arbitrarily controlled. Also, before discharging the developer onto the wafer, pure water is discharged onto the wafer,
Pretreat the entire surface of the wafer with resist with pure water,
It is possible to improve the spread (coating property) of the developer with respect to the resist. In this case, the resist can be uniformly developed even if the discharge amount of the developing solution is suppressed. In addition, for a small amount of the developing solution, within the developing time, blowing, ultrasonic waves, or vertical or horizontal vibrations are adjusted and applied, and by controlling the number of rotations of the wafer, development is performed with higher accuracy. Can be controlled.

As described above, by changing the mixing ratio between the developer and pure water, the control of the developing process can be arbitrarily performed with high accuracy and widely. Further, it is not necessary to connect a plurality of developers having different concentrations, and the cost can be reduced from the viewpoint of material management. Further, since pure water is added to the developing solution, a high-concentration developing solution is prepared in advance, so that the consumption of the developing solution itself can be greatly reduced, and the cost can be reduced.

For example, when a 23.8% aqueous solution of tetraammonium hydroxide is used as a developer,
By preparing a 23.8% aqueous solution of tetraammonium hydroxide as a stock solution and diluting it to 1/10 before use, the amount of developer used can be reduced to 1/10. In this case, the purchase cost of the developer is determined by the amount regardless of the concentration, and the cost of pure water is negligible compared to the cost of the developer. Therefore, the cost of the developer can be reduced to about 1/10. . Further, since the capacity of the developer storage tank can be reduced to 1/10, it is very effective from the viewpoint of installation space.

In the above resist developing apparatus, the temperature of the developing solution, the wafer and the developing cup, and the concentration of the developing solution are changed. Can be larger than

In EUV (ultra-ultraviolet) lithography, electron beam lithography, F2 laser lithography, ArF excimer laser lithography, KrF excimer laser lithography, i-line lithography, etc., resist materials have changed depending on the exposure wavelength. Has developed a resist material that is compatible with the developer conventionally used from the viewpoint of following the process. However, as described above, by using a resist developing device that can arbitrarily select the concentration of the developing solution, it becomes possible to arbitrarily select the concentration of the developing solution that maximizes the performance of the resist material. For this reason, while improving the performance of the resist, the development cost of the resist material can be reduced,
The material cost of the resist can be reduced.

Further, since the resist developing device can be heated or cooled even with a developing cup, the temperature control of the wafer performed by the plate can be performed by the developing cup. further,
By equipping the coater cup with a function of returning the temperature of the wafer to the temperature of the atmosphere and a function of exposing the periphery of the wafer, it is possible to perform a series of processes of the resist developing device using only the developing cup.

When the resist of the first to ninth embodiments is developed using the resist developing apparatus as described above, the consumption of the developing solution can be greatly reduced, and the cost can be reduced.

Further, in addition to the means for changing the concentration of the developing solution, the measuring means for measuring the concentration of the developing solution at the discharge nozzle portion of the developing solution by the electric resistance of the developing solution, By providing control means for controlling the concentration of the developer based on the measurement result, the concentration of the developer can be strictly controlled to the set concentration. The means for changing the concentration of the developer is provided as a functional unit in a buffer tank for mixing the developer and pure water. The measuring means measures the electric conductivity of the developer,
Calculate and output the concentration of the developer. At this time, since the ionization constant of the solute of the developing solution with respect to water changes depending on the temperature, it is necessary to measure the electric conductivity of the developing solution at a constant temperature. Therefore, this resist developing device is provided with means for controlling the temperature of the developing solution. Based on the output of the measuring means, if the concentration of the developing solution is lower than the set value, the control means causes the undiluted solution to be added to the developing solution to increase the concentration, while if the concentration of the developing solution is high, the developing solution Control is performed so as to lower the concentration by adding pure water. By using a resist developing apparatus having such a developing solution management system, development can be performed at a constant developing solution concentration, and the process margin of the developing process is widened.

Further, since the concentration of the developing solution to be purchased can be relaxed, it is possible to purchase the developing solution at low cost. Furthermore, if only the solute of the developer is purchased and the solute is mixed with pure water to adjust the developer, the process can be performed at lower cost.

In the developing step, that is, in the step of immersing the wafer with the resist in the developing solution, the resist developing device has an EPD (end point detection) function, a function capable of performing over-etching, and a function for calculating the concentration of the developing solution. Then, the function of controlling the concentration of the developer is activated.

When developing the resist with a developing cup,
The PD function checks the etching state of the resist, calculates the optimal time for immersing the resist in the developing solution from the concentration of the fixed developing solution, and immerses the resist in the developing solution. For this reason, it is possible to prevent the resist remaining after the development and the reduction of the resist pattern due to excessive immersion in the developing solution. In addition, a range of time for EPD (endpoint detection) is determined in advance, and when EPD (endpoint detection) cannot be performed within the time range, an alarm sounds, an error is displayed, and processing is performed. Is stopped. Alternatively, a function may be provided for displaying which wafer has an abnormality after the development process proceeds. By doing this,
Stable development of resist can be performed.

Also, EPD (end point detection) includes
If a pad for measurement is placed in any part of the pattern, EPD can be performed more accurately. The pad size of 50 μm square is sufficient. Further, the space for EPD measurement may be a portion where the resist at the edge of the wafer is not patterned.

In addition to developing the resist, a measuring means for measuring the thickness of the resist while immersing the resist in a developing solution when thinning the resist is provided. In this case, simply by inputting the target film thickness of the resist to be thinned to the resist developing device, based on the output of the measuring means,
The resist can be automatically made thinner with better controllability.

Regarding the concentration of the developing solution, even when the concentration of the developing solution is changed, when developing the resist,
With the PD function, it is possible to check the etching state of the resist, calculate the optimum time for immersing the resist in the developer from the concentration of the developer, and immerse the resist in the developer. In addition, when the concentration of the developer is changed, a function capable of displaying an etching rate when the resist is etched with the developer having the changed concentration is provided, and a developer having a more optimal concentration is selected and developed. be able to. Therefore, stable development of the resist can be performed. In addition, the developer has a function of measuring the concentration using an electric resistance. This makes it easier to prevent the resist from remaining after development and the reduction of the resist pattern due to excessive immersion in the developing solution. Further, when the concentration of the developing solution is measured using an electric resistance at the nozzle portion immediately before the discharging of the developing solution, the concentration of the developing solution immediately before the discharging can be detected and the concentration of the developing solution can be controlled with higher accuracy. In addition, it is easy to confirm the correct value of the concentration of the developer discharged next.

The measured density of the developing solution is compared with a preset threshold value of the density, and if the measured density is within a predetermined range, the developing process is continued. If it deviates, an alarm sounds, an error is displayed, and the process is stopped. Alternatively, the development process proceeds,
A function for displaying which wafer is abnormal later may be provided. This enables more strict control of the concentration of the developer.

Further, the EPD (end point detection) function, the mixing function of the developer and pure water, the function of measuring the concentration of the developer, and the output of these functions and the past experimental data are used. Calculating the developing time of the developing solution or the concentration of the developing solution. This makes it possible to determine the concentration of the developer by fixing the time for immersing the resist in the developer, or to determine the time for immersing the resist in the developer by fixing the concentration of the developer. For this reason, it is possible to achieve an increase in the throughput in the developing step and a reduction in material costs using a low-concentration developer. Further, since the resist pattern after development and the reduction of the resist pattern due to excessive immersion in the developing solution can be prevented, a great effect is exhibited in developing a finer resist pattern.

A function of calculating an etching rate by inputting, as data, the type of resist polymer, the type of developer, the concentration of developer, the temperature of pre-bake (bake after coating), the temperature of developer, etc. Have.
For example, it has a function of correcting simulation data such as an etching rate obtained using PROLITH (manufactured by Finle) or Depict (manufactured by TMA) based on actual experimental results. Thereby, the relationship between the developing time and the concentration of the developing solution can be instantaneously known.

[0229]

As is clear from the above, according to the present invention, after the step of flatly applying a resist on a stepped base, the thickness of the resist is made positively smaller than that immediately after the application. Since the process is provided, the resist pattern can be reliably formed in a self-aligned manner only on the lower portion of the step without considering the influence of the alignment deviation. Also,
By forming a resist pattern that does not run over the step and reducing the height of the resist pattern, deformation and collapse of the resist pattern can be prevented. In particular, since the resist pattern can be stuck not only to the bottom surface of the concave portion of the base but also to the side wall of the step, deformation and collapse of the resist pattern can be prevented. Further, since it is not necessary to provide an alignment margin for the underlying pattern, the semiconductor device can be miniaturized.

Further, according to the present invention, after the step of flatly applying the resist to the stepped base, the step of positively reducing the thickness of the resist immediately after the application is provided. Can be prevented. further,
After the resist is applied flat on the stepped base, the resist having a flat surface is thinned, so that when the resist is thinned to the upper part of the step, a resist pattern having a sufficient film thickness can be left at the lower part of the step. . Therefore, the durability of the resist pattern against etching can be improved. Further, a resist pattern can be formed even in a large area under the step.

In one embodiment of the present invention, the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist is performed between the step of applying the resist and the step of exposing. Therefore, the resist can be made thinner than the film thickness immediately after the application with good controllability. Further, since the step of positively thinning the resist is performed before the step of developing the resist, the resist can be developed with good controllability, and the undeveloped portion and the pattern reduction can be suppressed.

In one embodiment of the present invention, the step of positively reducing the thickness of the resist immediately after coating is described in the following.
Since it is performed between the step of exposing and the step of developing, exposure can be performed with good controllability similarly to ordinary photolithography, and the line width of the pattern can be stabilized. In addition, the process of actively thinning the resist,
Since the development is performed before the step of developing the resist, the development can be performed with good controllability, and the undeveloped portion and the reduction of the pattern can be suppressed.

Further, in one embodiment of the present invention, the step of positively reducing the thickness of the resist immediately after coating is described as follows.
Because it is performed after the step of developing the resist, it has good controllability,
The resist can be exposed. Further, since the resist is positively thinned after the formation of the resist pattern is confirmed, an abnormality of the resist pattern can be found at an early stage.

In one embodiment of the present invention, a region where the resist thickness is to be positively reduced is exposed and developed to positively reduce the resist thickness in that region. The apparatus used in the developing step can be used without using the device, and the manufacturing method of this embodiment can be realized without making new capital investment. further,
In this embodiment, since the processing is limited to the processing in the area where the photolithography process is performed, the problem of dust due to transportation or the like is solved. Further, this developing step includes:
Since a commonly used developing solution can be used, there is no need to prepare a new developing solution, and no additional cost is generated for this embodiment.

Further, in one embodiment of the present invention, since the resist applied flat on the stepped base is positively thinned by wet etching, damage to the resist can be suppressed to a low level. . Furthermore, by using a developer for wet etching, processing can be performed in an area where photolithography is performed, and problems such as dust adhesion can be suppressed.
Further, since this embodiment can be carried out using a normal developing device, there is an advantage that it is not necessary to make a new capital investment.

In one embodiment of the present invention, the first wiring, which is a step formed at the minimum pitch in advance, is formed in a concave portion between the first wirings, a resist pattern formed in the concave portion is formed. To form the second wiring,
The second wiring can be formed in a self-aligned manner with good controllability. Therefore, the density of wiring can be increased beyond the limit of the lithography technology. In addition, since a desired second wiring pattern can be obtained even in a region where the first wiring does not exist, the degree of freedom in design is dramatically improved.

In one embodiment of the present invention, after the step of applying a resist flat on a base having a step, the flat resist is subjected to overlap exposure for exposing a region reaching the upper part of the step. Even if the deviation occurs, it is possible to surely expose even the side wall portion of the step. Therefore, the resist can be patterned only in the lower part of the step in a self-aligned manner. At this time, since the resist pattern adheres not only to the bottom surface of the step (the bottom surface of the concave portion) but also to the side wall of the step, deformation and collapse of the resist pattern can be prevented. Further, since it is not necessary to provide an alignment margin for the underlying pattern, the semiconductor device can be miniaturized.

In one embodiment of the transistor,
Since the source / drain stacked diffusion layers without facets are formed with good controllability by the above manufacturing method, the short channel effect can be suppressed even if the gate length is shortened and the element is miniaturized. Also, since the process temperature is low, there is no occurrence of junction leak due to thermal stress or the like. Further, since the width of the stacked source / drain diffusion layers can be set freely, the margin and the degree of freedom when forming a contact on the source / drain region can be increased. Further, even if the contact is formed so as to overlap with the element isolation region, the contact area of the contact is not reduced, so that the contact resistance does not increase.

The resist coating apparatus according to one embodiment of the present invention includes means for changing the temperature of a resist, a wafer, or a coater cup, or means for changing the amount of a solvent in a resist, thereby optimizing the viscosity of the resist. Therefore, by controlling the number of rotations of the wafer after the discharge of the resist,
By using the above means, the film thickness can be controlled more widely than before even with the same resist and the same viscosity. Also,
In one embodiment, a means for cooling the resist, or
Since a means capable of both heating and cooling is provided, the film thickness can be controlled more widely. Also, according to the above embodiment,
Since there is no need to connect multiple containers or piping systems for resists with different viscosities to the resist coating device,
Cost reduction can also be achieved in terms of material management. further,
Since the solvent is added to the resist, the amount of the resist used can be reduced. Therefore, by preparing a high-viscosity resist in advance, and by suppressing the discharge amount of the resist,
The consumption of the resist can be greatly reduced, and the cost can be reduced.

Since the resist developing apparatus according to one embodiment of the present invention includes means for changing the temperature of the developing solution, the wafer and the developing cup, and means for changing the concentration of the developing solution, the wafer is immersed in the developing solution. By adjusting the time and using the above means, even with the same developing solution and the same concentration, development control can be broadened for various resists than before. Also, depending on the resist and developer,
By providing a means capable of performing both heating and cooling as well as the means for heating, the film thickness can be controlled more widely. Further, the control of the development process can be arbitrarily controlled by changing the mixing ratio of the developer and pure water,
There is no need to connect a plurality of tanks or piping systems of developer solutions having different concentrations, and the cost can be reduced in terms of material management. Further, since pure water is added to the developer, the amount of the developer used can be reduced. Therefore, by preparing a high-concentration developer in advance and suppressing the discharge amount of the developer, the consumption of the developer itself can be significantly reduced,
Reduce costs.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams illustrating a base having a step, which is used in an embodiment of the present invention, wherein FIG. 1A is a cross-sectional view and FIG.

FIG. 2 is a diagram illustrating each step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention, wherein the upper diagram is a cross-sectional view;
The lower diagram is a plan view.

FIG. 3 is a diagram illustrating each step of a method for manufacturing a semiconductor device according to a second embodiment of the present invention, wherein the upper diagram is a cross-sectional view;
The lower diagram is a plan view.

FIG. 4 is a diagram illustrating each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention, wherein the upper diagram is a cross-sectional view;
The lower diagram is a plan view.

FIG. 5 is a diagram for explaining each step of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention, wherein the upper diagram is a cross-sectional view;
The lower diagram is a plan view.

FIG. 6 is a diagram illustrating each step of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention, wherein the upper diagram is a cross-sectional view;
The lower diagram is a plan view.

FIG. 7 is a diagram for explaining each step of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention, wherein the upper diagram is a sectional view;
The lower diagram is a plan view.

FIG. 8 is a diagram for explaining each step of the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.
The lower diagram is a plan view.

FIG. 9 is a diagram for explaining each step of the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.
The lower diagram is a plan view.

FIG. 10 is a diagram illustrating an embodiment in which sidewalls are provided on side walls of a step of a base, wherein an upper diagram is a cross-sectional view and a lower diagram is a plan view.

FIG. 11 is a view for explaining an embodiment in which a gap is provided between the side wall of the step on the base and the resist pattern, wherein the upper figure is a cross-sectional view and the lower figure is a plan view.

FIG. 12 is a graph showing a relationship between an etching amount of a low-concentration developer with respect to a negative resist and time.

FIG. 13 is a graph showing the relationship between the etching rate of a low-concentration developer for a negative resist and the concentration of the developer.

FIG. 14 is a graph showing a relationship between an etching amount of a high-concentration developer with respect to a positive resist and time.

FIG. 15 is a graph showing the relationship between the etching rate of a high-concentration developer with respect to a positive resist and the concentration of the developer.

FIG. 16 is a diagram illustrating each step of the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention;

FIG. 17 is a diagram illustrating each step of the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention;

FIG. 18 is a diagram illustrating each step of a method for manufacturing a semiconductor device according to an eighth embodiment of the present invention.

FIG. 19 is a diagram illustrating each step of the method for manufacturing a semiconductor device according to the eighth embodiment.

FIG. 20 is a sectional view of the semiconductor device of the eighth embodiment.

FIG. 21 is a plan view illustrating the state of FIG.

FIG. 22 is a plan view illustrating the state of FIG.

FIG. 23 is a diagram illustrating each step of the method for manufacturing the semiconductor device according to the ninth embodiment of the present invention;

FIG. 24 is a diagram illustrating each step of the method for manufacturing a semiconductor device according to the ninth embodiment.

FIG. 25 is a diagram illustrating each step of a conventional method for manufacturing a semiconductor device.

FIG. 26 is a diagram illustrating the occurrence of a defect in the conventional method of manufacturing a semiconductor device.

FIG. 27 is a diagram illustrating each step of a conventional method for manufacturing a semiconductor device.

FIG. 28 is a diagram illustrating a method for manufacturing the conventional semiconductor device.

[Explanation of symbols]

101, 1401, 1501, 1601 Substrate 105, 1505, 1604 Gate electrode 201, 301, 401, 501, 601, 701 Resist 206, 307, 406, 507, 606, 707 Resist pattern 200, 300, 400, 500, 600, 700,8
00,900 Underlayer 1403,1408 Wiring

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 H01L 21/88 D 29/78 301S 301P (72) Inventor Shigeyasu Mori Abeno, Osaka City, Osaka 22-22, Nagaike-cho, Ward Sharp Corporation (72) Inventor Masayuki Nakano 22-22, Nagaikecho, Abeno-ku, Osaka, Osaka Prefecture Inside Sharp Corporation (72) Hiroshi Iwata 22, Nagaikecho, Abeno-ku, Osaka, Osaka No. 22 Inside Sharp Corporation (72) Inventor Koichiro Adachi No. 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka F-term (reference) 2H096 AA00 AA25 CA12 DA10 EA02 EA04 EA05 EA06 EA07 FA10 GA02 GA08 GA21 HA30 JA02 JA03 JA04 5F033 HH03 HH04 HH08 HH11 HH13 HH18 HH19 HH33 QQ01 QQ08 QQ11 RR04 SS11 WW04 XX03 XX15 5F040 DA10 DC01 EC01 EC07 EC13 EF01 EF10 EH0 2 EK05 FA05 FA07 FA10 FB07 FC19 5F046 AA17 JA21 JA22 LA12 LA14 LA18

Claims (14)

[Claims] A step of flatly applying a resist to a stepped base; and a step of positively reducing the thickness of the resist applied to the stepped base below the thickness immediately after the application of the resist. A method for manufacturing a semiconductor device, comprising: a step of exposing the resist; and a step of developing, wherein a resist pattern is formed below the step. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of positively reducing the film thickness of the resist is smaller than the film thickness immediately after the application of the resist. A method of manufacturing a semiconductor device, wherein the method is performed between a step of applying and a step of exposing the resist. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist includes the step of exposing the resist. And a step of developing the semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of positively reducing the thickness of the resist from the thickness immediately after the application of the resist is performed after the step of developing. A method for manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 1, wherein a region where the thickness of the resist is to be reduced is exposed and developed, and the thickness of the resist in the region is reduced. A method for manufacturing a semiconductor device, characterized by thinning. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the step of positively reducing the thickness of the resist is smaller than the thickness immediately after the application of the resist. A method for manufacturing a semiconductor device, comprising a wet etching step. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the wet etching is performed using a developing solution. 8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step of wet etching using the developing solution, when the resist to be etched is a negative resist, the concentration is one half of a standard value. Using the following tetramethylammonium hydroxide developer,
In the case of a positive resist, a method for manufacturing a semiconductor device, comprising using a tetramethylammonium hydroxide developer having a concentration of at least twice a standard value. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the step of positively reducing the thickness of the resist is smaller than the thickness immediately after the application of the resist, A method for manufacturing a semiconductor device, which is a chemical mechanical polishing step or a dry etching step. 10. The method of manufacturing a semiconductor device according to claim 1, wherein the step of exposing the resist is performed by exposing a region which is larger than the resist pattern below the step to be actually left and extends to the upper part of the step. A method for manufacturing a semiconductor device, comprising a step of performing lap exposure. 11. A transistor manufactured using the method for manufacturing a semiconductor device according to claim 1, wherein the transistor is a stacked diffusion layer type MOSFET. 12. A portable information terminal comprising the transistor according to claim 11. 13. A resist coating apparatus comprising means for supplying a solvent to a resist to change the viscosity of the resist. 14. A resist developing apparatus comprising means for changing the concentration of a developing solution by adding pure water to the developing solution.