JP2002100200A - Verifying signal generating device for semiconductor integrated circuit, verifying device for semiconductor integrated circuit provided with the same, verifying signal generating method for semiconductor integrated circuit, and verifying method for semiconductor integrated circuit having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To verify simultaneously these RAMs by a checker system for a short time by generating a verifying signal for each RAMs of which the number of columns is different, in a semiconductor integrated circuit provided with storage devices such as SRAM, DRAM, or the like of which the number of columns is different. SOLUTION: A test pattern generating device 6 generates a basic pattern rawD1 which repeats alternately a signal '0' in which value of all bits are 0 and a signal '1' in which values of all bits are 1. A clock frequency-dividing circuit 5 frequency-divides the clock signal into frequencies of double of the number of columns Cx of a RAM to be verified, and generates a 1/8 frequency-dividing signal EN1 and a 1/4 frequency dividing signal EN2 respectively corresponding to a RAM of four columns and a RAM of two columns. Exclusive OR circuits 17, 18 receives the 1/8 frequency-dividing signal EN1 or the 1/4 frequency dividing signal EN2, while receives the basic pattern rawD1. Output of these exclusive OR circuits 17, 18 are outputted respectively to the RAM of four columns and the RAM of two columns.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a verification circuit and a verification method for verifying each storage device in an LSI having a plurality of storage devices such as RAMs.

[0002]

2. Description of the Related Art First, the configuration of a storage device to be verified will be described using an SRAM as an example. First, the factors that determine the specifications of the SRAM to be verified are the number of bits,
The number of words and the number of columns will be described.

The data capacity that can be stored in one address is called the number of bits, and the data capacity that can be stored in the entire SRAM is called the number of words. In general, the number of words is larger than the number of bits, and is usually about 10 to 500 times. Therefore, when the SRAM is mounted on the LSI, the lengths in the row direction and the column direction are made as close as possible by arranging them in the row direction for each specific number of words.
Facilitates AM implementation. The unit implemented together is called the number of columns.

For example, a 3-bit 48-word 4-column S
In the RAM, as shown in FIG. 3, an area for storing 1 bit, that is, a cell (in FIG. 3, an area surrounded by a square)
Is arranged. As shown in the figure, the 1-word area at address 0 is arranged in the first row, first column, first row, fifth column, and first row, ninth column, and is arranged every four cells in the row direction. Is done.
Addresses 1 to 47 are similarly arranged. If the length and width length ratios of the cells are the same, the length ratio in the row direction and the column direction is 1: 1 when the number of columns is 4, and 1: 1 when the number of columns is 1. .

Next, a method of verifying the SRAM will be described. First, the verification method includes a checker method and a marching method. First, a verification method using the checker method will be described.

As shown in FIG. 4 (a), the initial value of all addresses is undefined when the number of bits is 8, the number of words is 1024, and the number of columns is 1 (in FIG. 4A, the undefined state of 8 bits is "xxxxxx").
The sequence of the checker method will be described using an SRAM of “xxx”). The verification procedure according to the same method is the following procedures (1) to (4).
“0101010” or “01010101” is written alternately, and the data stored in the SRAM becomes a check pattern. By performing the checker-type verification, it can be verified that cells adjacent in the row direction are realized as designed.

(1) As shown in FIG. 4B, "10101010" is written in ascending order from address 0 to 1023.

(2) As shown in FIG. 4C, data is read out from address 0 to address 1023 in ascending order, and "101" is read out.
01010 ".

(3) As shown in FIG. 4D, "01010101" is written in ascending order from address 0 to 1023.

(4) As shown in FIG. 4E, data is read in ascending order from address 0 to 1023, and "010
10101 ".

Next, a method of verifying the SRAM by the marching method will be described. A marching method sequence will be described with reference to the SRAM shown in FIG. The verification procedure by the marching method is as follows (1) to (6), and "11111111" is used in ascending or descending order of addresses.
Since “1” or “00000000” is written,
It looks as if ones or zeros are marching through the data storage area in the RAM. By performing the marching method verification, it can be verified that cells adjacent in the column direction are realized as designed.

(1) As shown in FIG. 5A, "00000000" is written in ascending order from address 0 to 1023.

(2) As shown in FIG. 5B, data is read from addresses 0 to 1023 in ascending order.
000 "and then" 111111 "
11 "is written.

(3) As shown in FIG. 5C, data is read out from address 1023 to 0 in descending order and "1111" is read out.
1111 "and then" 00000
000 ”is written.

(4) As shown in FIG. 5D, "11111111" is written in ascending order from address 0 to 1023.

(5) As shown in FIG. 5 (e), data is read from address 0 to 1023 in ascending order, and "1111" is read.
1111 "and then" 00000
000 ”is written.

(6) As shown in FIG. 5 (f), data is read from address 1023 to address 0 in descending order, and "0000" is read out.
0000 "and then" 11111 "
111 ”is written.

Next, a conventional semiconductor integrated circuit verification device will be described. If there are a plurality of SRAMs inside the LSI, the LSI designer may use BIST (B
It is considered that the number of cases in which a “wilt in self test” method is selected increases. The reason is SCAN
In the method, SCAN chains are required for the number of SRAMs, and it is difficult to incorporate the SCAN chains. Therefore, the disadvantage that the verification time is increased exceeds the advantage of reducing the area without incorporating a dedicated test circuit. Therefore, the BIST method is adopted. However, even if the BIST method is used, if the SRAM has a different capacity, a plurality of verification vectors are required, and thus a problem that the circuit area and the verification time increase is expected. . These problems are caused, for example, in the technique disclosed in Japanese Patent Publication No. 7-70240, by controlling a SRAM having a small address space using a decode circuit for a write enable signal.
Solved. Hereinafter, the circuit configuration and operation of the above publication will be described with reference to FIG.

FIG. 6 shows a circuit configuration for verifying an SRAM 1 having three bits, six words and two columns and an SRAM 2 having three bits, 16 words and 4 columns. When the write enable signal NWE is 1, the SRAM1 and the SRAM2 output the read data from the terminal DO at the rise of the clock CKI, and the signal NWE becomes 0.
In this case, the input data is written through the terminal DI at the rising edge of the clock CKI. In the circuit of FIG. 6, reference numeral 50 denotes an LSI input port to which a verification start signal is input, and reference numeral 51 denotes a BIST circuit, which starts operation in response to the verification start signal. The BIST circuit 51 is an SRAM
1 and data for verifying the SRAM 2 by the marching method are output from the terminal DO, and the address AD is changed to the SRA.
It outputs the write enable signal NWEO to the SRAM 2 and the decode circuit 52, and outputs the verification result to the LSI output port 53 after the completion of the verification. Reference numeral 52 denotes a decoding circuit which outputs a write enable signal NWE to S
Output to RAM1. Also, in FIG.
01, 102, 103, 104, 105, 106 are SR
Six selectors 200, 2 and 2 arranged immediately before AM1
01, 202, 203, 204, 205, 206, 20
Reference numeral 7 denotes seven selectors disposed immediately before the SRAM 2. These selectors are used for input during normal operation and SRAM.
1. Switching between input from the BIST circuit 51 at the time of testing the SRAM 2.

The two SRAMs 1 and 2 overlap from address 0 to address 5 and have an address of 10 words.
The capacity of the RAM 1 is small. Therefore, when the address output from the terminal AD of the BIST circuit 51 is 6 or more,
When the address AD generated by the ST circuit 51 exceeds the address area of the SRAM 1, writing is prohibited by the decode circuit 52 to prevent access to the SRAM 1 that is not included in verification by the marching method. FIG. 7A shows the internal configuration of the decoding circuit 52 and its truth table.
And (b).

As described above, in the conventional circuit configuration, even when a plurality of SRAMs exist and each SRAM has a difference in the number of words, verification by the marching method can be performed with a short verification time and a circuit area. It is possible.

[0022]

However, it has been found that the conventional circuit configuration has a drawback that verification by the checker method cannot be partially realized. Hereinafter, this disadvantage will be described.

In the conventional circuit of FIG. 6, when the verification sequence (a) of the checker method is performed for the SRAM 1, the data output from the terminal DO of the BIST circuit 51 is "111", "000", " 00
0 "," 111 "," 111 ", and" 000 ". Here, the cell arrangement of the SRAM1 and the SRAM2 is as shown in FIGS. However, data is stored in the data area of the SRAM 2 as shown in FIG. 10, and the first column is not “1010101010110” but “1001”.
10011001 ”, the checker method cannot be verified (x indicates an undefined state). On the other hand, when the same sequence (a) is performed on the SRAM 2,
The data output from the terminal DO of the BIST circuit 51 is “111”, “000”, “111”, “00”
0 ”,“ 000 ”,“ 111 ”,“ 000 ”,“ 11 ”
1 "," 111 "," 000 "," 111 "," 00 "
0 ”,“ 000 ”,“ 111 ”,“ 000 ”,“ 11 ”
1 ". However, when the output AD of the BIST circuit is 6 or more, the decoding circuit 52 inhibits the write operation.
Data is stored in the data area of AM1 as shown in FIG. 11, and verification becomes impossible.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to provide a verification circuit and a verification method for a semiconductor integrated circuit having storage devices such as SRAMs and DRAMs having different numbers of columns. It is to verify well in a short time by the method.

[0025]

In order to achieve the above object, in the present invention, a verification signal for each storage device is generated individually for each type of storage device having a different number of columns.

Specifically, the verification signal generating apparatus for a semiconductor integrated circuit according to the first aspect of the present invention verifies each of the storage devices of the semiconductor integrated circuit having a plurality of storage devices having different numbers of columns (Cx). Signal generating device for generating a basic pattern, receiving the basic pattern, and inverting the basic pattern for each column number (Cx) for each storage device having a different number of columns, Pattern inverting means for outputting each inverted signal as a verification signal to the corresponding storage device.

According to a second aspect of the present invention, there is provided a verification signal generating apparatus for a semiconductor integrated circuit according to the present invention, wherein each of the storage devices of the semiconductor integrated circuit includes a plurality of storage devices having different numbers of columns Cx (Cx is an even number). A verification signal generator for verifying by a checker method, wherein all bits are “0” having a value of 0
Pattern generating means for generating a basic pattern that alternately repeats a signal and a “1” signal having a value of 1; and receiving the basic pattern, inverting the basic pattern for each column number for each of the storage devices having the different column numbers. Pattern inverting means for outputting each inverted signal as a verification signal to the corresponding storage device.

According to a third aspect of the present invention, in the semiconductor integrated circuit verification signal generating apparatus according to the first aspect,
The pattern inverting means includes a frequency dividing circuit for dividing the clock signal by twice the number of columns (Cx) for each of the different numbers of columns (Cx), and a basic pattern of the pattern generating means and the frequency dividing circuit. And a plurality of exclusive OR circuits to which one of the divided signals is input.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit verifying device comprising the semiconductor integrated circuit verifying signal generating device according to the second or third aspect and writing and reading for each storage device. An address generation circuit that generates and outputs an address; a write enable signal generation circuit that generates and outputs a write enable signal for each of the storage devices; and a verification signal that is written to and read from each of the storage devices. Receiving, as expected values, an inverting circuit for inverting the verification signal from each storage device for each column number (Cx) of the storage device, and a basic pattern of a pattern generation means provided in the verification signal generation device. Each inverted signal is received from the inverting circuit, and each inverted signal is compared with the expected value. It is characterized by comprising an expected value comparing circuit for obtaining a verification result of over method.

Further, the invention according to claim 5 is characterized in that m (2 ≦ m) LSI built-in RAMs classified into n (2 ≦ n) groups for each column number (Cx) (2 ≦ Cx). A verification device for a semiconductor integrated circuit for performing verification, wherein the test pattern generation device generates a signal serving as a basis of a test pattern for each clock;
A clock frequency dividing device that divides the frequency by two times, a signal serving as a basis of the test pattern, and x for each of the n groups that receives the frequency-divided signal divided by the clock frequency dividing device.
Receiving the outputs of the exclusive OR devices (1 ≦ x ≦ n) and the exclusive OR device for each of the n groups, the RA of the same number of columns belonging to the group for each of the n groups
M, an output port for each of n groups, an output port provided for each of the RAMs, a plurality of input ports to which the output data of each RAM are input, and each of the frequency dividers divided by the clock frequency divider. Y (1 ≦ y ≦ m) delay devices for each RAM for delaying the peripheral signal, and y exclusive devices for each RAM that receive output data of each RAM from the input port and output of the delay device A logical sum device, a delay device for delaying a signal based on the test pattern to generate an expected value, an expected value of the delay device, and y for each RAM.
Receiving the output of the exclusive OR device, comparing and verifying each output with the expected value, and generating an expected value comparing device for outputting the verification result to an output port, and write and read addresses for the RAMs An address generation circuit for outputting each address to an output port to each RAM;
A write enable signal generating circuit for generating a write enable signal for each of the RAMs and outputting the write enable signal to an output port to the RAM; and a verification start signal, The clock divider, the expected value comparator,
And an input port for outputting to the address generation device and the write enable signal generation device.

Further, in the semiconductor integrated circuit verification signal generation method according to the present invention, each storage device of the semiconductor integrated circuit having a plurality of storage devices having different numbers of columns (Cx) is verified by a checker method. And generating a basic pattern in which all bits alternately alternate between a “0” signal having a value of 0 and a “1” signal having a value of 1;
Next, the basic pattern is inverted for each column number (Cx) for each storage device having a different number of columns, and each inverted signal is output to the corresponding storage device as a verification signal.

According to a seventh aspect of the present invention, in the method of generating a verification signal for a semiconductor integrated circuit according to the sixth aspect, when inverting the basic pattern for each column number (Cx), a clock signal is first used. Is divided into twice the number of columns (Cx) for each of the different numbers of columns (Cx),
Thereafter, the divided signals are input to exclusive OR circuits of the respective storage devices, and the basic patterns are input to the respective exclusive OR circuits, and the outputs of the respective exclusive OR circuits are output. A signal is obtained as the inverted signal.

In addition, a semiconductor integrated circuit verification method according to the present invention includes a method for generating a verification signal for a semiconductor integrated circuit according to the present invention. Each of the verification signals is input, and the verification signal from each of the storage devices is inverted for each column number (Cx) of the storage device. Thereafter, the basic pattern is received as an expected value, and the inverted signals are received. Then, each of the inverted signals is compared with the expected value, and a check result of the checker method of each of the storage devices is obtained based on the coincidence and the disagreement.

Further, according to the semiconductor integrated circuit verification method of the present invention, m (2 ≦ m) groups are classified into n (2 ≦ n) groups for each column number (Cx) (2 ≦ Cx). ) L
A verification method of a semiconductor integrated circuit for verifying a RAM with a built-in SI, wherein a signal serving as a basis of a test pattern for each clock is generated, and a clock is generated based on each column number (Cx)
A plurality of frequency-divided signals are generated by dividing the frequency by a factor of two, and an exclusive OR of the signal as a basis of the generated test pattern and each of the frequency-divided signals is obtained. Is input to each of the y (1 ≦ y ≦ m) RAMs, and then the output signal from each of the y RAMs and the divided signal are divided by 1
The exclusive OR of the signal delayed by the clock is calculated, and the result of each exclusive OR is compared with the expected value signal obtained by delaying the signal serving as the basis of the test pattern by one clock, to verify each RAM. It is characterized by performing.

According to the above, claims 1, 2, 3, 6 and 7
In the semiconductor integrated circuit verification signal generation device and the generation method according to the described invention, since the verification signals are generated for the storage devices having different numbers of columns, even if the plurality of built-in storage devices have different numbers of columns, These storage devices can be simultaneously and satisfactorily verified in a short time.

Further, in the semiconductor integrated circuit verification device and the verification method according to the present invention, the data in which the verification signal has been written to each storage device is read and thereafter the number of columns is increased. Is repeated at the point in time when the number equal to the number is read out. Then, a series of data subjected to the inversion processing is an expected value (basic pattern).
Therefore, it is possible to satisfactorily verify each storage device.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of a semiconductor memory device verification apparatus according to the present invention. In this embodiment, first, second, and third RAMs are provided as storage devices provided inside the LSI, and the first RAM has eight bits and one word.
6, the number of columns is 4, the second RAM has 8 bits, 16 words, and 2 columns, and the third RAM has 6 bits, 6 words, and 2 columns.
The case where the checker method is verified for M will be described. The RAM may be an SRAM or a DRAM. The present invention is applicable not only to the case where the storage device is provided inside the LSI, but also to the case where the storage device is arranged outside the LSI.

In the figure, reference numeral 6 denotes a test pattern generation device (pattern generation means) which generates a test pattern (basic pattern) rawDI as a basis of a verification signal. As shown in FIG. 2, the test pattern rawDI is a signal that repeats a “0” signal in which all 8 bits have a value of 0 and a “1” signal in which all 8 bits have a value of 1 for each clock signal CKI.

5 is a clock frequency dividing device (frequency dividing circuit)
And divides the frequency of the clock signal CKI. This frequency division is performed because the first RAM with built-in LSI has four columns and the second and third RAMs have two columns.
x is doubled, that is, divided by 8 and divided by 4. The eight-frequency-divided signal is indicated by a frequency-divided signal EN1 in FIG. 2, and the four-frequency-divided signal is indicated by a frequency-divided signal EN2 in FIG. Exclusive OR circuits 17 and 18 receive the test pattern rawDI from the test pattern generator 6. Further, one of the exclusive OR circuits 17 receives the divide-by-8 signal EN1 of the clock frequency divider 5 and the other exclusive OR circuit 18 receives the divide-by-4 signal of the clock frequency divider 5. Signal EN2 is input. One exclusive OR circuit 17
Is output to an output port 19 (DI1), and the output of the other exclusive OR circuit 18 is output to an output port 20 (DI1).
2) Output to 2, 21 (DI3). Therefore, as shown in FIG. 2, the output signal of the output port 19 (DI1) (that is, the output signal of the one exclusive OR circuit 17) is a signal (inverted signal) obtained by inverting the test pattern rawDI every four clocks. ) And output port 20 (DI2) 2,
The output signal of 21 (DI3) (that is, the output signal of the other exclusive OR circuit 18) is a signal (inverted signal) obtained by inverting the test pattern rawDI every two clocks.
The inverted signal from the output port 19 (DI1) is input as a verification signal to a first RAM (not shown) having four columns, and the inverted signal from the output port 20 (DI2) is
A second RAM having two columns (not shown) as a verification signal
And the inverted signal from the output port 21 (DI3) is input as a verification signal to a third RAM (not shown) having two columns. The clock inverting device 5 and the two exclusive OR circuits 17 and 18 constitute the pattern inverting means 30 of the first aspect.

An address generation device (address generation circuit) 15 outputs the address of the first RAM to the first RAM through the output port 23 (AD1), and outputs the address of the second RAM to the output port. The data is output to the second RAM through the output port 24 (AD2), and the address of the third RAM is output to the third RAM through the output port 25 (AD3). Reference numeral 16 denotes a write enable signal generation device (write enable signal generation circuit) which outputs a write enable signal of the first RAM to the first RAM through the output port 26 (NWE1), and outputs a write enable signal of the second RAM. Is output to the second RAM through the output port 27 (NWE2), and the write enable signal of the third RAM is output to the third RAM through the output port 28 (NWE3).

In addition, reference numerals 10, 11, and 12 denote exclusive OR circuits (second inverting circuits), respectively. The exclusive OR circuit 10 receives the data (verification signal) written and read from the first RAM via the input port 2 (DO1). Similarly, the data read from the second RAM is input to the input port 3 (DO) in the exclusive OR circuit 11.
2), and the exclusive OR circuit 12 receives the data read from the third RAM in the input port 4 (DO).
Input via 3). Further, the exclusive OR circuit 1
0, the divide-by-8 signal EN1 of the clock frequency divider 5 is input via the delay circuit 7 (FFO1) with a delay of one clock, and the other two exclusive OR circuits 11 and 12 receive the above-mentioned signals. The divide-by-4 signal EN2 of the clock divider 5 is input with a delay of one clock via the delay circuits 8 (FFO2) and 9 (FFO3). Therefore, the output signals cnvDO1, cnv of these three exclusive OR circuits 10, 11, 12
DO2 and cnvDO3 are, as shown in FIG. 2, a first RAM having four columns, a second RAM having two columns,
The verification signal read from the third RAM having two columns is inverted for each column and becomes a signal returned to the test pattern of the test pattern generator 6.

In FIG. 1, reference numeral 14 denotes an expected value comparing device (expected value comparing circuit). This expected value comparison device 14
The test pattern rawDI of the test pattern generation device 6 is input via the delay circuit 13 (FFI) with a delay of one clock, and the delayed test pattern rawD
Let I be the expected value. The output signals cnvDO1, cnvDO2, and cnvDO3 of the three exclusive OR circuits 10, 11, and 12 are input to the expected value comparison device 14, and these output signals are respectively converted to the expected value rawDI.
As a result of the comparison, "1" is output from the output port 22 (RESULT) as "success" if they match and "0" as failure if they do not match.

Further, reference numeral 1 denotes an input port to which a verification start signal START is input, and this input port 1
T is output to the test pattern generator 6, the clock divider 5, the expected value comparator 14, the address generator 15, and the byte enable signal generator 16.

Next, the operation when the checker system is verified using the semiconductor integrated circuit verification circuit of the present embodiment will be described with reference to the timing chart of FIG.

At time 2, verification start signal START
Changes from LO to HI, and the test pattern rawDI of the checker method is output from the test pattern generation device 6 between time 3 and time 34. The test pattern rawDI is input to the expected value comparing device 14 as the expected value expDO for verification with a delay of one clock through the delay circuit 13.

Next, a verification procedure for each RAM will be described. For the first RAM having 8 bits, 16 words, and 4 columns, in order to write data (checker pattern) to addresses 0 to 15 from time 3 to time 18, the write enable signal NWE1 is set to LO, and AD1 is incremented in the order of 0 to 15, and at the same time, the exclusive OR of each bit of the test pattern rawDI and the divide-by-8 signal EN1 is calculated by the exclusive OR circuit 17.
To generate an inverted signal DI1 obtained by inverting the test pattern rawDI every four clocks.
Is written to the first RAM as a verification signal, and the check pattern is stored.

Subsequently, from time 19 to time 34, in order to read the written test pattern (verification signal), the write enable signal NWE1 is set to HI, the address AD1 is incremented in the order of 0 to 15, and The exclusive-OR circuit 10 performs an exclusive-OR operation on each bit of the data DO1 read from the RAM and the eight-frequency-divided signal EN1 delayed by one clock to obtain the data DO1 from the first RAM. Is generated every four clocks to generate an inverted signal cnvDI1 and output it to the expected value comparing device 14. The expected value comparing device 14 compares the expected value expDO with the inverted signal cnvDO1 from time 20 to time 35 and verifies it (confirmed to be equal in FIG. 2).

In the second RAM having 8 bits, 16 words, and 2 columns, the write enable signal NWE2 is set to LO in order to write a checker pattern to addresses 0 to 15 from time 3 to time 18, and At the same time as incrementing the address AD2 in the order of 0 to 15, the exclusive OR circuit 18 takes the exclusive OR of each bit of the test pattern rawDI and the divide-by-4 signal EN2, and inverts the test pattern rawDI every two clocks. The inverted signal DI2 is generated, and the inverted signal DI2 is written to the second RAM as a verification signal (checker pattern).

Next, from time 19 to time 34, in order to read the written test pattern, the write enable signal NWE2 is set to HI, and the address AD2 is set to 0.
To 15 and simultaneously with the second RA
The exclusive OR circuit 11 takes the exclusive OR of each bit of the data DO2 read from the M and the divide-by-4 signal delayed by one clock, and converts the read data DO2 from the second RAM into 2 bits. Inverted signal cnv inverted every clock
DI2 is generated and output to the expected value comparison device 14. In the expected value comparison device 14, the expected value e
xpDO is compared with the inverted signal cnvDO2 and verified (confirmed to be equal in the figure).

Further, in the third RAM having 6 bits, 6 words, and 2 columns, the write enable signal NWE2 is set to LO in order to write the checker pattern to addresses 0 to 5 at times 3 to 8, and At the same time as incrementing the address AD3 in the order of 0 to 5, each bit of the test pattern rawDI and the divide-by-4 signal EN2
The exclusive OR circuit 18 takes an exclusive OR with the exclusive OR circuit 18 to generate an inverted signal DI3 obtained by inverting the test pattern rawDI every two clocks, and uses the inverted signal D32 as a verification signal (checker pattern) in the third RAM. Write to.

Next, from time 19 to 24, in order to read the written test pattern, the write enable signal NWE2 is set to HI, and the address AD3 is set to 0.
At the same time as incrementing in the order of
The exclusive OR circuit 12 takes the exclusive OR of each bit of the data DO3 read from the third bit and the divided-by-4 signal delayed by one clock, and outputs the data DO3 read from the third RAM for two clocks. Inverted signal cnvD inverted every time
I3 is generated and output to the expected value comparison device 14. In the expected value comparison device 14, the expected value e
xpDO is compared with the inverted signal cnvDO1 and verified (confirmed to be equal in the figure).

In the timing chart of FIG.
Since the output value of the second and third RAMs is equal to the expected value, at time 36, the output port 22 (RESUL
The HI pulse is output from T), and the verification of these RAMs is completed.

[0054]

As described above, claims 1 and 2,
According to the verification signal generation device and the generation method for a semiconductor integrated circuit according to the invention described in 3, 6, and 7, since the verification signals are generated for storage devices having different numbers of columns, each storage device has a different number of columns. Also, all of the data stored in the storage devices can be checked, and the plurality of storage devices can be simultaneously and satisfactorily verified by the checker method in a short time.

Further, according to the semiconductor integrated circuit verifying apparatus and the verifying method of the present invention, the verification signals generated for the storage devices having different numbers of columns are respectively returned to the original basic patterns. Since the processing is performed and compared with the expected value (basic pattern), there is an effect that a plurality of storage devices having different numbers of columns can be satisfactorily verified.

[Brief description of the drawings]

FIG. 1 is a diagram showing an internal configuration of a semiconductor integrated circuit verification circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation description of the semiconductor integrated circuit verification circuit.

FIG. 3 is a diagram showing a cell arrangement of a 3-bit, 48-word, 4-column SRAM.

FIG. 4 is a diagram showing an SRAM verification sequence by a checker method.

FIG. 5 is a diagram showing an SRAM verification sequence by a marching method.

FIG. 6 is a diagram showing a configuration of a conventional semiconductor integrated circuit verification circuit.

FIG. 7 is a diagram showing a configuration and a truth table of a decode circuit provided in a conventional semiconductor integrated circuit verification circuit.

FIG. 8 shows an SR having three bits, six words and two columns.
It is a figure which shows the cell arrangement of AM1.

FIG. 9: S of bit number 3, word number 16 and column number 4
FIG. 3 is a diagram showing a cell arrangement of a RAM 2.

FIG. 10 is a diagram illustrating a state of data storage in the SRAM2, which indicates that verification cannot be performed simultaneously in the SRAM2 when verification of the SRAM1 is to be performed by the checker method;

FIG. 11 is a diagram showing a state of data storage in the SRAM1, which indicates that verification cannot be performed simultaneously in the SRAM1 when verifying the SRAM2 using the checker method;

[Explanation of symbols]

Reference Signs List 5 clock frequency divider (frequency divider) 6 test pattern generator (pattern generator) 10, 11, 12 exclusive OR circuit (inverter) 14 expected value comparator (expected value comparator) 15 address generator ( Address generation circuit) 16 Write enable signal generation device (Write enable signal generation circuit) 17, 18 Exclusive OR circuit 30 Pattern inversion means

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G06F 12/16 330 G01R 31/28 V B

Claims (9)

[Claims] 1. A verification signal generator for verifying each storage device of a semiconductor integrated circuit having a plurality of storage devices having different numbers of columns (Cx), wherein a pattern for generating a basic pattern (rawDI) is provided. Receiving the basic pattern (rawDI), and inverting the basic pattern (rawDI) for each column number (Cx) for each storage device having a different number of columns (Cx). And a pattern inverting means (30) for outputting the verification signal as a verification signal to the corresponding storage device. 2. A verification signal generator for verifying each storage device of a semiconductor integrated circuit having a plurality of storage devices having different numbers of columns (Cx) (Cx is an even number) by a checker method. A pattern generation means (6) for generating a basic pattern (rawDI) in which a bit is a signal of "0" having a value of 0 and a signal of "1" having a value of 1; and receiving the basic pattern (rawDI). Pattern inversion means (30) for inverting the basic pattern (rawDI) for each column number (Cx) for each storage device having a different (Cx), and outputting each inverted signal as a verification signal to the corresponding storage device; A verification signal generator for a semiconductor integrated circuit, comprising: 3. The pattern inverting means (30) transmits a clock signal (CKI) to the different number of columns (C
x) separately, a frequency dividing circuit (5) for dividing the frequency to twice the number of columns (Cx), and a basic pattern (rawD) of the pattern generating means (6).
I) and one of the frequency-divided signals divided by the frequency-dividing circuit (5).
The verification signal generation device for a semiconductor integrated circuit according to claim 2, further comprising (8). 4. An address generation circuit (15), comprising: the verification signal generation device for a semiconductor integrated circuit according to claim 2; and generating and outputting a write and read address for each storage device. A write enable signal generation circuit (16) for generating and outputting a write enable signal for each of the storage devices; receiving the verification signals written to and read from each of the storage devices; An inversion circuit (10, 11, 12) for inverting a signal for each column number (Cx) of the storage device, and a pattern generation means (6) provided in the verification signal generation device
As the expected value, receives the inverted signals from the inverting circuits (10, 11, 12), and compares each inverted signal with the expected value.
A semiconductor integrated circuit verification device comprising: an expected value comparison circuit (14) for obtaining a check result of the checker method of each of the storage devices based on the coincidence and disagreement. 5. m (2 ≦ m) Ls classified into n (2 ≦ n) groups for each column number (Cx) (2 ≦ Cx)
A verification apparatus for a semiconductor integrated circuit for verifying RAMs 1 to RAM with built-in SI, a test pattern generation apparatus (6) for generating a signal based on a test pattern for each clock; ), A clock divider (5) that divides the frequency of the test pattern by two times, a signal as a basis of the test pattern, and the n groups that receive the divided signal divided by the clock divider (5). X (1 ≦ x ≦ n) exclusive OR devices (17, 18) for each of the n exclusive OR devices (17, 1) for each of the n groups
8) an output port (19, 20, 21) for each of n groups for receiving the output of 8) and outputting the same to the same number of columns of RAM belonging to the group for each of the n groups; A plurality of input ports (2, 3, 4) to which output data of each RAM is input, and y number of each RAM for delaying each frequency-divided signal divided by the clock frequency divider (5) (1 ≦ y ≦ m) delay devices (7, 8, 9); output data of each RAM from the input ports (2, 3, 4) and outputs of the delay devices (7, 8, 9) Receiving exclusive-OR devices for each RAM (10, 11, 12)
A delay device (13) for delaying a signal serving as a basis of the test pattern to generate an expected value; an expected value of the delay device (13); and y exclusive OR devices for each RAM ( 10, 11 and 12), and compares and verifies each output with the expected value, and outputs the verification result to an output port (22).
4) and an address generation circuit (1) for generating addresses for writing and reading to and from the RAMs and outputting the addresses to output ports (23, 24 and 25) to the RAMs.
5) generating a write enable signal for each of the RAMs, and outputting each of the write enable signals to an output port (2
6, 27, and 28) and a verification start signal (START) are input. The verification start signal is supplied to the test pattern generation device (6) and the clock frequency divider (5). ), An input port (1) for outputting to the expected value comparison device (14), the address generation device (15), and the write enable signal generation device (16). apparatus. 6. A method of generating a verification signal for verifying each storage device of a semiconductor integrated circuit having a plurality of storage devices having different numbers of columns (Cx) by a checker method, wherein all bits have a value of 0. To generate a basic pattern (rawDI) that alternately repeats a “0” signal of “1” and a “1” signal of a value of 1. Then, for each storage device having a different number of columns (Cx),
The above basic pattern (rawDI) is converted to the number of columns (Cx)
A verification signal generating method for a semiconductor integrated circuit, wherein the verification signal is output to the corresponding storage device as a verification signal. 7. When inverting the basic pattern (rawDI) for each column number (Cx), first, a clock signal (CKI) is divided by two of the column number (Cx) for each of the different column numbers (Cx). The frequency-divided signals (EN1, EN2) are input to exclusive OR circuits (17, 18) for the respective storage devices, and the exclusive OR circuits (17, 18). 17, 18)
7. The method according to claim 6, wherein the basic pattern (rawDI) is input to the input terminal, and an output signal of each of the exclusive OR circuits (17, 18) is obtained as the inverted signal. . 8. A method for generating a verification signal for a semiconductor integrated circuit according to claim 6, wherein said verification signals written and read to and from each of said storage devices are respectively input and read from each of said storage devices. Is inverted for each column number (Cx) of the storage device, and thereafter, the basic pattern (rawDI) is received as an expected value, and the inverted signals (cnvDO1, cnvDO) are received.
vDO2, cnvDO3), comparing each of the inverted signals with the expected value, and obtaining a check result of the checker method of each of the storage devices based on the coincidence or disagreement. 9. m (2 ≦ m) Ls classified into n (2 ≦ n) groups for each column number (Cx) (2 ≦ Cx)
A verification method for a semiconductor integrated circuit for verifying a RAM with built-in SI to RAMm, wherein a signal serving as a basis of a test pattern for each clock is generated, and a clock is divided into twice the number of columns (Cx). To generate a plurality of frequency-divided signals, perform an exclusive OR operation on the signal serving as the basis of the generated test pattern and each of the frequency-divided signals, and calculate the result of each exclusive OR operation in the y (1 ≦ 1) y ≦ m), and exclusive-ORs the output signal from each of the y RAMs with a signal obtained by delaying the frequency-divided signal by one clock. A method for verifying a semiconductor integrated circuit, comprising comparing a result of the sum with an expected value signal obtained by delaying a signal serving as a basis of the test pattern by one clock, and verifying each RAM.