JP2002098987A - Liquid crystal display device and application equipment of liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device, capable of coping with the deformation of a circuit substrate, which is generated by being linked with the high resolution of the display device and with the large screen of the device, by absorbing deformation of the substrate due to heat at the time of manufacturing a liquid crystal module. SOLUTION: In the liquid crystal display device includes a liquid crystal panel 1, plural source driver ICs supplying signals to signal lines, a gate driver IC supplying signals to scanning lines and a liquid crystal display control circuit controlling the source driver ICs and the gate drive IC, the source driver ICs are mounted on k sets (k is a natural number >=2) of source driver substrates 3, and these k sets of the source driver substrates 3 are arranged along the long-side direction of the liquid crystal panel 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and its application equipment.

[0002]

2. Description of the Related Art A display method of a conventional liquid crystal display device is shown in FIG.
This will be described with reference to FIG. FIG. 18 is a view showing a conventional liquid crystal display device. In FIG. 18, 201 is a liquid crystal panel,
202 is a display control board, 203 is a signal line electrode drive circuit board or a source driver board (hereinafter described as a source driver board), and 204 is a scan line electrode drive circuit board or a gate driver board (hereinafter described as a gate driver board). ) And 205 are means for connecting the source driver IC and the liquid crystal panel, 206 is means for connecting the gate driver IC and the liquid crystal panel, 207 is a connection cable between the source driver board and the display control board, and 208 is a connection between the gate driver board and the display control board Cable. FIG. 19 is a diagram showing a main configuration of a display control board portion of a conventional liquid crystal display device. In FIG. 19, 211 is an input terminal, 212 is a display control means, and 213 is an output terminal. FIG. 20 is a diagram showing a panel and a source driver substrate of a conventional liquid crystal display device. In FIG. 20, 221 is a liquid crystal panel, and 222 is a source driver substrate. The source driver board 222 is constituted by one sheet.

[0003]

In recent years, there has been remarkable progress in increasing the resolution of displays. When color displays began to spread, the resolution was VGA (Video Grade).
The display was 640 pixels (horizontal) and 480 lines (phics Array). This is called SVGA (Super VGA), which has 800 horizontal pixels and 600 vertical pixels, and XGA (Exten VGA).
Dedicated Graphics Architecture), which has 1024 horizontal pixels and 768 vertical lines, and is called SXGA (Super XGA), which has 1280 horizontal pixels and 1024 vertical lines, and UXGA (Ultra
XGA), 1600 horizontal pixels, 1200 vertical lines,
It is referred to as HDTV (High Definition Television), which has 1920 horizontal pixels, 1080 vertical lines, and QXGA (Q
uadruple XGA), 2048 horizontal pixels, 153 vertical pixels
Up to six resolutions have appeared. FIG. 21 shows examples of these resolutions. In FIG. 21, 231 is a VGA, 23
2 is SVGA, 233 is XGA, 234 is SXGA, 2
35 is UXGA, 236 is HDTV, 237 is QXGA
Is shown. Furthermore, high-resolution ones, resolutions in which the flatness ratio of 4: 3 or 5: 4 is widened (widened) to 16: 9, etc., broadcasting standards (NTSC, PAL, SECAM, etc.) and computer standards of each country (Computers manufactured by International Business Machines, Sun Microsystems, Apple Computer, etc.). Such an advance in resolution increases the performance of high definition, but raises the problem of increasing the clock frequency of the drive circuit. The total number of pixels at each resolution is: Total Pixel = Horizontal Dot × Vertical Line (Equation 1) Here, Total Pixel: number of pixels, Horizontal Pixel: number of horizontal pixels, Vertical Line: number of vertical lines. Equation 1
Therefore, in VGA (640 × 480), 307,200
Pixel, 480,00 for SVGA (800 × 600)
0 pixels, 786,4 for XGA (1024 × 768)
For 32 pixels, SXGA (1280 × 1024), 1,
310,720 pixels, UXGA (1600 × 1200)
Then, 1,920,000 pixels, HDTV (1920 ×
1080), 2,073,600 pixels, QXGA
In (2048 × 1536), it is 3,145,728 pixels.

[0004] At present, even in a liquid crystal display,
As in the case of a CRT (Cathode Ray Tube) display, most of the displays are driven in consideration of a blank period, but here, for simplicity, a trial calculation is first performed excluding the blank period. Next, as a blank period, for example,
The value obtained by adding 40% is shown. This allows for about 30% of the horizontal blank period and about 10% of the vertical blank period. The following are all frame frequencies of 60H
This is the clock frequency when z is set. For each resolution given above, the resolution, clock frequency without blank period, and clock frequency with blank period are listed as follows: Frequency Without Blanking = Total Pixel x Frame (Equation 2) And Frequency With Blanking = Total Pixel x Frame × Blanking Rate (Equation 3) where Frequency Without Blanking: clock frequency without blanking period, Frequency With Blanking:
Clock frequency with blanking period, Frame: number of frames per second, Blanking Rate: coefficient of blank period (here, 1.4).

From equations (2) and (3), VGA (640 × 48
0), 18.4 MHz, 25.8 MHz, SVGA
(800 × 600), 28.8 MHz, 40.3 M
Hz, XGA (1024 × 768), 47.2 MH
z, 66.1 MHz, SXGA (1280 × 1024)
Then, 78.6 MHz, 110 MHz, UXGA (16
00 × 1200), 115 MHz, 161 MHz,
In HDTV (1920 × 1080), 124 MHz,
At 174 MHz, QXGA (2048 × 1536),
189 MHz and 264 MHz.

At the time of writing this specification, available source driver ICs have a specification of 2 pixels / clock (data of 2 pixels can be input per clock), a clock frequency of about 65 MHz, and data transfer. When converted to a rate, it is 130 MHz, but the data transmission path as it is cannot support a resolution of UXGA, QXGA or higher including a blank period.

[0007] In addition, in many cases, high resolution is not simply high definition but is accompanied by enlargement of the screen. This is because the added value is more easily understood by the consumer when the resolution is increased and the screen is enlarged than when the definition is increased with the same screen size. In this case, it is attached around the LCD panel,
There is a problem that the length of the printed circuit board becomes long. As an example, if the pixel pitch is 0.3 mm for each of the above-mentioned resolutions, the length of the source driver substrate and the length of the gate driver substrate can be roughly described as: Length of Source PCB = Horizontal Pixel Pitch × Horizontal Pixel (Equation 4) where Length of Source PCB: length of source driver board, Horizontal PixelPitch: horizontal pixel pitch, Horiz
ontal Pixel: The number of horizontal pixels. Length of Gate PCB = Vertical Pixel Pitch x Vertical Line (Equation 5) where Length of Gate PCB: length of gate driver board, Vertical Pixel Pitch: vertical pixel pitch, Vertical
Line: The number of vertical lines.

From equations 4 and 5, VGA (640 × 48
0), 192 mm and 144 mm, SVGA (8
00 × 600), 240 mm and 180 mm, X
307.2 mm and 230.4 mm for GA (1024 × 768), 384 mm and 307.2 mm for SXGA (1280 × 1024), UXGA (16
00 × 1200), 480 mm and 360 mm,
For HDTV (1920 × 1080), 576 mm and 324 mm, and for QXGA (2048 × 1536),
614.4 mm and 460.8 mm. However, this is calculated using only pixels, and there is a difference in practice.

In the above example, the SXGA, UXGA, HDT,
With a resolution of V, QXGA or higher, the length of a single substrate is long, so when connecting the liquid crystal panel and the source driver IC, the printed circuit board contracts, which may cause a defect and decrease the yield. is there. For the gate driver substrate, TCP (Tap
Since the output pin pitch and pin width of the e Carrier Package are several times wider than the source driver IC, this problem is less likely to occur than the source driver substrate. However, in the above example, care must be taken at a resolution exceeding UXGA.

In order to solve the above-mentioned conventional problems, the present invention absorbs the deformation of a substrate due to heat during the production of a liquid crystal module, and responds to the deformation of a circuit board accompanying the enlargement of the screen in conjunction with higher resolution. It is an object to provide an apparatus and its applied equipment.

(Definition of Terms) The definitions of some terms used in this specification are clarified here.

"Pixels" and "pixels" represent points, areas, and the like having all color information. "Dot" is the three primary colors of light R,
A point, area, or the like having only one of the color information G and B is represented. In the liquid crystal display device described in this specification, unless otherwise specified, a color display is described,
The “pixel” and “pixel” are a set of three “dots” of R, G, and B. For a monochrome display, "pixel", "pixel" and "dot" are synonymous. FIG. 22 shows pixels, pixels, and dots in a color display. In FIG. 22, reference numeral 241 denotes a liquid crystal panel. FIG. 22 shows an example in which the number of horizontal pixels is four and the number of vertical lines is four. A portion surrounded by a dotted line at 242a is a pixel, which is a pixel. 242A is an enlarged view of this 242a. 242A is 243, 24
4, 245 are R dots, 244 are G dots, and 245 are B dots. FIG.
3 shows pixels, pixels and dots on a black and white display. In FIG. 23, reference numeral 251 denotes a liquid crystal panel. FIG. 23 shows an example in which the number of horizontal pixels is four and the number of vertical lines is four.
Reference numeral 252a denotes a pixel, which is a pixel surrounded by a dotted line surrounded by a dotted line. 252A is an enlarged view of 252a. 243 is a single dot.

[0013] "Dot clock" and "pixel clock" are frequency units for displaying the "pixel" or "pixel". The term “dot clock” is used for a pixel unit because it is standardly used as a term of a display signal source device. In this specification, a portion that does not require special attention is described as “dot clock” or “dot clock (pixel clock)”.

[0014]

In order to solve such a problem, a liquid crystal display device according to the present invention comprises two substrates sandwiching a liquid crystal material and one of the two substrates. A plurality of pixel electrodes arranged in a matrix, a liquid crystal panel including a plurality of signal lines and scanning lines that drive the pixel electrodes and are orthogonal to each other, and a plurality of source driver ICs that supply signals to the signal lines. , A gate driver IC for supplying a signal to the scanning line, and a source driver IC
And a liquid crystal display control circuit for controlling a gate driver IC and the plurality of source driver ICs mounted on k (k is a natural number of 2 or more) source driver substrates. A source driver substrate is arranged along a long side direction of the liquid crystal panel.

In the liquid crystal display device, it is preferable that the liquid crystal panel has a high resolution of 1280 horizontal pixels and 1024 vertical lines or more.

Further, the liquid crystal display control circuit includes an input terminal, a frequency dividing means, and an output terminal, and the liquid crystal display control circuit divides the frequency of the image data input from the input terminal by n by the frequency dividing means. Division (n is 2
After performing the above natural number, it is preferable that the input image data whose frequency is divided by n be transmitted from the output terminal to k source driver boards (k is a natural number of 2 or more).

Further, the liquid crystal display control circuit includes an input terminal, a frequency dividing unit, a frequency adjusting unit, a storage unit, and an output terminal, and the liquid crystal display control circuit is configured to control input image data input from the input terminal. The frequency is divided into n (n is a natural number of 2 or more) by the frequency dividing means,
After temporarily storing the input image data in the storage unit, when transmitting the stored input image data to the k (k is a natural number of 2 or more) source driver substrates, the frequency adjustment unit sets the n-divided input image data to It is preferable that the frequency of data is adjusted to a frequency (a is a real number) and transmitted.

Next, a liquid crystal display applied device according to the present invention is characterized in that it is a liquid crystal display applied device using any one of the above liquid crystal displays.

[0019]

(Embodiment 1) A liquid crystal display device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a liquid crystal display device of the present embodiment. As shown in FIG. 1, the liquid crystal display device includes a liquid crystal panel 1, a display control board 2, a source driver board 3, a gate driver board 4, a connection means 5 between the source driver IC and the liquid crystal panel, and a connection between the gate driver IC and the liquid crystal panel. It comprises a connecting means 6, a connecting means 7 between the source driver substrate and the display control board, and a connecting means 8 between the gate driver board and the display control board. For details of the display control board 2,
This will be described with reference to FIG. FIG. 2 is a diagram showing the display control board 2 of the liquid crystal display device of the present embodiment. Display control board 2
Is composed of an input terminal 11, a frequency division unit 12, a display control unit 13, a storage unit 14, and an output terminal 15. The signal of the bus width w (bit) input at the frequency f (Hz) from the input terminal 11 is divided into n frequencies by the frequency dividing means 12, and the frequency becomes f / n (Hz).
The bus width becomes n × w (bits) and is input to the display control means 13. Thereafter, through a read / write operation to / from the storage means 14, the signals are divided and output to k output terminals 15 in order to transmit a signal to k source driver substrates.

The k output terminals 15 are sequentially output terminal 15
-1, output terminal 15-2 (omitted in the middle), output terminal 15
Call it -k.

FIG. 3 is a diagram showing another example of the display control board 2 of the liquid crystal display device according to the present embodiment. The display control board 2 includes an input terminal 21, a frequency division unit 22, a display control unit 23, a storage unit 24, an output terminal 25, and a frequency adjustment unit 26. A signal having a bus width w (bit) input at a frequency f (Hz) from the input terminal 21 is
The frequency is divided by n by the frequency dividing means 22, and the frequency is f / n (Hz) and the bus width is n × w (bits). Here, the output frequency from the display control means 23 to the storage means 24 is f / n (H
z). Thereafter, through a write / read operation to the storage means 24, the signal is divided and output to k output terminals 25 in order to transmit a signal to k source driver substrates.
Here, the frequency is adjusted by a times by the frequency adjusting means 26. First, the output frequency from the display control means 23 to the frequency adjustment means 26 is f / n. Then, as a result of the adjustment, the output frequency from the frequency adjusting unit 26 to the storage unit 24 becomes (a × f) / n (Hz), which is a times the input frequency. The image data is read out to the display control means 23 at the output frequency (a × f) / n (Hz). As a result, with respect to the output from the display control means 23 to the output terminal 25, the bus width does not change, and only the frequency becomes (a × f) / n (Hz).

The k output terminals 25 are sequentially output terminal 25
-1, output terminal 25-2 (omitted midway), output terminal 25
Call it -k.

For details of the source driver board 4,
This will be described with reference to FIG. FIG. 4 is a diagram illustrating the source driver substrate 4 of the liquid crystal display device according to the present embodiment. The source driver board 4 is divided into k pieces such as a source driver board 32-1, a source driver board 32-2 (omitted in the middle), and a source driver board 32-k.

Now, as an example, two pixels / clock (two pixels (RGB × 2) are input in one clock cycle)
Source driver I with operating frequency 65MHz (Max.)
Assuming that C is used, the transfer frequency per pixel (RGB) is 65 MHz × 2 = 130 MHz.

This is shown in FIG. 5 and FIG. FIG. 5 is a diagram illustrating a driver IC used in the present embodiment. In FIG.
41 is a source driver IC, 42 is a liquid crystal panel, and 43 is data input per operation clock. The source driver IC 41 according to the present embodiment has an
Data of two pixels, that is, data of 6 dots is input. FIG.
The frequency of the portion indicated by a in FIG. FIG. 6 is a diagram in which the operation of this driver is rewritten as the operation of one pixel. In FIG. 6, reference numeral 51 denotes a source driver I.
C and 52 are liquid crystal panels, and 53 is data input per operation clock. The source driver IC 51 shown in FIG.
Inputs data of one pixel, that is, three dots per operation clock. In FIG. 6, the frequency of the portion indicated by b is reduced to half the data amount by the conversion of the number of dots in the case of FIG. 5, so the frequency is doubled to 65 × 2 = 130.
MHz (Max.).

Next, assuming that the frame frequency of the high-resolution display with a blank period is 60 Hz, according to Equation 3, UXGA (1600 × 1200)
At 161 MHz and HDTV (1920 × 1080),
174 MHz, WUXGA (Wide-UXGA, 19
20 × 1200), 194 MHz, QXGA (20
In the case of (48 × 1536), since the frequency is 264 MHz, even if the source driver IC is connected as it is, the operation is inconvenient due to an excessive frequency. Therefore, when these clock frequencies are divided by 130 MHz and rounded up to the nearest whole number (using the ROUNDUP function), the UXGA
OUNDUP (161 ÷ 130) = 2, R for HDTV
OUNDUP (174 @ 130) = 2, ROUXUP (194 @ 130) = 2 for WUXGA, ROUNDUP (264 @ 130) = 3 for QXGA, respectively, are calculated as 2, 2, 2, and 3 respectively. It turns out that it is good to divide. Similarly, it can be easily considered that the same calculation is performed for the other resolutions, the number of divisions is obtained by Expression 6, and the source driver IC is divided. n = roundup (dclk / pclk) (Equation 6) Here, n is the number of driver IC divisions, dclk is a dot clock (or pixel clock) for display, pclk.
Is the operating frequency of the driver IC (converted per pixel).

As an example, if the resolution is UXGA (1600
A color liquid crystal display device in the case of (pixels × 1200 scanning lines) will be described. The UXGA has a resolution as shown in FIG.

When the resolution is UXGA, the number of divisions of the source driver IC becomes two by the calculation of Expression 6. At this time, the following processing is sequentially performed on the input image data signal. First, during one frame period, R (0,0) and G (0,
0), B (0,0), R (1,0), G (1,0), B
(1, 0), (omitted on the way), R (x, y), G (x,
y), B (x, y), (omitted on the way), R (1598, 1)
199), G (1598, 1199), B (1598,
1199), R (1599, 1199), G (159)
9,1199) and 5,76 of B (1599,1199)
000 dots (dots described here are R,
G and B are independent dots, not pixels), and R, G, and B dots are sequentially input as a set in synchronization with the dot clock dclk. Here, x is a horizontal pixel number starting from 0 to 1599, and y is a vertical scanning line number starting from 0 to 1199. FIG.
FIG. 4 is a diagram showing an XGA valid data signal.

When the input data is sequentially received, the input data is stored in the storage means. Now, the output number of the driver to be used is 3
Assuming 84 outputs, UXGA uses 1600 × RGB
(= 3) ÷ 384 = 12.5, so a minimum of 13 drivers are required. D0, D1, D1
2, (omitted in the middle), D12.

The source driver board is composed of two boards. One board has six source driver ICs D0, D1, (omitted in the middle), D4 and D5, and the other board has D6, D7,
(Omitted on the way), seven source driver ICs D11 and D12 are mounted. FIG. 9 is a diagram showing a form of the source driver substrate. In FIG. 9, reference numerals 81 and 82 denote source driver substrates. 81 is equipped with six source driver ICs,
Reference numeral 82 includes seven source driver ICs. 83 is a source driver IC. 84 and 85 are connectors for receiving data from the display control board.

The size of the board on which seven are mounted is about 270 mm. At the time of displaying an image, the image data is output from the storage means to the driver. At this time, R (0,0), G
(0,0), B (0,0), (omitted midway), R (12
7,0), G (127,0) and B (127,0) to D0
To R (128,0), G (128,0), B (12
8,0), (omitted on the way), R (255,0), G (25
5,0) and B (255,0) are output simultaneously to D1 with the same clock, but this clock is dclk / 2. This simultaneous output to the two drivers with the same clock is described in
Divided into individual pieces ".

Further, following the output to D0 and D1, R
(256,0), G (256,0), B (256,0)
0), (omitted on the way), R (383, 0), G (383,
0), B (383,0) to D2, R (384,0),
G (384, 0), B (384, 0), (omitted midway),
R (511, 0), G (511, 0), B (511, 0)
0) to D3 simultaneously with the same clock.

Hereinafter, similarly, D4 and D5, D6 and D7,
The image data is output from the storage means to D8 and D9 and to D10 and D11. Following output to D10 and D11, R (1536,0), G (1536,0), B (1
536, 0), (omitted on the way), R (1599, 0), G
(1599,0) and B (1599,0) are output to D12 with the same clock as described above.

FIG. 10 shows a method of outputting the above data. In FIG. 10, reference numeral 91 denotes data (part 1) output simultaneously. When the data of 91 has been output to D0 and D1, then the data of 92 (same as the second) and
The data of two driver ICs are sequentially output simultaneously with the same clock in the order of (No. 3, No. 4, 94, No. 4, No. 5, No. 5, 96, No. 6, No. 6).
Is independently output to D12.

Thus, the output for one scanning line is completed, and the process proceeds to the next scanning line. When this is repeated for 1200 scanning lines, U
This is equivalent to one frame of XGA effective image data.

The frequency and bus width at this time are considered as follows. First, the input dot clock of the image signal to the input terminal 11 is 161 MHz as described above.
The bus width at this time is 24 bits. This is divided by 2 by the frequency dividing means 12. At this point the frequency is 8
0.5 MHz. The bus width doubles to 48 bits. When the image data is temporarily stored in the storage unit 14 via the display control unit 13 and the image data is output, the image data is output to the two output terminals 15 at the same time.
Therefore, the frequency can be finally reduced to 40.25 MHz. The bus width is further doubled to 96 bits. 40.25MHz is the source driver I used
Since the clock frequency of C is lower than 65 MHz, there is no problem in operation.

The image data is output from the storage means to the source driver simultaneously with the same clock as in the above-described example. It can be easily understood that the same effect can be obtained if the operating frequency of the driver is reduced.

In the above example, the output order of the image data from the storage means is described as D0 and D1, D2 and D3, D4 and D5, D6 and D7, D8 and D9, D10 and D11, and D12. However, this order is not uniquely determined, and as another example, the output order of the image data from the storage unit is D0 and D6, D1 and D7, D2 and D8, D3 and D3.
9, D4 and D10, D5 and D11, D12,
Further, as another example, the output order of the image data from the storage means is D12 and D10, D8 and D6, D4 and D2, D0 and D11, D9 and D7, D5 and D3, D1, and other combinations. The same effect can be obtained.
D12 is unique with respect to the amount of data,
There is no problem if data is output simultaneously in combination with other drivers D0 to D11.

In the above example, the resolution of UXGA has been described. However, by performing the same processing for other resolutions, it is easy to divide the source driver IC and reduce the frequency. It can be understood.

In the above example, 384 outputs and an operating frequency of 6
5 MHz (2 pixels / clock) source driver I
Although this example uses C, even if the number of output terminals and the operating frequency are changed, the present example can be applied by recalculating each item.

If the structure of the display control board 2 includes the frequency adjusting means 26 as shown in FIG. 3, the frequency of the output signal to the output terminal 25 is adjusted to be higher than 40.25 MHz, for example, the operation of the source driver. The upper limit of the clock can be raised to about 65 MHz, and as a result, the refresh rate can be improved and the display quality can be further improved.

(Embodiment 2) A liquid crystal display device according to Embodiment 2 of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a liquid crystal display device of the present embodiment. As shown in the figure, the liquid crystal display device has a liquid crystal panel 1,
Display control board 2, source driver board 3, gate driver board 4, source driver IC-to-liquid crystal panel connection means 5, gate driver IC-to-liquid crystal panel connection means 6, source driver board-to-display control board connection means 7, gate It comprises a connecting means 8 for connecting a driver board and a display control board. Details of the display control board 2 will be described with reference to FIG.

FIG. 2 is a view showing the display control board 2 of the liquid crystal display device of the present embodiment. The display control board 2 includes an input terminal 11, a frequency division unit 12, a display control unit 13, a storage unit 14, and an output terminal 15. The signal of the bus width w (bit) input from the input terminal 11 at the frequency f (Hz) is divided into m frequencies by the frequency dividing means 12, the frequency is f / m (Hz), and the bus width is m ×
w (bit) and is input to the display control means 13.
After that, through a write / read operation to the storage means 14,
It is divided and output to k output terminals 15. The k output terminals 15 include an output terminal 15-1, an output terminal 15-2,
(Omitted in the middle), and is referred to as output terminal 15-k.

FIG. 3 is a diagram showing another example of the display control board 2 of the liquid crystal display device according to the present embodiment. The display control board 2 includes an input terminal 21, a frequency division unit 22, a display control unit 23, a storage unit 24, an output terminal 25, and a frequency adjustment unit 26. A signal having a bus width w (bits) input at a frequency f (Hz) from the input terminal 21 is divided into m frequencies by a frequency dividing means 22,
Frequency is f / m (Hz), bus width is m × w (bit)
Is input to the display control means 23. Here, the output frequency from the display control means 23 to the storage means 24 is f /
m (Hz). Thereafter, the data is divided and output to k output terminals 25 through a read / write operation to the storage means 24. Here, the frequency is adjusted to a times by the frequency adjustment means 26. First, the output frequency from the display control means 23 to the frequency adjustment means 26 is f / m. And
As a result of the adjustment, the output frequency from the frequency adjusting means 26 to the storage means 24 is (a × f) / m (H) times the input frequency.
z), and receiving the clock of this frequency, the image data is output from the storage unit 24 at the output frequency (a × f) / m (H
The data is read out to the display control means 23 in z). As a result, regarding the output from the display control means 23 to the output terminal 25,
The bus width is unchanged, and only the frequency is (a × f) / m (H
z).

The k output terminals 25 are sequentially output terminal 25
-1, output terminal 25-2,..., Output terminal 25-k.

For details of the source driver board 4,
This will be described with reference to FIG. FIG. 4 is a diagram illustrating the source driver substrate 4 of the liquid crystal display device according to the present embodiment. The source driver board 4 is divided into k pieces such as a source driver board 32-1, a source driver board 32-2 (omitted in the middle), and a source driver board 32-k.

Now, as an example, two pixels / clock (two pixels (RGB × 2) are input in one clock cycle)
Assuming that a source driver IC with an operating frequency of 65 MHz (Max.) Is used in the specification, one pixel (RG
The transfer frequency per B) is 65 MHz × 2 = 130 MH
The clock frequency with a blank period for high-resolution display is expressed by the following equation (3), where the frame frequency is 60 Hz.
Therefore, in UXGA (1600 × 1200), 161M
Hz, HDTV (1920 × 1080), 174M
Hz, WUXGA (Wide-UXGA, 1920 × 1
200), 194 MHz, QXGA (2048 × 1
In 536), since the frequency is 264 MHz, even if the source driver IC is connected as it is, there is a problem in operation due to excessive frequency. For this reason, these clock frequencies are each divided by 130 MHz and rounded up to the nearest whole number (ROU
NDUP function) and ROUND in UXGA
UP (161 ÷ 130) = 2, ROUND in HDTV
UP (174 ÷ 130) = 2, ROUX in WUXGA
DUP (194 ÷ 130) = 2, ROX in QXGA
DUP (264 ÷ 130) = 3 is calculated,
It can be seen that it is better to divide into two, two, two, and three, respectively. Similarly, it can be easily considered that the above-mentioned calculation is similarly performed for other resolutions, the number of divisions is obtained by Expression 6, and the source driver IC is divided.

As an example, if the resolution is UXGA (1600
A color liquid crystal display device in the case of (pixels × 1200 scanning lines) will be described. When the resolution is UXGA, the number of divisions of the source driver IC becomes two by the calculation of Expression 6. At this time, the following processing is sequentially performed on the input image data signal.

First, during one frame period, the input data signal is set as R (0,0), G (0,
0), B (0,0), R (1,0), G (1,0), B
(1, 0), (omitted on the way), R (x, y), G (x,
y), B (x, y), (omitted on the way), R (1598, 1)
199), G (1598, 1199), B (1598,
1199), R (1599, 1199), G (159)
9,1199) and 5,76 of B (1599,1199)
000 dots (dots described here are R,
G and B are independent dots, not pixels), and R, G, and B dots are sequentially input as a set in synchronization with the dot clock dclk. Here, x is a horizontal pixel number starting from 0 to 1599, and y is a vertical scanning line number starting from 0 to 1199.

When the input data is sequentially received, the input data is stored in the storage means. Now, the output number of the driver to be used is 3
Assuming 84 outputs, UXGA uses 1600 × RGB
(= 3) ÷ 384 = 12.5, so a minimum of 13 drivers are required. D0, D1, D1
2, (omitted in the middle), D12.

The source driver substrate is made up of a single substrate.
13 source driver ICs 0, D1, (omitted in the middle) and D12 are mounted. FIG. 11 is a diagram showing a form of the source driver substrate. In FIG. 11, reference numeral 101 denotes a source driver substrate. 102 is a source driver IC. 1
03 is a connector for receiving data from the display control board.

At the time of image display, the image data is output from the storage means to the driver. At this time, R (0,
0), G (0,0), B (0,0), (sometimes omitted), R
(127,0), G (127,0), B (127,0)
To D0, R (128,0), G (128,0), B
(128,0), (omitted midway), R (255,0), G
(255,0) and B (255,0) to D1, the same clock, but this clock is dclk /
2 and output simultaneously. This simultaneous output to two drivers with the same clock is described in "Source Driver I
C is divided into two ". Following the output to D0 and D1, R (256,0), G (25
6,0), B (256,0), (omitted midway), R (38
3,0), G (383,0) and B (383,0) to D2
To R (384,0), G (384,0), B (38
4,0), (omitted on the way), R (511, 0), G (51
1, 0) and B (511, 0) are simultaneously output to D3 with the same clock.

Hereinafter, similarly, D4 and D5, D6 and D7,
The image data is output from the storage means to D8 and D9 and to D10 and D11. Following output to D10 and D11, R (1536,0), G (1536,0), B (1
536, 0), (omitted on the way), R (1599, 0), G
(1599,0) and B (1599,0) are output to D12 with the same clock as described above.

FIG. 12 shows a method of outputting the above data. In FIG. 12, reference numeral 111 denotes data (part 1) output simultaneously. When the data of 111 has been output to D0 and D1, then the data of 112 (the same, part 2), and
113 (same, 3), 114 (same, 4), 115
(Same, No. 5), 116 (Same, No. 6) and data for two driver ICs are sequentially output simultaneously with the same clock,
Finally, the data of 117 is independently output to D12.

Thus, the output for one scanning line is completed, and the process proceeds to the next scanning line. When this is repeated for 1200 scanning lines, U
This is equivalent to one frame of XGA effective image data.

The frequency and bus width at this time are considered as follows. First, the input dot clock of the image signal to the input terminal 11 is 161 MHz as described above.
The bus width at this time is 24 bits. This is divided by 2 by the frequency dividing means 12. At this point the frequency is 8
0.5 MHz. The bus width doubles to 48 bits. When the image data is temporarily stored in the storage unit 14 via the display control unit 13 and the image data is output, the image data is output to the two output terminals 15 at the same time.
Therefore, the frequency can be finally reduced to 40.25 MHz. The bus width is further doubled to 96 bits. 40.25MHz is the source driver I used
Since the clock frequency of C is lower than 65 MHz, there is no problem in operation.

The output of image data from the storage means to the source driver is not limited to the case of simultaneous output with the same clock as in the above-described example. It can be easily understood that the same effect can be obtained if the operating frequency of the driver is reduced.

In the above example, the output order of the image data from the storage means is described as D0 and D1, D2 and D3, D4 and D5, D6 and D7, D8 and D9, D10 and D11, and D12. However, this order is not uniquely determined, and as another example, the output order of the image data from the storage unit is D0 and D6, D1 and D7, D2 and D8, D3 and D3.
9, D4 and D10, D5 and D11, D12,
Further, as another example, the output order of the image data from the storage means is D12 and D10, D8 and D6, D4 and D2, D0 and D11, D9 and D7, D5 and D3, D1, and other combinations. The same effect can be obtained.
D12 is unique with respect to the amount of data,
There is no problem if data is output simultaneously in combination with other drivers D0 to D11.

In the above example, the UXGA resolution has been described. However, by performing the same processing for other resolutions, it is easy to divide the source driver IC and reduce the frequency. It can be understood.

In the above example, 384 outputs and an operating frequency of 6
5 MHz (2 pixels / clock) source driver I
Although this example uses C, even if the number of output terminals and the operating frequency are changed, the present example can be applied by recalculating each item.

If the configuration of the display control board 2 includes the frequency adjusting means 26 as shown in FIG. 3, the frequency of the output signal to the output terminal 25 is adjusted to be higher than 40.25 MHz, for example, the operation of the source driver. The upper limit of the clock can be raised to about 65 MHz, and as a result, the refresh rate can be improved and the display quality can be further improved.

(Embodiment 3) A liquid crystal display device according to Embodiment 3 of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a liquid crystal display device of the present embodiment. As shown in the figure, the liquid crystal display device has a liquid crystal panel 1,
Display control board 2, source driver board 3, gate driver board 4, source driver IC-to-liquid crystal panel connection means 5, gate driver IC-to-liquid crystal panel connection means 6, source driver board-to-display control board connection means 7, gate It comprises a connecting means 8 for connecting a driver board and a display control board.

Now, as an example, two pixels / clock (two pixels (RGB × 2) are input in one clock cycle)
Assuming that a source driver IC with an operating frequency of 65 MHz (Max.) Is used in the specification, one pixel (RG
The transfer frequency per B) is 65 MHz × 2 = 130 MH
z, and the clock frequency with a blank period for high-resolution display is UXG when the frame frequency is 60 Hz.
A (1600 × 1200), 161 MHz, HDT
V (1920 × 1080), 174 MHz, WUX
In the case of GA (Wide-UXGA, 1920 × 1200), the frequency is 194 MHz, and in the case of QXGA (2048 × 1536), it is 264 MHz.
MHz and round up to the nearest whole number (ROUNDUP
UXGA) and ROUNDUP (1
61 ÷ 130) = 2, ROUNDUP (1
74 ÷ 130) = 2, ROUNDUP in WUXGA
(194 ÷ 130) = 2, ROUNDUP for QXGA
(264 ÷ 130) = 3, 2
It is necessary to divide into two, two, three.

Similarly, for the other resolutions, the above-described calculation is similarly performed, the number of divisions is obtained by Expression 6, and a configuration in which the source driver IC is divided can be easily considered.

As an example, if the resolution is HDTV (1920)
A case of a color liquid crystal display device having (pixels × 1080 scanning lines) will be described. HDTV is a resolution as shown in FIG. When the resolution is HDTV, the number of divisions of the source driver IC becomes two by the calculation of Expression 6.

However, in the case of HDTV, since the horizontal resolution is 1920 pixels, the total number of source driver ICs is 1920 × RGB (= 3) ÷ 384 = 15.
A scheme of three divisions can also be considered. In the case of two divisions, the same processing as in the first embodiment may be performed, and therefore, description of this example will be omitted.

At this time, for the input image data signal,
The following processing is sequentially performed. First, the input data signal is used as a valid data signal during one frame period.
(0,0), G (0,0), B (0,0), R (1,
0), G (1,0), B (1,0), (omitted midway), R
(X, y), G (x, y), B (x, y), (omitted midway), R (1918, 1079), G (1918, 10)
79), B (1918, 1079), R (1919, 1)
079), G (1919, 1079), B (1919,
1079) (dots described here are independent dots of R, G, and B, not pixels) in synchronization with the dot clock dclk,
It is assumed that R, G, and B dots are sequentially input as a set. Here, x is a horizontal pixel number starting from 0 and 1920.
And y is the vertical scanning line number, starting from 0 and up to 1080. FIG. 14 is a diagram showing a valid data signal of HDTV.

When the input data is sequentially received, the input data is stored in the storage means. Now, the number of source drivers to be used is fifteen, and the fifteen drivers are arranged in the order of D0, D1, D2,.
(Sometimes omitted), referred to as D14.

The source driver board is composed of three boards, one of which has five source driver ICs D0, D1, (not shown in the middle) and D4, and the other board has D5, D6, (not shown in the middle), D9. 5 source driver ICs, and D10, D11 (omitted in the middle), D14
The source driver ICs are mounted. FIG. 15 is a diagram showing a form of the source driver substrate. In FIG.
1 is a source driver board. Each of the three 141s has five source driver ICs mounted thereon. 142 is a source driver IC. 143 is a connector for receiving data from the display control board.

At the time of displaying an image, the image data is output from the storage means to the driver. At this time, R (0,
0), G (0,0), B (0,0), (sometimes omitted), R
(127,0), G (127,0), B (127,0)
To D0, R (128,0), G (128,0), B
(128,0), (omitted midway), R (255,0), G
(255,0), B (255,0) to D1, R (25
6,0), G (256,0), B (256,0), (omitted midway), R (383,0), G (383,0), B
(383, 0) to D2 and the same clock, but this clock is output simultaneously at dclk / 3. This simultaneous output to the three drivers with the same clock means "split the source driver IC into three". Also, following output to D0, D1, and D2, R (384,0), G (384,0),
B (384, 0), (omitted on the way), R (511, 0),
G (511,0), B (511,0) to D3, R (5
12,0), G (512,0), B (512,0),
(Omitted on the way), R (639,0), G (639,0),
B (639,0) to D4, R (640,0), G (6
40,0), B (640,0), (omitted midway), R (7
67,0), G (767,0) and B (767,0) to D
5 and are output simultaneously with the same clock.
Hereinafter, similarly, D6, D7, and D8, D9, D10, and D1
1. Image data is output from the storage means to D12, D13 and D14.

FIG. 16 shows a method of outputting the above data. In FIG. 16, reference numeral 151 denotes data (part 1) output simultaneously. When the output of the data 151 is completed to D0, D1, and D2, the data 152 (the same, No. 2) is then output to the data 153 (the third), 154 (the fourth), and 155.
(Same as No. 5) and data for three driver ICs are sequentially output at the same clock. FIG. 17 shows an example in which the data output order is changed. Data having the same reference numerals 161 to 165 are data output to the driver IC at the same time.

Thus, the output for one scanning line is completed, and the process proceeds to the next scanning line. When this is repeated for 1080 scanning lines, H
One frame of DTV effective image data.

The output of image data from the storage means to the source driver is not limited to the case of simultaneous output with the same clock as in the above example. It can be easily understood that the same effect can be obtained if the operating frequency of the driver is reduced.

In the above example, the resolution of the HDTV has been described. However, it is easily understood that by performing the same processing for the other resolutions, the source driver IC can be divided and the frequency can be reduced. it can.

In this embodiment, the HDTV (1920 × 108)
0), W-UXGA (1920 × 1
200), the number of scanning lines is from 1080 to 1200
It can be considered in the same way, considering that it has increased.

[0076]

As described above, according to the present invention,
Since data is transmitted to the source driver board divided into k (k is a natural number of 2 or more), it is possible to design to absorb the deformation due to heat of the board during the production of the liquid crystal module, and to enlarge the screen in conjunction with the higher resolution. It is possible to cope with the accompanying deformation of the circuit board.

Further, by dividing the signal data bus into n parts (n is a natural number) after the input, the frequency f becomes f / n, and the processing clock frequency can be reduced. -In development, the source driver I whose frequency performance is not sufficient for the target resolution
C can be used.

Further, the signal data is temporarily stored in the storage means, and the frequency of the input image data divided into n is converted into a frequency (a is a real number), thereby harmonizing with the driving frequency of the source driver IC. The design can be adjusted so as to output, and the capability of the source driver IC can be maximized.

Further, by using the liquid crystal display device of the present invention as an applied device of the liquid crystal display device, it is possible to obtain a high resolution and a large screen.

[Brief description of the drawings]

FIG. 1 illustrates a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a display control substrate in the liquid crystal display device according to the embodiment;

FIG. 3 is a diagram showing another example of the display control board in the liquid crystal display device according to the embodiment;

FIG. 4 is a diagram showing a source driver substrate in the liquid crystal display device according to the embodiment;

FIG. 5 is a diagram showing a driver IC used in the embodiment;

FIG. 6 shows one driver IC used in the embodiment.
Diagram rewritten to operate per pixel

FIG. 7 is a diagram showing a resolution UXGA according to the embodiment;

FIG. 8 is a diagram showing a valid data signal of UXGA according to the embodiment;

FIG. 9 is a diagram showing an example of a mode of a source driver substrate in Embodiment 1;

FIG. 10 is a diagram showing a method for outputting data to a source driver according to the first embodiment;

FIG. 11 is a diagram showing an example of a mode of a source driver substrate in Embodiment 2;

FIG. 12 is a diagram showing a method for outputting data to a source driver according to the second embodiment;

FIG. 13 is a diagram showing a resolution HDTV according to the embodiment;

FIG. 14 is a diagram showing an effective data signal of HDTV according to the embodiment;

FIG. 15 is a diagram showing an example of a mode of a source driver substrate in Embodiment 3;

FIG. 16 is a diagram showing a method for outputting data to a source driver according to the third embodiment.

FIG. 17 is a diagram showing another example of a method for outputting data to a source driver according to the third embodiment.

FIG. 18 illustrates a conventional liquid crystal display device.

FIG. 19 is a diagram showing a main configuration of a display control board portion of a conventional liquid crystal display device.

FIG. 20 is a diagram showing a panel and a source driver substrate of a conventional liquid crystal display device.

FIG. 21 is a diagram showing an example of a conventional resolution.

FIG. 22 is a diagram showing pixels, pixels, and dots of a color display;

FIG. 23 is a diagram showing pixels, pixels, and dots of a monochrome display.

[Explanation of symbols]

1,42,201,251 Liquid crystal panel 2,13,202,212 Display control board 3,23,32,81,82,141,203,222 Source driver board 4,204 Gate driver board 5,205 Connection means between source driver IC and liquid crystal panel 6,206 Connection means between gate driver IC and liquid crystal panel 7,207 Source driver Connection means between substrate and display control board 8,208 Connection means between gate driver board and display control board 11,21,211 Input terminal 12,26 Frequency division means 14,24 Storage means 15,25,213 Output terminal 22 Frequency division means 31,221 Liquid crystal panel 41,51 , 83, 101, 142 Source driver IC 43, 53 Data input per operation clock 84, 85, 103, 143 Connectors 91, 111, 151, 161 for receiving data from display control board Data output simultaneously (No. 1) 92, 112, 152, 162 Data output simultaneously (No. 2) 93, 113, 153, 163 Data output simultaneously (part 3) 94,114,154,164 Data output simultaneously (part 3) 4) 95,115,155,165 Data output simultaneously (Part 5) 96,116 Data output simultaneously (Part 6) 97,117 Data output alone 231 VGA resolution 232 SVGA resolution 233 XGA resolution 234 R dots 244 G dots 245 B dots 252 pixels , 253 pixels

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09F 9/30 338 G09F 9/30 338 5G435 9/35 9/35 9/40 9/40 C G09G 3 / 20 621 G09G 3/20 621M 623 623V 631 631Q 670 670L 3/36 3/36 F-term (reference) 2H092 GA40 GA50 GA59 JB22 NA29 2H093 NC11 ND53 5C006 AA22 AF04 BB16 BC16 BC23 CC15 FA15 5C080 AJ03 CC02 DD15 AA10 AA14 BA03 BA43 CA19 DA01 DA04 DA09 DB01 DB05 EA04 EA07 5G435 AA03 BB12 CC09 EE37

Claims (5)

[Claims] 1. Two substrates for sandwiching a liquid crystal substance, a plurality of pixel electrodes arranged in a matrix on one of the two substrates, and driving the pixel electrodes to be orthogonal to each other. Liquid crystal panel including a plurality of signal lines and scanning lines, and a plurality of source driver ICs for supplying signals to the signal lines
A liquid crystal display device including: a gate driver IC for supplying a signal to the scanning line; and a liquid crystal display control circuit for controlling the source driver IC and the gate driver IC. A liquid crystal display device comprising: a plurality of source driver substrates mounted on a liquid crystal panel (k is a natural number of 2 or more); and the k source driver substrates are arranged along a long side direction of the liquid crystal panel. 2. The liquid crystal display device according to claim 1, wherein the liquid crystal panel has a high resolution of 1280 horizontal pixels and 1024 vertical lines or more. 3. The liquid crystal display control circuit includes an input terminal, a frequency dividing unit, and an output terminal, and the liquid crystal display control circuit divides a frequency of image data input from the input terminal into n by the frequency dividing unit. 2. After division (n is a natural number of 2 or more), the input image data whose frequency is divided by n is transmitted from the output terminal to k (k is a natural number of 2 or more) source driver substrates.
Or the liquid crystal display device according to 2. 4. The liquid crystal display control circuit includes an input terminal, a frequency dividing unit, a frequency adjusting unit, a storage unit, and an output terminal, and the liquid crystal display control circuit is configured to control input image data input from the input terminal. The frequency is divided by the frequency dividing means into n
After dividing (n is a natural number of 2 or more) and temporarily storing it in the storage unit, when transmitting the stored input image data to the k source driver boards (k is a natural number of 2 or more), 3. The liquid crystal display device according to claim 1, wherein the frequency adjusting unit adjusts the frequency of the n-divided input image data to a frequency (a is a real number) and transmits the data. 5. A liquid crystal display device application device using the liquid crystal display device according to claim 1.