JP2002094013A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which reduces plasma damage during etching and improves the characteristics of FeRAM memory cells. SOLUTION: An information transfer MISFET Qs and a capacitor C are formed on the main surface of a semiconductor substrate 1, an oxide silicon film 13 on an upper electrode 12a and a lower electrode 10a of the capacitor C is removed to form contact holes 22 and then a TiN film 15 is formed on the silicon oxide film 13, including the insides of the contact holes 22. As a result, if a resist is ashed or plasma-etched, charges resulting from these processes are removed through the TiN film 15 to reduce the plasma damage during etching and improve the characteristics of FeRAM memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an FeRAM (ferroelectric memory).

[0002]

2. Description of the Related Art A memory cell of an FeRAM is composed of one memory cell selecting MISFET and one information capacitor. Further, MISFETs and the like for driving the memory cells are formed around the memory cell array.

[0003]

SUMMARY OF THE INVENTION
A ferroelectric material such as PZT is used. The inventors of the present invention have examined this ferroelectric material, and as a result, it has been found that the ferroelectric material is damaged by plasma during etching and the characteristics are deteriorated. That is, after forming a contact hole on the lower electrode and the upper electrode of the capacitor,
When a contact hole is formed on a device in the peripheral circuit region, plasma etching or ashing is performed. At this time, a charge is generated and accumulated in the ferroelectric film, and the write / read characteristics deteriorate.

[0004] For example, the influence of Al wiring etching on SBT capacitance characteristics is taken up in the 44th Spring Meeting of the 1997 Japan Society of Applied Physics Proceedings 30p-ZF-3 (p487).

An object of the present invention is to provide a technique for reducing plasma damage during etching.

Another object of the present invention is to improve the characteristics of FeRAM memory cells by reducing plasma damage during etching.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A method of manufacturing a semiconductor integrated circuit device according to the present invention is directed to an information transfer M formed on a main surface of a semiconductor substrate.
A method of manufacturing a semiconductor integrated circuit device having an ISFET and a capacitor connected in series to the information transfer MISFET, comprising: (a) forming a gate insulating film and a gate electrode on the semiconductor substrate; b) forming source and drain regions in the semiconductor substrate on both sides of the gate electrode; and (c) sequentially forming a first conductive film, a capacitor insulating film made of a ferroelectric material, and a second conductive film. Depositing and patterning to form the capacitor comprising a lower electrode made of the first conductive film, a capacitor insulating film, and an upper electrode made of a second conductive film; (d) Forming an insulating film on the capacitor and removing the insulating films on the upper electrode and the lower electrode to form a contact hole; and (e) forming a contact hole in the contact hole. And forming a third conductive film on free the insulating film.

(2) The method for manufacturing a semiconductor integrated circuit device according to the present invention is directed to a method for manufacturing an information transfer M formed on a main surface of a semiconductor substrate.
A method of manufacturing a semiconductor integrated circuit device having an ISFET and a capacitor connected in series to the information transfer MISFET, comprising: (a) forming a gate insulating film and a gate electrode on the semiconductor substrate; b) forming source and drain regions in the semiconductor substrate on both sides of the gate electrode; and (c) forming the gate electrode and the source.
Forming a first insulating film on the drain region;
(D) a step of forming a first contact hole by removing the first insulating film on the source and drain regions; and (e) a first conductive film and a capacitive insulating film made of a ferroelectric material. And a second conductive film is sequentially deposited and patterned to form a capacitor composed of a lower electrode made of the first conductive film, a capacitor insulating film, and an upper electrode made of a second conductive film. Forming,
(F) forming a second insulating film on the capacitor and removing the second insulating film on the upper electrode and the lower electrode to form a second contact hole; Forming a third conductive film on the second insulating film including inside the first and second contact holes; and (h) forming the first, second insulating film, and the third conductive film. And forming a third contact hole by removing the third contact hole.

(3) The method for manufacturing a semiconductor integrated circuit device according to the present invention is directed to a method for manufacturing an information transfer M formed on a main surface of a semiconductor substrate.
A method of manufacturing a semiconductor integrated circuit device having an ISFET and a capacitor connected in series to the MISFET, comprising: (a) forming a gate insulating film and a gate electrode on the semiconductor substrate; Forming a source and drain region in the semiconductor substrate on both sides of the gate electrode; (c) forming a first insulating film on the gate electrode and the source and drain regions; and (d) forming the source and drain regions Forming a first contact hole by removing the first insulating film on the region; (e) a first conductive film, a capacitive insulating film made of a ferroelectric material, and a second conductive film Are sequentially deposited and patterned to form a capacitor comprising a lower electrode made of the first conductive film, a capacitor insulating film and an upper electrode made of a second conductive film. (F) forming a second insulating film on the capacitor, and removing the second insulating film on the upper electrode and the lower electrode to form a second contact hole. (G) forming a third conductive film on the second insulating film including the insides of the first and second contact holes; and (h) forming a third conductive film and a third conductive film. Forming a third contact hole by removing the third conductive film;
(I) a wiring for connecting the upper electrode to a source / drain region by forming a fourth conductive film on the third conductive film and patterning the fourth conductive film; Forming a wiring made of a conductive film.

(4) Further, the semiconductor integrated circuit device comprises:
A semiconductor integrated circuit device having a memory cell array in which the information transfer MISFET and the capacitor are formed, and a peripheral circuit region, wherein the third contact hole is formed on an element formed in the peripheral circuit region. You may.

(5) A semiconductor integrated circuit device according to the present invention is an information transfer MISFET formed on a main surface of a semiconductor substrate.
And a capacitor, and a wiring connecting the information transfer MISFET and the capacitor. (A) The information transfer MISFET includes a source and a drain region formed in the semiconductor substrate. A gate electrode formed between the source and the drain with a gate insulating film interposed therebetween; a first insulating film formed on the gate electrode and the source and drain regions; and a gate electrode formed on the source and drain regions. (B) the capacitor has a lower electrode made of a first conductive film, a capacitor insulating film made of a ferroelectric material, and an upper part made of a second conductive film. An electrode, a second insulating film formed on the upper electrode, and a second contact hole formed on the upper electrode and the lower electrode;
(C) The wiring has a third conductive film and a fourth conductive film extending from the upper electrode to the source / drain region.

According to the above-described means, the third conductive film is formed on the second insulating film including the inside of the second contact hole on the upper electrode and the lower electrode. , Via the third conductive film, for example,
Since it is connected to the source and drain regions, even if ashing or plasma etching of the resist is performed thereafter, charges generated during these processes can be removed through the third conductive film. Therefore, it is possible to prevent the characteristic deterioration of the capacitance insulating film due to the accumulation of the charge.

Further, according to the above-described means, the third conductive film is left as a wiring connecting the upper electrode to the source and drain regions, so that the wiring resistance can be reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

A method of manufacturing an FeRAM according to an embodiment of the present invention will be described in the order of steps with reference to FIGS.

First, as shown in FIG.
A p-type well 3 and an n-type well 4 are formed in a semiconductor substrate 1 made of n-type single crystal silicon having a specific resistance of about cm. The p-type well 3 is formed by ion-implanting a p-type impurity, for example, boron (B) into the semiconductor substrate 1,
The semiconductor substrate 1 is formed by annealing to thermally diffuse impurities. The n-type well 4 is provided on the semiconductor substrate 1.
After ion implantation of an n-type impurity, for example, phosphorus (P), the semiconductor substrate 1 is formed by annealing to thermally diffuse the impurity.

Next, a field oxide film 2 for element isolation is formed on the main surface of the semiconductor substrate 1. This field oxide film 2 is formed by a known LOCOS method.

Next, after the surface of the semiconductor substrate 1 (p-type well 3 and n-type well 4) is wet-cleaned using a hydrofluoric acid-based cleaning solution, each of the p-type well 3 and the n-type well 4 is wet-oxidized. A clean gate oxide film 5 is formed on the surface of the substrate.

Next, a conductive film such as a polycrystalline silicon film is deposited on the gate oxide film 5, and a thin insulating film such as a silicon oxide film is deposited and patterned. As a result, on the wide field oxide film 2 on the n-type well 4, a capacitance element D is formed with the lower electrode FG being a polycrystalline silicon film and the capacitance insulating film 6 being a silicon oxide film. This capacitive element D
Of the MISFETs Qs and Qp formed on the main surfaces of the p-type well 3 and the n-type well 4, respectively.
Formed simultaneously with G.

Next, a conductive film such as a polycrystalline silicon film is deposited on the semiconductor substrate 1 and patterned. Thus, gate electrodes SG are formed on the main surfaces of p-type well 3 and n-type well 4. Further, on the field oxide film 2, a conductive layer SG1 used for wiring, resistance, and the like is formed. Further, an upper electrode SG2 is formed on the capacitance insulating film 6. Next, an n-type impurity, for example, phosphorus (P) is ion-implanted on both sides of the gate electrode SG on the p-type well 3 to form an n-type semiconductor region 7 (source, drain).
Further, a p-type impurity, for example, boron (B) is ion-implanted on both sides of the gate electrode SG on the n-type well 4 to form a p-type semiconductor region 8 (source, drain). Next, a silicon oxide film 9 is deposited on the semiconductor substrate 1 by a CVD method. Through the above steps, an n-channel MISFET Qs forming the FeRAM and a p-channel MISFET Qp forming the peripheral circuit are formed.

Next, as shown in FIG. 2, a Ti electrode serving as a lower electrode is formed on the silicon oxide film 9 by sputtering.
A laminated film 10 of Pt film and Pt film is deposited.
Depositing a layer _{(Pb (Zr y Ti z)} O 3) 11. Thereafter, annealing is performed to improve the characteristics of the PZT film 11. Next, a laminated film 12 of a Ti film and a Pt film serving as an upper electrode is deposited on the PZT film 11.

Next, the upper electrode 12a is formed by patterning the laminated film 12. Next, the capacitor insulating film 11a and the lower electrode 10a are formed by patterning the laminated film 10 and the PZT film 11. Here, the lower electrode 10a is formed larger than the upper electrode, and a contact hole 22 to be described later is formed on a region not facing the upper electrode. By the above steps, Fe
A capacitor C constituting the RAM is formed (FIG. 3).

Next, as shown in FIG. 4, a silicon oxide film 13 is deposited by a CVD method.

Subsequently, the n-type semiconductor region 7 (source, drain) and the p-type semiconductor region 8 (source, drain)
A resist film (not shown) having an opening is formed thereon. Next, as shown in FIG. 5, using this resist film as a mask, the silicon oxide films 9 and 13 on the n-type semiconductor region 7 (source and drain) and the p-type semiconductor region 8 (source and drain) are subjected to plasma etching. The contact holes 21 are formed by the removal. Next, the resist film is removed by ashing, and the contact hole 2 is removed.
Forming a Pt film on the silicon oxide film 13 including inside
By performing the heat treatment, the Pt film and the n-type semiconductor region 7 are formed.
The silicide layer 14 is formed at a contact portion with the (source, drain) or the p-type semiconductor region 8 (source, drain).

Subsequently, a resist film (not shown) having an opening is formed on the upper electrode 12a and the lower electrode 10a of the capacitor C. Next, as shown in FIG. 6, the contact hole 22 is formed by removing the silicon oxide film 13 on the upper electrode 12a and the silicon oxide film 13 and the capacitor insulating film 11a on the lower electrode 10a of the capacitor C by plasma etching. . Next, the resist film is removed by ashing, and annealing is performed in an O ₂ atmosphere to improve the film quality of the PZT film (capacitive insulating film 11a).

Subsequently, as shown in FIG. 7, a Ti film is formed on the silicon oxide film 13 including the insides of the contact holes 21 and 22.
An N film 15 (third conductive film) is formed to a thickness of about 50 nm.

Subsequently, the conductive layer S on the field oxide film 2
A resist film (not shown) having an opening is formed on G1 and the upper electrode SG2 of the capacitor D. Next, the silicon oxide films 9, 1 of the conductive layer SG1 and the upper electrode SG2 are formed.
3 and the TiN film 15 are removed by plasma etching to form a contact hole 23 (FIG. 8). Next, the resist film is removed by ashing.

As described above, in the present embodiment, T
Since the iN film 15 is formed, charges generated during plasma etching when forming the contact hole 23 or ashing for removing the resist can be removed via the TiN film 15. This contact hole 23
Is formed after the formation of the contact hole 22 in order to prevent the surfaces of the conductive layer SG1 and the upper electrode SG2 from being oxidized during the annealing.

Next, as shown in FIG. 9, a TiN film 16 (fourth conductive film) is deposited to a thickness of about 80 nm on the silicon oxide film 13 including the insides of the contact holes 21, 22, and 23. Next, as shown in FIG.
The wiring L1 is formed by patterning 16.

Next, as shown in FIG. 11, a silicon oxide film 17 is formed on the wiring L1 and the silicon oxide film 13, and the silicon oxide film 13 on the wiring L1 is removed to form a contact hole 18 (FIG. 12). To form Next, as shown in FIG. 13, for example, a TiN film, an Al film is formed on the silicon oxide film 17 including the inside of the contact hole 18.
A first layer wiring M1 is formed by sequentially depositing and patterning a film and a TiN film. Next, a silicon oxide film 19 is formed on the first layer wiring M1 (FIG. 14).

Thereafter, a conductive film and a silicon oxide film are alternately formed on the silicon oxide film 19,
Although a multi-layer wiring is formed, its figure and detailed description are omitted.

As described above, in the present embodiment, F
After a contact hole 22 was formed on the upper electrode 12a and the lower electrode 10a of the capacitor C constituting the eRAM, a TiN film 15 was formed on the silicon oxide film 13 including the inside of the contact hole 22. Charges generated during plasma etching for forming the holes 23 or ashing for removing the resist can be removed via the TiN film 15. Therefore, it is possible to prevent the characteristic deterioration of the capacitance insulating film due to the accumulation of the charge.

For example, when the contact hole 22 is formed without forming the TiN film 15, the capacitance insulating film 11
While the residual polarization of the PZT film a was deteriorated by 50%, the contact hole 2 was formed after the TiN film 15 was formed.
When No. 2 was formed, the deterioration of the residual polarization amount of the PZT film could be suppressed to 10% or less.

The TiN film 15 is formed on the upper electrode 12a and n
Wiring L1 is connected to the TiN films 15 and 16
And the wiring resistance can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

In particular, in the above embodiment, the p-channel MISFET is provided in the n-type well 4 as the peripheral circuit region.
Although Qp is formed, an n-channel MISFET may be formed by forming a p-type well in the peripheral circuit region.

In the above embodiment, the capacitor C
Although a laminated film of a Pt film and a Ti film was used as the upper or lower electrode of Pt, the present invention is not limited to this.
A single-layer film mainly composed of a platinum group metal such as Ir, IrO ₂ , Ru, RuO ₂ or an oxide or multiple oxide thereof, or a laminated film composed of two or more kinds of conductive films selected therefrom May be.

Further, in this embodiment, the PZT film is used as the ferroelectric film for the capacitor insulating film, but the present invention is not limited to this. For example, BST, PLT,
A dielectric film having a heroovskite structure such as PLZT, SBT or the like or a structure similar thereto and mainly composed of a high to ferroelectric material may be used.

[0041]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, the contact hole is formed in the insulating film on the upper electrode and the lower electrode constituting the capacitor, and then the conductive film is formed on the insulating film including the inside of the contact hole. Thereafter, even if resist ashing or plasma etching is performed, charges generated during these processes can be removed through the conductive film. Therefore, it is possible to prevent the characteristic deterioration of the capacitance insulating film due to the accumulation of the charge.

Further, this conductive film is formed by using an upper electrode and a source,
Since it was left as a wiring connecting to the drain region,
Wiring resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a substrate, illustrating a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 6 is a diagram showing a structure of a plug of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 11 is a diagram showing a structure of a plug of the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device according to the embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field oxide film 3 p-type well 4 n-type well 5 gate oxide film 6 capacitive insulating film FG lower electrode SG2 upper electrode D capacitive element SG1 conductive layer SG gate electrode 7 n-type semiconductor region 8 p-type semiconductor region 9 oxidation Silicon film 10 Laminated film of Ti film and Pt film 10a Lower electrode 11 PZT film 11a Capacitive insulating film 12 Laminated film of Ti film and Pt film 12a Upper electrode 13 Silicon oxide film 14 Silicide layer 15 TiN film 16 TiN film 17 Silicon oxide film Reference Signs List 18 contact hole 19 silicon oxide film 21 contact hole 22 contact hole 23 contact hole C capacitor L1 wiring M1 first layer wiring Qp p-channel MISFET Qs n-channel MISFET

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Keiichi Yoshizumi, Inventor 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. (72) Inventor Mitsuhiro Mori, Josuihoncho, Kodaira-shi, Tokyo No. 20-1 F-term in Hitachi Semiconductor Co., Ltd. Semiconductor Group 5F083 FR02 GA30 JA15 JA35 JA38 JA39 JA53 KA01 KA11 NA02 NA03 PR43 PR53

Claims (5)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device comprising: an information transfer MISFET formed on a main surface of a semiconductor substrate; and a capacitor connected in series to the information transfer MISFET. Forming a gate insulating film and a gate electrode on a semiconductor substrate; (b) a source in the semiconductor substrate on both sides of the gate electrode;
Forming a drain region; and (c) sequentially depositing and patterning a first conductive film, a capacitor insulating film made of a ferroelectric material, and a second conductive film, thereby forming the first conductive film. Forming the capacitor comprising a lower electrode made of a capacitor insulating film and an upper electrode made of a second conductive film; and (d) forming an insulating film on the capacitor, and forming the upper electrode and the lower electrode. Forming a contact hole by removing an insulating film on the electrode; and (e) forming a third conductive film on the insulating film including the inside of the contact hole. Of manufacturing a semiconductor integrated circuit device. 2. A method of manufacturing a semiconductor integrated circuit device, comprising: a MISFET for information transfer formed on a main surface of a semiconductor substrate; and a capacitor connected in series to the MISFET for information transfer, wherein: Forming a gate insulating film and a gate electrode on a semiconductor substrate; (b) a source in the semiconductor substrate on both sides of the gate electrode;
Forming a drain region; (c) forming a first insulating film on the gate electrode, source and drain regions; and (d) removing the first insulating film on the source and drain regions. (E) forming a first contact hole, and (e) sequentially depositing and patterning a first conductive film, a capacitor insulating film made of a ferroelectric material, and a second conductive film. Forming the capacitor comprising a lower electrode made of one conductive film, a capacitor insulating film, and an upper electrode made of a second conductive film; and (f) forming a second insulating film on the capacitor. Forming a second contact hole by removing the second insulating film on the upper electrode and the lower electrode; and (g) including inside the first and second contact holes. Forming a third conductive film on the second insulating film; and (h) forming a third contact hole by removing the first, second insulating film and the third conductive film. A method for manufacturing a semiconductor integrated circuit device, comprising: 3. A method for manufacturing a semiconductor integrated circuit device having an information transfer MISFET formed on a main surface of a semiconductor substrate and a capacitor connected in series to the MISFET, comprising: Forming a gate insulating film and a gate electrode on the semiconductor substrate; (b) forming a source in the semiconductor substrate on both sides of the gate electrode;
Forming a drain region; (c) forming a first insulating film on the gate electrode, source and drain regions; and (d) removing the first insulating film on the source and drain regions. (E) forming a first contact hole, and (e) sequentially depositing and patterning a first conductive film, a capacitor insulating film made of a ferroelectric material, and a second conductive film. Forming the capacitor comprising a lower electrode made of one conductive film, a capacitor insulating film, and an upper electrode made of a second conductive film; and (f) forming a second insulating film on the capacitor. Forming a second contact hole by removing the second insulating film on the upper electrode and the lower electrode; and (g) including inside the first and second contact holes. Forming a third conductive film on the second insulating film; and (h) forming a third contact hole by removing the first, second insulating film and the third conductive film. And (i) forming a fourth conductive film on the third conductive film and patterning the wiring to connect the upper electrode to a source / drain region; Forming a wiring made of a fourth conductive film. A method for manufacturing a semiconductor integrated circuit device, comprising: 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device includes a memory cell array in which the information transfer MISFET and the capacitor are formed, and a peripheral circuit region. 4. The method according to claim 3, wherein the semiconductor integrated circuit device is formed on an element formed in the circuit region. 5. An information transfer MISFET formed on a main surface of a semiconductor substrate, a capacitor, and the information transfer M
A semiconductor integrated circuit device having a wiring connecting an ISFET and a capacitor, wherein: (a) the information transfer MISFET includes a source / drain region formed in the semiconductor substrate;
A gate electrode formed between the drains via a gate insulating film, a first insulating film formed on the gate electrode, the source, and the drain region; and a first electrode formed on the source and the drain region. (B) the capacitor has a lower electrode made of a first conductive film, a capacitance insulating film made of a ferroelectric material, an upper electrode made of a second conductive film, A second insulating film formed on the upper electrode, and a second contact hole formed on the upper electrode and the lower electrode; and (c) the wiring is formed from the upper electrode to a source and drain region. A semiconductor integrated circuit device, comprising: a third conductive film and a fourth conductive film extending up to the third conductive film.