JP2002094012A - Esd protective element for soi integrated circuits - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-leakage ESD protective element for SOI-integrated circuits of which is easy to control the withstanding voltage and which allows a high ESD resistance to be taken. SOLUTION: A protective element is shown which is constituted with a silicon single-crystal film on an insulation film, in order to allow an applied current exceeding a withstanding level to escape to a SOI integrated circuit.. On an optical transferring path of a signal from an input terminal (input pin) IN to an inner logic circuit ILGC via an input buffer, there is a transversal array of a p+ region 11 wired to a p+ polycrystalline silicon member 10, an n- region 12, a p- region 13 and an n+ region 14 connected to an n+ polycrystalline silicon member 15 coupled with a reference potential (ground potential GND). This array of the regions 11-14 forms a thyristor structure to be triggered by punch- through.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to electrostatic discharge (ESD) protection of electronic circuits, and more particularly to ESD protection for SOI integrated circuits of SOI (Silicon On Insulator) technology. Related to the element.

[0002]

2. Description of the Related Art The SOI (Silicon On Insulator) technology has a configuration in which an insulator layer is embedded in a semiconductor substrate and extends below an active region of an integrated circuit. Since the parasitic capacitance of the element is low, higher-speed operation can be expected than a circuit element manufactured on a bulk silicon substrate. Since it operates at high speed even with a low voltage power supply, application of a low power consumption LSI is drawing attention. Thus, an ESD (Electro Static Discharge) that applies a high voltage from a charged object and causes fatal damage to an integrated circuit.
charge) requires adequate protection.

As a conventional ESD protection circuit applied to the SOI technology, there is one disclosed in, for example, Japanese Patent Application Laid-Open No. H10-294430. This includes a silicon controlled rectifier (SC
A circuit for ESD protection is configured by a bistable pseudo SCR switch using the pseudo R.

[0004] In the above disclosed technology, the configuration of the NPN transistor and the PNP transistor is provided. The NPN transistor and the PNP transistor are formed in independent active regions separated from each other by a field oxide region and an upper buried oxide film. In addition, it requires an optional resistor formed in another active region that interconnects the two NPN and PNP transistors.

[0005]

SUMMARY OF THE INVENTION In an SOI integrated circuit,
High speed operation with low power consumption is expected due to the reduction in parasitic capacitance. However, a problem such as a reduction in drain breakdown voltage due to the substrate floating effect is a problem. In the above-described disclosed technology, when it is desired to operate the protection element at a low voltage, it is difficult to control the withstand voltage, and it is difficult to provide an appropriate protection element.

Further, when an ESD protection circuit is formed by simply utilizing the breakdown phenomenon of a PN junction, regions of P ⁺ and N ⁺ having a concentration in consideration of the breakdown voltage of the junction are made adjacent to each other. However, in this configuration, particularly when it is desired to operate the protection element at a low voltage, a large amount of leakage occurs due to a tunnel current, so that the input current of the LSI is unduly increased.

Also, unlike a bulk silicon substrate, heat hardly escapes in the direction of the substrate in an SOI integrated circuit, so that a problem of destruction due to heat concentration occurs. With this, ES
D tends to be difficult to withstand.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a low-leakage ESD protection element for a SOI integrated circuit, which can easily control the withstand voltage and has a large ESD resistance. .

[0009]

SUMMARY OF THE INVENTION An ESD protection element for an SOI integrated circuit according to the present invention is a protection element formed of a silicon single crystal film on an insulating film in order to release a current applied to the SOI integrated circuit that exceeds a withstand voltage. A first polycrystalline silicon member connected to an arbitrary signal transmission path to an internal circuit and having a first conductivity type impurity introduced at a predetermined concentration;
A first conductive type first semiconductor region formed in the silicon single crystal film connected to the polycrystalline silicon member, and a first conductive type formed in the silicon single crystal film and adjacent to the first semiconductor region. A second semiconductor region of a second conductivity type of opposite conductivity type, a third semiconductor region of a first conductivity type formed in the silicon single crystal film and adjacent to the second semiconductor region, and a silicon single crystal film. A fourth semiconductor region of a second conductivity type formed and adjacent to the third semiconductor region; and a fourth semiconductor region connected to the fourth semiconductor region and having a predetermined concentration of a second conductivity type impurity connected to a predetermined potential. And 2 polycrystalline silicon members.

The above-mentioned ESD for an SOI integrated circuit according to the present invention.
According to the protection element, a thyristor structure is provided by the arrangement of the first to fourth semiconductor regions formed on the insulating film. This thyristor structure has a structure in which a trigger is applied by punch-through. Note that the arrangement of the first semiconductor region to the fourth semiconductor region is formed so as to have a dimension that can be conducted by punch-through at least in a situation exceeding the withstand capacity.

In order to realize a thyristor structure, the first semiconductor region and the fourth semiconductor region are characterized in that a higher concentration of impurities is introduced than the second semiconductor region and the third semiconductor region. Further, the first semiconductor region and the fourth semiconductor region are formed by diffusion of impurities contained in the first polycrystalline silicon member and the second polycrystalline silicon member, respectively.

[0012]

FIG. 1 is a cross-sectional view showing a configuration of a main part of an ESD protection element for an SOI integrated circuit according to an embodiment of the present invention. FIG. 2 shows a protection element formed of a silicon single crystal film on an insulating film (SOI) in order to release an applied current exceeding a withstand amount to an SOI integrated circuit through another path.

The protection element in this embodiment is connected in the middle of a transmission path of an arbitrary signal from an input terminal (input pin) IN to an internal logic circuit ILGC via an input buffer, for example. Having a configuration.

For example, the polycrystalline silicon member 10 connected to the signal transmission path has a high concentration of P-type impurities (10 ²⁰ to 10 ²⁰ ).
P ⁺ type introduced at 10 ²¹ cm ^-3 ). The polycrystalline silicon member 10 is connected to a P ⁺ type region 11 formed in the silicon single crystal film. In the silicon single crystal film, an N ⁻ -type region 12 in which an N-type impurity is introduced at a low concentration (10 ¹⁵ to 10 ¹⁶ cm ⁻³ ) is adjacent to the P ⁺ -type region 11.
Are formed. Further, a P ⁻ type region 13 is formed adjacent to the N ⁻ type region 12 in the silicon single crystal film. This P ⁻ -type region 13 is doped with a P-type impurity at a low concentration (10 ¹⁵ to 10 ¹⁶ cm ⁻³ ). Further arranged N ⁺ -type region 14, N-type impurity high concentration (10 ^20-1
0 ²¹ cm ^-3 ) and is connected to a polycrystalline silicon member 15 that is connected to a reference potential (here, a ground potential GND). The polycrystalline silicon member 15 is an N ⁺ type in which N type impurities are introduced at a high concentration (10 ²⁰ to 10 ²¹ cm ⁻³ ).

According to the configuration of the above embodiment, the insulating film (S
OI) P ⁺ type regions 11 to N ⁺ type regions 14 formed on
Have a thyristor structure. This thyristor structure has a structure in which a trigger is applied by punch-through instead of breakdown. The above P ⁺ type region 1
The lateral arrangement of the 1-N ⁺ -type regions 14 is at least ESD
It may be formed to have a dimension that can be conducted by punch-through in a situation where the amount exceeding the tolerance that may affect the internal circuit due to the input of. For example, the N− type region 12 and P
^- dimensions of the combined type region 13 is set to about 0.5 [mu] m.

According to the above configuration, almost no junction leak occurs until a punch-through occurs, such as when an excessive voltage such as ESD is applied. Thereby, a low-leakage ESD protection element can be realized.

Further, the P ⁺ type region 11 to the N ⁺ type region 1
In the horizontal arrangement of 4, the snap-off voltage is determined by controlling the mask size and the dose. Further, the holding current can be changed and adjusted by changing the mask shape. This makes it easy to control the breakdown voltage.

The above P ⁺ type region 11 to N ⁺ type region 1
In the lateral arrangement of 4, the elements are formed on the insulating film, and the junction capacitance does not increase unduly, so that the device operates with low parasitic capacitance. Further, such a thyristor structure consumes power in the entire device, so that there is an advantage that a hot spot is hardly generated and a large ESD resistance can be obtained.

Also, polycrystalline silicon members (10, 15)
Has a high melting point and is compatible with metal (metal wiring), and is easy to release heat. That is, since the polycrystalline silicon members 10 and 15 themselves serve as heat radiation electrodes, a rise in temperature is suppressed. Therefore, an ESD protection element that is hardly damaged by self-heating can be realized.

Further, the thyristor structure of the P ⁺ -type regions 11 to N ⁺ -type regions 14 and the polycrystalline silicon members 10, 1
5 has an advantage that it can be formed without requiring a special mask in the manufacturing process. For example, it can be configured using a CMOS process. This will be described below.

FIGS. 2 to 4 each show the ES shown in FIG.
It is sectional drawing which shows the formation method of a D protection element in order of a process. As shown in FIG. 2, in the silicon single crystal film on the insulating film (SOI), an N ⁻ type region 12 and a P ⁻ type region 13 are formed simultaneously with the process of PMOS channel doping and NMOS channel doping.

Next, as shown in FIG. 3, an oxide film mask 31 is formed in a predetermined region using a gate oxide film forming step. Thereafter, polycrystalline silicon 32 is deposited in a gate electrode forming step.

Next, as shown in FIG. 4, simultaneously with the step of patterning the gate electrode, the polycrystalline silicon members 10 and 15 are formed.
Adjust the shape of. Thereafter, the polycrystalline silicon members 10 and 15 are respectively set to a predetermined P ⁺ type and N ⁺ by using respective ion implantation processes for forming the source / drain of the PMOS and NMOS.
Type. Thereafter, a P ⁺ type region 11 is formed below the polycrystalline silicon member 10 by annealing diffusion, and an N ⁺ type region 14 is formed below the polycrystalline silicon member 15. Through such a CMOS process, an ESD protection element as shown in FIG. 1 can be formed.

FIG. 5 is a cross-sectional view showing a main configuration of an ESD protection element for an SOI integrated circuit as a modification of FIG.
The configuration shown in FIG. 1 is opposite in conductivity type to that of the N ⁺ type polycrystalline silicon member 20, the N ⁺ type region 21, the P ⁻ type region 22,
The N ⁻ type region 23, the P ⁺ type region 23, and the P ⁺ type polycrystalline silicon member 24 realize an ESD protection element. The rest of the configuration is the same as in the configuration of FIG. 1, and the same effects as in FIG. 1 can be expected. Further, the configuration can also be manufactured using a CMOS process.

The configuration of the above ESD protection element has dimensions,
The dose is not limited, and may be considered so as to function as an appropriate ESD protection element of the SOI integrated circuit to be used.

[0026]

As described above, the SO according to the present invention can be used.
According to the I-type integrated circuit ESD protection element, a thyristor structure is formed by laterally arranging the semiconductor regions formed on the insulating film. Since polycrystalline silicon members having good heat dissipation properties are formed at both ends, breakage due to self-heating can be significantly reduced. The thyristor structure is formed to have a dimension that can be triggered by punch-through. As a result,
It is possible to provide a low-leakage ESD protection element for an SOI integrated circuit in which the withstand voltage is easily controlled and the ESD resistance is large.

[Brief description of the drawings]

FIG. 1 shows an E for SOI integrated circuit according to an embodiment of the present invention.
It is sectional drawing which shows the principal part structure of an SD protection element.

FIG. 2 is a first cross-sectional view showing a method of forming the ESD protection element as shown in FIG. 1 in a process order.

FIG. 3 is a second cross-sectional view showing a method of forming the ESD protection element as shown in FIG. 1 in the order of steps;

FIG. 4 is a third sectional view showing a method of forming the ESD protection element as shown in FIG. 1 in the order of steps;

FIG. 5 shows an ESD for an SOI integrated circuit as a modification of FIG.
It is sectional drawing which shows the principal part structure of a protection element.

[Explanation of symbols]

10, 24 ... P ⁺ -type polycrystalline silicon member 11 ... P ⁺ -type regions 12 and 23 ... N ^- -type region 13 and 22 ... P ^- -type region 14, 21 ... N ⁺ -type region 15, 20 ... N ⁺ -type Polycrystalline silicon member 31 ... Oxide mask 32 ... Polycrystalline silicon IN ... Input terminal (input pin) ILGC ... Internal logic circuit

Claims (4)

[Claims] 1. A protection element formed of a silicon single crystal film on an insulating film in order to release an applied current exceeding a withstand voltage to an SOI integrated circuit, which is connected to an arbitrary signal transmission path to an internal circuit. A first polycrystalline silicon member into which impurities of a first conductivity type are introduced at a predetermined concentration; and a first polycrystalline silicon member formed on the silicon single crystal film connected to the first polycrystalline silicon member. A semiconductor region, a second semiconductor region formed in the silicon single crystal film and having a second conductivity type opposite to the first conductivity type and adjacent to the first semiconductor region, and formed in the silicon single crystal film A third semiconductor region of a first conductivity type adjacent to the second semiconductor region; a fourth semiconductor region of a second conductivity type formed in the silicon single crystal film and adjacent to the third semiconductor region; Connected to the area and prescribed A second polycrystalline silicon member into which impurities of a second conductivity type leading to the potential of the second conductivity type are introduced at a predetermined concentration.
ESD protection element for I integrated circuits. 2. The semiconductor device according to claim 1, wherein the arrangement of the first semiconductor region to the fourth semiconductor region is formed to have a dimension that allows conduction by punch-through at least when the amount exceeds the withstand amount. ESD protection element for SOI integrated circuit. 3. The semiconductor device according to claim 1, wherein the first semiconductor region and the fourth semiconductor region have a higher impurity concentration than the second semiconductor region and the third semiconductor region.
An ESD protection element for an SOI integrated circuit according to the above. 4. The semiconductor device according to claim 1, wherein the first semiconductor region and the fourth semiconductor region are formed by diffusion of impurities contained in the first polycrystalline silicon member and the second polycrystalline silicon member, respectively. The ESD protection device for an SOI integrated circuit according to claim 3.