JP2002093675A - Method for producing semiconductor device comprising a plurality of chips - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfy the characteristics required for a semiconductor device without lowering the yield of each of a plurality of chips constituting the semiconductor device. SOLUTION: A decision is made, in units of wafer lot, whether the characteristic value of a chip obtained through wafer test falls within a reference level or not. When the characteristic value of chip does not fall within the reference level, an assembly is pended and when the number of pending lots reaches a preset value, characteristic data of the pending lot is transmitted to the semiconductor chip manufacturing process of other chip constituting a device in order to alter the manufacturing conditions and the pending lot is assembled in combination with a lot subjected to alteration of manufacturing conditions Furthermore, the semiconductor chip manufacturing process, a wafer test process and a device manufacturing process for assembling are connected on a computer network and information related to production, e.g. wafer test information and manufacturing conditions is transmitted/received between respective processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for producing a semiconductor device comprising a plurality of chips.

[0002]

2. Description of the Related Art When assembling a plurality of chips into one semiconductor device, the following will occur because each chip has manufacturing variations.

[0003] First, one of semiconductor devices composed of a plurality of chips is described.
First, DC stabilized power supply (low-loss regulator)
There is. As shown in FIG. 1, the DC stabilized power supply includes a control IC chip 2 and an output transistor chip (PNP transistor chip) 3 through which a load current can flow.
And outputs a stabilized voltage to the output terminal 6.

As an additional circuit of the stabilized DC power supply 1, an overcurrent protection circuit 4 is generally incorporated. The overcurrent characteristic obtained by the overcurrent protection circuit 4 is a characteristic that, when an abnormally high current as an output current of the low-loss regulator, that is, an overcurrent flows, the output current is reduced, and a device with high safety is provided. This is a very important characteristic.

The principle of operation of the overcurrent protection circuit 4 is that a current from the emitter of the NPN transistor 5 in the control IC chip 2 is monitored by a detection resistor in the overcurrent protection circuit 4 and the value is set to a set value. As described above, the base current of the NPN transistor 5 is reduced, and the output current Ic is reduced as shown in FIG.

In other words, since the base current of the output transistor chip 3 is monitored, manufacturing variations in the detection resistance value in the overcurrent protection circuit 48 and the current amplification factor (hFE) of the output transistor chip 3 are reduced. The variation in manufacturing is integrated, and the output current value to which an overcurrent is actually applied varies.

For example, when the detection resistance value in the overcurrent protection circuit 4 varies to a smaller value and the hFE of the output transistor chip 3 varies to a larger value, the overcurrent detection point of the output current Ic increases (see FIG. 2)
If the opposite is true, the smaller one will be (FIG. 2).

More specifically, in the overcurrent protection circuit 4, when the voltage across the overcurrent detection resistor in the circuit becomes equal to or higher than a preset voltage value, the overcurrent protection is activated, The base current of P (FIG. 1) will be reduced.

[0009] Explaining in concrete numerical values, the center value of the overcurrent detection resistance value is 30Ω, the center value of the hFE of the output transistor chip 3 is 140, and the preset voltage at both ends of the overcurrent detection resistor is. When the voltage is set to 9 V, as a manufacturing variation, usually, the overcurrent detection resistance value varies by about ± 20% (24Ω to 36Ω), and the hFE of the output transistor chip 3 varies by about 80 to 200.

Accordingly, when the overcurrent detection resistance value is MAX. 36
When it becomes Ω, the overcurrent protection circuit 4 operates when the base current of the NPN transistor 5 is 25 mA. When this control IC chip 2 and the output transistor chip 3 with hFE = 80 are combined, the output current becomes 2
At A, overcurrent protection is applied. In the opposite case,
When the overcurrent detection resistance value is MIN. When the control IC chip 2 of 24Ω and the output transistor 3 of hFE = 200 are combined, the overcurrent protection is not activated unless the output current becomes 7.5A.

As described above, when two chips are randomly combined with normal variations, the characteristics often become considerably large.

Conventionally, in order to suppress the variation of the overcurrent detection point, the inspection standard of the corresponding item of each chip 2 and 3 (the inspection standard of the detection value in the overcurrent protection circuit for the control IC, and the output standard) In the case of a transistor, the reference value of the hFE is strictly set, or the heat radiation characteristics of the DC stabilized power supply 1 can be satisfied even if the chip combination characteristics are the worst (FIG. 2) in anticipation of variation. It is designed to be.

On the other hand, in a conventional semiconductor device production system, a semiconductor chip manufacturing process, a semiconductor chip test process (wafer test process), a semiconductor device manufacturing process, and the like are controlled by independent computers, respectively. The status and the work-in-progress stock status were managed.

Further, a chip manufacturing factory, a chip test factory, and a chip assembly factory are different.
There is a tendency that the physical distance between each factory and the assembly factories overseas is increasing.

[0015]

As described above, when a plurality of semiconductor chips are assembled into one device and manufactured as one semiconductor device, the characteristic variations in the manufacturing of each chip are integrated, and the semiconductor device is manufactured. Will result in a large variation. If the test standard of each chip is strict in order to suppress this variation, there arises a problem that the non-defective product rate (yield) of the chip decreases.

In addition, as for the characteristics required for the semiconductor device, stricter characteristics than before are required, and in order to cope with this, it is necessary to further strictly set the chip test standard. The problem that a rate falls further arises.

On the other hand, if one semiconductor device is manufactured by setting a relatively wide test standard for each of a plurality of chips to be assembled into one device, the resulting semiconductor device can have the integrated variation. Is gone.

For example, the stabilized DC power supply 1 shown in FIG.
In the case of (1), the dimensions (frame dimensions, etc.) of the apparatus itself are increased by the design that assumes the worst combination characteristic (design considering heat radiation characteristics).

The present invention has been made in view of such circumstances, and a semiconductor device capable of satisfying characteristics required for a semiconductor device without lowering the yield of each of a plurality of chips constituting the semiconductor device. The purpose is to provide a production method.

[0020]

According to the present invention, there is provided a method of assembling a plurality of chips into one device and producing the same as a single semiconductor device, using a wafer test information of a specific chip among the plurality of chips to be assembled. It is determined whether or not the chip characteristic value is within the reference value on a wafer or wafer lot basis. If the chip characteristic value is within the reference value, assembly is performed on a wafer or wafer lot basis. Also, if the chip characteristic value is not within the reference value, suspend the assembly,
When the number of the reserved wafers or the number of the reserved lots becomes equal to or larger than a preset number, the characteristic data of the reserved wafer or the reserved lot is transmitted to a semiconductor chip manufacturing process other than the specific chip, and It is characterized by changing the manufacturing conditions based on the transmission characteristic data.

According to the present invention, the chip constituting one device, for example, the hFE value of the output transistor chip can be used over a wide range, and the chip can be used without waste. In addition, if the number of die-bonding pending lots exceeds a certain number of lots, the information is periodically fed back to the chip manufacturing process, so accurate chip inventory management is possible without producing a large number of unmatched chips. become.

According to the present invention, in a method of assembling a plurality of chips into one device and producing as one semiconductor device, the characteristic value of each chip is within a reference value by using wafer test information of each of the plurality of chips to be assembled. It is determined whether or not each chip is included in each wafer or each wafer lot. If the characteristic value of each chip is within the reference value, the assembly of the chips is performed in each wafer or each wafer lot. In addition, for chips whose characteristic values are not within the reference values, the assembly is suspended,
The characteristic values of the plurality of pending chips are compared in units of wafers or wafer lots, and if there is a combination that satisfies the characteristics as a device, it is characterized by performing assembly with the combination.

According to the present invention, a chip that satisfies the characteristics as a device even when the characteristic values of the chips constituting one device, for example, the control IC chip and the output transistor chip do not fall within the reference values. The chip assembly is performed by selecting the combination of
Each characteristic value of the overcurrent detection resistance value of the C chip and the hFE value of the output transistor chip can be used in a wide range. Therefore, the chips can be used without waste.

In the present invention, of a plurality of types of pending chips, a wafer or a wafer lot of a chip having no combination satisfying the characteristics as a device is resuspended, and the number of reserved wafers or lots is set in advance. When the quantity becomes equal to or greater than the quantity, the characteristic data of the reserved wafer or the reserved lot is transmitted to the semiconductor chip manufacturing process other than the chip that has been re-reserved,
The manufacturing conditions in the semiconductor chip manufacturing process may be changed based on the transmission characteristic data.

If such processing is adopted, the information is periodically fed back to the chip manufacturing process when the number of die-bonding-pending lots exceeds a certain number of lots.
Accurate chip inventory management becomes possible without producing a large number of unmatched chips.

In each of the above inventions, a plurality of semiconductor chip manufacturing steps for individually manufacturing a plurality of chips to be assembled, a plurality of wafer test steps for performing a wafer test on each chip, and a device manufacturing step for performing an assembly are described. A connection may be made on a computer network such as the Internet so that the production-related information such as the wafer test information and the information on suspension of assembly may be transmitted and received between the respective steps.

If such a network system is constructed, a semiconductor chip manufacturing process, a wafer test process,
The device manufacturing process is controlled by independent computers, and even if the semiconductor chip manufacturing factory, wafer test factory, and device manufacturing factory are far apart, production of wafer test information, assembly pending information, and reserved lot characteristic data, etc. The related information can be mutually utilized between the factories, and the distance between the processes can be reduced.

If the semiconductor chip manufacturing process, the wafer test process, and the device manufacturing process are connected to a host computer via a computer network such as the Internet, wafer test information, assembly suspension information and suspension lots can be obtained. It is possible to collectively manage the exchange of production-related information such as characteristic data and control of each process. In addition, it is possible to build a system capable of receiving a customer's order through a host computer via the Internet and producing a semiconductor device (for example, a DC stabilized power supply) having the characteristics as ordered, meeting customer needs. Products can be produced in a timely manner.

According to the present invention, in a method of assembling a plurality of chips into one device and producing it as one semiconductor device, wafer test information of each of a plurality of chips to be assembled is used, and the test information corresponds to each other on a wafer. Characterization is performed by mapping in a positional relationship, selecting an optimal combination of chips that satisfies device characteristics based on the mapping test data, and assembling with the combination.

According to the present invention, even if there is a large variation in the manufacturing characteristics of each chip, the assembly is performed by selecting a chip combination that improves the total characteristics when a plurality of chips are combined. Can be solved by accumulating the characteristic variations of the above, and deteriorating the characteristics as an assembly.

In the present invention, the characteristic value of each chip is compared for each wafer or wafer lot using wafer test information of each of a plurality of chips to be assembled.
The mapping process may be executed after selecting a combination of wafers or wafer lots based on a predetermined criterion.

In the present invention, a plurality of semiconductor chip manufacturing processes for individually manufacturing a plurality of chips to be assembled, a plurality of wafer test processes for performing a wafer test for each chip, and a device manufacturing process for performing an assembly are
A connection may be made on a computer network so that production-related information such as the wafer test information and the mapping test data is transmitted and received between the respective steps.

If such a network system is constructed, a semiconductor chip manufacturing process, a wafer test process,
The device manufacturing process is controlled by independent computers, and even if the semiconductor chip manufacturing factory, wafer test factory, and device manufacturing factory are far apart, production related information such as wafer test information, mapping test data, and wafer lot comparison information. Information can be mutually used between the factories, and the distance between processes can be reduced.

If the semiconductor chip manufacturing process, the wafer test process, and the device manufacturing process are connected to a host computer via a computer network such as the Internet, the wafer test information, mapping test data, and wafer lot number can be obtained. It is possible to collectively manage exchange of production-related information such as comparison information and control of each process. In addition, it is possible to build a system capable of receiving a customer's order through a host computer via the Internet and producing a semiconductor device (for example, a DC stabilized power supply) having the characteristics as ordered, meeting customer needs. Products can be produced in a timely manner.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

In this embodiment, a DC stabilized power supply (FIG. 1) is constructed by combining two chips of an output transistor chip (PNP transistor chip) and a control IC chip.
2) shows an example in which the present invention is applied to a method for producing the same.

First, the steps in the case of manufacturing a stabilized DC power supply device are roughly classified, as shown in FIG. 3, as shown in FIG. 3, a control IC chip manufacturing step 11 and an output transistor chip manufacturing step 12. The wafer test processes 21 and 22 for individually performing the characteristic tests of the wafers manufactured in Step 12 and the device manufacturing process (DC stabilized power supply device manufacturing process) 30 are performed. These steps may be located in a single factory or may be distributed to remote factories.

The control IC chip manufacturing step 11 and the output transistor chip manufacturing step 12 include control sections 11a and 12a for controlling the respective steps, epitaxial steps 11b and 12b and their control sections, and isolation steps 11c and 11c. 12c and its control unit, the diffusion process and 11
d, 12d and their control units and interface 11
e, 12e and the like.

The wafer test processes 21 and 22 are respectively composed of test processes 21 a and 22 a and their control units,
1b and 22b, and interfaces 21c and 22c.

The device manufacturing process 30 includes the tested 2
In the step of converting one chip into one semiconductor device, a chip die bond combination control unit 30a, a transistor chip die bond step 30b, an Ic chip die bond step 3
0c, wire bonding step 30d, molding step 30
e, an interface unit 30f, and the like.

The interfaces 11e, 12e, 21c, 22c, and 30f of the above-described manufacturing steps 11 and 12, the wafer testing steps 21 and 22, and the device manufacturing step 30.
Is connected on a computer network such as the Internet, and can transmit and receive information between each process.

The details of the present embodiment will be described below.

First, the cause of variation in the overcurrent detection current of the stabilized DC power supply device is mainly the hFE of the output transistor chip. The reason for this is that the manufacturing variation of the detection resistor (overcurrent detection resistance value) in the overcurrent protection circuit of the control IC chip is relatively small, for example, in the range of 26 to 34Ω, while the output transistor The variation in the hFE characteristics of the chip in manufacturing is as large as, for example, about 80 to 200, and the variation in the hFE characteristics greatly affects the device characteristics.

Therefore, in this embodiment, the chip assembly is performed by the processing shown in FIG. 4 in consideration of the variation of the output transistor chip. 4 is performed by the chip die bond combination control unit 30a in the device manufacturing process 30.
Execute at

First, wafer test information (chip B test information) of an output transistor chip (chip B) transmitted via a computer network is received from wafer test step 22 (B test step) (ST).
1) It is determined whether or not a certain characteristic value is within a preset reference value (ST2).

Specifically, it is determined whether the hFE value of the wafer test information is in the range of 120 to 160. hFE
If the value is within the reference value, the wafer lot of the output transistor chip (chip B) is put into the transistor chip die bonding step 30b in the device manufacturing step 30 (S
T3). At this time, the wafer lot of the control IC chip having relatively small variation is also reduced to the Ic chip die bonding step
(ST4), and die bonding is performed with this combination (ST5).

When the hFE value is not within the reference value,
The wafer lot is put on hold in the die bonding step (ST6). When the number of reserved lots becomes equal to or greater than the preset number of lots, the characteristic data (hFE value) of the reserved lot is transmitted to the control IC chip manufacturing process 11 (A manufacturing process) (ST7).

Process 1 for manufacturing IC chip for controlling characteristic data
When 1 is received, the control unit 11a of the manufacturing process 11
The control unit in each of the steps 11b, 11c, and 11d is instructed to change the manufacturing conditions so as to match the received transmission data (hFE value) (ST8).

More specifically, if there are lots of reserved lots having a high hFE value, for example, 160 lots or more, the control IC
The control unit 11a in the chip manufacturing process 11 instructs a necessary process to change the manufacturing condition in a direction to increase the value of the detection resistor in the overcurrent protection circuit 4 (FIG. 1) of the control IC chip.

Die bonding is performed by combining the control IC chip wafer lot (A wafer lot) whose manufacturing conditions have been changed in this way with the output transistor chip wafer lot for which the die-bonding process input has been suspended (ST).
9).

According to this embodiment, the hFE value of the output transistor chip can be used over a wide range, and the chip can be used without waste. In addition, if the number of die-bonding pending lots exceeds a certain number of lots, the information is periodically fed back to the chip manufacturing process, so accurate chip inventory management is possible without producing a large number of unmatched chips. become.

Next, another embodiment of the present invention will be described.

This embodiment is an example of processing in a case where the variation in manufacturing characteristics is relatively large in both the control IC chip and the output transistor chip.

In this embodiment, the device manufacturing process 30
The process of FIG. 5 is performed by the chip die bond combination control unit 30a. The specific processing content will be described.

<Processing of Control IC Chip (Chip A)>
From the wafer test process 21 (A test process), wafer test information (chip A test information) of the control IC chip transmitted via the computer network is received (STa1), and a certain characteristic value is set to a predetermined reference. It is determined whether the value is within the value (STa2).

Specifically, it is determined whether or not the overcurrent detection resistance value in the wafer test information is in the range of 28 to 32Ω. If the overcurrent detection resistance value is within the reference value, the control IC
The wafer lot of the chip is determined by the I in the device manufacturing process 30.
c chip die bonding step 30b (STa
3). If the overcurrent detection resistance value of the control IC chip is not within the reference value, the wafer lot is
Suspend the input to the die bonding process (reservation A1) (ST
a4).

<Output Transistor Chip (Chip B)
Processing> From wafer test step 22 (B test step),
It receives wafer test information (chip B test information) of the output transistor chip (chip B) transmitted via the computer network (STb1) and determines whether or not a certain characteristic value is within a preset reference value. A determination is made (STb2).

Specifically, it is determined whether the hFE value of the wafer test information is in the range of 120 to 160. hFE
If the value is within the reference value, the wafer lot of the output transistor chip is put into the transistor chip die bonding step 30b in the device manufacturing step 30 (STb3). If the hFE value of the output transistor chip does not fall within the reference value, the wafer lot is put on hold in the die bonding step (hold B1) (STb4).

<Die Bonding Process> Die bonding is performed by combining the wafer lot input to the Ic chip die bonding process 30b in the process of step STa3 with the wafer lot input to the transistor chip die bonding process 30b in the process of step STb3 ( STc
1).

<Combination processing> Wafer lot of control IC chips for which the die bonding process input has been suspended (reservation A1)
Is compared with the characteristic values of the wafer lot (reservation B1) of the output transistor chips for which the input of the die bonding process is suspended (STa5, STb5), and if there is a combination that satisfies the characteristics as a device, The wafer lot is put into the die bonding process (STa6, STb
6), die bonding is performed with the combination (STc)
2).

<Process for Changing Manufacturing Conditions> Step STa
If there is no combination that satisfies the characteristics as a device in the processing of STb5 and STb5, the wafer lots of these uncombinable chips are re-reserved (reservation A2, reservation B2) for the die bonding process (STa).
7, STb7).

Next, when the number of reserved lots of the control IC chip (reserved A2) is equal to or larger than the preset number of lots, the characteristic data of the reserved lot (overcurrent detection resistance value)
To the output transistor chip manufacturing process 12 (B manufacturing process) (STa8). When the output transistor chip manufacturing process 12 receives the characteristic data, the control unit 12a of the manufacturing process 12 controls the processes 12b, 12c, 12
The controller d instructs the manufacturing conditions to match the reception characteristic data (overcurrent detection resistance value) (STa
9). Specifically, when there is a reserved lot having a small overcurrent detection resistance value, for example, a resistance value of 28Ω or less, the control unit 12a of the output transistor chip manufacturing process 12 may reduce the hFE value of the output transistor chip. Of necessary manufacturing steps is instructed.

In this way, die bonding is performed by combining the wafer lot of the output transistor chip whose manufacturing conditions have been changed and the wafer lot of the control IC chip (reservation A 2) for which the input of the die bonding process has been re-reserved (S 2).
Ta10).

On the other hand, when the number of reserved lots of output transistor chips (reserved B 2) is equal to or larger than the preset number of lots, the characteristic data (hFE value) of the reserved lot is converted to the control IC chip manufacturing process 11 (A). (STb8). When the control IC chip manufacturing process 11 receives the characteristic data, the control unit 11a of the manufacturing IC 11
Instructs the control unit of each step 11b, 11c, 11d to change the manufacturing conditions so as to match the received transmission data (hFE value) (STb9). Specifically, those with a high hFE value in the reserved lot. For example, when there are 160 or more, the control unit 11a of the control IC chip manufacturing process 11
Instructs the necessary process to change the manufacturing conditions in the direction of increasing the value of the detection resistor in the overcurrent protection circuit 4 (FIG. 1).

In this manner, die bonding is performed by combining the control IC chip wafer lot whose manufacturing conditions have been changed and the output transistor chip wafer lot (reservation B2) for which the die bonding process has been re-pended (S2).
Tb10).

According to this embodiment, even when the characteristic values of the control IC chip and the output transistor chip do not fall within the reference values, a combination of chips that satisfies the characteristics as a device is selected. Therefore, the characteristic values of the overcurrent detection resistance value of the control IC chip and the hFE value of the output transistor chip can be used in a wide range. Therefore, the chips can be used without waste. In addition, if the number of die-bonding pending lots exceeds a certain number of lots, the information is periodically fed back to the chip manufacturing process, so accurate chip inventory management is possible without producing a large number of unmatched chips. become.

In the above two embodiments, the case where two chips are combined into one device has been described. However, the same processing can be performed when three or more chips are combined.

For example, when three chips are combined, two chips A and B may be processed as chip A shown in FIG. 4, and another chip C may be processed as chip B shown in FIG. . In this case, the characteristic data of the reserved lot of the chip C may be transmitted to the control unit of the manufacturing process of the chips A and B, or may be transmitted to the control unit of one of the chip manufacturing processes. The choice is
What is necessary is just to judge which of the manufacturing processes of the chips A or B should be changed in order to better match the reserved lot of the chip C.

Next, another embodiment of the present invention will be described.

This embodiment also shows an example in which the present invention is applied to a method of producing a stabilized DC power supply device by combining two chips, an output transistor chip and a control IC chip. The process of producing the stabilized DC power supply device is the same as that shown in FIG. 3 described above, and the description thereof is omitted here.

This embodiment is characterized by processing in the case where the manufacturing characteristics of the control IC chip and the output transistor chip are relatively large within one wafer.

Specifically, the processing shown in FIG. 6 is performed by the chip die bond combination control unit 30a of the device manufacturing process 30 shown in FIG.
To perform assembly processing. The processing content will be described below.

First, from the wafer test step 21 (A test step), wafer test information (chip A test information) of the control IC chip (chip A) transmitted via the computer network is received (STa 21). Using the wafer test information, each position on the wafer is mapped 1: 1 with the characteristic value (overcurrent detection resistance value) of each chip, and the mapping test data D shown in FIG.
A is created (STa22).

Further, from the wafer test step 22 (B test step), wafer test information (chip B test information) of the output transistor chip (chip B) transmitted via the computer network is received (STb2).
1) Using the wafer test information, each position on the wafer is mapped 1: 1 with the characteristic value (hFE value) of each chip, and the mapping test data D shown in FIG.
B is created (STb22).

Next, the mapping test data DA and the mapping test data DB are compared with each other to select an optimum combination of chips that satisfies the characteristics as a device (STc21), and die bonding is performed with the combination (STc22).

The method of die bonding in the optimum combination is as follows: [Base current for overcurrent operation of control IC chip]
X [hFE value of output transistor chip] 3 to 5
For example, there is a method of selecting a pair which is a combination of A and die-bonding two chips. Specifically, in the example of FIG. 1 and output transistor chip: No. 21 and control I
C chip: No. 1 and output transistor chip: N
o. A method of selecting a combination with 21 and die-bonding each pair is adopted.

As described above, the characteristics of the control IC chip having a large overcurrent detection resistance value and the h
The two chips are combined by selecting a combination of characteristics with a large FE or a combination of a characteristic with a small overcurrent detection resistance value of the control IC chip and a characteristic with a small hFE of the output transistor chip. In this case, the total overcurrent protection points cancel each other, and the variation of each point can be suppressed.

Here, since the characteristics of the chips tend to be biased in units of wafer lots, it is more efficient to first set the combinations in units of wafer lots and then to perform die bonding by the above mapping method.

As a method of setting a combination for each wafer lot, there is the following combination method. (1) A lot in which the average value of the overcurrent detection resistance value is large for each wafer lot of the control IC and a lot in which the average value of the hFE value is large for each wafer lot of the output transistors are combined. (2) A lot in which the average value of the overcurrent detection resistance value is small in a wafer lot unit of the control IC and a lot in which the average value of the hFE value is small in a wafer lot unit of the output transistor are combined. (3) A lot in which the average value of the overcurrent detection resistance value is an intermediate value for each wafer lot of the control IC and a lot in which the average value of the hFE values is an intermediate value for each wafer lot of the output transistors.

It is also possible to use a combination method in which a combination is set not for each wafer lot but for each wafer, and the data amount of each is reduced.

In the embodiment shown in FIG. 6, a case where two chips are combined into one device has been described.
Similar processing can be performed even when three or more chips are combined.

In each of the above embodiments, the control I
The DC stabilized power supply device in which the C chip and the output transistor chip are combined has been described. However, as another device in which the characteristics of the semiconductor device are determined by the combination of a plurality of chips, for example, a light emitting diode and a light receiving element are combined.
There are a photocoupler made into a device, a photointerrupter made into a device by combining a light emitting diode and a light receiving element, and the like.

In the photocoupler, since the characteristics of the CTR are determined by the combination of the light emitting diode and the light receiving element, the combination can be selected so that the optimum CTR can be obtained, and there is a great effect in improving the yield and the like.

In the photointerrupter, by optimizing the combination of the light emitting diode and the light receiving element, there is a great effect on the detection sensitivity and the influence of disturbance noise.

[0085]

As described above, according to the present invention,
Judge whether chip characteristic value by wafer test is within the reference value in wafer lot units, etc., and if the chip characteristic value is not within the reference value, suspend assembly and set the number of reserved lots in advance If the quantity exceeds the specified quantity, the characteristic data of the reserved lot is sent to the manufacturing process of other chips that make up the device to change the manufacturing conditions, or for the chip whose characteristic value is not within the reference value. Suspends assembly, compares the characteristic values of multiple types of pending chips on a wafer or wafer lot basis, and if there is a combination that satisfies the characteristics as a device, performs assembly with that combination. It can be used over a wide range of characteristic values of each chip constituting one device, and chips can be used without waste. That.

Further, according to the present invention, wafer test information of each of a plurality of chips to be assembled is used, and the test information is mapped on a wafer in a positional relationship corresponding to each other. The optimal combination of chips that satisfies the characteristics as described above is selected, and assembly is performed with that combination, so that even if there is large variation in the manufacturing characteristics of each chip, the total characteristics when multiple chips are combined are improved. And the chip can be used without waste.

Therefore, according to the present invention, it is possible to satisfy strict characteristics required for a semiconductor device without lowering the yield of each of a plurality of chips constituting the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a stabilized DC power supply device.

FIG. 2 is a graph showing output characteristics of the stabilized DC power supply device.

FIG. 3 is a block diagram illustrating a production process of the stabilized DC power supply device.

FIG. 4 is a flowchart showing the contents of processing executed in the embodiment of the present invention.

FIG. 5 is a flowchart showing the contents of processing executed in another embodiment of the present invention.

FIG. 6 is a flowchart showing the contents of processing executed in another embodiment of the present invention.

FIG. 7 is an explanatory diagram of a combination process executed in another embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 DC stabilized power supply (low-loss regulator) 2 control IC chip 3 output transistor chip 4 overcurrent protection circuit 5 NPN transistor 11 control IC chip manufacturing process (process A) 12 output transistor chip manufacturing process (process B) 21) Wafer test process (A test process) 22 Wafer test process (B test process) 30 Device manufacturing process

Claims (8)

[Claims] 1. A method of assembling a plurality of chips into one device and producing as one semiconductor device, wherein a chip characteristic value is within a reference value by using wafer test information of a specific chip among the plurality of chips to be assembled. Judgment is made on a wafer or wafer lot basis, and if the chip characteristic value is within the reference value, assembly is performed on a wafer or wafer lot basis, and the chip characteristic value is not within the reference value In this case, the assembly is suspended, and when the number of the reserved wafers or the number of the reserved lots becomes equal to or greater than a preset amount, the characteristic data of the reserved wafer or the reserved lot is transmitted to a semiconductor chip manufacturing process other than the specific chip. Changing the manufacturing conditions in the semiconductor chip manufacturing process based on the transmission characteristic data. A method for producing a semiconductor device comprising a plurality of chips. 2. A method of assembling a plurality of chips into one device and producing as one semiconductor device, wherein a characteristic value of each chip falls within a reference value using wafer test information of each of the plurality of chips to be assembled. Is determined for each wafer or wafer lot.If the characteristic value of each chip is within the reference value, the assembly of those chips is performed for each wafer or wafer lot, and the characteristic value is within the reference value. The assembly is suspended for chips that are not included, and the characteristic values of multiple types of pending chips are compared for each wafer or wafer lot, and if there is a combination that satisfies the characteristics as a device, the assembly is combined with that combination. A method for producing a semiconductor device comprising a plurality of chips. 3. Among a plurality of types of pending chips, for a wafer or a wafer lot of a chip having no combination that satisfies the characteristics as a device, the assembly is re-reserved, and the number of retained wafers or lots is a preset number. When the above is reached, the characteristic data of the reserved wafer or the reserved lot is transmitted to the semiconductor chip manufacturing process other than the re-reserved chip, and the manufacturing conditions in the semiconductor chip manufacturing process are determined based on the transmission characteristic data. 3. The method according to claim 2, wherein the semiconductor device comprises a plurality of chips. 4. A plurality of semiconductor chip manufacturing processes for individually manufacturing a plurality of chips to be assembled, a plurality of wafer test processes for performing a wafer test for each chip, and a device manufacturing process for performing an assembly on a computer network. 4. The method for producing a semiconductor device comprising a plurality of chips according to claim 1, wherein said semiconductor device is connected to each other, and said production-related information such as said wafer test information and information on assembly suspension is transmitted and received between respective steps. 5. A method for assembling a plurality of chips into one device and producing as one semiconductor device, wherein wafer test information of each of a plurality of chips to be assembled is used, and the test information is placed on a wafer in a positional relationship corresponding to each other. A method for producing a semiconductor device comprising a plurality of chips, wherein a chip of an optimal combination that satisfies the characteristics as a device is selected based on the mapping test data, and an assembly is performed by the combination. 6. Using the wafer test information of each of a plurality of chips to be assembled, comparing the characteristic values of each chip in a unit of a wafer or a unit of a wafer lot, and selecting a combination of a wafer or a wafer lot based on a predetermined criterion. 6. The method according to claim 5, wherein the mapping process is performed. 7. A plurality of semiconductor chip manufacturing processes for individually manufacturing a plurality of chips to be assembled, a plurality of wafer test processes for performing a wafer test for each chip, and a device manufacturing process for performing an assembly on a computer network. 7. The method for producing a semiconductor device comprising a plurality of chips according to claim 5, wherein said semiconductor device comprises a plurality of chips connected to each other to transmit and receive production-related information such as said wafer test information and mapping test data. 8. A plurality of semiconductor chip manufacturing processes for individually manufacturing a plurality of chips to be assembled, a plurality of wafer test processes for performing a wafer test of each chip, and a device manufacturing process for performing an assembly via a computer network. 7. The method for producing a semiconductor device comprising a plurality of chips according to claim 1, wherein the method is connected to a host computer, and the respective steps are collectively managed by the host computer.