JP2002092065A - Method for designing circuit and device for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit designing method and device for effectively reducing power consumption by selectively gated clocking an F/F. SOLUTION: This method comprises a step (2) for searching the operation condition of an F/F by analyzing RTL description, and for extracting an enable signal, a step (3) for changing the RTL description into RTL description indicating the corresponding relation of the enable signal and the F/F, a step (5) for inputting the changed RTL description and test vectors, and for simulating this circuit, a step for searching an active rate being a rate at which an enable state is obtained from the simulated result, a step (7) for changing the F/F to the gated clocked F/F based on the active rate, and a step (8) for outputting the result as the RTL description.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit design method and a circuit design apparatus for converting an F / F (flip-flop) whose contents are updated in synchronization with a clock signal into a gated clock when an enable signal is in an enable state. .

[0002]

2. Description of the Related Art Hitherto, it has been known that in an F / F operating in synchronization with a clock signal, the F / F is converted into a gated clock in order to reduce power consumption. For example, a case where the circuit shown in FIG. 8 is converted into a gated clock as shown in FIG. 9 will be described. In FIG. 8, when the enable (en) signal is enabled, the multiplexer (M
UX) 101, the input (d1, d2) selected by MUX 10 or the enable signal is disabled.
Output of F / F 102 selected by 1 (q1, q2)
Is taken in and held by the F / F 102 in synchronization with the clock signal (clk), and the held content is stored in the F / F 102
Output from In the configuration shown in FIG. 8, F / F1
02 is two for convenience, but it is assumed that there are many.

In such a configuration, the frequency of the active state of the enable signal is low, the output (q1, q2) of the F / F 102 is not updated so much, and the number of F / Fs operated by the same enable signal is reduced. As shown in FIG. 9, the clock signal (clk) is input to the F / F 102 only when the enable signal is in the active state. That is, the active state of the enable signal is latched by the latch circuit 103 in synchronization with the low level of the clock signal, and the clock signal is supplied to the F / F 102 via the AND gate 104 having the latched enable signal as one input. / F102 is gated clock. Accordingly, the F / F 102 is not supplied with the clock signal when the content of the F / F 102 is not updated while the enable signal is disabled, and does not operate in synchronization with the clock signal, thereby reducing power consumption. Becomes

In recent years, in order to improve the efficiency of circuit design, LSIs are often designed by describing a circuit configuration using a hardware description language (HDL) by, for example, RTL (Register Transfer Level) description. It has become to. FIGS. 10 and 11 show Ver, which is one of the HDLs.
F / F10 using ilog (registered trademark) -HDL
What is the value of F / F10 when 2 makes one clock transition
FIG. 10 is a diagram showing an RTL description indicating whether or not the RTL is to be assigned to 2, and FIG. 10 is an RTL description having a configuration shown in FIG. 9 and FIG. 11 is an RTL description having a configuration shown in FIG. Therefore, as described above, the circuit design for converting the F / F into a gated clock is also performed at the stage of designing the LSI based on the RTL description.

[0005] Therefore, F / F is effective in reducing power consumption.
In order to convert only F into a gated clock, it is necessary to extract an enable signal of each F / F and obtain an active ratio of a ratio in which the extracted enable signal is in an enabled state. However, on the RTL description, F /
In the conventional circuit design in which F is gated clock, the above-described operation has not been performed.

Further, in the conventional circuit design in which the F / F is gated clocked on the RTL description, the gated clocking of the F / F is performed in the process of logic synthesis for converting the RTL description to a gate level. Thus, the circuit design result of the gated clock was output in the gate level HDL description. Therefore, it is difficult to change the design again based on the output circuit design result.

[0007]

As described above,
In a conventional circuit design in which an F / F is gated clock, a simulation for reliably extracting an enable signal of the F / F from an RTL description of the circuit and accurately obtaining an active rate of the extracted enable signal has not been performed. Was. Therefore, based on the accurate active rate, the F / F
It is difficult to selectively generate a gated clock. In addition, since the circuit design result is output in the form of a gate-level description, there is a problem that it is difficult to change the design based on the output result.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to selectively convert a F / F into a gated clock based on an accurately obtained active rate, thereby reducing power consumption. It is an object of the present invention to provide a circuit design method and a circuit design device which can be reduced in number.

It is another object of the present invention to provide a circuit design method and a circuit design apparatus which can easily change the design of the gated clock of the F / F.

[0010]

In order to achieve the above object, a first means for solving the problem is a first F / F whose contents are updated in synchronization with a clock signal when an enable signal is in an enable state. An RTL description of a circuit including the first F / F, using a circuit design method for changing an F (flip-flop) to a second F / F in which the clock signal is gated based on the enable signal. Is input, the RTL description is analyzed to determine the first F / F operating condition, and the first F / F enable signal is extracted based on the first F / F operating condition. A first step and the RTL description input in the first step
A second step of changing to an RTL description indicating a correspondence relationship between the enable signal extracted in the first step and the first F / F corresponding to the enable signal;
A third step of inputting the RTL description and the test vector changed in the step of simulating the circuit including the first F / F, and as a simulation result of the third step, the first F / F A fourth step of obtaining an active ratio of a ratio at which the enable signal given to the F becomes an enable state, and the first F / F based on the active ratio of the enable signal obtained in the fourth step. And a fifth step of selectively changing to the second F / F.

[0011] The second means is the first means,
After selectively changing the first F / F to the second F / F in the fifth step, a sixth step of outputting a circuit after gated clocking in RTL description is provided. And

The third means includes a first F / F (flip-flop) whose contents are updated in synchronization with a clock signal when the enable signal is in an enable state, wherein the first F / F is gated based on the enable signal. A circuit design apparatus for changing to a clocked second F / F,
An RTL description of a circuit including the first F / F is input, and the RTL description is analyzed to obtain an operating condition of the first F / F. Extracting an enable signal of the first F / F based on the input RTL description, and converting the input RTL description into an RTL description indicating a correspondence relationship between the extracted enable signal and the first F / F corresponding to the enable signal. An extractor that outputs a changed RTL description, and an RTL description and a test vector output from the extractor are input, and a circuit including the first F / F is simulated, and the first F / F is simulated. A simulation unit for determining an active ratio of a ratio at which the enable signal given to F is in an enable state; and an active ratio of the enable signal determined by the simulation unit. Wherein 1 the F / F selectively the second F
/ F for changing to / F.

A fourth means is the third means,
The gated clocking change unit outputs the circuit after the gated clocking in RTL description.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a circuit design apparatus according to one embodiment of the present invention, and FIG. 2 is a flowchart showing the operation of the apparatus shown in FIG. In FIG. 1, a circuit design apparatus receives an RTL description and a test vector corresponding to a circuit before gated clocking, and outputs an RTL description corresponding to a circuit after gated clocking. An enable (en) signal It comprises an extraction unit 2, a simulation unit 5, and a gated clocking change unit 7. The enable signal extraction unit 2 inputs and analyzes the RTL description 1 of the circuit before the gated clock conversion, and assigns what value to all F / Fs under what conditions. All the operating conditions are extracted, the enable signal of each F / F is extracted, and an RTL description 3 representing the correspondence between each F / F and the corresponding enable signal is output. Simulation unit 5
Receives the RTL description 3 output from the enable signal extraction unit 2 and a test vector 4 serving as a test input for simulating a circuit, performs circuit simulation, and obtains an active ratio of an enable signal of each F / F. Output as simulation result 6. The gated clocking change unit 7 receives the RTL description 3 output from the enable signal extraction unit 2 and the simulation result 6 output from the simulation unit 5, and has a large number of F / Fs that operate with the same enable signal, and An F / F with a low active ratio of the F / F enable signal is detected from the simulation result, the detected F / F is gated clocked, and the result is output as an RTL description 8.

Next, a circuit design procedure in such a configuration will be described with reference to FIG. 2 and the RTL description shown in FIGS.

For example, an RTL description (step S1) of the circuit before the gated clock as shown in FIG. 3 is input to the enable signal extraction unit 2 (step S2), and the syntax of the RTL description is analyzed. As a result of the analysis, what values are substituted under what conditions (operating conditions) for all F / Fs are extracted. As a result of the analysis, as shown in FIG. 4, n Fs from q [0] to q [n-1] are obtained.
Condition where the value of / F is the same (cond1), and! (Cond
1) &&! It is updated under (cond2) && (cond3), and the exception is the F / F value of q [i]!
It is found that the update has been performed under (cond1) && (cond2). Based on these analysis results, FIG.
As shown in (1), the enable signal of each F / F is extracted, and the RTL description 1 input to the enable signal extraction unit 2 is rewritten into the RTL description that the value of the F / F is updated by the extracted enable signal. , Rewritten RT
The L description is output from the enable signal extraction unit 2 (Step S3).

R output from the enable signal extraction unit 2
The TL description 3 is provided to the simulation unit 5 together with the test vector, and a circuit simulation is performed.
The active ratio of the enable signal is obtained and output as a simulation result (step S5). Here, the active ratio of the enable signal indicates the ratio of the period during which the enable signal is in the enable state in the circuit simulation period using the test vector.

R output from the enable signal extractor 2
In the TL description 3, it is determined whether or not an assignment statement to F / F exists (step S4). If the assignment statement exists, the result of the simulation performed by the simulation unit 5 (step S5) is performed. Therefore, the number of F / Fs and the active rates of the enable signals of the F / Fs are obtained (step S6), and it is determined whether or not the F / Fs are gated clock based on the number of F / Fs and the active rate. (Step S7). For example, when the active ratio of the F / F is high, the process returns to step S4 without performing the gated clock. On the other hand, when the gated clock is used, the active ratio of the enable signal is different from that of other F / Fs.
Is determined (step S8). If not, all F / Fs are similarly gated clocked (step S9).

On the other hand, if there is an F / F in which the active ratio of the enable signal is different from the others, the clock is selectively gated according to the active ratio of the F / F (step S10). In such a case, in order to more effectively reduce the power, all the F / Fs are gated clocked, including the F / Fs in which the active ratio of the enable signal is different from the others, and all the F / Fs are gated. Operate in synchronization with the clock. In such a case, R
FIG. 6 shows the TL description. In FIG. 6, n F / Fs from q [0] to q [n-1] are similarly gated clocked. This method has an effect of reducing power when the active ratio of the enable signal of the F / F whose active ratio is different from the others is not so different from the others. Or
F / Fs in which the activation rate of the enable signal is different from the others are not gated clocked, or gated clocking is performed separately even if gated clocking is performed. FIG. 7 shows an RTL description of the circuit in such a case. In FIG. 7, q [0] to q [i-1], q [i
+1] to q [n-1] (n-1) F / Fs are similarly gated clocked, and q
The F / F in [i] is gated clocked. This method is effective when the active ratio of the F / F enable signal is higher than the others. In any case, the method to be used is determined based on the active ratio and the number of F / F enable signals.

As described above, the conversion of the F / F to the gated clock is advanced, and if there is no assignment statement in the RTL description output from the enable signal extraction unit 2, the F / F after the conversion of the F / F to the gated clock is used. The RTL description is output (step S11), and the gated clock of the F / F ends.

As described above, in the above embodiment, the enable signal of each F / F is extracted before the simulation of the circuit using the test vector is performed, so that an accurate active ratio can be obtained. . Then, by using the acquired active rate, only the F / F that is effective in reducing the power consumption can be turned into a gated clock. In addition, when the gated clock is used, if there is an F / F whose value is substituted by an enable signal different from the enable signal of another F / F, the gated clock is integrated with or separated from the other F / F. By doing so, power consumption can be reduced more effectively. Furthermore, by outputting the RTL description of the circuit after the gated clock, the designer can easily change the design again so as to reduce the active ratio of the enable signal as compared with the gate level description. .

[0023]

As described above, according to the present invention, the F / F is selectively gated based on the active ratio of the enable signal of each F / F. Power consumption can be effectively reduced. Also. Since the circuit after the gated clock is output in the RTL description, the design can be easily changed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a circuit design device according to an embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the apparatus shown in FIG.

FIG. 3 is a diagram illustrating an example of an RTL description of a circuit input to a circuit design device.

FIG. 4 is a diagram showing an analysis result of the RTL description shown in FIG. 3;

FIG. 5 is a diagram showing an RTL description in which an enable signal is extracted from the RTL description shown in FIG. 3;

FIG. 6 is a diagram showing an RTL description of a gated clock circuit.

FIG. 7 is a diagram illustrating an RTL description of another gated clock circuit.

FIG. 8 is a diagram showing a conventional configuration of a circuit before gated clocking.

9 is a diagram showing a configuration in which the circuit shown in FIG. 8 is converted to a gated clock.

FIG. 10 is a diagram showing an RTL description of the circuit shown in FIG. 9;

FIG. 11 is a diagram showing an RTL description of the circuit shown in FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 RTL description before gated clock 2 Enable signal extraction part 3 RTL description which extracted enable signal 4 Test vector 5 Simulation part 6 Simulation result 7 Gated clock change part 8 RTL description after gated clock

Claims (4)

[Claims] 1. A first F / F whose contents are updated in synchronization with a clock signal when an enable signal is in an enable state.
(Flip-flop) is connected to a second gate in which the clock signal is gated based on the enable signal.
A circuit design method for changing to the F / F of the above, inputting an RTL description of a circuit including the first F / F, analyzing the RTL description to obtain an operating condition of the first F / F, The first F / F is operated based on the operating conditions of the first F / F.
A first step of extracting an enable signal of the F / F of the RTL description;
Indicating the correspondence between the enable signal extracted in the step and the first F / F corresponding to the enable signal.
A second step of changing to an L description, a third step of inputting the RTL description and the test vector changed in the second step, and simulating a circuit including the first F / F; A fourth step of obtaining, as a simulation result of the third step, an active ratio of a ratio at which the enable signal given to the first F / F is in an enabled state; and an enable signal of the enable signal obtained in the fourth step. A fifth step of selectively changing the first F / F to the second F / F based on an active ratio. 2. The first F / F in the fifth step.
6. The circuit design method according to claim 1, further comprising the step of: after selectively changing the second F / F to the second F / F, outputting the circuit after the gated clock in RTL description. 3. A first F / F whose contents are updated in synchronization with a clock signal when the enable signal is in an enable state.
(Flip-flop) is connected to a second gate in which the clock signal is gated based on the enable signal.
A RTL description of a circuit including the first F / F, analyzing the RTL description to obtain an operating condition of the first F / F, The enable signal of the first F / F is extracted based on the obtained operating condition of the first F / F, and the input RTL description is converted to the extracted enable signal and the first signal corresponding to the enable signal. An RTL description that indicates the correspondence between the first F / F and the test vector; and an extractor that outputs the changed RTL description and an RTL description and a test vector that are output from the extractor. A simulation section for simulating a circuit including: a simulation section for calculating an active ratio of a ratio at which the enable signal applied to the first F / F is in an enable state; Based on the active ratio of the enable signal, the circuit design apparatus characterized by having a gated clock changing unit for changing the first the F / F selectively the second the F / F. 4. The circuit design apparatus according to claim 3, wherein the gated clocking change unit outputs the circuit after the gated clocking in an RTL description.