JP2002083968A - Input/output protective circuit, liquid-crystal display device, and image display application device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input/output protective circuit having more stable TFT characteristics which is best for a liquid-crystal display device. SOLUTION: There are provided a first input/output protective transistor 14 comprising an N-type thin-film transistor with no LDD structure which has a yield voltage and a hold voltage lower than a TFT of N-type LDD structure constituting a switching element used for driving pixels, a second input/output protective transistor 15 which comprises, having a yield voltage and a hold voltage lower than the TFT of N-type LDD structure, a P-type thin-film transistor with no LDD structure and is complimentary-connected to the first input/ output protective transistor, and a resistance element 16 for by-passing the excessive current between source electrodes of the first and second input/output protective transistors and an external electrode or the liquid-crystal display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology and a structure for incorporating an input / output protection circuit as a countermeasure against static electricity such as current surge and voltage noise in a liquid crystal display device using a glass substrate.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display device using a thin film transistor (hereinafter, referred to as a TFT) made of low-temperature polycrystalline silicon, a switching TFT provided at each pixel position, a driving circuit of a liquid crystal panel, and input protection. The circuit is an N-type impurity low-concentration implantation drain (hereinafter, N-type LD
D) (hereinafter referred to as N)
(Referred to as type LDD / TFT).

FIG. 4 is an equivalent circuit diagram showing a configuration of an input / output protection circuit having a conventional structure. In FIG. 4, resistors R1 to R3,
An input / output protection circuit 40 including input / output protection transistors 42 and 43 is provided. A current surge and voltage noise applied to the pad 41 are absorbed by the input / output protection circuit 40 and the input / output protection circuit 40 A predetermined voltage for driving is supplied to signal electrodes, scanning electrodes, counter electrodes, and the like.

The input / output protection transistors 42, 4
3 and the input first-stage transistor 44 have an LDD structure T
FT. When these TFTs are used in a liquid crystal display device, thin film transistors and the like are not formed on a semiconductor substrate such as silicon as in a general semiconductor element, but are formed on a glass substrate by ordinary photolithography or etching. This is a TFT formed on a polycrystalline silicon thin film. In the TFT of such a liquid crystal display device, the channel layer is made of an intrinsic semiconductor (silicon without added impurities, etc.), and a reference potential is not given to the glass substrate, that is, to the channel layer in many cases.

[0005] Next, TFT snapback (Snap Bac
k) The phenomenon will be described with reference to FIGS. FIG. 5 is a cross-sectional view of a conventional TFT having an LDD structure, and FIG. 6 is a diagram showing snapback characteristics based on a relationship between a drain-source voltage (applied voltage: Vds) and a current (Ids).

First, a method for manufacturing the TFT having the LDD structure shown in FIG. 5 will be described.

First, a polycrystalline silicon thin film is formed on an undercoat 51 made of an insulator such as a CVD (chemical vapor deposition) oxide film, and a gate insulating film 52 is formed thereon. Next, a conductive film to be used as a gate material is formed,
The gate electrode 53 is formed using ordinary photolithography or etching. Using the pattern of the gate electrode 53 as a mask, a low-concentration impurity is doped into the polycrystalline silicon layer to form a drain region 54 and a source region 55, and an intermediate region between them is a channel region 56. Lastly, for example, 1.0 (μ)
m) A resist is patterned by photolithography in the expanded region, and source / drain implantation of N-type impurities is performed in other regions.

The LDD structure TF manufactured as described above
For T, the source is a low-potential power supply Vss (generally Gn
d) and the control voltage Vcnt is applied by commonly connecting the drain and the gate. By varying the control voltage Vcnt, the applied voltage Vds between the drain and the source is controlled, and a change in Ids flowing between the drain and the source is examined.

As a result, the current I with respect to the applied voltage Vds
ds changes as shown in FIG. As can be seen from FIG. 6, the applied voltage is once changed to BVds at point P in the figure.
When the voltage exceeds the (breakdown voltage), the current starts to flow rapidly, and the current does not decrease even when the applied voltage is equal to or lower than BVds. When the applied voltage is increased, the current decreases. Then, when the applied voltage is further reduced from BVds and becomes lower than the voltage at the point Q in the figure, the secondary breakdown occurs in which the current increases when the applied voltage is increased. Such a phenomenon is called snapback. Such a snapback characteristic is also called a bipolar action of a MOS transistor. Here, the voltage at point Q in the figure is called a hold voltage (HVds), and the current flowing at that time is called a hold current (HIds).

If the density difference between the drain of the TFT and the substrate (channel) is large, the snapback characteristic changes from a solid line to a broken line as shown in FIG. That is, the breakdown voltage BVds decreases, and the hold voltage HVd
s is also low. This type of TFT is referred to herein as a non-LDD TFT.

[0011]

A TFT in which both the breakdown voltage BVds and the hold voltage HVds shown in FIG. 6 are increased.
Is optimally used as a TFT for driving a liquid crystal cell, but is not suitable for use as the input / output protection transistors 42 and 43 shown in FIG. The reason is that P
This is because the TFT of the type has a lower driving force than the N-type, has no passage path for the surge current, and has a large variation in parameters such as the threshold voltage Vt and the breakdown voltage BVds of the TFT because the potential is not fixed in the channel portion. .

On the other hand, as described above, a TFT used in a liquid crystal display device using a glass substrate, which is an insulator, has a problem that the TFT characteristics become unstable because the substrate potential cannot be fixed.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide an input / output protection circuit having a more stable TFT characteristic which is optimal for use in a liquid crystal display device, and a liquid crystal display device using the same. And an image display application device using the liquid crystal display device.

[0014]

In order to achieve the above object, in a first input / output protection circuit according to the present invention, a switching element used for driving each pixel has a low-concentration impurity-implanted drain structure (LDD structure). An input / output protection circuit for a liquid crystal display device including an N-type thin film transistor (N-type LDD structure TFT), which has a lower breakdown voltage and hold voltage than an N-type LDD structure TFT and does not have an LDD structure. N-type thin film transistor (N-type non-LDD structure T
FT) and an N-type L
The second input / output protection transistor comprises a P-type thin film transistor (P-type non-LDD structure TFT) having a breakdown voltage and a hold voltage lower than that of the DD structure TFT and having no LDD structure, and complementary to the first input / output protection transistor. An input / output protection transistor; and a resistance element formed between each source electrode of the first and second input / output protection transistors and an external electrode of the liquid crystal display device for bypassing an overcurrent. I do.

In this input / output protection circuit, it is preferable that the resistance element is constituted by a wiring pattern of a light shielding layer formed on a glass substrate of the liquid crystal panel.

In this case, the wiring pattern of the light-shielding layer surrounds the display portion of the liquid crystal panel, and extends from each source electrode of the first and second input / output protection transistors to the external electrode, toward the inside of the liquid crystal panel, and inside. It is preferred that the wiring toward the outside is reversed and the wiring toward the outside of the liquid crystal panel is formed in a spiral shape.

In order to achieve the above object, a second input / output protection circuit according to the present invention provides an N-type thin-film transistor (N-type thin film transistor) having a low-concentration impurity-implanted drain structure (LDD structure) as a switching element for driving each pixel. An input / output protection circuit for a liquid crystal display device constituted by an N-type LDD structure TFT, which has a lower breakdown voltage and a lower hold voltage than an N-type LDD structure TFT and has no LDD structure. And a P-type thin film transistor having a lower breakdown voltage and hold voltage than the N-type LDD structure TFT and having no LDD structure (P-type non-LDD structure TFT). ), The second input / output protection transistor complementarily connected to the first input / output protection transistor, and a second input / output protection transistor disposed around the liquid crystal panel. And a capacitor formed between a light-shielding layer fixed at a ground potential and located at a position where the pixel driving circuit is shielded from light and a channel region of the first and second input / output protection transistors. I do.

In order to achieve the above object, a third input / output protection circuit according to the present invention provides an N-type thin film transistor (N-type thin film transistor) in which a switching element used for driving each pixel has a low-concentration impurity-implanted drain structure (LDD structure). An input / output protection circuit for a liquid crystal display device constituted by an N-type LDD structure TFT, which has a lower breakdown voltage and a lower hold voltage than an N-type LDD structure TFT and has no LDD structure. Non-LDD TFT)
A first input / output protection transistor having a drain and a gate connected to a common node, and a P-type thin film transistor (P-type non-LDD) having a lower breakdown voltage and hold voltage than an N-type LDD structure TFT and having no LDD structure Structure TF
T), a second input / output protection transistor having a drain and a gate connected to a common node, a first resistive element connected between the common node and the input / output circuit, and a first input / output protection transistor. A second resistive element and a first inductive element connected in series between the source electrode and ground potential;
A third resistive element and a second inductive element connected in series between the source electrode of the second input / output protection transistor and the ground potential; and a connection between the channel portion of the first input / output protection transistor and the ground potential And a second capacitive element connected between the channel portion of the second input / output protection transistor and the ground potential.

In order to achieve the above object, a fourth input / output protection circuit according to the present invention provides an N-type thin film transistor (N-type thin film transistor) having a low-concentration impurity-implanted drain structure (LDD structure) as a switching element for driving each pixel. An input / output protection circuit of a liquid crystal display device comprising a TFT with a LDD structure (type TFT), a glass substrate, a light shielding layer made of a metal material formed on the glass substrate, and an undercoat oxide film formed on the light shielding layer And an N-type first formed in an island shape on the undercoat oxide film and having a drain region, a source region, and a channel region between the drain region and the source region.
A polycrystalline silicon thin film and a P film formed in an island shape on the undercoat oxide film and having a drain region, a source region, and a channel region between the drain region and the source region.
A second polycrystalline silicon thin film of a mold, a gate oxide film formed on the first and second polycrystalline silicon thin films, and on the gate oxide film and opposed to a channel region of the first and second polycrystalline silicon thin films. A gate electrode formed on the gate electrode, an interlayer insulating film formed on the gate electrode, a common wiring electrode forming a common node formed on the interlayer insulating film, and a drain region of the first and second polysilicon thin films. A drain lead-out contact penetrating the gate oxide film and the interlayer insulating film to reach the common wiring electrode; a gate lead-out contact penetrating from the gate electrode to the common wiring electrode through the interlayer insulating film; and first and second polycrystalline silicon thin films A source lead-out contact that penetrates the undercoat oxide film from the source region to the light-shielding layer, and is electrically connected to the light-shielding layer formed on the interlayer insulating film. Characterized by comprising an external electrode connected to the ground potential.

In order to achieve the above object, in a liquid crystal display device according to the present invention, the first to fourth input / output protection circuits include:
The signal input / output circuit is provided between a metal pad connected to the common node and inputting / outputting a signal to / from the outside and a signal input / output circuit.

In order to achieve the above object, an image display application device according to the present invention is provided with the liquid crystal display device.

According to the above configuration, the following operation and effect can be obtained.

(1) LDD structure T constituting input / output circuit
The breakdown voltage BVd is higher than the input / output first stage transistor of the FT.
N-type and P-type non-LDD TFTs having a low s and hold voltage HVds are provided by a CMOS in an input / output protection circuit.
By using it as an input / output protection transistor with a structure, the input / output protection transistor operates before the input / output first-stage transistor for surge currents of both positive and negative polarities, and the surge current can flow reliably through the input / output protection transistor. it can.

(2) By connecting the source of the input / output protection transistor to a light-shielding layer in which the metal wiring is routed and the end of which is dropped to the Gnd potential, a bypass path for a current surge having a resistance / inductance component is formed. And the reverse current does not flow, so the diffusion layer of the transistor,
Destruction of the gate oxide film can be prevented.

(3) Since the wiring of the light-shielding layer has an inverted spiral structure, a magnetic field component generated by a surge current can be canceled out, and does not adversely affect a driving circuit disposed in a peripheral portion of the liquid crystal panel. You can do so.

(4) By forming a capacitor between the light-shielding layer fixed to the Gnd potential and the channel portion of the input / output protection transistor, the potential of the channel portion is fixed and the TFT is
Characteristics can be stabilized.

(5) By applying the input / output protection circuit having the above operation and effect, the reliability of the liquid crystal display device and the image display application equipment can be remarkably improved.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an input / output protection circuit according to one embodiment of the present invention.

In FIG. 1, reference numeral 11 denotes a pad of an input / output unit. A resistive element 13 (having a resistance value of about 300Ω to 2.0 kΩ) formed of, for example, a diffusion layer (for example, an N + layer used as a source or a drain) is provided between the pad 11 and the input / output first-stage transistor 12. First stage transistor 1
2 is provided for protection. The resistance element 13 is introduced to delay the response characteristic of the input / output protection circuit so that the surge current flows to the input / output protection circuit before flowing to the input / output circuit.

N between the resistance element 13 and the pad 11
A first input / output protection transistor 14 configured as a type non-LDD structure TFT is provided. The breakdown voltage BVds and the hold voltage HVds at the time of snapback (bipolar action of the MOS transistor) of the first input / output protection transistor 14 are set lower than those of the input / output first-stage transistor 12. Therefore, the input / output protection circuit operates before the input / output circuit operates. The gate width of the input / output protection transistor 14 is set so that the input / output first-stage transistor 1 is not damaged by a surge of a large current.
2 (the gate width is determined by the power, but is preferably 100 (μm) or more).

Further, in parallel with the first input / output protection transistor 14, a second P-type non-LDD TFT is formed.
An input / output protection transistor is provided.

First and second input / output protection transistors 1
The source terminals (S) 4 and 15 are connected to a light-shielding layer made of a metal material, which will be described later. The source terminals of the first and second input / output protection transistors 14 and 15 are connected to the ground (Gnd) in the light-shielding layer. By routing the wiring to the external terminal 17, the resistance element 16, the inductor 18, and the capacitor 19 immediately below the channel of each input / output protection transistor are formed as shown in FIG. This capacitor 1
By providing 9, the potential of the channel of each input / output protection transistor is fixed, and TFT characteristics can be stabilized. In addition, a current surge bypass path is formed by the resistance element 16 and the inductor 18.

Next, a method of manufacturing the input / output protection circuit shown in FIG. 1 will be described with reference to FIG.

FIG. 2 is a sectional view showing a semiconductor structure of the input / output protection circuit shown in FIG.

In FIG. 2, first, a metal film such as Ta or Cr is applied to a glass substrate 21 by PVD (Ph
ysical Vapor Deposition method or CVD (Chemi
A film having a thickness of about 100 (nm) is formed by a cal vapor deposition method. This metal film is patterned by a usual photolithography etching lithography technique to form a light shielding layer 22. Here, the light-shielding layer 22 is made of a metal such as Cr or Ta, and prevents light of the backlight of the liquid crystal panel from irradiating the drive circuit and the like. Thus, an increase in leakage current of the TFT due to light can be suppressed, and the off characteristics can be improved.

Next, the undercoat oxide film 23 is formed by CVD.
A thickness of about 600 (nm) is formed by the method. Next, with respect to the light-shielding layer 22, the source layer of the N-type non-LDD TFT serving as the first input / output protection transistor 14 and the source layer of the P-type non-LDD TFT serving as the second input / output protection transistor 15 are connected. The first contact holes 24 and 25 respectively connected to the light shielding layer 22 are patterned by ordinary photolithographic etching. After that, the amorphous silicon film is CVD
A thickness of 50 to 80 (nm) is formed by a method. Next, EL
The amorphous silicon film is turned into a polycrystalline silicon thin film by A (excimer laser annealing). This polycrystalline silicon thin film is patterned by ordinary photolithographic etching to form a channel layer 26.

Next, in order to form the source layer 27 and the drain layer 28 of the N-type non-LDD structure TFT which is the first input / output protection transistor 14 by ordinary photolithography,
Pattern the resist and select PH ₃ or P
Doping with a pentavalent ion species such as (phosphorus) ion. At this time, in order to make the polycrystalline silicon film in the first contact hole 24 conductive, the source lead-out contact 24 '.
70 to 100 (k)
By simultaneously performing high energy ion doping of eV), the polycrystalline silicon of the source extraction contact 24 'is made N-type.

Thereafter, the gate oxide film 29 is formed to a thickness of about 60 to
A film is formed only by 120 (nm) by a CVD method. Next, M
oW or Al with a thickness of about 20 by CVD or sputtering
After forming a film having a thickness of 0 to 300 (nm), patterning is performed by ordinary photolithographic etching to form a gate electrode 30.

Next, in order to form the source layer 31 and the drain layer 32 of the P-type non-LDD structure TFT, which is the second input / output protection transistor 15, by ordinary photolithography,
It is patterned and ion-doped with B (boron) or BF ₂ . Here, in order to make the polycrystalline silicon in the first contact hole 25 conductive, B (boron) is applied to the source lead-out contact 25 'by 150 to 200 (ke).
By simultaneously performing V) high energy ion doping, the polycrystalline silicon of the source lead-out contact 25 'is made P-type.

After that, an interlayer insulating film 33 is formed by a CVD method.

Next, the second contact holes 34 are patterned by ordinary photolithographic etching. Next, a metal such as Al or W is formed by a CVD method or a sputtering method, and a normal photolithography etching is performed, and an electrode 35 for commonly connecting the extraction wiring of the gate electrode 30 and the extraction wiring of the drain of each input / output protection transistor.
By patterning, an input / output protection circuit having the circuit configuration shown in FIG. 1 is obtained.

At this time, an Al electrode extracted from the light-shielding layer 22 via the N-type polycrystalline silicon layer is formed as the external terminal 17 shown in FIG. 1, and is connected to the Gnd potential.

Next, the light-shielding layer 22 is formed by the routing and the external terminal 17 lowered to the Gnd potential.
A current surge bypass path including the resistance element 16 and the inductor 18 will be described with reference to FIG.

FIG. 3 is a plan view of the light shielding layer formed on the liquid crystal panel as viewed from the glass substrate side.

In FIG. 3, the first input / output protection transistor 14 (N-type non-LDD structure T
FT) source layer 27 and second input / output protection transistor 1
5 (P-type non-LDD structure TFT) source layers 31 are connected to the light-shielding layer 22 via source lead-out contacts 24 'and 25', respectively. The wiring of the light-shielding layer 22 extends from the source extraction contacts 24 ′ and 25 ′ to the external terminal 17.
First, the glass substrate 21 is spirally arranged toward the inside, and then inverted and spirally arranged toward the outside. Thereby, the resistance element 16 (resistance value R) and the inductor 18 (inductance L) shown in FIG. 1 are formed, and this RL component plays a role of bypassing and absorbing a current surge.

A pixel display section 36 is provided at the center of the glass substrate 21, and a peripheral portion of the pixel display section 36 includes a driver circuit section 3 including a driver.
7 As described above, with respect to this drive circuit portion, the light-shielding layer 22 is formed by spirally connecting the source lead-out contacts 24 ′ and 25 ′ to the external terminals with the wiring going inside the glass substrate 21 and the wiring going outside. Stagger them. Thereby, even if a surge current flows through the light shielding layer 22,
The magnetic field components generated by the inductor 18 cancel each other,
The drive circuit can be prevented from being adversely affected.

[0048]

As described above, according to the present invention,
The following effects are obtained.

(1) LDD Structure T Constituting Input / Output Circuit
The breakdown voltage BVd is higher than the input / output first stage transistor of the FT.
N-type and P-type non-LDD TFTs having a low s and hold voltage HVds are provided by a CMOS in an input / output protection circuit.
By using it as an input / output protection transistor with a structure, the input / output protection transistor operates prior to the input / output first-stage transistor for both positive and negative surge currents, and the surge current can flow reliably through the input / output protection transistor. .

(2) By connecting the source of the input / output protection transistor to a light-shielding layer in which the metal wiring is routed and the end of which is dropped to the Gnd potential, a bypass path for a current surge having a resistance / inductance component is formed. And the reverse current does not flow, so the diffusion layer of the transistor,
Destruction of the gate oxide film can be prevented.

(3) Since the wiring of the light-shielding layer has an inverted spiral structure, a magnetic field component generated by a surge current can be canceled out, and does not adversely affect a driving circuit disposed in a peripheral portion of the liquid crystal panel. You can do so.

(4) By forming a capacitor between the light-shielding layer fixed to the Gnd potential and the channel portion of the input / output protection transistor, the potential of the channel portion is fixed and the TFT is
Characteristics can be stabilized.

(5) By applying the input / output protection circuit having the above effects, it is possible to significantly improve the reliability of the liquid crystal display device and the image display application device.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an input / output protection circuit according to an embodiment of the present invention.

FIG. 2 is a sectional view showing a semiconductor structure of the input / output protection circuit shown in FIG. 1;

FIG. 3 is a plan view of a light-shielding layer 22 formed on a liquid crystal panel as viewed from a glass substrate side.

FIG. 4 is a circuit diagram showing a configuration of a conventional input / output protection circuit.

FIG. 5 is a sectional view of a TFT having an LDD structure.

FIG. 6 shows an LDD structure TFT (solid line) and a non-LDD structure T
Diagram showing snapback characteristics of FT (broken line)

[Explanation of symbols]

Reference Signs List 11 pad 12 input / output first-stage transistor 13 resistive element for protection of input / output transistor 14 first input / output protection transistor (N-type non-LDD structure TFT) 15 second input / output protection transistor (P-type non-LDD structure TFT) 16 current surge bypass Resistance element 17 external terminal 18 inductor for reducing current surge 19 capacitor for fixing TFT potential 21 glass substrate 22 light shielding layer 23 undercoat oxide film 24 first contact hole for N-type non-LDD structure TFT 24 ′ N-type non-type Source lead-out contact for LDD structure TFT 25 First contact hole for P-type non-LDD structure TFT 25 'Source lead-out contact for P-type non-LDD structure TFT 26 Channel layer 27 Source layer of N-type non-LDD structure TFT 28 N-type Drain layer of non-LDD structure TFT 29 Gate insulating film 30 Gate electrode 31 Source layer of P-type non-LDD structure TFT 32 Drain layer of P-type non-LDD structure TFT 33 Interlayer insulating film 34 Second contact hole 35 Gate and drain of N-type and P-type non-LDD structure TFT Common connection electrode 36 Pixel display unit 37 Drive circuit unit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8238 H01L 29/78 616A 27/092 623A 21/336 626C H04N 5/66 101 F term (reference) 5C058 AA06 BA01 BA35 5F038 BH02 BH03 BH07 BH13 EZ06 EZ20 5F048 AA02 AC04 AC10 BA16 BC06 BG05 CC01 CC05 CC09 CC18 5F110 AA22 BB02 BB04 CC02 DD02 DD13 EE03 EE06 EE38 EE44 EE23 FF23 GG02 NN23 GG03 NN46 NN71 NN72 NN78 PP03 QQ11

Claims (8)

[Claims] An input / output protection circuit of a liquid crystal display device in which a switching element used for driving each pixel is constituted by an N-type thin film transistor (N-type LDD structure TFT) having a low-concentration impurity-implanted drain structure (LDD structure). A first input / output protection transistor having an N-type thin film transistor (N-type non-LDD structure TFT) having a breakdown voltage and a hold voltage lower than that of the N-type LDD structure TFT and having no LDD structure; A P-type thin film transistor (P-type non-LDD structure TFT) having a breakdown voltage and a hold voltage lower than that of the N-type LDD structure TFT and having no LDD structure;
A second input / output protection transistor that is complementarily connected to the first input / output protection transistor, and is formed between each source electrode of the first and second input / output protection transistors and an external electrode of the liquid crystal display device;
An input / output protection circuit comprising: a resistance element for bypassing an overcurrent. 2. The input / output protection circuit according to claim 1, wherein said resistance element is constituted by a wiring pattern of a light shielding layer formed on a glass substrate of a liquid crystal panel. 3. The wiring pattern of the light-shielding layer surrounds a display section of the liquid crystal panel, and goes from each source electrode of the first and second input / output protection transistors to the external electrode toward the inside of the liquid crystal panel. 2. The input / output protection circuit according to claim 1, wherein the wiring and the wiring toward the inside are reversed and the wiring toward the outside of the liquid crystal panel is formed in a spiral shape. 4. An input / output protection circuit for a liquid crystal display device in which a switching element used for driving each pixel is constituted by an N-type thin film transistor (N-type LDD structure TFT) having a low-concentration impurity-implanted drain structure (LDD structure). A first input / output protection transistor having an N-type thin film transistor (N-type non-LDD structure TFT) having a breakdown voltage and a hold voltage lower than that of the N-type LDD structure TFT and having no LDD structure; A P-type thin film transistor (P-type non-LDD structure TFT) having a breakdown voltage and a hold voltage lower than that of the N-type LDD structure TFT and having no LDD structure;
A second input / output protection transistor complementarily connected to the first input / output protection transistor; and a light-shielding layer formed at a position for shielding a pixel driving circuit disposed at the periphery of the liquid crystal panel and fixed to a ground potential. An input / output protection circuit comprising: a capacitor formed between the first and second input / output protection transistors and a channel region of the first and second input / output protection transistors. 5. An input / output protection circuit for a liquid crystal display device in which a switching element used for driving each pixel is constituted by an N-type thin film transistor (N-type LDD structure TFT) having a low-concentration impurity-implanted drain structure (LDD structure). An N-type thin film transistor (N-type non-LDD structure TFT) having a breakdown voltage and a hold voltage lower than that of the N-type LDD structure TFT and having no LDD structure;
A first input / output protection transistor having a drain and a gate connected to a common node; a P-type thin film transistor (P-type thin film transistor) having a breakdown voltage and a hold voltage lower than that of the N-type LDD structure TFT and having no LDD structure. Non-LDD TFT)
A second input / output protection transistor having a drain and a gate connected to the common node; a first resistive element connected between the common node and the input / output circuit; a source electrode of the first input / output protection transistor A second resistive element and a first inductive element connected in series between the ground and the ground potential; a third resistive element connected in series between the source electrode of the second input / output protection transistor and the ground potential And a second inductive element, a first capacitive element connected between a channel portion of the first input / output protection transistor and a ground potential, and a first capacitive element connected between the channel portion of the second input / output protection transistor and a ground potential. An input / output protection circuit comprising: a second capacitive element connected therebetween. 6. An input / output protection circuit for a liquid crystal display device in which a switching element used for driving each pixel is constituted by an N-type thin film transistor (N-type LDD structure TFT) having a low-concentration impurity-implanted drain structure (LDD structure). A glass substrate; a light-shielding layer formed on the glass substrate and made of a metal material; an undercoat oxide film formed on the light-shielding layer; an island formed on the undercoat oxide film in an island shape; An N-type first polycrystalline silicon thin film having a region, a source region, and a channel region between the drain region and the source region; an island-shaped formed on the undercoat oxide film; A p-type second polycrystalline silicon thin film having a channel region between a drain region and a source region; and the first and second polycrystalline silicon A gate oxide film formed on the thin film; a gate electrode formed on the gate oxide film and facing a channel region of the first and second polycrystalline silicon thin films; and a gate electrode formed on the gate electrode. An interlayer insulating film, a common wiring electrode formed on the interlayer insulating film and forming a common node, and penetrating the gate oxide film and the interlayer insulating film from the drain regions of the first and second polysilicon thin films. A drain extraction contact reaching the common wiring electrode, a gate extraction contact reaching the common wiring electrode from the gate electrode through the interlayer insulating film, and a source extraction contact from the first and second polysilicon thin films. A source lead-out contact that penetrates the undercoat oxide film and reaches the light-shielding layer; An input / output protection circuit comprising: an external electrode electrically connected to the layer and connected to a ground potential. 7. The input / output protection circuit according to claim 1, wherein the input / output protection circuit is connected between the metal pad connected to the common node to input / output a signal to / from the outside and the signal input / output circuit. A liquid crystal display device, comprising: 8. An image display application device comprising the liquid crystal display device according to claim 7.