JP2002082424A - Halftone phase shaft mask - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a halftone phase shift mask having high phase angle controllability and dimensional controllability and high alignment accuracy even when there are microholes in a short time and at a low cost and in a high yield. SOLUTION: This halftone phase shift mask consists of a halftone phase shift mask structure having resist deposited on the halftone films of wafer alignment mark parts and the light shielding belt parts existing on the outside of pattern forming regions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photomask used for manufacturing a semiconductor device, a superconducting device, a micromachine, an electronic device, etc., and more particularly to a halftone phase shift mask suitable for forming a fine pattern.

[0002]

2. Description of the Related Art In the manufacture of semiconductor integrated circuit devices,
A lithography technique is used as a method of transferring a fine pattern onto a semiconductor wafer. In a lithography technique, a projection exposure apparatus is mainly used, and a pattern of a photomask mounted on the projection exposure apparatus is transferred onto a semiconductor wafer to form a device pattern.

As shown in FIG. 2, the exposure area of the exposure apparatus having a high resolution is smaller than the size of the wafer 21, so that the exposure area is divided into a plurality of shots, and a plurality of chips 22 are exposed by step or scan feed. At the time of the exposure, a scribe area 23 for cutting out a chip is prepared around the chip. Generally, the wafer alignment mark 24 is formed in the scribe area 23.

In recent years, miniaturization of patterns to be formed has been promoted in order to meet demands for higher integration of devices and improvement of device operation speed. Against this background,
An exposure method called a halftone phase shift method is used. The halftone phase shift mask is a mask in which a film (referred to as a halftone film) translucent to exposure light is formed on a transparent substrate (blanks).

[0005] The transmittance of the halftone film to exposure light is usually adjusted within a range of 1% to 25%. The film is adjusted so that a phase difference occurs between the exposure light transmitted through the film and the exposure light transmitted through the opening having no film. The phase difference that brings out the highest resolution performance is 180 degrees and an odd multiple thereof, but if the phase difference falls within a range of 90 degrees before and after 180 degrees, an effect of improving resolution can be obtained. When a halftone mask is used, the resolution is generally 5
From about 20%. Note that MoSi, CrFO, TaSi is used as the halftone film.
An inorganic film of O, MoSiN, SiON, SiN, ZrSiO, or the like is used.

When chip exposure is performed, a part of the outer frame region of the next shot overlaps the pattern forming portion. The light shielding film is Cr
In a photomask having a sufficient light-shielding property such as that described above, there is no problem because the light transmitted through the outer frame region is sufficiently small. However, in a halftone mask, the outer frame region is a semi-permeable film and is not a complete light-shielding material. For this reason, light that passes through this portion while being dimmed is superimposed on the pattern to be formed, and a problem arises in that the portion where the light is superimposed results in resist film loss and a reduction in resolution.

Therefore, conventionally, this problem has been dealt with by forming a Cr light shielding film in the outer frame region. This Cr light shielding film is called a Cr light shielding band. Although the exposure apparatus is provided with a mechanism called a masking blade for changing the size of the exposure area, its positioning accuracy is as low as about 50 μm, and it does not have sharp light-shielding characteristics. Since the masking blade has an insufficient function to prevent such exposure fogging in the periphery, a Cr light-shielding band that is sharply shielded from light has been used.

As an alternative to the Cr light-shielding band, a dense grating pattern or a checker pattern finer than the resolution of an exposure apparatus, such as that described in JP-A-6-175347, is cut into a halftone film to reduce the diffraction phenomenon. There is a halftone light-shielding band method in which the transmittance of this portion to exposure light is sufficiently reduced by utilizing the method. However, in this method, since it is necessary to form a large number of dense patterns finer than the resolution of the exposure apparatus, the amount of pattern data for mask drawing is greatly increased, and a long time is required for mask drawing.
There has been a problem that the mask cost increases and the mask manufacturing TAT also drops significantly. Incidentally, as a description regarding the halftone phase shift, see, for example, Japanese Patent Laid-Open No. 5-18125.
No. 7 publication.

[0009]

A conventional halftone phase shift mask using a Cr light-shielding band has a two-layer structure in which a Cr film is adhered in addition to a halftone film. Was.

(1) The processing of the Cr film and the processing of the halftone film are required, and the number of steps is large and the cost is high.

(2) In addition to the large number of steps, there is a step in which foreign matter defects are likely to occur, such as spattering and etching of a Cr film, so that the production yield is low.

(3) When the cap of the Cr film as the inorganic film is removed, the halftone film as the inorganic film is partially non-uniformly etched, and the phase controllability and the pattern dimensional accuracy are reduced.

(4) As a halftone material, on the one hand, a material having an etching selectivity with Cr must be selected, and on the other hand, a Cr and a halftone film must be overlapped and etched with high dimensional accuracy. Is narrowed, and it is difficult to improve the accuracy. In particular, ArF excimer laser (wavelength 193 nm) or F ₂ , in which the energy of exposure light increases and exposure light irradiation resistance becomes a problem,
In the case of a mask for an excimer laser (wavelength: 157 nm), this limitation on the material selection range is a particularly serious problem.

Further, in the halftone phase shift mask using the halftone light shielding band, as described above, the amount of mask pattern data is greatly increased, and it takes a long time to draw a mask. There was a problem that also decreased.

[0015]

In order to solve the problems of the above-mentioned conventional phase shift mask, in the present invention, FIG.
As shown in (a) and (b), a halftone phase shift mask having a structure in which a light shielding band made of a resist 6 is formed in a region outside the chip region 2 on the halftone film 1. In FIG. 1, 1 is a halftone film, 2 is a chip area, 3 is a circuit pattern, 4 is a wafer alignment mark, 5 is a reticle alignment mark, 6 is a resist, and 7 is a blank made of quartz glass. Also, in the figure, the pattern forming surface is turned up in consideration of the mask manufacturing process, but when the mask is mounted on the exposure apparatus, the direction is inverted upside down and the pattern surface is turned down.

According to the present invention, the resist film functions as a sufficient light-shielding film, and it is possible to effectively prevent the resist film from being exposed on the wafer at the multiple exposure at the time of transfer and the resolution from being poor. Cr
Since the problems of film deposition and processing are eliminated, the above problem is solved.

Here, the resist used in the present invention is a photosensitive composition which reacts with light or an electron beam and dissolves in a portion which has reacted when developed or a portion which has not reacted, and conversely, a pattern is formed. This means that the film is not necessarily limited to a film having a large resistance to dry etching and wet etching.

Incidentally, for the purpose of simplifying the manufacturing process of a normal photomask and improving the accuracy, for example, Japanese Patent Laid-Open No. 5-28
No. 9307 discloses a method of forming a mask pattern itself with a resist film. This mask is a so-called binary mask composed of an exposure light transmitting portion and a sufficient light-shielding body, and has no problem of overlapping exposure of the outer frame. Japanese Patent Application Laid-Open No. 9-211837 discloses an application of a resist light-shielding body to a halftone phase mask, which is intended to prevent sub-peak transfer in a chip area, and is used in the vicinity of a pattern edge. This is to form a so-called rim type halftone mask which is only halftoned. The purpose and effect are different from this method. Therefore, the place where the resist is formed is different. That is, in Japanese Patent Application Laid-Open No. 9-211837, the resist is formed on the entire surface except for the vicinity of the opening, whereas in the present application, the resist is formed on the outside of the exposure region and on the wafer alignment mark portion. This difference is an essential difference between the phase shift exposure method using a part of the light from the rim portion and the phase shift exposure method using the transmitted light from the entire halftone portion.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present application, the pattern surface of a mask is classified into the following regions. Area where the integrated circuit pattern to be transferred is arranged “chip area”, area covered with pellicle “pellicle cover area”, pellicle cover area other than integrated circuit pattern area “peripheral area of integrated circuit pattern”, pellicle cover Outer area "peripheral area" that is not touched, of the peripheral area, the inner area where the optical pattern is formed "peripheral internal area", and other peripheral areas used for vacuum suction etc. "peripheral external area" .

(Embodiment 1) FIGS. 1A and 1B
Shows the structure of the halftone phase shift mask according to the first embodiment of the present invention. FIG. 2A shows the mask of the present invention viewed from above, and FIG. 2B shows a cross section taken along a line connecting A and A ′ in FIG. In the figure, 1 is a halftone film, 2 is a chip area, 3 is a circuit pattern, 4 is a wafer alignment mark, 5 is a reticle alignment mark, 6 is a resist, and 7 is a blank made of quartz glass.

Here, when the resist 6 serving as the light-shielding band comes into contact with the stage or the transport system of the exposure apparatus, it is peeled off and causes a foreign matter defect. Therefore, the resist should not be left in such a portion. In this embodiment, the planar shape of the resist 6 is a mouth-shaped band, and the resist is not left in a contact portion such as a stage of an exposure apparatus. However, the shape of the light-shielding band is limited to the mouth-shaped. Not something. Note that, in the resist light-shielding band 6, a wafer mark 4 for positioning between masks is also arranged.

FIGS. 3A to 3G show a method of manufacturing the halftone phase shift mask according to the first embodiment of the present invention. First, as shown in FIG. 3A, a halftone film 31 is formed on a quartz glass substrate (blanks) 7.
Further, a resist film 32 was formed thereon, and a desired pattern was exposed (33). Here, a CrO _x F _y film is used as the halftone film, but this is only an example, and
rSi _x O _y film, SiON film, SiN film, CrF _x film, M
inorganic films such as OSI _x can also be used. Also, for example, a two-layer inorganic film in which the x, y ratio of ZrSi _x O _y is changed can be used as the halftone film.

The film thickness d of the halftone film is set such that the wavelength of the exposure light is .lambda.
Λ / 2 (n
-1). The above-mentioned conditions are conditions that can maximize the resolution and exposure latitude of the transfer pattern, but are not limited to these conditions. The transmittance for the exposure light was set to 6%. However, this is also only one implementation condition and is not limited to this condition.

Next, as shown in FIG. 3B, development is performed to form a resist pattern 34, and using this resist pattern 34 as a mask, the halftone film 1 is etched as shown in FIG. 3C. Was. Next, as shown in FIG. 3D, the resist film 34 is peeled off to remove a desired circuit pattern 3.
And a halftone film on which the reticle alignment mark 5 was formed was formed.

Thereafter, as shown in FIG. 3E, a positive photoresist 35 is applied, and light (3) is applied from the glass surface 7 side to the entire surface.
6) was irradiated. As the exposure light at this time, light having a wavelength to which the photoresist 35 was exposed and which was attenuated by the halftone film 31 was used. In this embodiment, light used for wafer exposure is used.

Thereafter, as shown in FIG. 3F, portions other than the portions to be left as light-shielding bands were exposed (37) from the resist 35 side. At the time of this exposure, it is important to always expose a portion of the exposure apparatus that comes into contact with the stage or the transport system. Laser light was used for this exposure.

In order to reduce coating unevenness of the resist film 35, it was effective to make the thickness of the resist film 35 larger than the thickness of the halftone film 31. In this embodiment, the thickness of the resist 35 is 3 μm, but this is only an example. The upper limit of the film thickness was sufficient if the film thickness including the halftone film had a transmittance of 0.3% or less for exposure light. Also, the number of times of multiple exposure to the same place is 4
If it is up to the number of times, the film thickness may be such that the transmittance to exposure light including the halftone film is 1% or less. Note that a resist pattern may be formed on the halftone film in the chip region for the purpose of preventing sub-peak transfer.

Finally, development was performed to form a resist pattern 6 on the halftone film 31 as shown in FIG. Since the resist opening is formed in a self-aligned manner with respect to the halftone pattern opening by exposure 36 from the glass surface side, the wafer alignment mark formed in the resist light-shielding band is formed by the resist opening 38 and the halftone opening 39.
The mark has no misalignment between them. Further, as described above, if the resist remains at the peripheral portion of the mask, the resist is peeled off when the mask is mounted on the exposure apparatus and becomes a foreign substance, and a transfer defect occurs. It is removed by pattern exposure 37 from the side.

Thereafter, heat treatment is performed to form a resist pattern 6
And the resistance to exposure light irradiation was increased. In addition,
When a high-temperature heat treatment is applied while irradiating far-ultraviolet light, the resistance to irradiation and heat can be further improved. When the heat treatment or the far ultraviolet irradiation treatment is performed, the emission of gas and organic substances coming out of the resist when performing the mask exposure is reduced, and the problem that the pellicle attached to the lens or the mask of the exposure apparatus becomes cloudy is eliminated. .

According to the present invention, the dry etching step of Cr and the accompanying cleaning step are reduced, and foreign matter defects are reduced, so that the mask manufacturing yield is improved from 80% to 90%. The phase controllability was improved from 4% to 3%, and the dimensional accuracy was improved by 5%.

FIG. 4 shows a configuration example of a reduction projection exposure apparatus used in the present embodiment. Light source 1501 of reduction projection exposure apparatus
Exposure light emitted from the lens is a fly-eye lens 1502, an illumination shape adjustment aperture 1503, a condenser lens 150
4, 15505 and the mirror 1506 via the mirror 1506
07. Masking blade 1 on the mask
522 is provided so that the size of the opening can be adjusted according to the size of the exposure area.

The mask 1507 has a main surface (first main surface) on which the light-shielding pattern is formed (a semiconductor wafer 1509).
Side). Therefore, the exposure light is emitted from the back surface (second main surface) side of the mask 1507. Thus, the mask pattern drawn on the mask 1507 is projected onto the semiconductor wafer 1509 as a sample substrate via the projection lens 1508.

In some cases, a pellicle 1510 is provided on the first main surface of the mask 1507 to prevent pattern transfer failure due to foreign matter adhesion. The mask 150
7 is vacuum-adsorbed onto the mask stage 1512 controlled by the mask position control means 1511,
3, the center of the projection lens and the optical axis of the projection lens are accurately aligned.

The semiconductor wafer 1509 is placed on the sample stage 1514.
Absorbed on top. The sample stage 1514 is mounted on a Z stage 1515 movable in the optical axis direction of the projection lens 1508, that is, in the Z axis direction, and further mounted on an XY stage 1516. The Z stage 1515 and the XY stage 1516 are driven by respective driving units 1518 and 1519 according to a control command from the main control system 1517.
, And can be moved to a desired exposure position. The position is accurately monitored by the laser length measuring device 1521 as the position of the mirror 1520 fixed to the Z stage 1515. As the probe light of the position detecting means 1513, for example, the light of the exposure light source 1501 guided by the optical fiber 1523 is used.

The resist on the mask was exposed to light so that the resist film did not remain on the portion of the exposure device that was in contact with the stage or the transfer system, thereby preventing the generation of foreign matter caused by the transfer. Without this treatment, foreign matter was generated and caused transfer defects.

The present mask is mounted on the main exposure apparatus, and the wavelength 19
The mask pattern was transferred onto the wafer by performing step & scan exposure using a 3 nm ArF excimer. as a result,
No transfer defects occurred, and the dimensional accuracy was improved by about 2% as compared with the conventional method. Although an ArF excimer laser was used here, a similar effect could be obtained by using a KrF excimer laser (wavelength: 248 nm).

If the wavelength is longer than 200 nm, the absorbance of the resist film decreases and the light-shielding ratio decreases, but (1) the film is formed on a halftone film which originally has a low transmittance.
(2) increasing the absorbance by heat treatment of the resist;
(3) Since the resist light-shielding band does not require high dimensional accuracy, the film thickness can be increased as needed. Further, when the thickness of the resist pattern 6 was further increased to, for example, 10 μm, the above-described effect was obtained also in the ultraviolet exposure.

The resist light-shielding band is formed on the halftone film, and the exposure light reaches the resist light-shielding band via the halftone film. Therefore, since the resist is exposed by being reduced in light by the halftone film, the light resistance of the resist light-shielding band has no problem.

FIG. 6 shows a twin-type photomask using the mask of this embodiment.
1 shows a manufacturing process for manufacturing a semiconductor integrated circuit device having a well-type CMIS (Complementary MIS) circuit.

The semiconductor wafer 103 is made of, for example, a semiconductor thin plate having a circular plane. The semiconductor substrate 103s constituting the semiconductor wafer 103 is made of, for example, an n-type Si single crystal, and an n-well 106n and a p-well 106p are formed thereon, for example. n well 106n
Is doped with, for example, an n-type impurity such as phosphorus or As. In addition, for example, boron as a p-type impurity is introduced into the p well 106p.

On the main surface (first main surface) of the semiconductor substrate 103s, a field insulating film 107 for isolation made of, for example, a silicon oxide film is provided by LOCOS (Local Oxidization).
(Silicon) method or the like. Note that the separating portion may be a groove type. That is, the semiconductor substrate 103
The isolation portion may be formed by embedding an insulating film in a groove dug in the thickness direction of s.

In the active region surrounded by the field insulating film 107, nMIS (Qn) and pMIS
(Qp) is formed. nMIS (Qn) and p
The gate insulating film 108 of the MIS (Qp) is made of, for example, a silicon oxide film, and is formed by a thermal oxidation method or the like. For the gate electrodes 109 of nMIS (Qn) and pMIS (Qp), for example, a gate forming film made of low-resistance polysilicon is deposited by a CVD method or the like, and a resist pattern is formed on the film by photolithography.
It is formed by performing etching. Although not particularly limited, the gate length is, for example, 0.13 μm
It is about.

The semiconductor region 110 of nMIS (Qn)
For example, phosphorus or arsenic is introduced into the semiconductor substrate 103s by ion implantation or the like using the gate electrode 109 as a mask, so that the semiconductor substrate 103s is formed in a self-aligned manner with respect to the gate electrode 109. The semiconductor region 111 of pMIS (Qp) is formed in a self-aligned manner with respect to the gate electrode 109 by introducing, for example, boron into the semiconductor substrate 103s by ion implantation or the like using the gate electrode 109 as a mask. However, the gate electrode 109
Is not limited to being formed of, for example, a single film of low-resistance polysilicon, and can be variously changed. For example, a silicide layer such as tungsten silicide or cobalt silicide is provided on the low-resistance polysilicon film. Also, a so-called polycide structure may be used, or a so-called polymetal structure in which a metal film such as tungsten is provided on a low-resistance polysilicon film via a barrier conductor film such as titanium nitride or tungsten nitride. Good.

First, as shown in FIG. 6B, an interlayer insulating film 112 made of, for example, a silicon oxide film is deposited on such a semiconductor substrate 103s by a CVD method or the like, and then a polysilicon film is formed on the upper surface thereof. It is deposited by a CVD method or the like. Subsequently, after processing the polysilicon film by photolithography and etching, an impurity is introduced into a predetermined region of the patterned polysilicon film to form a wiring 113L and a resistor 113R made of the polysilicon film.

Thereafter, as shown in FIG. 6C, for example, a silicon oxide film 114 is deposited on the semiconductor substrate 103s, and then the interlayer insulating film 112 and the silicon oxide film 114 are formed.
A connection hole 115 such that the semiconductor regions 110 and 111 and a part of the wiring 113L are exposed is formed by photolithography and etching.

Further, for example, Ti and TiN are deposited on the semiconductor substrate 103s by a sputtering method, and then W is deposited by a sputtering method and a CVD method, and then the metal film is processed by photolithography and etching. As shown in FIG. 6D, a first layer wiring 116L1 is formed. Thereafter, the first layer wiring 116
Similarly to L1, the second and subsequent wiring layers are formed to manufacture a semiconductor integrated circuit device.

In custom LSI products, mask debugging is often performed particularly on the first wiring layer. The speed of the mask supply TAT to the first wiring layer determines the product development capability and increases the number of required photomasks. Therefore, applying the present invention to this step is particularly effective. In the present embodiment, the halftone mask of the present embodiment is applied to the formation of the connection hole 115 and the formation of the first layer wiring 116L1. The diameter of the connection hole is 0.
It was 15 μm. Since such a small hole was formed, the exposure amount was about twice as high as the exposure amount of the wiring system.

On the other hand, the pattern width of the wafer alignment mark is 2 μm or more, and for this pattern, the amount of exposure is excessive. When the wafer alignment mark is formed only by the halftone film, the light transmitted through the halftone film and the light transmitted through the wafer alignment mark opening interfere with each other. A problem arises that the shape of the wafer alignment mark to be transferred is asymmetrically distorted due to the optical interference and the aberration of the lens of the exposure apparatus. However, in the halftone phase shift mask of this embodiment, since the resist is covered without any misalignment on the wafer alignment mark halftone film portion, the light shielding ratio of the exposure light is high, and the above-described optical interference is reduced. Therefore, even when a fine hole is formed, a wafer alignment mark can be formed with high symmetry. For this reason, the alignment accuracy of the fine hole 115 and the first layer wiring 116L was high. Although the halftone phase shift mask of the present embodiment is applied to these two processes having particularly large effects, the cost and the mask manufacturing TAT are shorter than those of the conventional halftone phase shift mask even when used in other lithography processes. You can enjoy the advantages of

(Embodiment 2) In Embodiment 2, a transparent thin-film pellicle which acts to prevent foreign matter from adhering to the pattern forming surface (first main surface) of the mask is arranged on the main surface of the mask. An example will be described. The rest is the same as the first embodiment.

FIG. 5 shows a specific example of the mask according to the second embodiment. FIG. 5A is a plan view of the mask, and FIG.
Shows cross-sectional views each showing a state when the mask is mounted on a predetermined device.

In the second embodiment, a pellicle 62 is fixed to the main surface (first main surface) side of the mask via a pellicle attachment frame 61. The pellicle is used to prevent foreign matter from adhering to the mask.
This is a structure having a transparent protective film provided at a certain distance from the main surface or the main surface and the back surface of the mask substrate.

The predetermined distance is designed in consideration of the foreign matter adhering to the protective film surface and the transferability of the foreign matter to the semiconductor wafer. In the second embodiment, the pellicle 62 is arranged in the pellicle cover area of the mask. That is,
The pellicle 62 is arranged so as to surround the entire chip region 2 of the mask and the light-shielding band resist 6 including the wafer alignment mark 4 so as to overlap the halftone film on the peripheral region of the integrated circuit pattern.

In the second embodiment, the base of the pellicle attachment frame 61 is bonded and fixed in a state of directly contacting the halftone film 1 in the peripheral inner region of the mask. Thereby, peeling of the pellicle attaching frame 61 can be prevented. Further, if a resist film is formed at the position where the pellicle attachment frame 61 is attached, the resist film peels off when the pellicle 61 is attached / detached, thereby causing foreign matter.

In the second embodiment, since the pellicle bonding frame 61 is joined in a state of being directly in contact with the halftone film 1, such generation of foreign matters can be prevented. Such an effect is achieved by the pellicle pasting frame 61.
Can also be obtained by bonding and fixing in a state of being directly in contact with the mask substrate 7.

Further, as shown in FIG. 5B, a resist film was not formed on a portion 64 where the mask and the mounting portion 63 of the exposure apparatus were in contact. As a result, it is possible to prevent the generation of foreign matter due to the peeling or scraping of the resist film.

According to the second embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) By providing the pellicle on the mask, it is possible to prevent foreign matter from adhering to the mask, and to suppress or prevent the transfer pattern from being deteriorated due to the foreign matter adhering.

(2) By bonding the pellicle attachment frame 61 in a state of being directly in contact with the light shielding pattern 64 or the mask substrate 7, the resist film 6 for forming the light shielding pattern may be peeled off or scraped when the pellicle is attached or detached. Can be prevented. For this reason, it is possible to prevent the generation of foreign matter due to the peeling or scraping of the resist film 6.

[0059]

The effects obtained by the present invention will be briefly described as follows.

(1) The mask of the present invention has a small number of manufacturing steps, a short time required for manufacturing, and a low cost.

(2) The mask of the present invention has a high production yield because it is possible to omit sputter deposition and etching of a Cr film which is liable to cause foreign matter defects.

(3) Since there is no step of etching a light-shielding material on a halftone film such as Cr which has been conventionally performed, there is also a defect that the halftone film is unevenly etched and the film thickness is partially different. No generation occurs, the phase controllability of the halftone film is high, and the pattern dimensional accuracy is high.

(4) When selecting a halftone material,
Since there is no need to consider the etching selectivity of the halftone material, the range of material selection of the halftone material is widened.

(5) Since the wafer alignment mark has a sufficient light-shielding property, even when a fine pattern such as a hole is exposed with an exposure amount corresponding to the circuit pattern of the halftone portion, the shape defect of the alignment mark portion can be prevented. Does not occur. Therefore, high alignment accuracy can be obtained.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a sectional view showing a mask according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an outline of chip exposure on a wafer.

FIG. 3 is a sectional view showing a step of manufacturing a mask according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing an outline of an exposure apparatus used for carrying out the present invention.

FIGS. 5A and 5B are a plan view and a cross-sectional view showing a mask according to a second embodiment of the present invention.

FIG. 6 is an essential part cross sectional view of a semiconductor wafer showing a semiconductor integrated circuit manufacturing process according to an embodiment of the present invention;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Half tone film, 2 ... Chip area, 3 ... Circuit pattern, 4 ... Wafer alignment mark, 5 ... Reticle alignment mark, 6 ... Resist, 7 ... Quartz glass (blanks), 21 ... Wafer, 22 ... Chip, 23 ... Scribe area, 24: wafer alignment mark, 31: halftone film, 32: resist, 33: exposure light, 34: resist pattern, 35: resist, 36: exposure light, 37: exposure light, 38: resist opening, 39 … Halftone, 61
... Pellicle attachment frame, 62 ... Pellicle, 63 ...
Exposure device mounting part, 64 ... Exposure device stage contact part, 10
3 ... Semiconductor wafer, 103s ... Semiconductor substrate, 106n ...
n well, 106p ... p well, 107 ... field insulating film, 108 ... gate insulating film, 109 ... gate electrode, 1
10 ... nMISQn semiconductor region, 111 ... pMISQ
p semiconductor region, 112: interlayer insulating film, 113L: wiring, 113R: resistor, 114: silicon oxide film, 115
... Connection hole, 116L1 First layer wiring, 1501 Light source,
1502: fly-eye lens, 1503: illumination shape adjustment aperture, 1504, 1505: condenser lens,
1506 mirror, 1507 mask, 1508 projection lens, 1509 semiconductor wafer, 1510 pellicle, 1511 mask position control means, 1512 mask stage, 1513 position detection means, 1514 sample stage, 1515 Z stage, 1516 ... XY stage,
1517: main control system, 1518, 1519: driving means,
1520: mirror, 1521: laser measuring device, 1522
... Masking blade, 1523 ... Optical fiber.

Continued on front page F term (reference) 2H095 BB03 BC36 5F046 AA21 AA25 BA05 CA04 CB17 DA01 EA02 EA03 EA09 EA14 EB02

Claims (3)

[Claims] 1. A phase of a mask substrate and a film for attenuating exposure light, the phase of exposure light passing through the film being different from the phase of exposure light passing through an opening of the film which is not covered with the film. The semiconductor film prepared as described above is formed with an inorganic film (hereinafter referred to as a halftone film), and a wafer alignment mark is formed on the halftone film as a reference when performing alignment between a desired circuit pattern and exposure. A halftone phase shift mask used for exposure of an apparatus, wherein a resist is applied on a halftone film at a wafer alignment mark portion and outside a pattern formation region. 2. The halftone phase shift mask according to claim 1, wherein said resist is not provided at a position in contact with a stage and a transport system of said exposure apparatus. 3. The halftone phase shift mask according to claim 1, wherein the pellicle for protecting foreign matter is formed using a pellicle frame, and the resist is not provided outside the pellicle frame. Tone phase shift mask.