JP2002076912A - Apparatus and method for decoding - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform repetitive decoding with changed numbers of times of repetition without change to entire decoding delay through simple constitution. SOLUTION: An element decoder 50 generates action mode information through a control circuit 60 and, based on the action mode information, causes a selector 1202 to perform selecting operation and further an interleaver 100 to exercise address control. As a result, a plurality of delay modes in which entered data is delayed by a time equivalent to a processing time at least a soft-output decoding circuit 90 requires, delayed by a time equivalent to a processing time at least the interleaver 100 requires, or delayed by a time equivalent to a processing time at least the soft-output decoding circuit 90 and the interleaver 100 require, are established.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a decoding device and a decoding method suitable for iterative decoding.

[0002]

2. Description of the Related Art In recent years, studies have been made to reduce the symbol error rate by making the decoded output of an inner code in a concatenated code or the output of each iterative decoding operation in an iterative decoding method softer. Research on the law has been actively conducted. For example, as a method of minimizing the symbol error rate when decoding a predetermined code such as a convolutional code, “Bahl, Cocke, Jelinek and Raviv,“ Optimal
decoding of linear codes for minimizing symbol err
or rate ”, IEEE Trans. Inf. Theory, vol. IT-20, p
p. 284-287, Mar. 1974 ". In this BCJR algorithm, the likelihood of each symbol is output instead of outputting each symbol as a decoding result. Such an output is called a soft-output. Hereinafter, this B
The contents of the CJR algorithm will be described. In the following description, as shown in FIG. 112, digital information is convolutionally coded by a coding device 1001 provided in a transmitting device (not shown), and the output is passed through a no-memory communication channel 1002 with noise. , And decoding and observation by the decoding device 1003 included in the receiving device.

[0003] First, a shift included in the encoding apparatus 1001 is provided.
M states (transition states) representing the contents of the registers are represented by m
(0, 1,..., M−1) and the state at time t
S _tExpressed by Also, k-bit information is contained in one time slot.
Information is input, the input at time t is i
_t= (I_t1, I_t2, ..., i_tk) And the input system
I₁ ^T= (I₁, I_Two, ..., i_T). At this time,
If there is a transition from state m 'to state m,
The information bit corresponding to the transition is represented by i (m ', m) = (i
₁(M ', m), i_Two(M ', m), ..., i
_k(M ', m)). In addition, one time slot
Assuming that an n-bit code is output, at time t
X_t= (X_t1, X_t2, ..., x_tn)
Output system₁ ^T= (X₁, X_Two, ..., x_T)
You. At this time, the transition from state m 'to state m
In some cases, the sign bit corresponding to the transition is x
(M ', m) = (x₁(M ', m), x_Two(M ', m),
..., x_n(M ', m)).

[0004] Convolutional coding by the coding apparatus 1001 starts from state S ₀ = 0, outputs X ₁ ^T , and S _T =
It shall end with 0. Here, the transition probability P _t (m | m ′) between the states is defined by the following equation (1).

[0005]

(Equation 1)

The Pr shown on the right side of the above equation (1)
{A | B} is the conditional probability that A will occur under the condition that B occurs. The transition probability P _t (m | m ′) is, as shown in the following equation (2), when the input i transitions from the state m ′ to the state m, the input it at the time _t is i. is equal to the probability Pr {i _t = i}.

[0007]

(Equation 2)

[0008] The no-memory storage channel 1002 with noise is X ₁ ^T
And Y ₁ ^T is output. Here, assuming that an n-bit received value is output in one time slot, the output at time t is y _t = (y _t1 , y _t2 ,..., Y _tn )
, And Y ₁ ^T = (y ₁ , y ₂ ,..., Y _T ). The transition probabilities for the noisy memoryless channel 1002 are all t
(1 ≦ t ≦ T) can be defined using the transition probability Pr {y _j | x _j } of each symbol as shown in the following equation (3).

[0009]

(Equation 3)

Here, λ _tj is defined as in the following equation (4). Λ _tj shown in the following equation (4) represents the likelihood of input information at time t when Y ₁ ^T is received, and is a soft output that should be originally obtained.

[0011]

(Equation 4)

In the BCJR algorithm, the probabilities α _t , β _t and γ as shown in the following equations (5) to (7) are used.
Define _t . Note that Pr {A; B} represents the probability that both A and B occur.

[0013]

(Equation 5)

[0014]

(Equation 6)

[0015]

(Equation 7)

Here, the contents of these probabilities α _t , β _t and γ _t will be described with reference to FIG. 113, which is a trellis which is a state transition diagram in the encoding device 1001. In the figure, α _t−1 corresponds to the passage probability of each state at time t−1 calculated in chronological order based on the received values from the coding start state S ₀ = 0. Β _t corresponds to the passage probability of each state at time t calculated in reverse chronological order based on the received value from the encoding end state S _T = 0. Further, γ _t corresponds to the reception probability of the output of each branch that transitions between states at time t calculated based on the reception value and the input probability at time t.

Using these probabilities α _t , β _t and γ _t , the soft output λ _tj can be expressed by the following equation (8).

[0018]

(Equation 8)

By the way, for t = 1, 2,..., T, the following equation (9) holds.

[0020]

(Equation 9)

Similarly, the following equation (10) holds for t = 1, 2,..., T.

[0022]

(Equation 10)

Further, the following equation (11) holds for γ _t .

[0024]

[Equation 11]

Therefore, the decoding device 1003
When soft output decoding is performed by applying the R algorithm,
Based on these relationships, determine soft output lambda _t Through the series of steps shown in Figure 114.

First, as shown in the figure, in step S1001, the decoding apparatus 1003 uses the above equations (9) and (11) to obtain the probability α every time y _t is received.
Calculate _t (m) and γ _t (m ′, m).

Subsequently, the decryption device 1003 determines in step S
In 1002, after receiving all of the series Y ₁ ^T , the probability β _t (m) is calculated for each state m at all times t using the above equation (10).

Then, the decryption device 1003 performs step S
In step 1003, steps S1001 and S1001 are executed.
The soft outputs λ _t at each time _t are calculated by substituting the probabilities α _t , β _t and γ _t calculated in 1002 into the above equation (8).

The decoding apparatus 1003 can perform soft output decoding to which the BCJR algorithm is applied by going through such a series of processing.

Incidentally, in such a BCJR algorithm, it is necessary to perform the operation while holding the probability as a direct value, and there is a problem in that the amount of operation is large because it involves a product operation. Therefore, as a method of reducing the amount of computation,
“Robertson, Villebrun and Hoeher,“ A comparison o
f optimal and sub-optimal MAP decoding algorithms
operating in the domain ”, IEEE Int. Conf. on Comm
unications, pp. 1009-1013, June 1995 "and the Max-Log-MAP algorithm and Log-
MAP algorithm (hereinafter, Max-Log-BCJR)
Algorithm and Log-BCJR algorithm. ).

First, the Max-Log-BCJR algorithm will be described. The Max-Log-BCJR algorithm expresses the probabilities α _t , β _t , γ _t , and soft output λ _t in logarithmic form using natural logarithm, and performs the product operation of the logarithm as shown in the following equation (12). In addition to the sum operation, the probability sum operation is approximated by a logarithmic maximum value operation as shown in the following equation (13). The following equation (13)
Max (x, y) is a function for selecting the one having the larger value among x and y.

[0032]

(Equation 12)

[0033]

(Equation 13)

Here, for the sake of simplicity, the natural logarithm is abbreviated as I, and the natural logarithms of α _t , β _t , γ _t , and λ _t are _{expressed by} the following equations (14), respectively. Iα _t , Iβ _t , I
γ _t, it is intended to refer to the Iλ _t. Note that sgn shown in the following equation (14) is a constant indicating a sign for identifying positive or negative, that is, either “+1” or “−1”.

[0035]

[Equation 14]

As a reason for giving such a constant sgn,
Is mainly the probability α_t, Β_t, Γ_tTakes a value between 0 and 1.
From, the log likelihood that is generally calculated
Iα _t, Iβ_t, Iγ_tHas a negative value.

For example, if the decoding device 1003 is configured as software, it can process either positive or negative values, so the constant sgn may be either "+1" or "-1". When the decoding device 1003 is configured as hardware, it is desirable to invert the negative sign of the calculated negative value and treat it as a positive value for the purpose of reducing the number of bits.

That is, the constant sgn is determined by the decoding device 100
In the case where 3 is configured as a system that handles only negative values as log likelihood, it takes “+1”. When the decoding device 1003 is configured as a system that handles only positive values as log likelihood,
Take "-1". In the following, an algorithm that takes such a constant sgn into consideration will be described.

In the Max-Log-BCJR algorithm, these log likelihoods Iα _t , Iβ _t , and Iγ _t are calculated as follows:
The approximations are as shown in the following equations (15) to (17), respectively. Here, msgn (x, y) shown in the following formulas (15) and (16) is a function max for selecting the one having a larger value among x and y when the constant sgn is “+1”. (X, y), and when the constant sgn is “−1”, indicates a function min (x, y) for selecting a smaller value of x and y. The following equation (15)
The function msgn in the state m ′ on the right side of
It is determined in the state m ′ where the transition to the state m exists, and the state m ′ on the right side in the following equation (16)
Is obtained in a state m ′ in which a transition from the state m exists.

[0040]

(Equation 15)

[0041]

(Equation 16)

[0042]

[Equation 17]

[0043] In addition, in the Max-Log-BCJR algorithm, the same applies to the log soft-output Iλ _t,
It is approximated as shown in the following equation (18). Here, the following equation (1)
The function msgn of the first term on the right side in 8) is obtained in the state m ′ where the transition to the state m exists when the input is “1”, and the function msgn of the second term is obtained when the input is “0”. Sometimes, the transition to the state m is obtained in the state m 'where the transition exists.

[0044]

(Equation 18)

Therefore, the decoding device 1003 sets Max
When applying the -Log-BCJR algorithm performs soft output decoding, based on these relationships, determine soft output lambda _t Through the series of steps shown in Figure 115.

Firstly, decoder 1003, as shown in the figure, in step S1011, each time it receives a y _t, using the above equation (15) and the above equation (17), the log likelihood I.alpha _t ( m) and Iγ _t (m ′, m) are calculated.

Subsequently, the decryption device 1003 determines in step S
At 1012, after receiving all of the series Y ₁ ^T , the log likelihood Iβ _t (m) is calculated for each state m at all times t using the above equation (16).

Then, the decryption apparatus 1003 determines in step S
In step 1013, steps S1011 and S1011 are executed.
The log likelihood Iα _t , Iβ _t and I calculated in 1012
Substituting γ _t into the above equation (18), the log soft output Iλ _t at each time _t is calculated.

The decoding apparatus 1003 can perform soft-output decoding to which the Max-Log-BCJR algorithm is applied by going through such a series of processing.

As described above, since the Max-Log-BCJR algorithm does not include a product operation, the BCJR
Compared with the algorithm, the amount of calculation can be significantly reduced.

Next, the Log-BCJR algorithm will be described. The Log-BCJR algorithm uses M
The accuracy of approximation by the ax-Log-BCJR algorithm is further improved. Specifically, Log-B
The CJR algorithm transforms the summation of probabilities shown in the above equation (13) by adding a correction term as shown in the following equation (19) to obtain an accurate logarithmic value of the summation.
Here, such correction is referred to as log-sum correction.

[0052]

[Equation 19]

Here, the operation shown on the left side in the above equation (19) is referred to as a log-sum operation.
The operator of the g-sum operation is "SS Pietrobon," Imp
lemntation and performance of a turbo / MAP decode
r ”, Int. J. Satellite Commun., vol. 16, pp. 23-4
6, Jan.-Feb. 1998 ”, and for convenience, represented as“ # ”(however,“ E ”in the same paper) as shown in the following equation (20). Shall be.

[0054]

(Equation 20)

The above equations (19) and (20) are
The case where the above-described constant sgn is “+1” is shown. When the constant sgn is “−1”, the operations corresponding to the above equations (19) and (20) are as shown in the following equations (21) and (22), respectively.

[0056]

(Equation 21)

[0057]

(Equation 22)

Further, the operator of the cumulative addition operation of the log-sum operation is expressed by “# Σ” as shown in the following equation (23).
(However, it is expressed as "E" in the same paper.)

[0059]

(Equation 23)

Using these operators, Log-BC
The log likelihood Iα _t , Iβ _t and log soft output Iλ _t in the JR algorithm can be expressed as shown in the following equations (24) to (26), respectively. Since the log likelihood Iγ _t is represented by the above equation (17),
The description is omitted.

[0061]

(Equation 24)

[0062]

(Equation 25)

[0063]

(Equation 26)

Note that the cumulative addition operation of the log-sum operation in the state m ′ on the right side in the above equation (24) is
It is determined in the state m ′ where the transition to the state m exists, and the state m ′ on the right side in the above equation (25)
It is assumed that the cumulative addition operation of the log-sum operation in is obtained in a state m ′ where a transition from the state m exists. Also, l of the first term on the right side in the above equation (26)
The cumulative addition operation of the log-sum operation is obtained in the state m ′ where the transition to the state m exists when the input is “1”. The cumulative addition operation of the log-sum operation of the second term is
When the input is “0”, it is determined in the state m ′ where the transition to the state m exists.

Therefore, the decoding device 1003
When applying the -BCJR algorithm performs soft output decoding, based on these relationships, it is possible to obtain a soft-output lambda _t Through the series of steps shown in Figure 115 above.

[0066] First, the decoding apparatus 1003, as shown in the figure, in step S1011, each time it receives a y _t, using the above equation (24) and the above equation (17), the log likelihood I.alpha _t ( m) and Iγ _t (m ′, m) are calculated.

Subsequently, the decryption device 1003 determines in step S
At 1012, after receiving all of the series Y ₁ ^T , the log likelihood Iβ _t (m) is calculated for each state m at all times t using the above equation (25).

Then, the decryption device 1003 determines in step S
In step 1013, steps S1011 and S1011 are executed.
The log likelihood Iα _t , Iβ _t and I calculated in 1012
Substituting γ _t into the above equation (26), the log soft output Iλ _t at each time _t is calculated.

The decoding apparatus 1003 can perform soft output decoding to which the Log-BCJR algorithm is applied by going through such a series of processing. In the above equations (19) and (21), the correction term shown in the second term on the right-hand side is represented by a one-dimensional function with respect to the variable | x−y |. Is stored in advance in a ROM (Read Only Memory) or the like (not shown) as a table, so that accurate probability calculation can be performed.

Such a Log-BCJR algorithm increases the amount of operation as compared with the Max-Log-BCJR algorithm but does not include a product operation, and its output is the soft output of the BCJR algorithm except for the quantization error. Is the logarithmic value of

[0071]

The above-mentioned B
The CJR algorithm, the Max-Log-BCJR algorithm or the Log-BCJR algorithm is an algorithm that enables decoding of a trellis code such as a convolutional code. The trellis code is used as an element code, and a plurality of element encoders are interleaved. Can also be applied to decoding of a code generated by concatenation via. That is, the BCJR algorithm, Max-Log-BC
The JR algorithm or the Log-BCJR algorithm uses a parallel concatenated convolutional code (Parallel Concatenated Co.).
nvolutional Codes; hereinafter, referred to as PCCC. ) Or tandem concatenated convoluted code (Serially Concatenated Convolut)
ionalCodes; hereinafter, referred to as SCCC. ) And these P
Applying CCC or SCCC and combining with multi-level modulation,
Turbo Trellis Coded Modula (Turbo Trellis Coded Modula)
In the following, it is described as TTCM. ) Or Serial Concatenated Trellis Coded Modulation;
Hereinafter, it is referred to as SCTCM. ) Can be applied to decoding.

The decoding device for decoding these PCCC, SCCC, TTCM or SCTCM uses the BCJR algorithm, Max-Log-BCJR algorithm or Lo.
The maximum posterior probability based on the g-BCJR algorithm (Maxi
So-called iterative decoding is performed among a plurality of decoders that perform mum A Posteriori probability (MAP) decoding.

In order to determine the optimum number of repetitions according to the code in the iterative decoding, it is usually necessary to perform an experiment in which the number of repetitions is changed, and by connecting a number of decoders corresponding to the number of repetitions, a plurality of decoders are connected. An experiment can be performed by configuring a decoding device. Further, as a similar experiment, one decoding device is configured by connecting a number of decoders capable of performing iterative decoding with an arbitrary number of repetitions, and decoding corresponding to a desired number of repetitions equal to or less than the number of repetitions. It can also be done by pulling out the tap from the vessel.

However, in order to perform the former experiment, it is necessary to configure an enormous number of decoding devices, which may require a great deal of labor. Also, when performing the latter experiment, the circuit scale of the decoding device increases,
Since the decoding delay changes according to the number of repetitions, it is not desirable to compare the decoding results according to the change in the number of repetitions.

The present invention has been made in view of such circumstances, and it is possible to perform iterative decoding with a simple configuration and with a changed number of repetitions without changing the overall decoding delay, which is convenient. An object of the present invention is to provide a decoding device and a decoding method suitable for excellent iterative decoding.

[0076]

A decoding apparatus according to the present invention for achieving the above-described object obtains a probability of passing through an arbitrary state based on a received value that is a soft input, and uses this probability to generate a plurality of states. For repeatedly decoding a code generated by concatenating the element codes through an interleaver, a decoding device corresponding to the element code, performing soft output decoding by inputting received values and prior probability information, Soft output decoding means for generating soft output and / or external information at each time, and external information generated by the soft output decoding means,
Based on the same replacement position information as the interleaver, to rearrange and rearrange the order of the external information, or to restore the array of information rearranged by the interleaver,
Interleaving means for permuting and rearranging the order of the external information, and the input data, at least the processing time required by the soft output decoding means and the delay at the same time, at least the processing time required by the interleaving means and the delay at the same time, or at least Switching means for switching between a plurality of delay modes for simultaneously delaying the processing time required by the soft-output decoding means and the interleaving means is provided.

In such a decoding apparatus according to the present invention, the switching means causes the delay between the processing time required for at least the soft output decoding means and the delay required for at least the processing time required for the interleaving means, or at least A plurality of delay modes for simultaneously delaying the processing time required by the output decoding means and the interleaving means are switched.

Further, in the decoding method according to the present invention for achieving the above-described object, a probability of passing through an arbitrary state is obtained based on a received value which is a soft input, and the probability is obtained by using this probability.
A decoding method corresponding to an element code for repeatedly decoding a code generated by concatenating a plurality of element codes through a first interleaving step, comprising: receiving a received value and prior probability information; A soft output decoding step of performing decoding and generating soft output and / or external information at each time; and inputting the external information generated in the soft output decoding step, and replacing the same replacement position information as in the first interleaving step. The order of the external information is rearranged and rearranged based on
And a second interleaving step of permuting and rearranging the order of the external information so as to restore the arrangement of the information rearranged in the interleaving step. A plurality of delays that simultaneously delay the processing time and at least the processing time required for the second interleaving step, or at least the delay between the soft output decoding step and the processing time required for the second interleaving step It is characterized by switching the delay mode.

In the decoding method according to the present invention, the delay at least at the same time as the processing time required for the soft output decoding step, the delay at least at the same time as the processing time required at the second interleaving step, or at least the soft output A plurality of delay modes for simultaneously delaying the processing time required for the decoding step and the second interleaving step are switched.

Further, the decoding apparatus according to the present invention, which achieves the above-described object, obtains a probability of passing through an arbitrary state based on a received value that is a soft input, and uses this probability to generate a plurality of element codes. A decoding device that repeatedly decodes a code generated by being concatenated via an interleaver,
The decoding apparatus comprises a plurality of concatenated element decoders, each of which receives a received value and prior probability information, performs soft output decoding, and performs soft output and / or external output at each time. Soft output decoding means for generating information, and input the external information generated by the soft output decoding means, based on the same replacement position information as the interleaver, rearrange the order of the external information, or, Interleaving means for permuting and rearranging the order of the external information so as to restore the arrangement of the information rearranged by the interleaver; , At least a delay at the same time as the processing time required by the interleaving means, or at least a delay at the same time as the processing time required by the soft output decoding means and the interleaving means. It is characterized in that it comprises switching means for switching a plurality of delay mode for a delay.

In the decoding apparatus according to the present invention, when performing iterative decoding, the switching unit uses the switching unit to delay at least the processing time required by the soft output decoding unit, and at least the same time as the processing time required by the interleaving unit. Or a plurality of delay modes for simultaneously delaying at least the processing time required by the soft output decoding means and the interleaving means.

Further, in the decoding method according to the present invention for achieving the above-mentioned object, a probability of passing through an arbitrary state is determined based on a received value that is a soft input, and a plurality of element codes are determined using the probability. , Through a first interleaving step, is a decoding method for repeatedly decoding a code generated, wherein the decoding method includes performing a plurality of element decoding steps in succession. The process is
A soft output decoding step of receiving each received value and prior probability information and performing soft output decoding to generate soft output and / or external information at each time, and an external information generated in the soft output decoding step. Based on the same replacement position information as in the first interleaving step, the order of the external information is replaced and rearranged, or the arrangement of the information rearranged in the first interleaving step is restored. A second interleaving step of permuting and rearranging the order of the external information, wherein when the element decoding step is continuously performed a plurality of times, at least the processing time required for the soft output decoding step and A delay of the same time, a delay at the same time as the processing time required for at least the second interleaving step, or
A plurality of delay modes for simultaneously delaying at least the processing time required for the soft output decoding step and the second interleaving step are switched.

In the decoding method according to the present invention, at the time of iterative decoding, at least the delay between the processing time required for the soft output decoding step and the delay between the processing time required for at least the second interleaving step, and Delay, or
Switching between a plurality of delay modes for delaying at least the processing time required for the soft output decoding step and the second interleaving step at the same time.

[0084]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, as shown in FIG. 1, digital information is encoded by an encoding device 1 provided in a transmitting device (not shown), and its output is received via a no-memory storage channel 2 with noise. This is a data transmission / reception system applied to a communication model that is input to a device and is decoded by a decoding device 3 included in the receiving device.

In this data transmission / reception system, the encoding device 1 has a parallel concatenated code (Parallel Concatenated) using trellis codes such as convolutional codes as element codes.
Convolutional Codes; hereinafter, referred to as PCCC. ) Or tandem concatenated convolutional code (Serially Concatenated Convol
utional Codes; hereinafter, referred to as SCCC. ) Or Turbo Trellis Coded Modulati (Turbo Trellis Coded Modulati
on; hereinafter, referred to as TTCM. ) Or serial concatenated Trellis Coded Modulation (hereinafter, referred to as SCTCM). These encodings are called turbo encoding (Turbo encoding).
coding).

On the other hand, the decoding device 3 is for decoding the code coded by the coding device 1,
bertson, Villebrun and Hoeher, “A comparison of o
ptimal and sub-optimal MAP decoding algorithms ope
rating in the domain ”, IEEE Int. Conf. on Communi
cations, pp. 1009-1013, June 1995 ", the Max-Log-MAP algorithm or Log-M.
The maximum posterior probability (Maximum A Posteriori p) based on the AP algorithm (hereinafter referred to as Max-Log-BCJR algorithm or Log-BCJR algorithm).
robability; hereinafter, referred to as MAP. ) Decoding, so-called probabilities α, β, γ and soft-output λ are expressed in logarithmic likelihood (log likelihood) using natural logarithm, and log likelihoods Iα, Iβ, Iγ, And so-called posteriori probability informatio
n) a module including at least a soft output decoding circuit for obtaining a log soft output Iλ corresponding to n) and an interleaver for rearranging input data is regarded as one element decoder, and a plurality of element decoders are connected. It is configured to perform iterative decoding.

In particular, the decoding device 3 sets each element decoder to a delay at the same time as the processing time required for soft output decoding, at least a delay at the same time as the processing time required for interleaving processing,
Alternatively, it has a plurality of delay modes for simultaneously delaying at least the processing time required for the soft output decoding processing and the interleaving processing, and has a function of switching these delay modes.

In the following, each element decoder in the decoding device 3 performs M-based decoding based on the Log-BCJR algorithm.
Description will be made assuming that AP decoding is performed.

Hereinafter, the contents will be described along the following table of contents.

Table of Contents Overview of Encoding and Decoding Devices for Encoding and Decoding by PCCC, SCCC, TTCM, and SCTCM 1-1 Encoding and Decoding Devices for Encoding and Decoding by PCCC 1-2 Encoding and Decoding by SCCC 1. Encoding device and decoding device 2. Details of element decoder 2-1 Overall configuration of element decoder 2-2 Details of soft output decoding circuit 2-3 Details of interleaver 3. Decoding device configured by connecting elemental decoders Features of Entire Decoder 4-1 Code Likelihood Switching Function 4-2 Received Value Delay Function 4-3 Decoded Received Value Selection Function 4-4 Sharing of Decoding Storage Circuit and Delay Storage Circuit 4- 5 Frame delay information delay function 4-6 Soft output decoding circuit or interleaver single operation function 4-7 Delay mode switching function 4-8 Next stage information generation function 4-9 System verification function Features of Soft Output Decoding Circuit 5-1 How to Have Code Information 5-1-1 Calculation of Input / Output Patterns of All Branches on Trellis 5-1-2 Between Transition Source State and Transition Destination State Numbering 5-1-3 Numbering along time axis and numbering in reverse order to time axis 5-1-4 Numbering based on uniqueness of entire trellis 5-2 Method of inputting termination information 5-2 -1 Input of information for the number of input bits for the termination period 5-2-2 Input of information indicating the termination state in one time slot 5-3 Erasing position processing 5-4 Calculation and distribution of log likelihood Iγ 5 -4-1 Calculation and distribution of log likelihood Iγ for all input / output patterns 5-4-2 Calculation / distribution of log likelihood Iγ for at least some input / output patterns 5-4-3 For all input / output patterns Of logarithmic likelihood Iγ for each time point 5-4- Normalization of log likelihood Iγ for at least a part of input / output patterns 5-5 Calculation of log likelihood Iα and Iβ 5-5-1 Calculation of sum of log likelihood Iα and log likelihood Iγ 5-5 2 Preprocessing for Parallel Path 5-5-3 Sharing of Addition and Comparison Circuit 5-5-4 Output of Log Likelihood Iγ for Calculation of Log Soft Output Iλ 5-5-5 Log Likelihood Iα and Log for Parallel Path Calculation of the sum with likelihood Iγ 5-5-6 Selection of log likelihood according to code configuration 5-5-7 Normalization for log likelihood Iα and Iβ 5-5-8 Correction term in log-sum correction Calculation 5-5-9 Generation of control signal for selection in log-sum operation 5-6 Calculation of log soft output Iλ 5-6-1 Cumulative addition operation of log-sum operation using enable signal 5-6-2 Log-sum without using enable signal
5. Cumulative addition of calculation 5-7 Normalization for external information 5-8 Hard decision of received value Characteristics of Interleaver 6-1 Plural Types of Interleave Function 6-2 Sharing of Interleave Memory Circuit and Delay Memory Circuit 6-3 Operation Control of Memory Circuit by Clock Blocking Signal 6-4 Deinterleave Function 6-5 Write Generation of Address and Read Address 6-6 Delay Function for Interleave Length 6-7 How to Use Address Space 6-8 Writing and Reading Data Using Partial Write Function 6-9 Handling Even Length Delay and Odd Length Delay 6 10 I / O order change function Conclusion

1. PCCC, SCCC, TTCM and
Encoding apparatus for encoding / decoding by SCTCM and decoding
First outline of No. apparatus, in order to clarify the breadth of the present invention, prior to detailed description of the present invention, the encoding apparatus 1 'and the decoding of performing encoding and decoding by PCCC shown in FIGS. 2 and 3 The device 3 'and the coding device 1''and the decoding device 3''for performing coding / decoding by SCCC shown in FIGS. 4 and 5 will be described. These encoding devices 1 ′ and 1 ″ are positioned as examples of the encoding device 1, and the decoding devices 3 ′ and 3 ″ are positioned as an example of the decoding device 3. In particular, the decoding devices 3 ′ and 3 ″ can be configured by connecting elementary decoders.

1-1 Perform encoding / decoding by PCCC
Encoding device and decoding device First, an encoding device 1 'that performs encoding by PCCC.
And a decoding device 3 'for decoding a code by the coding device 1'.

As shown in FIG. 2, the encoding device 1 'includes a delay unit 11 for delaying input data, two convolutional encoders 12 and 14 for performing a convolution operation, and an order of the input data. Some include an interleaver 13 for rearranging. The encoding apparatus 1 ′ has an encoding rate of “1/1” for the input 1-bit input data D1.
3 "parallel convolution operation is performed to generate 3-bit output data D4, D5, and D6.
ry Phase Shift Keying; hereinafter referred to as BPSK. ) Modulation method and Quadrature Phase Shift Keying;
Hereinafter, it is described as QPSK. ) Output to the outside via a modulator (not shown) that performs modulation by a modulation method.

The delay unit 11 outputs 3-bit output data D
4, D5, and D6 are provided to match the output timing, and the 1-bit input data D1
Is input, the input data D1 is transferred to the interleaver 1
3 is delayed by the same time as the processing time required. Delay device 1
1 outputs the delayed data D2 obtained by delaying to the outside as output data D4, and supplies the output data D4 to the convolutional encoder 12 at the subsequent stage.

Upon receiving the 1-bit delay data D2 output from the delay unit 11, the convolutional encoder 12 performs a convolution operation on the delay data D2, and outputs the operation result to the outside as output data D5. .

The interleaver 13 inputs the input data D1 consisting of one bit sequence, and inputs the input data D1.
Are rearranged, and the generated interleaved data D3 is supplied to the subsequent convolutional encoder 14.

[0098] The convolutional encoder 14 outputs 1-bit interleaved data D supplied from the interleaver 13.
When 3 is input, a convolution operation is performed on the interleaved data D3, and the operation result is output to the outside as output data D6.

When such an encoding device 1 ′ receives 1-bit input data D 1, it outputs this input data D 1 as the tissue component output data D 4 to the outside as it is via the delay unit 11 and performs convolution. Encoder 12
The output data D5 obtained as a result of the convolution operation of the delayed data D2 according to the above and the output data D6 obtained as a result of the convolution operation of the interleaved data D3 by the convolution encoder 14 are output to the outside, so that the overall coding rate Performs the parallel concatenation operation of “１ ／”. The data encoded by the encoding device 1 '
Signal points are mapped by a modulator (not shown) based on a predetermined modulation method, and output to the receiving device via the memoryless communication path 2.

On the other hand, as shown in FIG. 3, a decoding device 3 'for decoding a code by the coding device 1' includes two soft output decoding circuits 15 and 17 for performing soft output decoding and Some include an interleaver 16 that rearranges the order, two deinterleavers 18 and 20 that restore the order of input data, and an adder 19 that adds two data. The decoding device 3 ′ has a soft input (soft-inpu
The input data D1 in the encoding device 1 'is estimated from the received value D7 as t) and output as decoded data D13.

The soft output decoding circuit 15 is provided corresponding to the convolutional encoder 12 in the encoding device 1 ', and performs MAP decoding based on Log-BCJR.
The soft output decoding circuit 15 receives the soft input received value D7 and a priori probability information (a priori probabi) for the soft input information bits output from the deinterleaver 18.
lity information) D8, and these received values D7
And soft-output decoding using the prior probability information D8. Then, the soft-output decoding circuit 15 outputs so-called external information (extrin
sic information) D9 is generated, and this external information D9 is output to the interleaver 16 at the subsequent stage as a soft output.

The interleaver 16 is used for the soft output decoding circuit 1
Interleaving based on the same permutation position information as the interleaver 13 in the encoding device 1 'is performed on the external information D9 for the soft input information bit output from the fifth input. The interleaver 16 outputs the data obtained by the interleaving as the prior probability information D10 for the information bits in the soft output decoding circuit 17 at the subsequent stage, and outputs the data to the adder 19 at the subsequent stage.

The soft output decoding circuit 17 is provided corresponding to the convolutional encoder 14 in the encoding device 1 ′, and, like the soft output decoding circuit 15, the Log-BCJ
MAP decoding based on the R algorithm is performed. The soft output decoding circuit 17 receives the soft input received value D7,
Prior probability information D10 for the soft-input information bits output from interleaver 16 is input, and soft output decoding is performed using received value D7 and prior probability information D10. Then, the soft-output decoding circuit 17 generates the external information D11 for the information bit determined by the code constraint condition, outputs the external information D11 to the deinterleaver 18 as a soft output, and outputs the external information D11 to the adder 19.

The deinterleaver 18 has the function of
The de-interleaving is performed on the soft-input external information D11 output from the soft-output decoding circuit 17 so that the bit array of the interleaved data D3 interleaved by the interleaver 13 in (1) returns to the original bit array of the input data D1. The deinterleaver 18 outputs data obtained by deinterleaving as prior probability information D8 for information bits in the soft output decoding circuit 15.

The adder 19 calculates prior probability information D1 for the soft input information bits output from the interleaver 16.
0 is added to the external information D11 for the information bit output from the soft output decoding circuit 17. The adder 19 outputs the obtained data D12 as a soft output to the deinterleaver 20 at the subsequent stage.

[0106] The deinterleaver 20 includes the encoding device 1 '
The de-interleaving is performed on the soft-output data D12 output from the adder 19 so that the bit array of the interleaved data D3 interleaved by the interleaver 13 is returned to the original bit array of the input data D1. The deinterleaver 20 outputs the data obtained by deinterleaving as decoded data D13 to the outside.

Such a decoding device 3 ′ includes soft output decoding circuits 15 and 17 corresponding to the convolutional encoders 12 and 14 in the encoding device 1 ′, thereby complicating a code with high decoding complexity. By decomposing into elements having a small degree, the characteristics can be sequentially improved by the interaction between the soft output decoding circuits 15 and 17. Decoding device 3 '
Receives the received value D7, performs iterative decoding with a predetermined number of repetitions, and outputs decoded data D13 based on soft-output external information obtained as a result of this decoding operation.

[0108] An encoding device that performs encoding by TTCM performs modulation by, for example, an 8-phase shift keying (hereinafter, referred to as 8PSK) modulation method in the last stage of the encoding device 1 '. This can be realized by providing a modulator. Also, a decoding device that decodes a code by TTCM can be realized with the same configuration as the decoding device 3 ′, and directly receives in-phase component and quadrature component symbols as received values.

1-2 Perform encoding / decoding by SCCC
Encoding device and decoding device Next, an encoding device 1 ″ that performs encoding by SCCC
And a decoding device 3 ″ for decoding a code by the coding device 1 ″.

As shown in FIG. 4, the encoding device 1 ″ includes a convolutional encoder 31 for encoding a code called an outer code, an interleaver 32 for rearranging the order of input data, and an inner Some include a convolutional encoder 33 for encoding a code called a code. The encoding device 1 ″ receives input 1-bit input data D2
1, a cascade convolution operation with an encoding rate of "1/3" is performed, and 3-bit output data D26, D27, D
28, and outputs it to the outside via a modulator (not shown) that performs modulation by, for example, the BPSK modulation method or the QPSK modulation method.

Upon receiving the 1-bit input data D21, the convolutional encoder 31 performs a convolution operation on the input data D21, and converts the operation result into 2-bit encoded data D22 and D23 in the subsequent interleaver 32.
To supply. That is, the convolutional encoder 31 performs a convolution operation with a coding rate of “１ ／” as the encoding of the outer code, and supplies the generated encoded data D22 and D23 to the interleaver 32 at the subsequent stage.

The interleaver 32 receives coded data D22 and D23 composed of two bit sequences supplied from the convolutional coder 31, and receives these coded data D22 and D23.
The bits of the bits 22 and D23 are rearranged in order, and the generated interleaved data D24 and D25 composed of two bit sequences are supplied to the convolutional encoder 33 at the subsequent stage.

The convolutional encoder 33 outputs the 2-bit interleaved data D supplied from the interleaver 32.
When the data 24 and D25 are input, a convolution operation is performed on the interleaved data D24 and D25, and the operation result is output to the outside as 3-bit output data D26, D27 and D28. That is, the convolutional encoder 33
Performs convolution operation with a coding rate of "2/3" as inner code coding, and outputs output data D26, D27, and D28 to the outside.

In the encoding apparatus 1 ″, the convolutional encoder 31 performs convolution operation with an encoding rate of “１ ／” as the encoding of the outer code.
3 by performing a convolution operation with a coding rate of "2/3" as the encoding of the inner code, so that the coding rate is "(1/2) .times. (2/3) = 1/3" as a whole. Perform cascade convolution operation. The data encoded by the encoding device 1 ″ is mapped to signal points by a modulator (not shown) based on a predetermined modulation method, and is output to the receiving device via the non-storage communication channel 2.

On the other hand, as shown in FIG. 5, as a decoding device 3 ″ for decoding a code by the encoding device 1 ″, two soft output decoding circuits 34 and 36 for performing soft output decoding are inputted. Deinterleaver 35 that restores the order of data
And an interleaver 37 for rearranging the order of input data. The decoding device 3 ″ estimates input data D21 in the coding device 1 ″ from a received value D29 that is soft input due to the influence of noise generated on the memoryless communication channel 2, and outputs the data as decoded data D36. .

The soft output decoding circuit 34 encodes the encoding device 1 ″
And performs MAP decoding based on Log-BCJR. The soft-output decoding circuit 34 receives the soft-input received value D29 and the prior-probability information D30 for the soft-input information bits output from the interleaver 37, and receives the received value D29 and the prior-probability information D30. Is used to perform MAP decoding based on the Log-BCJR algorithm, and perform soft-output decoding of the inner code. Then, the soft-output decoding circuit 34 generates the external information D31 for the information bit determined by the code constraint condition, and outputs the external information D31 to the subsequent deinterleaver 35 as a soft output. The external information D31 corresponds to the interleaved data D24 and D25 interleaved by the interleaver 32 in the encoding device 1 ″.

The deinterleaver 35 returns the bit arrangement of the interleaved data D24 and D25 interleaved by the interleaver 32 in the encoding device 1 '' to the original bit arrangement of the encoded data D22 and D23, respectively. , And deinterleave the soft-input external information D31 output from the soft-output decoding circuit. The deinterleaver 35 outputs the data obtained by deinterleaving as prior probability information D32 for the code bits in the soft output decoding circuit 36 at the subsequent stage.

The soft output decoding circuit 36 encodes the encoding device 1 ″
And performs MAP decoding based on Log-BCJR. The soft output decoding circuit 36 generates a priori probability information D for the soft input code bit output from the deinterleaver 35.
32, and input prior probability information D33 for the information bit whose value is “0”, perform MAP decoding based on the Log-BCJR algorithm using these prior probability information D32 and D33, Perform soft output decoding. The soft-output decoding circuit 36 generates external information D34 and D35 determined by the code constraint condition, outputs the external information D34 to the outside as decoded data D36, and outputs the external information D35 to the interleaver 37 as a soft output. .

The interleaver 37 is provided for the soft output decoding circuit 3
Interleaving based on the same replacement position information as the interleaver 32 in the encoding device 1 ″ is performed on the external information D35 for the soft input code bit output from 6. The interleaver 37 outputs the data obtained by the interleaving as prior probability information D30 for the information bits in the soft output decoding circuit 34.

The decoding device 3 ″ has soft output decoding circuits 36 and 34 corresponding to the convolutional encoders 31 and 33 in the encoding device 1 ″, respectively. In addition, a code having a high decoding complexity is decomposed into elements having a low complexity, and the soft output decoding circuits 34 and 3 are decomposed.
The properties can be successively improved by the interaction between the six. Upon receiving the reception value D29, the decoding device 3 ″ performs iterative decoding with a predetermined number of repetitions, and based on soft-output external information obtained as a result of this decoding operation,
The decoded data D36 is output.

It should be noted that an encoding device that performs SCTCM encoding is, for example, 8PS at the last stage of the encoding device 1 ″.
This can be realized by providing a modulator that performs modulation by the K modulation method. Also, a decoding device that decodes a code by SCTCM can be realized with the same configuration as the decoding device 3 ″, and directly receives in-phase component and quadrature component symbols as received values.

[0122] 2. Details of Element Decoder A decoding device 3 shown as an embodiment of the present invention has a module including at least a soft-output decoding circuit and an interleaver or a deinterleaver as shown by a broken line in FIG. 3 or a broken line in FIG. Is an element decoder described above, and a plurality of element decoders are connected to decode an arbitrary code among PCCC, SCCC, TTCM, or SCTCM.
Here, since the deinterleaver rearranges data based on the replacement position information opposite to the interleaver, it can be imitated as one form of the interleaver. Therefore, any element decoder may be used as long as it has a soft-output decoding circuit and an interleaver, and realizes interleaving and deinterleaving by switching functions between the interleaver and the deinterleaver. be able to. Therefore, in the following, in the case where no distinction is required, description will be made assuming that the interleaver also has a deinterleaver function.

Now, the elements in such a decoding device 3
The decoder will be described in detail below. In addition, below
Is, if necessary, used for each element encoding in the encoding device 1.
States representing the contents of the shift register of the device
(Transition state) is represented by m (0, 1,..., M−1),
The state at time t is S_tExpressed by In addition, one time slot
Assuming that k-bit information is input to the
The input at t is i_t= (I_t1, I_t2, ..., i_tk)
And the input system is I₁ ^T= (I₁, I_Two, ..., i_T)
Expressed by At this time, the transition from state m 'to state m
If there is a transition, the information bit corresponding to the transition is set to i
(M ', m) = (i₁(M ', m), i_Two(M ', m),
..., i_k(M ', m)). Furthermore, one
It is assumed that an n-bit code is output to the time slot.
And the output at time t is x_t= (X_t1, X_t2, ...
・, X_tn) And the output system is X₁ ^T= (X₁, X_Two, ...
・, X _T). At this time, stay from state m '
If there is a transition to m, the code corresponding to that transition
Let the bits be x (m ', m) = (x₁(M ', m), x
_Two(M ', m), ..., x_n(M ', m)). Ma
The memoryless communication path 2 is X₁ ^T, And Y₁ ^TOutput
Shall be. Here, one time slot has n bits.
Assuming that the received value is output, the output at time t
To y_t= (Y_t1, Y_t2, ..., y_tn) And Y₁ ^T=
(Y₁, Y_Two, ..., y_T).

2-1 Overall Configuration of Element Decoder Here, the overall configuration of the element decoder will be described with reference to FIGS.

The element decoder 50 schematically shown in FIG. 6 is configured as a large-scale integrated circuit (hereinafter, referred to as an LSI), in which each unit is integrated on a single semiconductor substrate and formed as one chip. . Element decoder 50
Includes a control circuit 60 for controlling each unit, a decoded reception value selection circuit 70 for selecting a reception value to be decoded, an edge detection circuit 80 for detecting the head of a frame, a soft output decoding circuit 90 for performing soft output decoding, An interleaver 100 that rearranges the order of the input data, an address storage circuit 110 that holds replacement destination address data referred to by the interleaver 100, and ten selectors 120 ₁ , 12
0 _2, 120 _3, 120 _4, 120 _5, 120 _6, 120 _7,
120 ₈ , 120 ₉ , 120 ₁₀ and a signal line 130 used for system verification.

Here, FIG. 7 shows the details of the left half of the element decoder 50 shown in FIG. 7, and FIG. 8 shows the details of the right half.

The control circuit 60 controls the decoding reception value selection circuit 7
0, a soft output decoding circuit 90, an interleaver 100, an address storage circuit 110, and nine selectors 12
0 _2, 120 _3, 120 _4, 120 _5, 120 _6, 120 _7,
Various kinds of information are generated and supplied to each of 120 ₈ , 120 ₉ , and 120 ₁₀ , and information from the address storage circuit 110 is received to control the operation of each unit.

More specifically, the control circuit 60 causes the decoded received value selection circuit 70 to select a decoded received value TSR which is a received value to be decoded from the received values R (received values TR). Generates and supplies received value selection information CRS.

The control circuit 60 controls the soft output decoding circuit 9
0, whether the data input as the received value R is actually the received value or the external information, and furthermore, the case where the encoding device 1 performs encoding by TTCM or SCTCM. Is the I / Q value at
Value format information CRTY indicating the format of the received value R
And prior probability information format information CAPP indicating the format of prior probability information such as whether prior probability information is input in units of bits or symbols.
Rate information C indicating the coding rate of the elementary encoder in
RAT, generator matrix information CG indicating a generator matrix of an element encoder in the encoding device 1, and TTCM
And signal point arrangement information CSIG indicating the arrangement of signal points when encoding is performed by SCTCM or SCTCM.

Further, control circuit 60 provides interleaver 100 with interleaver type information CINT indicating the type of interleaving to be performed, interleave length information CINL indicating the interleave length, and a plurality of symbols as described later. The interleaver 100 such as input / output replacement information for replacing the order with each other.
Interleaver input / output replacement information CI related to the processing contents of
PT and termination position information CNFT indicating the termination position of the code
, Termination period information CNFL indicating the termination period of the code, termination state information CNFD indicating the termination state of the code,
It generates and supplies puncture cycle information CNEL indicating a puncture cycle when codes are punctured, and puncture pattern information CNEP indicating a puncture pattern. Further, the control circuit 60 generates and supplies operation mode information CBF indicating an operation mode described later to the interleaver 100.

Further, when writing the address data of the replacement destination referred to by the interleaver 100 to the address storage circuit 110, the control circuit 60 sends the interleaver type information C to the address storage circuit 110.
INT, an address CIAD indicating the address of the address storage circuit 110, and write data CIWD which is address data of a replacement destination referred to by the interleaver 100.
And supply.

The control circuit 60 has six selectors 1
20 _2, 120 _3, 120 _4, 120 _5, 120 _6, 120 ₇
Supplies the operation mode information CBF to
For the three selectors 120 ₈ , 120 ₉ , 120 ₁₀ ,
Verification mode information CTHR indicating whether or not a verification mode is described later is supplied.

On the other hand, the control circuit 60 inputs the read address data ADA which is the replacement destination address data referred to by the interleaver 100 and held in the address storage circuit 110.

Such a control circuit 60 includes a decoded received value selection circuit 70, a soft output decoding circuit 90, an interleaver 10
0, and selectors 120 ₂ , 120 ₃ , 120 ₄ , 12
0 _5, 120 _6, 120 _7, 120 _8, 120 _9, 120 ₁₀
Supplies the generated various information to control the operation of each unit, and also performs the control and operation of writing address data to the address storage circuit 110.

The decoded reception value selection circuit 70 is provided for decoding an arbitrary code, as will be described later, and receives the reception value selection information CR supplied from the control circuit 60.
Based on S, a decoded reception value TSR is selected from the input reception values TR. The decoded received value selection circuit 70 supplies the selected decoded received value TSR to the soft output decoding circuit 90.

More specifically, the decoded received value selection circuit 70
For example, when the received value TR has six received values TR0, TR1, and T
R2, TR3, TR4, and TR5. Of these, the reception values of four systems are decoded reception values TSR0, TSR1, and TSR.
2 and TSR3, for example, as shown in FIG.
As shown in the figure, four selectors 71, 72, 73, 74
Can be realized. At this time,
The received value selection information CRS supplied from the control circuit 60 is
Each of the selectors 71, 72, 73, and 74 is individually given to four systems of received value selection information CRS 0, CRS 1, C
It consists of RS2 and CRS3.

That is, based on the received value selection information CRS0, the selector 71 receives the received values TR0, TR1, TR1
2, TR3, TR4 and TR5, a predetermined reception value is selected and supplied to the soft output decoding circuit 90 as a decoded reception value TSR0.

The selector 72 sets the received value selection information C
Based on the received values TR0, TR1, TR2, T
Select a predetermined reception value from among R3, TR4 and TR5,
It is supplied to the soft output decoding circuit 90 as a decoded reception value TSR1.

Further, based on the received value selection information CRS2, the selector 73 receives the received values TR0, TR1, TR2,
A predetermined received value is selected from TR3, TR4, and TR5, and supplied to the soft output decoding circuit 90 as a decoded received value TSR2.

Then, the selector 74 receives the received values TR0, TR1, TR2 and TR2 based on the received value selection information CRS3.
A predetermined received value is selected from TR3, TR4, and TR5, and supplied to the soft output decoding circuit 90 as a decoded received value TSR3.

As described above, the decoded reception value selection circuit 70
Based on the received value selection information CRS supplied from the control circuit 60, a decoded received value TSR is selected, and the soft output decoding circuit 9 is selected.
Supply 0.

The edge detection circuit 80 receives an externally supplied interleave start position, that is, an interleave start position signal ILS (interleave start position signal TILS) indicating the beginning of a frame, and forms an input received value TR. The beginning of the frame to be detected. The edge detection circuit 80 outputs the edge signal TEILS indicating the head of the detected frame to the soft output decoding circuit 90 and the selector 12.
0 ₅

More specifically, the edge detection circuit 80 can be realized as having a register 81 and an AND gate 82, for example, as shown in FIG.

The register 81 holds an interleave start position signal TILS of, for example, one bit for one clock. The register 81 supplies the held delay interleave start position signal TILSD to the AND gate 82.

The AND gate 82 takes the logical product of the interleave start position signal TILS and data obtained by inverting the delayed interleave start position signal TILSD supplied from the register 81, which is the interleave start position signal TILS one clock before. AND gate 82 supplies the soft-output decoding circuit 90 and the selector 120 ₅ The obtained logical product as an edge signal TEILS.

That is, the edge detection circuit 80 outputs the interleave start position signal TIL supplied from the outside, for example.
It is sufficient to detect that S switches from "0" to "1", and by taking the logical product by the AND gate 82, it is possible to detect that the head of the frame constituting the received value TR has been input. .

The soft output decoding circuit 90 receives the decoded received value TSR supplied from the decoded received value selection circuit 70 and external information or interleaved data EXT (external information or interleaved data T
EXT), and performs MAP decoding based on the Log-BCJR algorithm.

At this time, soft output decoding circuit 90 receives received value format information CRTY supplied from control circuit 60, prior probability information format information CAPP, and coding rate information CLAT.
ER (erasure information TERS) indicating externally supplied puncture patterns and prior probability information erasure information EAP (prior probability information erasure), in addition to the generation matrix information CG and the signal point arrangement information CSIG as necessary. Information TEA
P), termination time information TNP (termination time information TTNP) indicating the termination time of the code, and termination state information TNS (termination state information TTNS) indicating the termination state, and the decoding process is performed.

The soft output decoding circuit 90 outputs the soft output SOL and the external information SOE obtained as a result of the decoding process to the selector 12.
0 supply ₁ to. At this time, the soft output decoding circuit 90 converts the information for the information symbol or the information bit and the information for the code symbol or the code bit based on the output data selection control signal ITM (output data selection control signal CITM) supplied from the outside. Selectively output. When the soft output decoding circuit 90 makes a hard decision, the decoded value hard decision information SDH obtained by performing a hard decision on the soft output which is the decoded value is obtained.
Value hard decision information SR obtained by hard-deciding the received value
H is output to the outside. Also at this time, the soft output decoding circuit 90
Selectively outputs information on information symbols or information bits and information on code symbols or code bits based on an output data selection control signal CITM.

The soft output decoding circuit 90 can also delay the received value TR, external information or interleaved data TEXT, and the edge signal TEILS supplied from the edge detection circuit 80, respectively, as described later. . In this case, the soft output decoding circuit 90 outputs the delayed received value SDR obtained by delaying the received value TR to the selectors 120 ₃ and 120 ₃ .
Supplies 0 _6, external information or interleaved data TE
The selector 12 selects the delayed external information SDEX obtained by delaying the XT.
0 ₂ is supplied to supply the delayed edge signal SDILS obtained by delaying the edge signal TEILS to the selector 120 _5.

The details of the soft output decoding circuit 90 will be described in "2-2".

The interleaver 100 includes a selector 120
₄ based on the same replacement position information as the interleaver in the encoding device 1 (not shown) or the encoding device 1
Deinterleaving is performed such that the bit array of the interleaved data interleaved by the interleaver is returned to the bit array of the original data. At this time,
The interleaver 100 receives an externally supplied interleave mode signal DIN (interleave mode signal C
DIN) and functions as an interleaver or deinterleaver.

The interleaver 100 includes a selector 120
_FiveThe interleave start position signal TIS supplied from
When input, the address is stored in the address storage circuit 110.
Address by specifying the address IAA
Is stored in the address storage circuit 110.
Address data as read address data ADA
Read, based on the read address data ADA
Interleave or deinterleave. this
When the interleaver 100 is supplied from the control circuit 60,
Interleaver type information CINT
Leave length information CINL and interleaver input / output replacement information
Interleave or deinterleave using the
Perform a leave. Interleaver 100 is an interleaver
Interleaver obtained by interleaving or deinterleaving
Selector 120 for the force data IIO ₇To supply.

Further, as described later, the interleaver 100 receives one of the data TD of the received value TR and the delayed received value SDR supplied from the selector 120 _3.
I can also be delayed. At this time, the interleaver 100 delays the data TDI based on the operation mode information CBF supplied from the control circuit 60. The interleaver 100 selects the interleave length reception value IDO obtained by delaying the data TDI,
Supply to ₆ .

Further, as described later, the interleaver 100 outputs the termination position information C supplied from the control circuit 60.
Based on NFT, termination period information CNFL, termination state information CNFD, puncture cycle information CNEL, and puncture pattern information CNEP, when a plurality of the element decoders are connected, the code of the code in the next element decoder is determined. It generates termination time information IGT and termination state information IGS indicating termination time and termination state, and erase position information IGE and interleaver non-output position information INO indicating a puncture position of a code. At the same time, the interleaver 100 delays the interleave start position signal TIS supplied from the selector 120 ₅ to generate a delayed interleave start position signal IDS. The interleaver 100 uses the generated termination time information IGT, termination state information IGS, erasure position information IGE, interleaver non-output position information INO, and delay interleave start position signal IDS as generation next-stage information at the beginning of the frame. synchronized, to the selector 120 _10.

The details of the interleaver 100 will be described in “2-3”.

Although not shown, the address storage circuit 110 is, for example, a plurality of banks of RAM (Random Access Memory).
ry), a selection circuit, and the like, and retains, as address data, replacement position information of data referred to at the time of interleaving or deinterleaving by the interleaver 100. The address data held in the address storage circuit 110 is converted by the interleaver 100 so that the address of the address storage circuit 110 is changed to the address data IA.
By being designated as A, it is read as read address data ADA. Writing of address data to the address storage circuit 110 is performed by the control circuit 60, and the address storage circuit 110
Is designated as the address CIAD, the address data is written as the write data CIWD. In this way, an arbitrary interleaving pattern can be written in the address storage circuit 110. The address storage circuit 110 may be provided inside the interleaver 100. That is, the element decoder 50 performs the interleave processing or the deinterleave processing by using both the interleaver 100 and the address storage circuit 110.

The selector 120 ₁ selects _one of the soft output SOL supplied from the soft output decoding circuit 90 and the external information SOE based on the output data selection control signal CITM, and selects the selector 120 ₁ as data TLX. _Two
To supply. That is, the selector 120 ₁ determines whether the soft output decoding circuit 90 should output external information in the process of iterative decoding or should output a soft output as a final result. It is provided.

The selector 120 ₂ receives the operation mode information CB
Based on F, one of the delay external information SDEX supplied from the soft output decoding circuit 90 and the data TLX supplied from the selector 120 ₁ is selected, and the selectors 120 ₄ and 120 ₇ are selected as the data TDLX. To supply.

Here, the operation mode of the element decoder 50 will be described. The element decoder 50 has, for example, six operation modes. The first mode is a mode in which the soft output decoding circuit 90 and the interleaver 100 perform normal soft output decoding processing and interleave processing, respectively. The second is a mode in which only the soft output decoding circuit 90 performs normal soft output decoding processing. Third, a mode in which only the interleaver 100 performs a normal interleave process. Fourth, the soft output decoding circuit 90 and the interleaver 100
Are modes that function as delay circuits without performing normal soft-output decoding processing and interleaving processing, respectively. Fifth, there is a mode in which only the soft output decoding circuit 90 functions as a delay circuit without performing normal soft output decoding processing. Sixth, a mode in which only the interleaver 100 functions as a delay circuit without performing normal interleave processing. These operation modes are determined by the control circuit 60 and are supplied to each section as operation mode information CBF. Hereinafter, the first to third modes are collectively referred to as a normal mode, and the fourth to sixth modes are collectively referred to as a delay mode, as necessary.

[0161] Specifically, the selector 120 _2, the operation mode information CBF is, processing time soft-output decoding circuit 90 takes the same time delay, the processing time and the time interleaver 100 is necessary delay, or, soft If it indicates a delay mode in which any of the processing time required by the output decoding circuit 90 and the interleaver 100 is to be delayed, the delay external information SDEX is selected and output, and the operation mode information CBF is output. Indicates the normal mode in which the processing by the soft output decoding circuit 90 and / or the interleaver 100 is performed without performing the delay by the soft output decoding circuit 90 and / or the interleaver 100, the data TLX
Select and output. That is, the selector 120 ₂
Whether the operation mode of the element decoder 50 is the delay mode,
Alternatively, it is provided to determine whether the mode is the normal mode, and selects data to be output according to each operation mode.

The selector 120 ₃ receives the operation mode information CB
Based on F, one of the received value TR and the delayed received value SDR supplied from the soft output decoding circuit 90 is selected and supplied to the interleaver 100 as data TDI. Specifically, the selector 120 ₃ indicates that the operation mode information CBF indicates a normal mode in which only the processing by the interleaver 100 is performed, or a delay mode in which the processing time required by the interleaver 100 is to be delayed at the same time. If there is, the reception value TR is selected and output. If the operation mode information CBF indicates any other normal mode or delay mode, the delay reception value SDR
Select and output. That is, the selector 120 ₃
The data input to the interleaver 100 is provided to determine whether or not to use the soft output decoding process by the soft output decoding circuit 90 or the data delayed at the same time as the processing time required by the soft output decoding circuit 90. That can be
The data to be output is selected according to each operation mode.

The selector 120 ₄ receives the operation mode information CB
F or external information or interleaved data TE
XT and data TDL supplied from the selector 120 ₂
X and one of them is selected and supplied to the interleaver 100 as data TII. Specifically, the selector 120 ₄ indicates that the operation mode information CBF indicates a normal mode in which only the processing by the interleaver 100 is performed, or a delay mode in which the processing time required by the interleaver 100 is to be delayed at the same time. If there is, select and output the external information or interleaved data TEXT, and if the operation mode information CBF indicates any other normal mode or delay mode, the data TD
Select and output LX. That is, the selector 120 ₄
Is data input to the interleaver 100,
It is provided to determine whether or not to use a soft output decoding process by the soft output decoding circuit 90 or a delay that is the same as the processing time required by the soft output decoding circuit 90 or not. Select the data to output.

The selector 120 ₅ receives the operation mode information CB
F, one of the edge signal TEILS supplied from the edge detection circuit 80 and the delayed edge signal SDILS supplied from the soft output decoding circuit 90 is selected, and the interleaver is used as the interleave start position signal TIS. Supply 100. Specifically, selector 1
20 _5, the operation mode information CBF is, the interleaver 1
00 indicates a normal mode in which only the processing by 00 is performed or a delay mode in which the delay is to be performed at the same time as the processing time required by the interleaver 100, and selects and outputs the edge signal TEILS. Information CBF
Indicates the other normal mode or delay mode, selects and outputs the delayed edge signal SDILS. That is, the selector 120 ₅ determines whether or not to use, as the data input to the interleaver 100, the soft-output decoding processing by the soft-output decoding circuit 90 or the processing time required for the soft-output decoding circuit 90 and the delay that has been performed at the same time. This is provided to determine whether the data to be output is selected in accordance with each operation mode.

The selector 120 ₆ sets the operation mode information CB
Based on F, one of the delayed received value SDR supplied from the soft output decoding circuit 90 and the interleaved long delayed received value IDO supplied from the interleaver 100 is selected, and a selector is selected as the delayed received value TDR. 120
Supply ₈ More specifically, the selector 120 ₆ determines whether the operation mode information CBF is a normal mode in which only the processing by the soft output decoding circuit 90 is performed, or a delay mode in which the processing time required by the soft output decoding circuit 90 is to be delayed at the same time. , Select and output the delayed reception value SDR, and if it indicates any other normal mode or delay mode, select and output the interleave length delay reception value IDO. I do. That is, the selector 120 _6, as data to be output, is provided in order to determine whether to use having been subjected to the processing time and the time delay required interleaving processing or interleaver 100 by the interleaver 100 Yes, data to be output is selected according to each operation mode.

[0166] The selector 120 _7, the operation mode information CB
Based on F, and the interleaver output data IIO supplied from the interleaver 100, among the data TDLX supplied from the selector 120 _2, selects one, to the selector 120 ₉ as soft-output TSO. Specifically, the selector 120 _7, the operation mode information CBF is, normal mode or the delay mode to perform the processing time of the same time delay the soft-output decoding circuit 90 requires performs only processing by the soft-output decoding circuit 90 , The data TDLX is selected and output, and if it indicates any other normal mode or delay mode, the interleaver output data IIO is selected and output. That is, the selector 120 _7, as data to be output, is provided in order to determine whether to use having been subjected to the processing time and the time delay required interleaving processing or interleaver 100 by the interleaver 100 Yes, data to be output is selected according to each operation mode.

The selector 120 ₈ receives the verification mode information CT
Based on the HR, the delayed received value TDR supplied from the selector 120 _6, among the through signal transmitted by the signal line 130, selects one and outputs it to the outside as a delayed received value TRN. Note that the delay reception value TRN
Is output as the delayed reception value RN. That is, the selector 120 ₈ and is provided either to output the delayed received value for the next stage element decoder, whether to validate the system, in order determined.

[0168] The selector 120 _9, verification mode information CT
Based on the HR, and soft-output TSO supplied from the selector 120 _7, among the through signal transmitted by the signal line 130, selects one, the soft-output TINT
And output to the outside. Note that this soft output TINT is
It is output as a soft output INT. That is, the selector 1
20 ₉ and is provided either to output the soft output for the next element decoder, whether to validate the system, in order determined.

[0169] The selector 120 _10, verification mode information CT
Based on HR, termination time information IGT and termination state information IGS supplied from interleaver 100, erasure position information IGE and interleaver non-output position information I
NO and the generated next-stage information including the delay interleave start position signal IDS, and the through signal transmitted through the signal line 130, and selects one of the next-stage end time information TTNPN and the next-stage end state. Information TTN
SN, the next-stage erasure position information TERSN and the next-stage prior probability information erasure information TEAPN, and the next-stage interleave start position signal TILSN are output to the outside. The next-stage end time information TTNPN, the next-stage end state information TTNSN, the next-stage erasure position information TERSN, the next-stage prior probability information erasure information TEAPN, and the next-stage interleave start position signal TILSN are respectively set to the next-stage end. Time information TNPN, next-stage termination state information TNSN, next-stage erasure position information ERSN, next-stage prior probability information erasure information EAP
N and the next-stage interleave start position signal ILSN. That is, the selector 120 ₁₀ is provided either to output the next stage information for the next stage element decoder, whether to validate the system, in order determined.

As will be described later, the signal line 130 mainly
It is used for verifying the system when a decoding device 3 similar to the above-described decoding devices 3 'and 3''is constructed by connecting a plurality of element decoders 50. The signal line 130 transmits the received value TR, external information or interleaved data TEXT, erasure information TERS, prior probability information erasure information TEAP, termination time information TTNP, termination state information TTNS, and an interleave start position signal TILS. And the selectors 120 ₈ , 12
0 ₉ , 120 ₁₀ .

Such an element decoder 50 is equivalent to a module including at least a soft output decoding circuit and an interleaver or a deinterleaver, as shown by a broken line in FIG. 3 or a broken line in FIG. Things. The element decoder 50 has a PCC
A decoding device 3 that can decode any code among C, SCCC, TTCM, and SCTCM can be configured. The various features relating to the entire element decoder 50 will be further described in “4.” which will be described later.

Hereinafter, the soft output decoding circuit 90 and the interleaver 100 will be described in more detail.

2-2 Details of Soft Output Decoding Circuit First, the soft output decoding circuit 90 will be described in detail. As shown schematically in FIG. 11, the soft output decoding circuit 90 includes a code information generation circuit 151 for generating code information of an elementary encoder in the encoding device 1 and internal erasure information indicating a puncture pattern in the encoding device 1. , An end information generation circuit 153 for generating end information in the encoding device 1, a reception value to be input for decoding processing, and prior probability information,
A received value and prior probability information selection circuit 154 for replacing a position where no code output exists with a symbol having a likelihood of “0”;
A storage circuit 155 for storing both received data and delay data, a storage circuit 155 for delay, an Iγ calculation circuit 156 for calculating a log likelihood Iγ as a first log likelihood, Iγ that distributes the calculated log likelihood Iγ
A distribution circuit 157 and a log likelihood Iα that is a second log likelihood
158, an Iβ calculation circuit 159 for calculating a third log likelihood Iβ, an Iβ storage circuit 160 for storing the calculated log likelihood Iβ, and a log soft output Iλ. A soft output calculation circuit 161 for calculating, a reception value or prior probability information separation circuit 162 for separating a reception value and prior probability information, an external information calculation circuit 163 for calculating external information, and an amplitude of a log soft output Iλ are adjusted. In addition, it has an amplitude adjustment and clip circuit 164 for clipping to a predetermined dynamic range and a hard decision circuit 165 for hard-deciding a soft output and a received value as decoded values.

Here, FIG. 12 shows details of the left half portion of the soft output decoding circuit 90 shown in FIG. 12, and FIG. 13 shows details of the right half portion.

The code information generation circuit 151 includes the control circuit 60
Rate information CRAT and generator matrix information C supplied from
Based on G, code information of an element encoder in the encoding device 1 is generated. Specifically, the code information generation circuit 1
Reference numeral 51 denotes input bit number information IN indicating the number of input bits of an element encoder in the encoding device 1 and, when the element encoder in the encoding device 1 is a convolutional encoder, the convolutional encoder is The so-called Woze craft
type information WM indicating whether the type is an ncraft type or a Massy type, and a shift register of an element encoder in the encoding device 1, that is, the number of memories indicating the number of memories representing a state (transition state) Information MN and encoding device 1
In the trellis, which is a state transition diagram of the element encoder in, there are branch input / output information BIO indicating input / output information along the time axis for each branch, and an output from the element encoder in the encoding device 1. And the valid output position information PE indicating the validity of the output position indicating that the corresponding received value exists.

Here, a Bozencraft convolutional encoder and a Massy convolutional encoder will be described.

The Bozencraft convolutional encoder includes a delay element and a combination circuit, and holds data in a time series with respect to the delay element. As an example of a Bozencraft type convolutional encoder, for example, as shown in FIG. 14, four shift registers 201 ₁ ,
201 _2, 201 _3, and 201 _4, 16 exclusive OR circuits 202 _1, 202 _2, 202 _3, 202 _4, 202 _5,
202 _6, 202 _7, 202 _8, 202 _9, 202 _10, 20
2 ₁₁ , 202 ₁₂ , 202 ₁₃ , 202 ₁₄ , 202 ₁₅ , 20
2 ₁₆ and 20 AND gates G0 [0], GB
[0], GB [1], GB [2], GB [3], G1
[0], G1 [1], G1 [2], G1 [3], G1
[4], G2 [0], G2 [1], G2 [2], G2
[3], G2 [4], G3 [0], G3 [1], G3
Some have a combinational circuit represented by [2], G3 [3], G3 [4], and perform a convolution operation with a coding rate of “１ ／”. In this convolutional encoder, AND gates G0 [0], GB [0], GB
[1], GB [2], GB [3], G1 [0], G1
[1], G1 [2], G1 [3], G1 [4], G2
[0], G2 [1], G2 [2], G2 [3], G2
[4], G3 [0], G3 [1], G3 [2], G3
[3] and G3 [4] indicate whether or not to connect according to the code configuration, and not all AND gates are used. In other words, the convolutional encoder performs a logical operation on these AND gates G0 [0], GB [0], GB
[1], GB [2], GB [3], G1 [0], G1
[1], G1 [2], G1 [3], G1 [4], G2
[0], G2 [1], G2 [2], G2 [3], G2
[4], G3 [0], G3 [1], G3 [2], G3
[3], G3 [4], the combinational circuit changes, the code configuration changes, and the maximum number of states is "2 ⁴ = 16", and a convolution operation of the Bozencraft type can be performed. It is. The generator matrix G of the convolutional encoder is represented by the following equation (27). The following equation (2
7), GB (D), G1 (D), G2 (D),
G3 (D) is expressed by the following equations (28) to (3), respectively.
It is represented by 1).

[0178]

[Equation 27]

[0179]

[Equation 28]

[0180]

(Equation 29)

[0181]

[Equation 30]

[0182]

(Equation 31)

[0183] Examples of the convolutional encoder baud Zen craft type, for example, as shown in FIG. 15, the three shift registers 203 _1, 203 _2, 203 _3, 12 exclusive OR circuits 204 ₁ , 204 ₂ , 204 ₃ , 20
4 _4, 204 _5, 204 _6, 204 _7, 204 _8, 204 _9,
204 _10, 204 _11, 204 ₁₂ and 15 AND gates G1 [0], G1 [1 ], G1 [2], G1 [3],
G1 [4], G2 [0], G2 [1], G2 [2], G
2 [3], G2 [4], G3 [0], G3 [1], G3
[2], a combination circuit represented by G3 [3], and G3 [4], which performs a convolution operation with a coding rate of "2/3". Note that also in this convolutional encoder, AND gates G1 [0], G1 [1], G1
[2], G1 [3], G1 [4], G2 [0], G2
[1], G2 [2], G2 [3], G2 [4], G3
[0], G3 [1], G3 [2], G3 [3], G3
[4] indicates whether or not the connection is made by the code configuration. Not all AND gates are used.
The combinational circuit changes and the code configuration changes, so that the maximum number of states is "2 ³ = 8" and a convolution operation of the Bozencraft type can be performed.
The generator matrix G of the convolutional encoder is represented by the following equation (32). In the following equation (32), G11 (D), G21
(D), G31 (D), G12 (D), G22 (D),
G32 (D) is expressed by the following equations (33) to (3), respectively.
8).

[0184]

(Equation 32)

[0185]

[Equation 33]

[0186]

(Equation 34)

[0187]

(Equation 35)

[0188]

[Equation 36]

[0189]

(37)

[0190]

(38)

On the other hand, a Massy type convolutional encoder is
It is composed of a delay element and a combinational circuit, in which any of the input bits is output as a tissue component as it is, and data is not stored in the delay element in time series. Examples of Massey-type convolutional encoder, for example, as shown in FIG. 16, ₁ three shift registers 205, 205 _2, 205 ₃ and four XOR circuits 206 _1, 206 _2, 206 _3, 206 ₄ and 1
One AND gate GB [0], GB [1], GB
[2], G1 [0], G1 [1], G1 [2], G1
[3], G2 [0], G2 [1], G2 [2], G2
There is a combination circuit having a combinational circuit represented by [3] and performing a convolution operation with a coding rate of "2/3". Note that also in this convolutional encoder, the AND gate GB
[0], GB [1], GB [2], G1 [0], G1
[1], G1 [2], G1 [3], G2 [0], G2
[1], G2 [2], and G2 [3] indicate whether or not connection is made by a code configuration. Not all AND gates are used, but the combinational circuit changes and the code configuration changes. The maximum number of states is "2 ³ = 8", so that a Massy-type convolution operation can be performed. The generator matrix G of this convolutional encoder
Is represented by the following equation (39). In the following equation (39), G
B (D), G1 (D) and G2 (D) are represented by the following equations (40) to (42), respectively.

[0192]

[Equation 39]

[0193]

(Equation 40)

[0194]

[Equation 41]

[0195]

(Equation 42)

An example of a Massy type convolutional encoder
For example, as shown in FIG.
Jista 207₁, 207_TwoAnd three exclusive OR circuits 2
08 ₁, 208_Two, 208_ThreeAnd 11 AND gates G
B [0], GB [1], G1 [0], G1 [1], G1
[2], G2 [0], G2 [1], G2 [2], G3
Combinations represented by [0], G3 [1], G3 [2]
And a convolution operation having a coding rate of “3/3”
There is something to do. In this convolutional encoder,
Are also AND gates GB [0], GB [1], G1
[0], G1 [1], G1 [2], G2 [0], G2
[1], G2 [2], G3 [0], G3 [1], G3
[2] indicates whether or not to connect according to the code configuration.
Yes, not all AND gates are used,
The combinational circuit changes and the code configuration changes.
Therefore, the maximum number of states is “2”.^Two= 4 ”Massy type
A convolution operation can be performed. This fold
The generator matrix G of the embedded encoder is expressed by the following equation (43).
In the following equation (43), GB (D), G1 (D), G2
(D) and G3 (D) are expressed by the following equations (44) to (44), respectively.
It is represented by equation (47).

[0197]

[Equation 43]

[0198]

[Equation 44]

[0199]

[Equation 45]

[0200]

[Equation 46]

[0201]

[Equation 47]

Here, in order to specifically describe the information generated by the code information generation circuit 151, a specific example of each convolutional encoder will be shown.

First, as the Bozencraft type convolutional encoder shown in FIG. 14, 15 AND gates G
0 [0], GB [2], GB [3], G1 [0], G1
[1], G1 [3], G1 [4], G2 [0], G2
[2], G2 [4], G3 [0], G3 [1], G3
When [2], G3 [3] and G3 [4] are connected, FIG.
As shown in the figure, four shift registers 201 ₁ , 20
1 _2, 201 _3, and 201 _4, 11 of the exclusive-OR circuit 202 _1, 202 _4, 202 _5, 202 _7, 202 _8, 20
2 ₁₀ , 202 ₁₂ , 202 ₁₃ , 202 ₁₄ , 202 ₁₅ , 20
2 ₁₆ is conceivable. The convolutional encoder inputs the input data i ₀ of 1 bit, performs convolution with respect to the input data i _0, output data O ₀ 4-bit calculation result, O _1, O _2, O ₃ Output as

The description of the trellis in this convolutional encoder is as shown in FIG. In the figure,
The label attached to each branch indicates the branch number. The relationship between the state before and after the transition and the input data / output data for this branch number is as shown in Table 1 below. Here, state, shift register 201 _4, the shift register 2
01 _3, the shift register 201 ₂ and the shift register 20
Are those that sequentially arranged a 1 ₁ of the content, "0000",
“0001”, “0010”, “0011”, “010”
0 "," 0101 "," 0110 "," 0111 ",
“1000”, “1001”, “1010”, “101”
1 "," 1100 "," 1101 "," 1110 ",
The state numbers of “1111” are “0”,
"1", "2", "3", "4", "5", "6",
“7”, “8”, “9”, “10”, “11”, “1”
2 "," 13 "," 14 ", and" 15 ", and the input data / output data are i ₀ / O ₃ , O ₂ , O ₁ ,
O ₀ .

[0205]

[Table 1]

As described above, the number of states in the convolutional encoder shown in FIG. 18 is 16, the trellis has a structure in which two paths reach from each state to the state at the next time, and a total of 32 branches are used. Having a structure having

In the case of this convolutional encoder, the code information generator 151 sets “1 bit” as the input bit number information IN, “Bosencraft type” as the type information WM,
“4” as the number-of-memory information MN and the branch input / output information BIO
, An input / output pattern of each branch as shown in Table 1 is generated.

As the Bozencraft type convolutional encoder shown in FIG. 15, nine AND gates G1
[2], G1 [3], G2 [0], G2 [4], G3
[0], G3 [1], G3 [2], G3 [3], G3
Tying [4], as shown in FIG. 20, the three shift registers 203 _1, 203 _2, 203 _3, six of the exclusive OR circuit 204 _5, 204 _6, 204 _9, 204 _10,
Having a 204 _11, 204 ₁₂ are conceivable. When the convolutional encoder inputs 2-bit input data i ₀ , i ₁ , it performs a convolution operation on these input data i ₀ , i ₁ , and outputs the operation result as 3-bit output data O ₀ , O 1. output as _1, O _2.

The description of the trellis in this convolutional encoder is as shown in FIG. In the figure,
The label attached to each branch indicates the branch number. The relationship between the state before and after the transition and the input data / output data for this branch number is as shown in Table 2 below. Here, the states are shift register 203 ₃ , shift register 2
03 is _2, and that sequentially arranged shift registers 203 ₁ Contents, "000", "001", "010", "0
11 "," 100 "," 101 "," 110 "," 11 "
The state numbers of “1” are “0”, “1”,
They are represented as “2”, “3”, “4”, “5”, “6”, and “7”. The input data / output data are i ₁ , i ₀
/ O ₂ , O ₁ , O ₀ .

[0210]

[Table 2]

As described above, the number of states in the convolutional encoder shown in FIG. 20 is 8, the trellis has a structure in which four paths reach from each state to the state at the next time, and a total of 32 branches are used. It becomes what has.

In the case of this convolutional encoder, the code information generation section 151 sets “2 bits” as input bit number information IN, “Bosencraft type” as type information WM,
“3” as the number-of-memory information MN and the branch input / output information BIO
And an input / output pattern of each branch as shown in Table 2 is generated.

Further, as the Massey type convolutional encoder shown in FIG. 16, three AND gates GB
When [2], G1 [2] and G2 [1] are connected, FIG.
As shown in the figure, three shift registers 205 ₁ , 20
52 ₂ , 205 ₃ and two exclusive OR circuits 206 ₂ , 2
Those with and 06 ₃ can be considered. When this convolutional encoder receives 2-bit input data i ₀ and i ₁ ,
A recursive systematic convolution operation is performed on these input data i ₀ , i ₁ , and the operation result is output as 3-bit output data O ₀ ,
Output as O ₁ and O ₂ .

The trellis in this convolutional encoder is described as shown in FIG. In the figure,
The label attached to each branch indicates the branch number. The relationship between the state before and after the transition and the input data / output data for this branch number is as shown in Table 3 below. Here, the states are shift register 205 ₁ , shift register 2
05 is _2, and that sequentially arranged contents of the shift register 205 _3, "000", "001", "010", "0
11 "," 100 "," 101 "," 110 "," 11 "
The state numbers of “1” are “0”, “1”,
They are represented as “2”, “3”, “4”, “5”, “6”, and “7”. The input data / output data are i ₁ , i ₀
/ O ₂ , O ₁ , O ₀ .

[0215]

[Table 3]

As described above, the number of states in the convolutional encoder shown in FIG. 22 is 8, the trellis has a structure in which four paths reach from each state to the state at the next time, and a total of 32 branches are used. It becomes what has.

In the case of this convolutional encoder, the code information generation section 151 sets “2 bits” as input bit number information IN, “Massie type” as type information WM, “3” as memory number information MN, An input / output pattern of each branch as shown in Table 3 is generated as the branch input / output information BIO.

Further, the Massy type shown in FIG.
As the convolutional encoder, six AND gates GB
[1], G1 [0], G1 [1], G1 [2], G2
When [0] and G3 [0] are connected, as shown in FIG.
And two shift registers 207₁, 207_TwoAnd three
Exclusive OR circuit 208₁, 208_Two, 208_ThreeHave
Things are conceivable. This convolutional encoder has three bits.
Input data i₀, I₁, I _TwoTo enter these
Input data i₀, I₁, I_TwoRecursive tissue convolution for
Performs an operation and outputs the operation result as 3-bit output data O₀,
O₁, O_TwoOutput as

The trellis in the convolutional encoder is described as shown in FIG. In the figure,
The label attached to each branch indicates the branch number. The relationship between the state before and after the transition and the input data / output data for this branch number is as shown in Table 4 below. Here, the state, which has sequentially arranged shift registers 207 ₁ and the shift register 207 _{and second} contents, "00",
The state numbers "01", "10", and "11" are represented as "0", "1", "2", and "3", respectively.
The input data / output data are i ₂ , i ₁ , i ₀ /
O ₂ , O ₁ and O ₀ .

[0220]

[Table 4]

As described above, the number of states in the convolutional encoder shown in FIG. 24 is 4, and the trellis has a structure in which four sets of parallel paths reach from each state to the state at the next time. It will have branches.

In the case of this convolutional encoder, the code information generation section 151 sets “3 bits” as input bit number information IN, “Massie type” as type information WM, “2” as memory number information MN, An input / output pattern of each branch as shown in Table 4 is generated as the branch input / output information BIO.

As described above, the code information generation circuit 151
Code information corresponding to the element encoder in the encoding device 1 is generated. In particular, the code information generation circuit 151 calculates input / output patterns of all branches on the trellis according to the code,
The branch input / output information BIO is generated, which will be further described later. The code information generation circuit 151 converts the generated input bit number information IN into a termination information generation circuit 153, a reception value and prior probability information 154, an Iγ calculation circuit 156, and an Iγ
Distribution circuit 157, Iα calculation circuit 158, Iβ calculation circuit 1
59, a soft output calculation circuit 161, a received value or prior probability information separation circuit 162, and a hard decision circuit 165.
Further, the code information generation circuit 151 generates the type information WM.
Is supplied to the Iγ calculation circuit 156, the Iγ distribution circuit 157, the Iα calculation circuit 158, and the Iβ calculation circuit 159. Further, the code information generation circuit 151 transmits the generated memory number information MN to the termination information generation circuit 153 and the Iγ distribution circuit 15.
7, Iα calculation circuit 158, Iβ calculation circuit 159,
It is supplied to the soft output calculation circuit 161. Furthermore, the code information generation circuit 151 converts the generated branch input / output information BIO into
It is supplied to the Iγ distribution circuit 157 and the soft output calculation circuit 161. Further, the code information generation circuit 151 supplies the generated valid output position information PE to the internal erasure information generation circuit 152.

The internal erasure information generation circuit 152 includes an erasure information TERS supplied from the outside and a code information generation circuit 15
1 based on the effective output position information PE supplied from
Internal erasure position information IERS indicating a position where there is no code output obtained by considering the puncture pattern and the effective output position comprehensively is generated.

Specifically, internal erasure information generation circuit 152
Is, for example, as shown in FIG.
It can be realized as having a 1 _1, 211 _2, 211 _3, 211 _4.

[0226] OR gate 211 _1, 211 _2, 211 _3,
Each of the elements 211 ₄ ORs the erasure information TERS and data obtained by inverting the effective output position information PE supplied from the code information generation circuit 151. OR gate 21
1 _1, 211 _2, 211 _3, 211 _4, respectively, and supplies the received value and a priori probability information selection circuit 154 the logical sum obtained as internal erasure position information IERS.

As described above, internal erase information generation circuit 152
By taking the logical sum by an OR gate 211 _1, 211 _2, 211 _3, 211 _4, and generates an internal erasure position information IERS indicating the position code output is not present.

The termination information generation circuit 153 includes termination time information TTNP and termination state information TT supplied from outside.
Based on NS, the input bit number information IN and the memory number information MN supplied from the code information generation circuit 151, termination information in the encoding device 1 is generated. In particular,
The termination information generation circuit 153, based on termination time information TTNP, termination state information TTNS, input bit number information IN, and memory number information MN, terminate time information TPM indicating the termination time in the encoding device 1 and termination indicating the termination state. Generate state information TSM.

The termination information generation circuit 153 is provided, for example, in FIG.
As shown in FIG.₁, 212_Two, 21
2_Three, 212_Four, 212_Five, 212₆And a plurality of selectors 2
13 ₁, 213_Two, 213_Three, 213_Four, 213_Five, 21
3₆, 213₇, 213₈, 213 ₉And the AND gate 21
4 can be realized.

[0230] Register 212 _1, the termination time information TTNP supplied from the outside and held by one clock, and supplies the held termination time information TTNP the register 212 ₂ and the selector 213 _3.

The register 212 ₂ holds the termination time information TTNP supplied from the register 212 ₁ for one clock, and stores the retained termination time information TTNP in the register 212 _3.
And the selector 213 ₄ .

The register 212 ₃ holds the termination time information TTNP supplied from the register 212 ₂ for one clock, and stores the retained termination time information TTNP in the selector 213 _5.
To supply.

[0233] register 212 ₄ holds termination state information TTNS supplied from outside by one clock, and supplies the held termination state information TTNS the register 212 ₅ and selector 213 _6.

The register 212 ₅ holds the termination state information TTNS supplied from the register 212 ₄ for one clock, and supplies the retained termination state information TTNS to the register 212 ₆ and the selector 213 ₇ .

[0235] Register 212 _6, a termination state information TTNS supplied from the register 212 ₅ holds only one clock, and supplies the held termination state information TTNS to the selector 213 _8.

The selector 213 ₁ receives the input bit number information I.
Based on N, for example, information indicating that the number of memories of the elementary encoder in the encoding device 1 is “1” and information indicating that the number of memories is “2” in the memory number information MN. And one of them is selected. Specifically, for example, when the number of input bits in the encoding device 1 is “1”, the selector 213 ₁ selects information indicating that the number of memories is “1”. Selector 21
3 ₁ supplies to the selector 213 ₃ as a control signal for selecting the selected data.

The selector 213 ₂ receives the input bit number information I.
Based on N, for example, information indicating that the number of memories of the element encoder in the encoding device 1 is “2” and information indicating that the number of memories is “3” in the memory number information MN. And one of them is selected. Specifically, for example, when the number of input bits in the encoding device 1 is “1”, the selector 213 ₂ selects information indicating that the number of memories is “2”. Selector 21
3 ₂ supplies to the selector 213 ₄ as a control signal for selecting the selected data.

The selector 213 ₃ selects _one of the termination time information TTNP supplied from the register 212 ₁ and data having the value “1” based on the data selected by the selector 213 _1. . In particular,
The selector 213 _3, if the memory number of elements encoder in the encoder 1 is "1", the register 212
_The termination time information TTNP supplied from ₁ is selected. The selector 213 ₃ outputs the selected data to the AND gate 21.
4

The selector 213 ₄ selects one of the termination time information TTNP supplied from the register 212 ₂ and the data whose value is “1” based on the data selected by the selector 213 _2. . In particular,
When the number of memories of the element encoder in the encoding device 1 is “2”, the selector 213 ₄ operates as the register 212 4.
_The termination time information TTNP supplied from ₂ is selected. The selector 213 ₄ outputs the selected data to the AND gate 21.
4

[0240] The selector 213 _5, based on the number of memories information MN, out of the data termination time information TTNP value supplied is "1" from the register 212 _3, selects either. Specifically, the selector 213 ₅
The number of memories of the element encoder in the encoding device 1 is “3”
If it is selects the termination time information TTNP supplied from the register 212 _3. The selector 213 ₅ supplies the selected data to the AND gate 214.

The selector 213 ₆ selects one of the termination state information TTNS supplied from the register 212 ₄ and data whose value is “0”, based on the memory number information MN. Specifically, the selector 213 ₆
, When the number of memory elements encoder in the encoder 1 is "1", selects the termination state information TTNS supplied from the register 212 _4. Selector 21
3 ₆ supplies the selected data to the selector 213 _8.

[0242] The selector 213 _7, based on the number of memories information MN, termination state information TTNS value supplied from the register 212 ₅ out of the data is "0", selects either. Specifically, the selector 213 ₇
, When the number of memory elements encoder in the encoder 1 is "2", selects the termination state information TTNS supplied from the register 212 _5. Selector 21
3 ₇ supplies the selected data to the selector 213 _8.

[0243] The selector 213 ₈ based on the number of memories information MN, termination state information TTNS value supplied from the register 212 ₆ Out of the data is "0", selects either. Specifically, the selector 213 ₈
, When the number of memory elements encoder in the encoder 1 is "3", selects the termination state information TTNS supplied from the register 212 _6. Selector 21
3 ₈ supplies the selected data to the selector 213 _8.

The selector 213 ₉ receives the input bit number information I.
N, based on the termination state information T supplied from outside.
One of the TNS and the data supplied from the selectors 213 ₆ , 213 ₇ and 213 ₈ is selected. The selector 213 ₉ supplies the selected data to the reception data and delay storage circuit 155 as termination state information TSM.

The AND gate 214 has the termination time information TTNP supplied from the outside and the selectors 213 ₃ , 21 ₃
3 _4, 213 takes a logical product of the data supplied from the _5.
The AND gate 214 supplies the obtained logical product to the reception data and delay storage circuit 155 as termination time information TPM.

The termination information generation circuit 153 ascertains the termination period based on the memory number information MN and selects the data according to the termination period by the selectors 213 ₃ , 21 ₃ .
3 _4, 213 _5, by performing a 213 _6, 213 _7, 213 _8, it is possible to generate termination information for any termination period. In particular, as described later, when the element encoder in the encoding device 1 is a Bozencraft convolutional encoder, the termination information generation circuit 153 outputs information corresponding to the number of input bits as termination information. The termination state is specified by generating the termination period only. In addition, as described later, the termination information generation circuit 153 outputs termination information as the termination information when the element encoder in the encoding device 1 is other than a Bozencraft type convolutional encoder such as a Massy type. By generating information indicating the termination state in one time slot, the termination state is specified in one time slot.

Receiving value and prior probability information selecting circuit 154
Is provided for decoding an arbitrary code, as described later. The reception value and prior probability information selection circuit 154 includes a reception value format information CRTY supplied from the control circuit 60, input bit number information IN supplied from the code information generation circuit 151, and prior probability information erasure supplied from the outside. Based on the information TEAP and the internal erase position information IERS supplied from the internal erase information generation circuit 152,
Information necessary for performing soft-output decoding is selected from the input decoded reception value TSR and external information or interleaved data TEXT. Further, the reception value and prior probability information selection circuit 154 determines a position where no code output exists based on the internal erasure position information IERS supplied from the internal erasure information generation circuit 152, as described later, with a likelihood of “0”. Replace with the symbol. That is, the reception value and prior probability information selection circuit 154 sets the probability that the bit corresponding to the position where no code output exists is “0” or “1” to “1/2”. Output important information.

More specifically, selection of received value and prior probability information
The circuit 154, for example, decodes the decoded received value TSR into four systems.
From the received signal values TSR0, TSR1, TSR2 and TSR3
And external information or interleaved data TE
XT has three systems of external information or interleaved data TE
XT0, TEXT1, TEXT2
And, for example, as shown in FIG.
5₁, 215_Two, 215_Three, 215_Four, 215_Five, 215₆,
215₇, 215₈, 215₉, 215_Ten, 215 ₁₁, 2
Fifteen₁₂, 215₁₃, 215₁₄, 215_Fifteen, 215₁₆And
It can be realized as having.

The selector 215 ₁ receives the received value format information CR.
Based on TY, one of the decoded received value TSR0 and the external information or interleaved data TEXT0 is selected. Specifically, when the received value format information CRTY indicates external information, the selector 215 ₁ selects the external information or the interleaved data TEXT0. The selector 215 ₁ supplies the selected data to the selector 215 ₈ .

The selector 215 ₂ receives the received value format information CR.
Based on TY, one of the decoded received value TSR1 and the external information or the interleaved data TEXT1 is selected. Specifically, if the received value format information CRTY indicates external information, the selector 215 ₂ selects the external information or the interleaved data TEXT1. The selector 215 ₂ supplies the selected data to the selector 215 _9.

The selector 215 ₃ receives the received value format information CR.
Based on TY, one of the decoded received value TSR2 and the external information or the interleaved data TEXT2 is selected. Specifically, the selector 215 _3, when the received value type information CRTY was shows the external information, select the external information or interleaved data TEXT2. The selector 215 ₃ supplies the selected data to the selector 215 ₁₀ .

The selector 215 ₄ receives the received value format information CR.
Based on TY, external information or interleaved data T
Of EXT0 and the prior probability information whose value is “0”,
Select one of them. Specifically, the selector 215
₄ selects prior probability information whose value is "0" when the received value format information CRTY indicates external information. The selector 215 ₄ supplies the selected data to the selector 215 ₁₂ .

The selector 215 ₅ receives the received value format information CR.
Based on TY, external information or interleaved data T
EXT1 and the prior probability information whose value is “0”,
Select one of them. Specifically, the selector 215
₅ selects prior probability information having a value of "0" when the received value format information CRTY indicates external information. The selector 215 ₅ supplies the selected data to the selector 215 ₁₃ .

The selector 215 ₆ receives the received value format information CR.
Based on TY, external information or interleaved data T
EXT2 and the prior probability information whose value is “0”
Select one of them. Specifically, the selector 215
₆ selects prior probability information whose value is "0" when the received value format information CRTY indicates external information. The selector 215 ₆ supplies the selected data to the selector 215 ₁₄ .

The selector 215 ₇ receives the received value format information CR.
Based on the TY, for example, information indicating that the first symbol of the output bits output from the element encoder in the encoding device 1 does not exist in the internal erasure position information IERS, and that the second symbol exists Either of the information indicating not to be performed is selected. Specifically, the selector 215 ₇ determines that the encoding device 1 has TTCM or SCTC
If the received value format information CRTY indicates that the encoding is not performed by M, the information indicating that the second symbol does not exist is selected. Selector 215
_7, to the selector 215 ₉ as a control signal for selecting the selected data. Note that the selection operation by the selector 215 ₇ is caused by an erasing operation in the case where the encoding device 1 performs encoding by TTCM or SCTCM. That is, the encoding device 1
Erase operation in the case which was used to encode by M and SCTCM, since becomes to clear both the symbol of the in-phase and quadrature components, the selector 215 _7,
Information indicating that the second symbol does not exist is selected.

The selector 215 ₈ outputs the internal erase position information I
Based on the ERS, _{one of the} data supplied from the selector 215 ₁ and the information having a value of “0” is selected. Specifically, when the internal erasure position information IERS indicates that the first symbol of the output bits output from the element encoder in the encoding device 1 does not exist, the selector 215 ₈ determines , The value is “0”
Is selected. The data selected by the selector 215 ₈ is stored in the selectors 215 ₉ , 215 ₁₀ , 21
5 _14, 215 ₁₅ bundled together with the data supplied from, 215 _16, is supplied to the reception data and the delay storage circuit 155 as the selected received value and a priori probability information RAP.

The selector 215 ₉ selects one of the data supplied from the selector 215 ₂ and the information having the value “0” based on the data supplied from the selector 215 ₇ . Specifically, the selector 215 ₉
If the data supplied from the selector 215 ₇ indicates that the second symbol of the output bits output from the element encoder in the encoding device 1 does not exist, the value is “0”. Is selected. The data selected by the selector 215 ₉ is transmitted to the selector 21
5 ₈ , 215 ₁₀ , 215 ₁₄ , 215 ₁₅ , and 215 ₁₆ are bundled together with the data supplied thereto, and receive data and a delay storage circuit 1 are stored as selected reception values and prior probability information RAP
55.

Selector 215_TenIs the internal erase position information I
Based on the ERS, the selector 215 _ThreeSupplied by
Data or information with a value of "0"
Select Specifically, the selector 215_TenIs
The left position information IERS is encoded by the encoding device 1
The third symbol among the output bits output from the
If it indicates that there is no data, the value is “0”
Is selected. Selector 215_TenSelected by
The selected data is supplied to the selector 215₈, 215₉, 215₁₄,
215_Fifteen, 215₁₆Bundled with data supplied from
Received data as the selected reception value and the prior probability information RAP.
Data and a delay storage circuit 155.

The selector 215 ₁₁ receives the internal erase position information I
Based on the ERS, the decoded received value TSR3 and the value "0"
One of the information is selected. Specifically, the selector 215 ₁₁ outputs the internal erase position information IERS.
Indicates that the fourth symbol of the output bits output from the elementary encoder in the encoding device 1 does not exist, the information having the value “0” is selected. The selector 215 ₁₁ stores the selected data in the selector 2
15 Supply to ₁₅ .

The selector 215 ₁₂ selects one of the data supplied from the selector 215 ₄ and the information whose value is “0” based on the prior probability information erasure information TEAP. Specifically, when the prior probability information erasure information TEAP indicates that puncturing has been performed, the selector 215 ₁₂ selects information having a value of “0”. The selector 215 ₁₂ supplies the selected data to the selectors 215 ₁₅ and 215 ₁₆ .

The selector 215 ₁₃ selects one of the data supplied from the selector 215 ₅ and the information having the value “0” based on the prior probability information erasure information TEAP. Specifically, when the prior probability information deletion information TEAP indicates that puncturing has been performed, the selector 215 ₁₃ selects information having a value of “0”. The selector 215 ₁₃ supplies the selected data to the selector 215 ₁₆ .

[0262] The selector 215 _14, based on the a priori probability information erasure information TEAP, among the data supplied from the selector 215 _6, the value is "0" information, selects either. Specifically, when the prior probability information deletion information TEAP indicates that puncturing has been performed, the selector 215 ₁₄ selects information having a value of “0”. The data selected by the selector 215 ₁₄ is the selector 215 ₈ , 215 ₉ , 215 ₁₀ , 215 ₁₅ ,
The data is bundled together with the data supplied from 215 ₁₆ and supplied to the received data and delay storage circuit 155 as the selected reception value and the prior probability information RAP.

The selector 215_FifteenIs the input bit number information I
N, the selector 215₁₁Data supplied by
And selector 215₁₂Out of the data supplied by
Select one of them. Specifically, the selector 215
_FifteenIs that the coding rate of the elementary encoder in the encoding device 1 is
"1 / n" and the number of input bits is "1".
The input bit number information IN indicates that
Has a selector 215 ₁₁Select data supplied from
You. Selector 215_FifteenThe data selected by
Kuta 215₈, 215₉, 215_Ten, 215₁₄, 215₁₆
Bundled with the data supplied from the
And received data and delay storage as prior probability information RAP
The signal is supplied to the circuit 155.

Selector 215₁₆Is the input bit number information I
N, the selector 215₁₂Data supplied by
And selector 215₁₃Out of the data supplied by
Select one of them. Specifically, the selector 215
₁₆Is that the coding rate of the elementary encoder in the encoding device 1 is
"1 / n" and the number of input bits is "1".
The input bit number information IN indicates that
Has a selector 215 ₁₂Select data supplied from
You. Selector 215₁₆The data selected by
Kuta 215₈, 215₉, 215_Ten, 215₁₄, 215_Fifteen
Bundled with the data supplied from the
And received data and delay storage as prior probability information RAP
The signal is supplied to the circuit 155.

The received value and prior probability information selecting circuit 154 includes selectors 215 ₁ , 215 ₂ , 215 ₃ , 2
15 _4, by 215 _5, 215 ₆ to select the decoded received value TSR and extrinsic information or interleaved data TEXT, it is possible to switch between these decoded received value TSR and extrinsic information or interleaved data TEXT as a code likelihood , Information to be input for performing soft output decoding can be appropriately selected. The received value and prior probability information selection circuit 154 includes a selector 215
₈ , 215 ₉ , 215 ₁₀ , 215 ₁₁ , 215 ₁₂ , 21
By performing the selection operation using 5 ₁₃ and 215 _14, a position where no code output exists can be replaced with a symbol whose likelihood is “0”.

The received data and delay storage circuit 155
Although not shown, for example, it includes a plurality of banks of RAM, a control circuit, and a selection circuit. The reception data and delay storage circuit 155 includes the termination time information TPM and termination state information TSM supplied from the termination information generation circuit 153, and the selected reception value and prior probability information supplied from the reception value and prior probability information selection circuit 154. RAP is stored.

Then, the reception data and delay storage circuit 1
55 is one of the stored termination time information TPM and termination state information TSM under the control of the internal control circuit.
The predetermined information is selected by the selection circuit, and the Iα calculation circuit 15
8 and output as termination information TB0 and TB1 used in the Iβ calculation circuit 159. The termination information TAL is, after a predetermined delay, applied to the termination information TAL.
D is supplied to the Iα calculation circuit 158. Further, the termination information TB0 and TB1 are supplied to the Iβ calculation circuit 159 as termination information TB0D and TB1D after a predetermined delay, respectively.

The storage circuit for received data and delay 15
5 is a circuit for selecting predetermined information from the stored selected reception value and the prior probability information RAP by the selection circuit under the control of the internal control circuit, and using the reception data DA and Iβ calculation circuit used in the Iα calculation circuit 158. The data is output as two systems of received data DB0 and DB1 used in 159. The reception data DA is supplied to the Iγ calculation circuit 156, and after a predetermined delay, is supplied to the reception value or prior probability information separation circuit 162 as delay reception data DAD. The received data DB0 and DB1 are supplied to the Iγ calculation circuit 156, respectively.

The element decoder 50 performs so-called sliding window processing which is known as a method of processing continuous data. The reception data and delay storage circuit 155 and the Iβ storage circuit described later for performing the sliding window processing are used. As the memory management method in 160, the method described in International Publication No. WO99 / 62183, which has been already applied for by the applicant of the present invention, is adopted. That is, the element decoder 50
Briefly, the reception data divided by a predetermined censoring length is read out from the reception data and delay storage circuit 155, and the log likelihood Iβ is finally stored by the Iβ storage circuit 160. Log soft output Iλ
Is performed in such a way as to be obtained in the original chronological order. However, the element decoder 50 uses the international publication number W
As described in O99 / 62183, instead of calculating the log likelihood Iγ and then performing memory management, the received data is stored in the received data and delay storage circuit 155, and then an appropriate memory is stored. The received data is read under the management, and the log likelihood Iγ is calculated.

Further, storage circuit 1 for received data and delay
55 can also store delay data, as described below. That is, the reception data and delay storage circuit 155 stores the reception value TR and the edge signal TEILS supplied from the edge detection circuit 80, and delays it by the same time as the processing time required by the soft output decoding circuit 90. The reception data and delay storage circuit 155 converts the delayed reception value PDR obtained by delaying the reception value TR into a delayed reception value SDR.
Are supplied to the selectors 120 ₃ and 120 ₆ . Further, the reception data and delay storage circuit 155 outputs the edge signal TE.
Delayed edge signal PDIL obtained by delaying ILS
To the selector 120 ₅ as the delayed edge signal SDILS.
To supply.

The Iγ calculating circuit 156 receives the received data and the received data DA and D supplied from the delay storage circuit 155.
The log likelihood Iγ is calculated using B0 and DB1. Specifically, based on the notation described at the beginning of “2.”, the Iγ calculation circuit 156 performs an operation represented by the following equation (48) for each received value y _t , and calculates the log likelihood at each time t. Calculate Iγ. Note that sgn shown in the following equation (48) is a constant indicating a sign for identifying positive or negative, that is, “+1” or “−1”.
Is one of This constant sgn is calculated by the element decoder 50
Is set to "+1" when the system is configured to handle only negative values as log likelihood, and "-" is configured when the element decoder 50 is configured to handle only positive values as log likelihood.
1 ”. That is, the Iγ calculation circuit 156 expresses the log likelihood Iγ or the probability γ in logarithmic notation for the probability γ determined by the output pattern of the code and the received value for each received value y _t , and signifies the sign. The log likelihood Iγ with the identification code inverted is calculated.

[0272]

[Equation 48]

[0273] In the following, discussion will be made on a case where the element decoder 50 is configured as a system that handles only negative values or positive values as log likelihood, if necessary. The case where sgn is “−1”, that is, the element decoder 50 is configured as a system that handles only positive values as log likelihoods, and the higher the probability, the smaller the value.

At this time, the Iγ calculation circuit 156 determines whether the received value format information CRTY and the prior probability information format information CAPP supplied from the control
If the coding is performed by M or SCTCM, the signal point arrangement information CSIG and the code information generation circuit 151
Log likelihood Iγ is calculated based on the input bit number information IN and the type information WM supplied from. Iγ calculation circuit 1
56 supplies the calculated log likelihood Iγ to the Iγ distribution circuit 157. That is, the Iγ calculation circuit 156 supplies the log likelihood Iγ used in the Iα calculation circuit 158 to the Iγ distribution circuit 157 as the log likelihood GA, and also uses the log likelihood Iγ used in the Iβ calculation circuit 159 as the log likelihood GB0. , G
It is supplied to the Iγ distribution circuit 157 as B1.

The Iγ calculating circuit 156 has two log likelihoods Iβ0 and Iβ1 as shown in FIG. 29, for example.
Of an i? Computation circuit 220 ₁ for Aibeta0 for calculating a log likelihood i? Used to calculate the log likelihood Aibeta0, i? Calculation Iβ1 for calculating a log likelihood i? Used to calculate the log likelihood Iβ1 The circuit 220 ₂ and the log likelihood Iα
It can be realized as having a Iα for Iγ computation circuit 220 ₃ for calculating a log likelihood Iγ used to calculate. Here, these Iβ0 Iγ calculation circuits 2
20 ₁ , the Iβ1 Iγ calculating circuit 220 ₂ and the Iα Iγ calculating circuit 220 ₃ can be realized by the same configuration except that the input data is different.
performed Description of γ calculating circuit 220 ₁ only, the description of Iβ1 for Iγ computation circuit 220 ₂ and Iα for Iγ computation circuit 220 ₃ is omitted together shown.

The Iγ calculation circuit 220 ₁ for Iβ0 calculates
It has a sign Iγ calculation circuit 221 and an Iγ normalization circuit 222.

As will be described later, the information / code Iγ calculation circuit 221 receives the reception data DB0 including the reception value and the prior probability information, and receives the reception value format information CRTY, the prior probability information format information CAPP, and the signal point arrangement information CSIG. And the likelihood Iγ for all possible input / output patterns or the log likelihood Iγ for at least some input / output patterns based on the input bit number information IN.

At this time, the information / code Iγ calculation circuit 221
If the encoding device 1 does not perform encoding by TTCM or SCTCM, the input received data DB0
, The sum of the prior probability information and the so-called channel value is calculated as the log likelihood Iγ.

The information / code Iγ calculation circuit 221
If the encoding device 1 performs encoding by TTCM or SCTCM, the log likelihood Iγ is calculated by calculating the inner product of the input received data DB0. This means that the Euclidean distance on the I / Q plane is the log likelihood Iγ, but in the case of the PSK modulation method, the Euclidean distance is obtained because the transmission amplitude of the output from the encoding device takes a constant value. This is because this is equivalent to obtaining the inner product.

The information / code Iγ calculation circuit 221 supplies the calculated log likelihood Iγ to the Iγ normalization circuit 222.

The Iγ normalization circuit 222 performs normalization for correcting the bias of the distribution of the calculation result by the information / code Iγ calculation circuit 221 as described later. In particular,
The Iγ normalization circuit 222 includes an information / code Iγ calculation circuit 22
1 so that the log likelihood corresponding to the logarithmic likelihood Iγ having the maximum value among the plurality of log likelihoods Iγ calculated according to 1 is matched with the log likelihood corresponding to the maximum possible probability. Is subjected to a predetermined operation. That is, when the element decoder 50 treats the log likelihood as a negative value, the Iγ normalization circuit 222 has the maximum value among the plurality of log likelihoods Iγ calculated by the information / code Iγ calculation circuit 221. Then, normalization is performed such that a predetermined value is added to each of the plurality of log likelihoods Iγ so as to match the maximum value that can be represented by the element decoder 50. When the element decoder 50 treats the log likelihood as a positive value, the Iγ normalization circuit 222 has the minimum value among the plurality of log likelihoods Iγ calculated by the information / code Iγ calculation circuit 221. Then, normalization is performed such that a predetermined value is subtracted from each of the plurality of log likelihoods Iγ so as to match the minimum value that can be represented by the element decoder 50. The Iγ normalization circuit 222 performs clipping of the normalized log likelihood Iγ according to a required dynamic range, and sets Iγ as log likelihood GB0.
The signal is supplied to the distribution circuit 157.

The Iγ calculation circuit for Iβ0 220 ₁
Is the log likelihood I used to calculate the log likelihood Iβ0
γ is calculated, and the logarithmic likelihood GB0 is used as the Iγ distribution circuit 157.
To supply.

The Iγ calculation circuit 220 ₂ for Iβ1
Instead of the received data DB0 input to the Iβ0 Iγ calculation circuit 220 ₁ , the received data DB1 is input and Iβ0
It performs the same processing as use Iγ computation circuit 220 _1. The Iγ calculation circuit 220 ₂ for Iβ1 calculates the log likelihood Iγ used to calculate the log likelihood Iβ1, and supplies it to the Iγ distribution circuit 157 as the log likelihood GB1.

[0284] Similarly, Iγ computation circuit 220 ₃ for Iα is,
Instead of the received data DB0 inputted to Aibeta0 for Iγ computation circuit 220 _1, and inputs the received data DA, performs the same processing as Iγ computation circuit 220 ₁ for Aibeta0. Iγ for Iα
The calculation circuit 220 ₃ calculates the log likelihood Iγ used for calculating the log likelihood Iα, and supplies the result to the Iγ distribution circuit 157 as the log likelihood GA.

The Iγ calculation circuit 156 generates log likelihood GA, GB0, GB1 calculated as log likelihood Iγ using the received data DA, DB0, DB1, and generates these log likelihood GA, GB0. , GB1 to Iγ distribution circuit 1
57.

As described later, the Iγ distribution circuit 157
Log likelihood GA, GB supplied from Iγ calculation circuit 156
0 and GB1 are respectively distributed according to the code configuration.
That is, the Iγ distribution circuit 157 determines the log likelihood GA, GB so as to correspond to the branch on the trellis according to the code configuration.
0, GB1 are distributed. At this time, the Iγ distribution circuit 157
Is generated matrix information CG supplied from the control circuit 60,
Based on the input bit number information IN, type information WM, memory number information MN, and branch input / output information BIO supplied from the code information generation circuit 151, log likelihood GA, GB0, GB1
Distribute.

The Iγ distribution circuit 157 also has a function of bundling these parallel paths when decoding a code having parallel paths on the trellis, as described later.

The Iγ distribution circuit 157 converts the log likelihood Iγ obtained by the distribution into the Iα calculation circuit 158 and the Iβ calculation circuit 1
59. That is, the Iγ distribution circuit 157
The log likelihood Iγ used in the α calculation circuit 158 is
The signal is supplied to the Iα calculation circuit 158 as GA,
The log likelihood Iγ used in the β calculation circuit 159 is
The signals are supplied to the Iβ calculation circuit 159 as GB0 and DGB1. The Iγ distribution circuit 157 supplies the log likelihood Iγ obtained in a state where the parallel paths are not bundled to the Iα calculation circuit 158 as log likelihood DGAB, as described later.

More specifically, the Iγ distribution circuit 157 includes, for example, as shown in FIG. 30, a branch input / output information calculation circuit 223 for calculating input / output information of a branch on a trellis according to a code configuration.
And an Iγ distribution circuit 224 ₁ for Iβ0 that distributes the log likelihood Iγ used to calculate the log likelihood Iβ0 of the two systems of log likelihood Iβ0 and Iβ1, and is used to calculate the log likelihood Iβ1 I for Iβ1 that distributes log likelihood Iγ
γ distribution circuit 224 ₂ and Iα Iγ distribution circuit 22 for distributing log likelihood Iγ used for calculating log likelihood Iα
4 ₃ and a parallel path processing circuit 22 for Iβ0 that processes the parallel path used for calculating the log likelihood Iβ0 in the case of a code having a parallel path on the trellis.
5 ₁ and a parallel path processing circuit 22 for Iβ1 which processes the parallel path used for calculating the log likelihood Iβ1 in the case of a code having a parallel path on the trellis.
5 _2, and in the case of a code having a parallel path on the trellis, an Iα parallel path processing circuit 225 ₃ for processing the parallel path used to calculate the log likelihood Iα.
And can be realized.

The branch input / output information calculation circuit 223 generates generation matrix information CG, input bit number information IN, type information WM,
The code configuration is identified based on the memory number information MN and the branch input / output information BIO, and the branch input / output information is calculated in the reverse order to the time axis of the branch on the trellis corresponding to the code configuration. The branch input / output information calculation circuit 223 transfers the calculated branch input / output information BI to the Iβ0 Iγ distribution circuit 224 ₁ and Iβ1.
Supply circuit 224 ₂ .

Iγ Distribution Circuit 224 for Iβ0₁Is the log likelihood
When the degree GB0 is input, based on the branch input / output information BI,
Distribution according to the code configuration is performed. Iγ distribution circuit 2 for Iβ0
24 ₁Calculates the log likelihood PGB0 obtained by distribution as Iβ0
Parallel path processing circuit 225₁To supply.

Iγ distribution circuit 224 for Iβ1_TwoIs the log likelihood
When the degree GB1 is input, based on the branch input / output information BI,
Distribution according to the code configuration is performed. Iγ distribution circuit 2 for Iβ1
24 _TwoCalculates the log likelihood PGB1 obtained by distribution as Iβ1
Parallel path processing circuit 225_TwoTo supply.

When the logarithmic likelihood GA is input, the Iγ Iγ distribution circuit 224 ₃ performs distribution according to the code configuration based on the branch input / output information BIO. Iα distribution circuit 224 for Iα
₃ supplies the log likelihood PGA obtained by distribution to the Iα parallel path processing circuit 225 ₃ . In addition, Iγ for Iα
The distribution circuit 224 ₃ calculates the log likelihood PGA obtained by the distribution.
Is supplied to the Iα calculation circuit 158 as the log likelihood DGAB.

Parallel path processing circuit 225 for Iβ0
_As described later, when the log likelihood PGB0 is inputted as described later, if the log likelihood PGB0 corresponds to the parallel path, the log likelihood PGB0 is bundled and the log likelihood DGB0, that is, It is output as log likelihood Iγ used to calculate likelihood Iβ0. The parallel path processing circuit 225 ₁ for Iβ0 receives the input log likelihood P
If GB0 does not correspond to the parallel path, the log likelihood PGB0 is directly output as log likelihood DGB0. At this time, the Iβ0 parallel path processing circuit 225 ₁ selects the log likelihood DGB0 to be output based on the input bit number information IN.

More specifically, as shown in FIG. 31, the parallel path processing circuit 225 ₁ for Iβ0 is a log-sum operation circuit for the parallel path of the maximum number of states of the code to be decoded. 226 _n and a selector 227 for performing a two-to-one selection. Here, the parallel path processing circuit 225 ₁ for Iβ0 is a code represented by a trellis having a maximum of 32 branches and having a maximum of 4 states among codes having a parallel path on the trellis, more specifically, Is to decode a code having a parallel path on the trellis such that eight paths reach each state for four states, and convert 32 branches into 16 log likelihoods Iγ. Log-sum operation circuits 226 ₁ , 226 ₂ , 226 ₃ ,.
..., it shall have a 226 _16.

Log-sum operation circuit 2 for parallel path
26 ₁ includes two differentiators 229 ₁ ,
229 ₂ and three selectors 230, 231, 233
And a selection control signal generation circuit 232 for generating a control signal for controlling the selection operation by these selectors 230, 231, 233, and a ROM (Re) for storing the value of a correction term in so-called log-sum correction as a table
ad lookup memory) and an adder 235. Among these units, the difference units 229 ₁ and 229 ₂ , the selectors 230 and 23
1 and the selection control signal generation circuit 232 constitute a comparison and absolute value calculation circuit 228.

The comparison and absolute value calculation circuit 228 compares the magnitudes of the two input data, and calculates the absolute value of the difference value between these two data.

The difference unit 229₁Are 32 log likelihoods I
Two log likelihoods of the log likelihood PGB0 which is a set of γ
Of log likelihood PG00 and PG01, which are degrees Iγ
Take the difference. Strictly speaking, the difference unit 229₁Is the log likelihood P
G00 and PG01 are each composed of, for example, 9 bits.
The lower 6 bits of the log likelihood PG00
Data with “1” added to the most significant bit and the log likelihood
In the most significant bit of the lower 6 bits of data of PG01
The difference from the one with “0” is calculated. Differentiator 229
₁Selects the calculated difference value DA1 with the selector 230
Supply signal to the control signal generation circuit 232.

The differentiator 229 ₂ calculates the difference between the log likelihood PG01 and the log likelihood PG00. Strictly speaking, the difference unit 22
9 ₂ is the log likelihood PG01 assuming that the log likelihoods PG00 and PG01 are each composed of, for example, 9 bits.
And the difference between the lower 6 bits of the log likelihood PG00 and the lower 6 bits of the data of the logarithmic likelihood PG00, with the uppermost bit of “0”. The differentiator 229 ₂ outputs the calculated difference value DA0 to the selector 23.
0 and the control signal generation circuit 232 for selection.

[0300] The selector 230, based on the control signal SL1 supplied from the selection control signal generating circuit 232, a difference value DA1 supplied from differentiator 229 _1, differentiator 2
29 ₂ of the difference value DA0 supplied from, select the one large value. The selector 230 supplies the selected data CA to the selector 231.

The selector 231 receives the data CA supplied from the selector 230 and a predetermined value M based on the control signal SL2 supplied from the selection control signal generation circuit 232.
One of the data having Specifically, since the value of the correction term for the difference value supplied as the data CA has a property asymptotic to a predetermined value, the selector 231 determines that the value of the data CA exceeds the predetermined value M. If so, data having a predetermined value M is selected. The selector 231 supplies the data DM obtained by the selection to the lookup table 234.

The selection control signal generation circuit 232 generates a control signal SL1 for controlling the selection operation by the selectors 230 and 233 based on the log likelihoods PG00 and PG01 and the difference values DA1 and DA0. Control signal SL for controlling the selection operation by selector 231
Generate 2. At this time, the selection control signal generation circuit 232
Generates control signals SL1 and SL2 indicating a decision sentence for selection by dividing upper bits and lower bits of a metric based on log likelihoods PG00 and PG01, which will be described later.

The comparison and absolute value calculation circuit 228
Calculates the absolute value of the difference between the log likelihoods PG00 and PG01. At this time, in the comparison and absolute value calculation circuit 228, as will be described later, if the log likelihoods PG00 and PG01 are each composed of, for example, 9 bits, the data supplied to the differentiator 229 ₁ is logarithmic likelihood. Degree PG00
Of the lower 6 bits of the log likelihood PG01 and "0" added to the upper bits of the lower 6 bits of the log likelihood PG01. Similarly,
In the comparison and absolute value calculation circuit 228, the difference unit 22
9 data supplied _2, the lower log likelihood PG00 6
The uppermost bit of the bit data is "0" and the uppermost bit of the lower 6 bits of the log likelihood PG01 is "1". That is, the logarithmic likelihoods PG00, PG01 are provided to the difference units 229 ₁ and 229 _2.
"1" or "0" in the most significant bit of the lower bits of
Is supplied, which is the log likelihood P
G00 and PG01 are to be compared at high speed.
Also, this is related to creating a judgment text for selection by dividing the upper bit and the lower bit of the metric by the selection control signal generation circuit 232. This will be described later.

The selector 233 selects one of the log likelihoods PB00 and PG01 having a smaller value based on the control signal SL1 supplied from the selection control signal generation circuit 232. The selector 233 controls the data S obtained by the selection.
The PG is supplied to the adder 235.

The look-up table 234 stores log-
The value of the correction term in the sum correction is stored as a table. The look-up table 234 reads the value of the correction term corresponding to the value of the data DM supplied from the selector 231 from the table, and adds the value as a data RDM to the adder 235.
To supply.

The adder 235 adds the data SPG supplied from the selector 233 and the data RDM supplied from the look-up table 234 to calculate a log likelihood Iγ. The adder 235 supplies the calculated log likelihood Iγ to the selector 227 as the log likelihood PPG00.

The log-sum for such a parallel path
The arithmetic circuit 226 ₁ bundles two log likelihoods PG00 and PG01 corresponding to the parallel path, and forms a log likelihood PPG00.
Is supplied to the selector 227.

Log-sum operation circuit 2 for parallel path
26 ₂ is a parallel path log-sum operation circuit 22
6 It has the same configuration as ₁
Log likelihood PP by bundling two log likelihoods PG02 and PG03
G01 is supplied to the selector 227.

The log-sum operation circuit 226 ₃ for the parallel path has the same configuration as the log-sum operation circuit 226 ₁ for the parallel path, and bundles two log likelihoods PG04 and PG05 corresponding to the parallel path. The log likelihood PPG02 is supplied to the selector 227.

Further, the log-sum operation circuit 226 ₁₆ for the parallel path has the same configuration as the log-sum operation circuit 226 ₁ for the parallel path, and bundles two log likelihoods PG030 and PG031 corresponding to the parallel path,
The log likelihood PPG 15 is supplied to the selector 227.

As described above, a plurality of parallel path log
Each of the −sum operation circuits 226 _n bundles two log likelihoods corresponding to a parallel path. The log likelihoods PPG00, PPG01, PPG02,... Obtained by bundling by the parallel-path log-sum operation circuits 226 _n.
.., PPG 15 is the selector 2 as log likelihood PPG.
27.

In the parallel path processing circuit 225 ₁ for Iβ0, the selector 227 corresponds to the lower metric of the log likelihood PGB0 supplied from the Iγ distribution circuit 224 ₁ for Iβ0 based on the input bit number information IN. And the log-sum operation circuit 22 for each parallel path
6n, one of the log likelihoods PPG supplied from _n . Specifically, the selector 227 selects the log likelihood PPG when the element encoder in the encoding device 1 performs encoding in which a parallel path exists on the trellis. That is, here, the input bit number information IN is used as a control signal for controlling the selection operation by the selector 227, but actually,
A control signal indicating whether or not the code has a parallel path on the trellis is input to the selector 227.

When the Iβ0 parallel path processing circuit 225 ₁ receives the log likelihood PGB0, if the log likelihood PGB0 corresponds to a parallel path, the parallel path processing circuit 225 ₁ is bundled by the selector 227. A log likelihood PPG is selected, and the log likelihood PPG and the log likelihood PG
Among the B0, the one corresponding to the higher-order metric is supplied to the Iβ calculation circuit 159 as the log likelihood DGB0. Also, the parallel path processing circuit 225 for Iβ0
₁ indicates that if the log likelihood PGB0 does not correspond to the parallel path, the log likelihood PGB0 is output as it is as the log likelihood DGB0.

The parallel path processing circuit 225 for Iβ1
₂ has a configuration similar to that of the Iβ0 parallel path processing circuit 225 _1, and a detailed description thereof will be omitted.
When GB1 is input, if the log likelihood PGB1 corresponds to a parallel path, the log likelihood PGB1
1 and log likelihood DGB1, that is, log likelihood Iβ
1 is supplied to the Iβ calculation circuit 159 as the log likelihood Iγ used to calculate 1. When the input log likelihood PGB1 does not correspond to the parallel path, the Iβ1 parallel path processing circuit 225 ₂ supplies the log likelihood PGB1 as the log likelihood DGB1 to the Iβ calculation circuit 159 as it is. I do.

The Iα parallel path processing circuit 225
₃ also has the same configuration as that of the Iβ0 parallel path processing circuit 225 _1, and a detailed description is omitted.
When the GA is input, if the log likelihood PGA corresponds to the parallel path, the log likelihood PGA is bundled and the log likelihood DGA, that is, the log likelihood used to calculate the log likelihood Iα Iα calculation circuit 158 as degree Iγ
To supply. Also, the Iα parallel path processing circuit 225
₃ , when the input log likelihood PGA does not correspond to the parallel path, the log likelihood PGA is supplied to the Iα calculation circuit 158 as it is as the log likelihood DGA.

The Iγ distribution circuit 157 distributes the log likelihoods GA, GB0, and GB1 according to the code configuration, and decodes a code having a parallel path on the trellis. These parallel paths are bundled and the obtained log likelihoods DGA and DGAB are supplied to the Iα calculation circuit 158, and the obtained log likelihood DGB is obtained.
0 and DGB1 are supplied to the Iβ calculation circuit 159.

[0317] The Iα calculation circuit 158
Using the log likelihood DGA and DGAB supplied from 7,
The log likelihood Iα is calculated. Specifically, the Iα calculation circuit 1
58 performs an operation represented by the following equation (49) using the log likelihood Iγ based on the notation described at the beginning of “2.”
The log likelihood Iα at each time t is calculated. The operator “#” in the following equation (49) is a so-called log-s
um operation, and the state m '
Log likelihood when transitioning from to state m,
It shows a log-sum operation with log likelihood at the time of transition from state m '' to state m with input "1". More specifically, the Iα calculation circuit 158
When the constant sgn is “+1”, by performing the operation shown in the following equation (50), the constant sgn becomes “−1”.
In this case, the logarithmic likelihood Iα at each time t is calculated by performing the calculation shown in the following equation (51). That is, the Iα calculation circuit 158 calculates, based on the log likelihood Iγ,
For each received value y _t , a logarithmic likelihood Iα in which the probability α from the encoding start state to each state in chronological order is logarithmically expressed or a logarithmic likelihood Iα in which the probability α is logarithmically expressed and the sign discrimination code is inverted is calculated. .

[0318]

[Equation 49]

[0319]

[Equation 50]

[0320]

(Equation 51)

At this time, the Iα calculation circuit 158 calculates the generation matrix information CG supplied from the control circuit 60, the input bit number information IN, the type information WM and the memory number information MN supplied from the code information generation circuit 151, The log likelihood Iα is calculated based on the received data and the termination information TALD supplied from the delay storage circuit 155. Iα calculation circuit 15
8 supplies the calculated sum of the log likelihood Iα and the log likelihood Iγ to the soft output calculation circuit 161. That is, as described later, the Iα calculation circuit 158 does not output the calculated log likelihood Iα as it is, but calculates the sum of the log likelihood Iα and the log likelihood Iγ used for calculating the log soft output Iλ as data A
Output as G.

Specifically, as shown in FIG. 33, for example, the Iα calculation circuit 158 includes a control signal generation circuit 240 for generating a control signal and two paths from each state on the trellis to the state at the next time. , An addition / comparison / selection circuit 241 for performing an add / compare select process and a process of adding a correction term by log-sum correction, and a state on the trellis to a state at the next time. And an addition / comparison / selection circuit 242 that performs addition / comparison / selection processing and processing for adding a correction term by log-sum correction to a code that reaches four paths or eight paths depending on the code. Degree I
It can be implemented as having an Iα + Iγ calculation circuit 243 that calculates the sum of α and the log likelihood Iγ, and a selector 244 that performs a three-to-one selection.

The control signal generation circuit 240 uses the generation matrix information CG, the input bit number information IN, the type information WM, and the memory number information MN to generate four paths from each state on the trellis to the state at the next time. The transition source state of the code that arrives is calculated and supplied to the addition / comparison / selection circuit 242 as the control signal PST.

The addition / comparison / selection circuit 241 adds a correction term by addition / comparison / selection processing and log-sum correction to a code such that two paths arrive from each state on the trellis to the state at the next time. The log-sum operation is performed by performing the following processing.

More specifically, the addition / comparison / selection circuit 241
As shown in FIG. 34, among codes in which two paths arrive from each state on the trellis to the state at the next time, log of the maximum value of the number of states of the code to be decoded is used. -Sum operation circuit 245 _n is provided. Here, the addition / comparison / selection circuit 241 has a maximum of 16
It is assumed that a code having a state is decoded, and 16 log-sum operation circuits 245 ₁ , 245 ₂ , 245 ₃ ,
.., 245 ₁₆ .

The log-sum operation circuit 24
5 _1, 245 _2, 245 _3, ..., the 245 _16, respectively, based on the transition of the trellis, a log likelihood Iγ of a branch corresponding to the output pattern in the trellis, one time before in each state Is supplied. That is, the log-sum operation circuits 245 ₁ , 245 ₂ , 245
_3,..., And the 245 _16, respectively, the log likelihood DGA
Among them, the one corresponding to the log likelihood Iγ of the branch corresponding to the output pattern on the trellis and the one corresponding to the log likelihood Iα in each state among the calculated log likelihoods one time before are supplied. Is done. The log-sum operation circuits 245 ₁ , 245 ₂ , 245 ₃ ,.
₁₆ finds the log likelihood Iα in each state at the next time as the log likelihood AL. Each log-sum operation circuit 245 _1, 245 _2, 245 _3, ..., 245 ₁₆
The distribution of the log likelihood AL differs depending on the code configuration, and is determined here by a selector or the like (not shown) based on the memory number information MN. The distribution of the log likelihood AL will be further described later.

More specifically, the log-sum operation circuit 24
5 ₁ has three adders 246 ₁ , 246 ₂ , 249 and l
It has a correction term calculation circuit 247 for calculating the value of the correction term in the og-sum correction, a selector 248, and an Iα normalization circuit 250.

The adder 246 ₁ inputs the log likelihood DGA00 of the log likelihood DGA and, among the log likelihood AL calculated one time before, applies the log likelihood AL corresponding to the sign to the log likelihood. A0 and these log likelihoods D
GA00 and A0 are added. The adder 246 ₁ converts the data AM0 indicating the sum of the log likelihood Iα and the log likelihood Iγ obtained by the addition into the correction term calculation circuit 247 and the selector 248.
To supply.

The adder 246 ₂ receives the log likelihood DGA01 of the log likelihood DGA and, among the log likelihood AL calculated one time before, applies the log likelihood AL corresponding to the sign to the log likelihood DGA01. A1 and their log likelihood D
GA01 and A1 are added. The adder 246 ₂ supplies the data AM1 indicating Iα + Iγ obtained by the addition to the correction term calculation circuit 247 and the selector 248.

The correction term calculation circuit 247 includes an adder 246 ₁
A data AM0 supplied from inputs the data AM1 supplied from the adder 246 ₂ calculates the data DM indicating the value of the correction term. As shown in FIG. 35, the correction term calculation circuit 247 includes two differentiators 251 ₁ and 251 ₂ ,
Two look-up tables 252 ₁ , 25 that store the value of the correction term in the log-sum correction as a table
2 ₂ , a selection control signal generation circuit 253 for generating a control signal for controlling a selection operation by the three selectors 248, 254, 255, and two selectors 254, 25
And 5.

The differentiator 251 ₁ calculates the difference between the data AM 0 supplied from the adder 246 ₁ and the data AM ₁ supplied from the adder 246 ₂ . Strictly speaking, the differentiator 251
₁ indicates that the data AM0 and AM1 are, for example, 12
Assuming that the data consists of bits, the most significant bit of the lower 6 bits of the data AM0 is "1",
The difference from the data with the most significant bit of the lower 6 bits of data AM1 appended with “0” is obtained. Differentiator 251
₁ is a look-up table 2
52 ₁ and the control signal generation circuit 253 for selection.

[0332] The differentiator 251 _2, a data AM1, taking the difference between the data AM0. Strictly speaking, the differentiator 251
₂ indicates that the data AM0 and AM1 are, for example, 12
Assuming that the data consists of bits, the most significant bit of the lower 6 bits of the data AM1 is given "1";
The difference from the data with lowermost 6 bits of data AM0 with “0” added to the most significant bit is obtained. Differentiator 251
₂ is a table that stores the calculated difference value DA0 in a lookup table 2
52 ₂ and supplied to the selection control signal generating circuit 253.

Look-up tables 252 ₁ , 252
₂ stores the value of the correction term in the log-sum correction as a table. Lookup table 2
52 ₁ reads the value of the correction term corresponding to the value of the difference value DA ₁ supplied from the differentiator 2511 from the table, and supplies it to the selector 254 as data RDA 1. The look-up table 252 ₂ reads the value of the correction term corresponding to the value of the difference value DA0 supplied from the differentiator 251 ₂ from the table, and selects the value of the correction term as data RDA0 from the selector 254.
To supply.

The selection control signal generation circuit 253 generates a control signal SEL for controlling the selection operation by the selectors 248 and 254 based on the data AM0 and AM1 and the difference values DA1 and DA0, and
55 generates a control signal SL for controlling the selection operation. At this time, the control signal generation circuit for selection 253 divides the upper bit and the lower bit of the metric based on the data AM0 and AM1 and performs the determination for selection in the same manner as the above-described control signal generation circuit 232 for selection. Control signals SEL and SL indicating a sentence are generated, which will be described later.

[0335] The selector 254, based on the control signal SEL supplied from the selection control signal generating circuit 253, the data supplied from the look-up table 252 ₁ RD
One of A1 and data RDA0 supplied from the lookup table 252 ₂ is selected. Specifically, the selector 254, when the value of the data AM0 is larger than the value of the data AM1 selects data RDA1 from the look-up table 252 _1. That is, the selector 254 selects the value of the correction term corresponding to the absolute value of the difference between the data AM0 and the data AM1. The selector 254 supplies the selected data CA to the selector 255.

The selector 255 converts one of the data CA supplied from the selector 254 and the data having a predetermined value M based on the control signal SL supplied from the selection control signal generation circuit 253. select. More specifically, since the value of the correction term for the difference value supplied as data CA has the property of asymptotically approaching a predetermined value, selector 255 determines that the value of data CA is a predetermined value M
Is exceeded, data having a predetermined value M is selected. The selector 255 supplies the data DM obtained by the selection to the adder 249.

The correction term calculation circuit 247 calculates the lo
The value of the correction term in the g-sum correction is calculated. At this time, the correction term calculation circuit 247 calculates the values of a plurality of correction terms, instead of calculating the absolute value of the difference value between the two input data, as described later. ,
Choose the appropriate one from them. In the correction term calculation circuit 247, the data supplied to the differentiator 251 ₁ is such that the data AM0 supplied from the adder 246 ₁ and the data AM1 supplied from the adder 246 ₂ are, for example, from 12 bits. Data A
The uppermost bit of the lower 6 bits of data of M0 is "1", and the uppermost bit of the lower 6 bits of data AM1 is "0". Similarly,
In correction term calculation circuit 247, the data to that denoted by "0" to the most significant bit of the lower 6 bits of the data of the data AM0 supplied to the differentiator 251 _2, data AM
This is obtained by adding “1” to the most significant bit of the lower 6 bits of 1 data. That is, the differentiators 251 ₁ and 252 ₂
Of the data supplied from the adders 246 ₁ and 246 _{2 are} supplied with data in which the most significant bit of the lower bit is set to “1” or “0”.
0, AM1 in order to perform the magnitude comparison at high speed.
This is related to the division of the upper bit and the lower bit of the metric by the selection control signal generation circuit 253 to create a judgment text for selection. This will be described later.

The selector 248 selects one of the data AM0 and AM1 having a smaller value based on the control signal SEL supplied from the selection control signal generation circuit 253. The selector 248 selects the data SAM obtained by the selection.
Is supplied to the adder 249.

The adder 249 adds the data SAM supplied from the selector 248 and the data DM supplied from the correction term calculation circuit 247 to calculate the log likelihood Iα. The adder 247 supplies the calculated log likelihood Iα to the Iα normalization circuit 250 as log likelihood CM.

The Iα normalization circuit 250 determines whether the adder 249
To correct the bias of the distribution of log likelihood CM supplied from
Is normalized. There are various methods for this normalization process.
This is considered, but will be described later. In addition, Iα positive
The normalization circuit 250 uses the termination information TALD to perform the termination processing.
Also do the work. The Iα normalization circuit 250 calculates the log likelihood after normalization.
Degree Iα according to the required dynamic range
And logarithmic likelihood AL00 as a predetermined log-
sum operation circuit 245₁, 245_Two, 245_Three, ...,
245₁₆To supply. At this time, the log likelihood AL00 is
Delayed by one time by a register not shown
Thereafter, a predetermined log-sum operation circuit 245 ₁, 245_Two,
245_Three, ..., 245₁₆Supplied to

The log-sum operation circuit 245 as described above
₁ obtains and outputs the log likelihood AL00, and combines the data AM0 and AM1 and outputs the data as data AG00. That is, the log-sum operation circuit 245 ₁
The calculated log likelihood AL00 is calculated as log likelihood I at the next time.
In order to use α for calculation of α, it is supplied to predetermined log-sum operation circuits 245 ₁ , 245 ₂ , 245 ₃ ,..., 245 ₁₆ and the log likelihood Iα calculated in the process of calculating log likelihood Iα Data AG00 indicating the sum Iα + Iγ of the log likelihood Iγ is output.

The log-sum operation circuit 245 ₂ outputs
Since the configuration is the same as that of the g-sum operation circuit 245 ₁ , the detailed description is omitted, but the log likelihoods DGA02 and DGA03 of the log likelihood DGA and the log likelihood AL calculated one time earlier are shown. Of these, those corresponding to the codes are input as log likelihoods A0 and A1, and these log likelihoods D0 and A1 are input.
A log likelihood Iα is calculated using GA02, DGA03, A0, and A1, and a predetermined log likelihood AL01 is calculated as a predetermined log likelihood AL01.
−sum operation circuits 245 ₁ , 245 ₂ , 245 ₃ ,.
· Supplies to 245 _16, and outputs the data AG01 indicating the sum I.alpha + i? A log likelihood I.alpha and log likelihood i?.

The log-sum operation circuit 245
_ThreeIs also a log-sum operation circuit 245₁From the same configuration as
Therefore, the detailed description is omitted, but the log likelihood DGA
Log likelihood DGA04 and DGA05, and one hour before
Of the calculated log likelihood AL, corresponding to the sign
Are input as log likelihoods A0 and A1 and their logarithms
Using likelihoods DGA04, DGA05, A0, A1,
The number likelihood Iα is calculated, and a predetermined log likelihood AL02 is calculated.
log-sum operation circuit 245₁, 245_Two, 245 _Three,
..., 245₁₆And the log likelihood Iα and
Data AG02 indicating the sum Iα + Iγ of the log likelihood Iγ
Output.

The log-sum operation circuit 245₁₆
Is also a log-sum operation circuit 245 ₁From the same configuration as
Therefore, the detailed description is omitted, but the log likelihood DGA
The log likelihood DGA30 and DGA31 and one time before
Of the calculated log likelihood AL, corresponding to the sign
Are input as log likelihoods A0 and A1 and their logarithms
Using likelihood DGA30, DGA31, A0, A1,
The number likelihood Iα is calculated, and a predetermined log likelihood AL15 is calculated.
log-sum operation circuit 245₁, 245_Two, 245_Three,
..., 245₁₆And the log likelihood Iα and
Data AG15 indicating the sum Iα + Iγ with the log likelihood Iγ is
Output.

The addition / comparison / selection circuit 241 performs log likelihood Iα in a code such that two paths arrive from each state on the trellis to the state at the next time.
Is calculated. The addition / comparison / selection circuit 241 does not output the calculated log likelihood Iα but outputs a sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ, as described later.
That is, the addition / comparison / selection circuit 241 performs log-sum
Arithmetic circuits 245 ₁ , 245 ₂ , 245 ₃ ,..., 245
Data AG00, AG0 obtained by each of ₁₆
1, AG02,..., AG15, and data AGT
To the selector 244.

The addition / comparison / selection circuit 242 performs addition / comparison / selection processing and log processing for a code such that four paths or, depending on the code, eight paths arrive from each state on the trellis to the state at the next time. By performing a process of adding a correction term by −sum correction, log−
Perform a sum operation.

More specifically, the addition / comparison / selection circuit 242
As shown in FIG. 36, there are four lines from each state on the trellis to the state at the next time, or eight depending on the code.
Log-su of the maximum value of the number of states of the code to be decoded among the codes that can reach this path
It has an m operation circuit 256 _n . Here, it is assumed that the addition / comparison / selection circuit 242 decodes a code having a maximum of eight states, and the eight log-sum operation circuits 25
6 _1, ..., it shall have a 256 _8.

These log-sum operation circuits 25
6₁, ..., 256₈, Respectively,
Log-sum operation circuit 24 in comparison selection circuit 241
5₁, 245_Two, 245_Three, ..., 245₁₆alike,
Output putter on trellis based on transition on trellis
Likelihood Iγ of the branch corresponding to the
The log likelihood Iα one time before is supplied. That is, lo
g-sum operation circuit 256 ₁, ..., 256₈In the
The output pattern on the trellis of the log likelihood DGA is
The log likelihood Iγ of the branch corresponding to the
Of the log likelihood AL one hour before issued,
Of the log likelihood Iα is supplied. Soshi
And the log-sum operation circuit 256₁, ..., 256₈
Are the log likelihood I in each state at the next time, respectively.
α is obtained as a log likelihood AL. Each log-sum operation
Circuit 256₁, ..., 256₈Log likelihood AL for
The distribution depends on the code configuration, where the control signal P
It is determined by a selector or the like (not shown) based on ST.
You. The distribution of the log likelihood AL will be further described later.
You.

Specifically, the log-sum operation circuit 25
6 ₁ is composed of five adders 257 ₁ , 257 ₂ , 257 ₃ and 25
7 ₄ , 271, and six correction term calculation circuits 258 ₁ , 258 ₂ , which calculate the value of the correction term in the log-sum correction
258 ₃ , 258 ₄ , 258 ₅ , 258 ₆ and 11 selectors 259, 260, 261, 262, 263, 26
4, 265, 266, 267, 268, 269, a selection control signal generation circuit 270 for generating a control signal for controlling the selection operation by the selector 269, and an Iα normalization circuit 272.

The adder 257 ₁ receives the log likelihood DGA00 of the log likelihood DGA and, among the log likelihood AL calculated one time before, applies the log likelihood AL corresponding to the sign to the log likelihood. A0 and their log likelihood D
GA00 and A0 are added. The adder 257 ₁ converts the data AM0 indicating the sum of the log likelihood Iα and the log likelihood Iγ obtained by the addition into the correction term calculation circuits 258 ₁ , 258 ₃ , 258
₅ and the selector 259.

The adder 257 ₂ receives the log likelihood DGA01 of the log likelihood DGA and, among the log likelihood AL calculated one time ago, applies the log likelihood AL corresponding to the sign to the log likelihood DGA01. A1 and their log likelihood D
GA01 and A1 are added. The adder 257 ₂ supplies the data AM1 indicating Iα + Iγ obtained by the addition to the correction term calculation circuits 258 ₁ , 258 ₄ , 258 ₆ and the selector 259.

The adder 257 ₃ receives the log likelihood DGA02 of the log likelihood DGA and, among the log likelihood AL calculated one time before, applies the log likelihood AL corresponding to the sign to the log likelihood. A2 and their log likelihood D
GA02 and A2 are added. The adder 257 ₃ supplies the data AM2 indicating Iα + Iγ obtained by the addition to the correction term calculation circuits 258 ₂ , 258 ₃ , 258 ₄ and the selector 260.

The adder 257 ₄ inputs the log likelihood DGA03 of the log likelihood DGA and, among the log likelihood AL calculated one time before, applies the corresponding log likelihood AL according to the sign. A3 and their log likelihood D
GA03 and A3 are added. The adder 257 ₄ supplies the data AM3 indicating Iα + Iγ obtained by the addition to the correction term calculation circuits 258 ₂ , 258 ₅ , 258 ₆ and the selector 260.

Since the correction term calculation circuit 258 ₁ has the same configuration as the correction term calculation circuit 247 shown in FIG. 35, its details are omitted here, but the data AM0 supplied from the adder 257 ₁ , Data AM1 supplied from the adder 257 _2, and data D indicating the value of the correction term.
Calculate M0. At this time, the correction term calculation circuit 258 ₁
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Also, in the correction term calculation circuit 258 ₁ , the data AM0 and AM1 supplied from the adders 257 ₁ and 257 ₂ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the magnitudes of the data AM0 and AM1 are compared at high speed. The correction term calculation circuit 258 ₁ outputs the calculated data DM0 to the selector 2
68. Further, the correction term calculation circuit 258 ₁ generates a control signal SEL0 for controlling the selection operation by the selectors 259, 261, 262, 263, 264.

Since the correction term calculation circuit 258 ₂ has the same configuration as the correction term calculation circuit 247 shown in FIG. 35, the details are omitted here, but the data AM2 supplied from the adder 257 ₃ , Data AM3 supplied from the adder 257 _4, and data D indicating the value of the correction term.
Calculate M1. At this time, the correction term calculation circuit 258 ₂
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, in the correction term calculation circuit 258 ₂ , the data AM 2 and AM 3 supplied from the adders 257 ₃ and 257 ₄ are replaced with data in which the most significant bit of the lower bit is “1” or “0”. By taking the difference, the data AM2 and AM3 are compared at high speed. The correction term calculation circuit 258 ₂ outputs the calculated data DM1 to the selector 2
68. Further, the correction term calculation circuit 258 ₂ generates a control signal SEL1 for controlling the selection operation by the selectors 260, 265, 266.

[0356] The correction term calculation circuit 258 _3, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM0 supplied from the adder 257 ₁ , Data AM2 supplied from the adder 257 _3, and data D indicating the value of the correction term.
Calculate M2. At this time, the correction term calculation circuit 258 ₃
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Also, in the correction term calculation circuit 258 ₃ , the data AM0 and AM2 supplied from the adders 257 ₁ and 257 ₃ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the magnitudes of the data AM0 and AM2 are compared at high speed. The correction term calculation circuit 258 ₃ outputs the calculated data DM2 to the selector 2
63. Further, the correction term calculation circuit 258 ₃ generates a control signal SEL2, which finally becomes a control signal SEL8 for controlling the selection operation by the selectors 267 and 268, and outputs the control signal SEL2 to the selector 261 and the selection control signal generation. The signal is supplied to the circuit 270.

Since the correction term calculation circuit 258 ₄ has the same configuration as the correction term calculation circuit 247 shown in FIG. 35, its details are omitted here, but the data AM1 supplied from the adder 257 ₂ , Data AM2 supplied from the adder 257 _3, and data D indicating the value of the correction term.
Calculate M3. At this time, the correction term calculation circuit 258 ₄
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, in the correction term calculation circuit 258 ₄ , the data AM 1 and AM ₂ supplied from the adders 257 ₂ and 257 ₃ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the data AM1 and AM2 are compared with each other at high speed. The correction term calculation circuit 258 ₄ outputs the calculated data DM3 to the selector 2
63. Further, the correction term calculation circuit 258 ₄ generates a control signal SEL3 which finally becomes a control signal SEL8 for controlling the selection operation by the selectors 267 and 268, and outputs the control signal SEL3 to the selector 261 and the selection control signal generation. The signal is supplied to the circuit 270.

[0358] The correction term computation circuit 258 _5, for the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM0 supplied from the adder 257 ₁ , Data AM3 supplied from the adder 257 _4, and data D indicating the value of the correction term.
Calculate M4. At this time, the correction term calculation circuit 258 ₅
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Also, in the correction term calculation circuit 258 ₅ , the data AM0 and AM3 supplied from the adders 257 ₁ and 257 ₄ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the magnitudes of the data AM0 and AM3 are compared at high speed. The correction term calculation circuit 258 ₅ outputs the calculated data DM4 to the selector 2
64. Further, the correction term calculation circuit 258 ₅ generates a control signal SEL4, which finally becomes a control signal SEL8 for controlling the selection operation by the selectors 267 and 268, and outputs the control signal SEL4 to the selector 262 and the control signal for selection. The signal is supplied to the circuit 270.

[0359] The correction term calculation circuit 258 _6, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM1 supplied from the adder 257 ₂ , Data AM3 supplied from the adder 257 _4, and data D indicating the value of the correction term.
Calculate M5. At this time, the correction term calculation circuit 258 ₆
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, the correction term computation circuit 258 _6, adder 257 _2, 257 ₄ between the most significant bit of the lower bits of the data AM1, AM3 supplied "1" or "0" is assigned data from By taking the difference, the magnitudes of the data AM1 and AM3 are compared at high speed. The correction term calculation circuit 258 ₆ outputs the calculated data DM5 to the selector 2
64. Further, the correction term calculation circuit 258 ₆ generates a control signal SEL5 serving as a control signal SEL8 for finally controlling the selection operation by the selectors 267 and 268, and outputs the control signal SEL5 to the selector 262 and the control signal for selection. The signal is supplied to the circuit 270.

The selector 259 includes a correction term calculation circuit 258
Based on the control signal SEL0 supplied from ₁ , data AM0 and AM1 are selected with a smaller value. The selector 259 supplies the selected data SAM0 to the selector 267.

The selector 260 has a correction term calculation circuit 258
Based on the control signal SEL1 supplied from ₂ , data AM2 and AM3 are selected with a smaller value. The selector 260 supplies the selected data SAM1 to the selector 267.

The selector 261 includes a correction term calculation circuit 258
_{One of} the control signals SEL2 and SEL3 is selected based on the control signal SEL0 supplied from ₁ . Specifically, when the data AM0 has a larger value than the data AM1, the selector 261 outputs the control signal S
Select EL3. The selector 261 supplies the selected control signal SEL6 to the selector 265.

The selector 262 includes a correction term calculation circuit 258
_{One of} the control signals SEL4 and SEL5 is selected based on the control signal SEL0 supplied from ₁ . Specifically, when data AM0 has a larger value than data AM1, selector 262 outputs control signal S0.
Select EL5. The selector 262 supplies the selected control signal SEL7 to the selector 265.

The selector 263 includes a correction term calculation circuit 258
Based on the control signal SEL0 supplied from _{1, one of} the data DM2 and DM3 is selected. Specifically, the selector 263 selects the data DM3 when the data AM0 has a larger value than the data AM1. The selector 263 selects the data DS obtained by the selection.
0 is supplied to the selector 266.

The selector 264 has a correction term calculation circuit 258
_{One of} the data DM4 and DM5 is selected based on the control signal SEL0 supplied from ₁ . Specifically, the selector 264 selects the data DM5 when the data AM0 has a larger value than the data AM1. The selector 264 selects the data DS obtained by the selection.
1 is supplied to the selector 266.

The selector 265 includes a correction term calculation circuit 258
Based on the control signal SEL1 supplied from ₂ , any one of the control signals SEL6 and SEL7 is selected. Specifically, when data AM2 has a larger value than data AM3, selector 265 controls signal S2.
Select EL7. The selector 265 supplies the control signal SEL8 obtained by selection as a control signal for selection in the selectors 267 and 268.

The selector 266 has a correction term calculation circuit 258
Based on the control signal SEL1 supplied from ₂ , any one of the data DS0 and DS1 is selected. Specifically, the selector 266 selects the data DS1 when the data AM2 has a larger value than the data AM3. The selector 266 selects the data DS obtained by the selection.
2 is supplied to the selector 269.

The selector 267 selects one of the data SAM0 and SAM1 based on the control signal SEL8. Specifically, when the control signal SEL8 is the control signal SEL7, the selector 267 selects the data SAM1. The selector 267 supplies the selected data SAM2 to the adder 271.

The selector 268 selects one of the data DM0 and DM1 based on the control signal SEL8. Specifically, the selector 268 outputs the control signal S
When EL8 is the control signal SEL7, the data D
Select M1. The selector 268 supplies the selected data DS3 to the selector 269.

The selector 269 operates based on the control signal SEL9 supplied from the selection control signal generation circuit 270.
One of the data DS2 and DS3 is selected. The selector 269 selects the data RDM obtained by the selection.
Is supplied to the adder 271.

The selection control signal generation circuit 270 generates a control signal SEL9 for controlling the selection operation by the selector 269 based on the control signals SEL2, SEL3, SEL4, and SEL5. Specifically, the selection control signal generation circuit 270 outputs the control signals SEL2, SEL3, S
The logical product of EL4 and SEL5 and the control signals SEL2 and SE
The control signal SEL9 is generated by taking the logical sum of the logical product of L3, SEL4, and SEL5 with the negation.

The adder 271 adds the data SAM2 supplied from the selector 267 and the data RDM supplied from the selector 269 to calculate the log likelihood Iα.
The adder 271 converts the calculated log likelihood Iα into the log likelihood CM
Is supplied to the Iα normalization circuit 272.

The Iα normalization circuit 272 performs the normalization for correcting the bias of the distribution of the log likelihood CM supplied from the adder 271 similarly to the Iα normalization circuit 250 described above. Also, the Iα normalization circuit 272 outputs the termination information TALD.
The termination process is also performed using. The Iα normalization circuit 272 is
Clipping is performed on the normalized log likelihood Iα according to a required dynamic range, and a predetermined log-sum operation circuit 256 ₁ ,.
To 256 ₈ . At this time, the log likelihood AL00 is
After a delay of one time by a register (not shown), a predetermined log-sum operation circuit 256 ₁ ,.
256 ₈ .

The log-sum operation circuit 256 as described above
₁ calculates and outputs the log likelihood AL00, and bundles the data AM0, AM1, AM2 and AM3 to generate the data A
Output as G00. That is, the log-sum operation circuit 256 ₁ uses the obtained log likelihood AL00 for calculating the log likelihood Iα at the next time.
g-sum operation circuit 256 _1, ..., and supplies to 256 _8, and outputs the data AG00 indicating the sum I.alpha + i? a log likelihood I.alpha and log likelihood i? determined in the process of calculating the log likelihood I.alpha.

At this time, the log-sum operation circuit 256 ₁
Is selected from data AM0, AM1, AM2, and AM3 indicating likelihoods corresponding to four paths that have reached each state, or four sets of paths obtained by bundling eight paths depending on codes. By comparing the magnitude of likelihood for all combinations of data corresponding to two paths,
Among these data AM0, AM1, AM2 and AM3, data corresponding to at least two or more paths having high likelihood is obtained, and from the data corresponding to these paths,
The data corresponding to the highest likelihood path which is the path with the highest likelihood is selected. More specifically, the log-sum operation circuit 2
56 _1, the data AM0, AM1, AM2, AM3, so to speak by performing an operation to be likened to the tournament, compared value of the data AM0, the value of the data AM1, the magnitude of the value of the value and data AM3 data AM2 , The data corresponding to the maximum likelihood path is selected.

Also, the log-sum operation circuit 256
₈ has the same configuration as the log-sum operation circuit 256 _1, and a detailed description thereof will be omitted, but the log likelihood DGA 28, DGA 29, DGA 30, and DGA 30 of the log likelihood DGA will be omitted.
Among the DGA 31 and the log likelihood AL calculated one time before, the one corresponding to the code is represented by the log likelihood A0, A1,
A2, A3 and their log likelihood DGA2
8, DGA29, DGA30, DGA31, A0, A
, A2, and A3 to calculate the log likelihood Iα, and as a log likelihood AL07, a predetermined log-sum operation circuit 2
56 _1, ..., and supplies to 256 _8, the data AG indicating the sum I.alpha + i? A log likelihood I.alpha and log likelihood i?
07 is output.

The addition / comparison / selection circuit 242 calculates the log likelihood Iα of a code such that four paths, or eight paths depending on the code, arrive from each state on the trellis to the state at the next time. I do. The addition / comparison / selection circuit 242 does not output the calculated log likelihood Iα, but outputs the sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ, similarly to the addition / comparison / selection circuit 241 described above.
That is, the addition / comparison / selection circuit 242 performs log-sum
, 25607 obtained by the arithmetic circuits 256 ₁ ,..., 256 ₈ are bundled and supplied to the selector 244 as data AGF. The addition / comparison / selection circuit 242 includes a log-sum operation circuit 25
6 _1, bundled ..., log likelihood AL00 determined by the respective 256 _8, ..., and AL07, log likelihood AL
Is supplied to the Iα + Iγ calculation circuit 243. Note that the addition / comparison / selection circuit 242 is originally provided to obtain the log likelihood Iα in a code such that four paths arrive from each state on the trellis to the state at the next time. As described above, the log likelihood I in a code such that eight paths arrive depending on the code.
α can be obtained. About this, "5-5
3 "and" 5-5-5 ".

The Iα + Iγ calculation circuit 243 is provided for decoding a code having a parallel path on the trellis, such as a code by the convolutional encoder shown in FIG. 17, as described later. Yes, the sum of the log likelihood Iα and the log likelihood Iγ is calculated. Specifically, I
As shown in FIG. 37, the α + Iγ calculation circuit 243 includes three selectors 273, 274, and 275, and here, four Iα + Iγ calculation cell circuits 276 ₁ , 276 ₂ , 276 ₃ ,
276 ₄ .

The selector 273 is based on the memory number information MN.
The log likelihood supplied from the addition / comparison / selection circuit 242
A predetermined log likelihood A corresponding to the sign of the degree AL
One of L00 and AL01 is selected. C
Lector 273 is a log likelihood AL01S obtained by selection.
To the Iα + Iγ calculation cell circuit 276₁, 276_Two, 27
6 _Three, 276_FourTo supply.

The selector 274 is based on the memory number information MN.
The log likelihood supplied from the addition / comparison / selection circuit 242
A predetermined log likelihood A corresponding to the sign of the degree AL
One of L01 and AL02 is selected. C
Lector 274 is a log likelihood AL02S obtained by selection.
To the Iα + Iγ calculation cell circuit 276₁, 276_Two, 27
6 _Three, 276_FourTo supply.

The selector 275 is based on the memory number information MN.
The log likelihood supplied from the addition / comparison / selection circuit 242
A predetermined log likelihood A corresponding to the sign of the degree AL
One of L01 and AL03 is selected. C
Lector 275 is a log likelihood AL03S obtained by selection.
To the Iα + Iγ calculation cell circuit 276₁, 276_Two, 27
6 _Three, 276_FourTo supply.

The Iα + Iγ calculation cell circuit 276 ₁ has eight adders 277 ₁ , 277 ₂ , 277 ₃ , 277 ₄ and 277
₅ , 277 ₆ , 277 ₇ , and 277 ₈ .

The adder 277 ₁ includes a predetermined log likelihood DGAB00 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157, and a log likelihood supplied from the addition / comparison / selection circuit 242. Among the ALs, a predetermined log likelihood AL00 corresponding to the sign is added. The adder 277 ₁ converts the data obtained by the addition into the data AM
Output as 0.

The adder 277 ₂ is provided with a predetermined log likelihood DGAB01 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157, and a log likelihood supplied from the addition / comparison / selection circuit 242. Among the ALs, a predetermined log likelihood AL00 corresponding to the sign is added. The adder 277 ₂ outputs the data obtained by the addition to the data AM
Output as 1.

The adder 277 ₃ is provided with a predetermined log likelihood DGAB 02 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157 and a selector 273.
Is added to the log likelihood AL01S supplied from. The adder 277 ₃ outputs the data obtained by the addition to the data AM2.
Output as

The adder 277 ₄ is provided with a predetermined log likelihood DGAB 03 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157 and a selector 273.
Is added to the log likelihood AL01S supplied from. The adder 277 ₄ outputs the data obtained by the addition to the data AM3
Output as

The adder 277 ₅ includes, of the log likelihood DGAB supplied from the Iγ distribution circuit 157, a predetermined log likelihood DGAB04 corresponding to a code and a selector 274.
Is added to the log likelihood AL02S supplied from. The adder 277 ₅ converts the data obtained by the addition into the data AM4
Output as

The adder 277 ₆ is provided with a predetermined log likelihood DGAB 05 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157 and a selector 274.
Is added to the log likelihood AL02S supplied from. The adder 277 ₆ converts the data obtained by the addition into the data AM5
Output as

The adder 277 ₇ is provided with a predetermined log likelihood DGAB 06 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157 and a selector 275.
Is added to the log likelihood AL03S supplied from. The adder 277 ₇ outputs the data obtained by the addition to the data AM6.
Output as

The adder 277 ₈ is provided with a predetermined log likelihood DGAB 07 corresponding to the sign of the log likelihood DGAB supplied from the Iγ distribution circuit 157 and a selector 275.
Is added to the log likelihood AL03S supplied from. The adder 277 ₈ outputs the data obtained by the addition to the data AM7
Output as

[0391] Such an Iα + Iγ calculation cell circuit 276
₁ is a log likelihood DGAB indicating a log likelihood Iγ obtained by the Iγ distribution circuit 157 in a state where the parallel paths are not bundled.
Is added to the log likelihood AL calculated by the addition / comparison / selection circuit 242 to obtain the log likelihood Iα used for obtaining the log soft output Iλ when the parallel paths are bundled.
And the sum of the log likelihood Iγ. The Iα + Iγ calculation cell circuit 276 ₁ calculates the calculated data AM0, AM1, AM
2, AM3, AM4, AM5, AM6 and AM7 are output as data AG00.

The Iα + Iγ calculation cell circuit 276
₂ has the same configuration as the Iα + Iγ calculation cell circuit 276 _1, and a detailed description thereof will be omitted, but the log likelihood DGAB
Of the predetermined log likelihood DGAB corresponding to the code
08, DGAB09, DGAB10, DGAB11, D
GAB12, DGAB13, DGAB14, DGAB1
5, a predetermined log likelihood AL00 corresponding to the sign of the log likelihood AL, and log likelihoods AL01S and AL02.
Using S and AL03S, the sum of the log likelihood Iα and the log likelihood Iγ used for obtaining the log soft output Iλ when the parallel paths are bundled is calculated. The Iα + Iγ calculation cell circuit 276 ₂ outputs the calculated data as data AG01.

Further, the Iα + Iγ calculation cell circuit 276 ₃
Has a configuration similar to that of the Iα + Iγ calculation cell circuit 276 _1, and a detailed description thereof will be omitted, but the log likelihood DGAB
Of the predetermined log likelihood DGAB corresponding to the code
16, DGAB17, DGAB18, DGAB19, D
GAB20, DGAB21, DGAB22, DGAB2
3, predetermined log likelihood AL00 corresponding to the sign of log likelihood AL, and log likelihood AL01S, AL02
Using S and AL03S, the sum of the log likelihood Iα and the log likelihood Iγ used for obtaining the log soft output Iλ when the parallel paths are bundled is calculated. I.alpha + i? Calculated cell circuit 276 ₃ outputs the calculated data as data AG02.

Further, the Iα + Iγ calculation cell circuit 27
6 _4, since the same configuration as I.alpha + i? Calculated cell circuit 276 _1, although a detailed description is omitted, the log likelihood DGA
B, a predetermined log likelihood DGA corresponding to the code
B24, DGAB25, DGAB26, DGAB27,
DGAB28, DGAB29, DGAB30, DGAB
31, predetermined log likelihood AL00 corresponding to the sign of log likelihood AL, and log likelihood AL01S, AL0
Using 2S and AL03S, the sum of log likelihood Iα and log likelihood Iγ used for obtaining log soft output Iλ when parallel paths are bundled is calculated. I.alpha + i? Calculated cell circuit 276 ₄ outputs the calculated data as data AG03.

The Iα + Iγ calculation circuit 243 is
The sum of the log likelihood Iα and the log likelihood Iγ is calculated, and the calculated data AG00, AG01, AG02, and AG03 are bundled and supplied to the selector 244 as data AGE.

The selector 244 receives the input bit number information IN
AGT indicating the sum of the log likelihood Iα and the log likelihood Iγ supplied from the addition / comparison / selection circuit 241 based on
And the log likelihood I supplied from the addition / comparison / selection circuit 242.
data AGF indicating the sum of α and log likelihood Iγ, and Iα +
One of the data AGE indicating the sum of the log likelihood Iα and the log likelihood Iγ supplied from the Iγ calculation circuit 243 is selected. Specifically, the selector 244
Is the code by the element encoder in the encoding device 1,
If there is no parallel path on the trellis and the code is such that two paths arrive from each state to the state at the next time, the data AGT is selected, and the element encoding in the encoding device 1 is performed. If there is no parallel path on the trellis and the code is such that four paths arrive from each state to the state at the next time, the data AGF is selected, and the coding device is selected. The code by the element encoder in 1 is represented by a trellis having a maximum of 32 branches and having a maximum of 4 states, more specifically, 8 paths are provided for each state for 4 states. If the parallel path to be reached is a code existing on the trellis, the data AG
Select E. That is, here, the input bit number information IN is used as a control signal for controlling the selection operation by the selector 244, but in practice, a control signal indicating the code configuration is input to the selector 244.

The Iα calculating circuit 158 calculates the log likelihood Iα, and outputs the calculated log likelihood Iα as it is, instead of outputting the calculated log likelihood Iα as it is, using the log likelihood Iα and the log likelihood Iα used for calculating the log soft output Iλ. The sum with the degree Iγ is output as data AG. The data AG is supplied to the soft output calculation circuit 161 as data AGD after a predetermined delay.

The Iβ calculating circuit 159 includes the Iγ distribution circuit 15
The log likelihood Iβ is calculated using the log likelihoods DGB0 and DGB1 supplied from. Specifically, based on the notation described at the beginning of “2.”, the Iβ calculation circuit 159 performs an operation represented by the following equation (52) using the log likelihood Iγ, and performs two operations at each time t. Are calculated in parallel. Note that the operator “#” in the following equation (52)
Indicates the log-sum operation as described above, and indicates the log likelihood at the time of transition from the state m ′ to the state m at the input “0”, and the state from the state m ″ at the input “1”. It shows a log-sum operation with log likelihood when transitioning to m. More specifically, the Iβ calculation circuit 159 determines that the constant sgn is “+1”.
In the case of (5), the operation shown in the following equation (53) is performed. On the other hand, when the constant sgn is “−1”, the following equation (5) is obtained.
By performing the operation shown in 4), the log likelihood Iβ at each time t is calculated. That is, the Iβ calculation circuit 15
9 is a log likelihood Iβ or a probability β, which is a logarithmic notation of the probability β from the truncated state to each state in the reverse order of the time series, based on the log likelihood Iγ, for each received value y _t , and is used for positive / negative identification. The log likelihood Iβ with the sign inverted is calculated.

[0399]

(Equation 52)

[0400]

(Equation 53)

[0401]

(Equation 54)

At this time, the Iβ calculation circuit 159 generates the generation matrix information CG supplied from the control circuit 60, the input bit number information IN, the type information WM and the memory number information MN supplied from the code information generation circuit 151, Termination information TB0D, T supplied from the reception data and delay storage circuit 155
The log likelihood Iβ is calculated based on B1D. The Iβ calculation circuit 159 supplies the calculated two systems of log likelihood Iβ to the Iβ storage circuit 160 as log likelihoods B0 and B1.

More specifically, as shown in FIG. 38, for example, as shown in FIG. 38, the Iβ calculating circuit 159 includes a control signal generating circuit 280 for generating a control signal and one log likelihood Iβ0 of two log likelihoods Iβ. And an Iβ0 addition / comparison / selection circuit 281 for calculating the log likelihood Iβ1
And an addition / comparison / selection circuit 282 for use.

The control signal generation circuit 280 uses the generation matrix information CG, the input bit number information IN, the type information WM, and the memory number information MN to generate four paths from each state on the trellis to the state at the next time. The state of the transition destination in the code that arrives is calculated and supplied to the Iβ0 addition / comparison / selection circuit 281 and Iβ1 addition / comparison / selection circuit 282 as a control signal NST.

The Iβ0 addition / comparison / selection circuit 281 is provided to calculate the log likelihood Iβ0. I
The β0 addition / comparison / selection circuit 281 performs addition / comparison / selection processing and log processing on a code such that two paths arrive from each state on the trellis to the state at the next time.
An addition / comparison / selection circuit 283 for performing a process of adding a correction term by −sum correction, and four from each state on the trellis to a state at the next time, or eight depending on the sign
An addition / comparison / selection circuit 284 that performs addition / comparison / selection processing and processing for adding a correction term by log-sum correction to a code that reaches this path, and a selector 285 that performs 2-to-1 selection. .

The addition / comparison / selection circuit 283 adds a correction term by addition / comparison / selection processing and log-sum correction to a code such that two paths arrive from each state on the trellis to the state at the next time. The log-sum operation is performed by performing the following processing.

Specifically, the addition / comparison / selection circuit 283
As shown in FIG. 39, the above-described addition / comparison / selection circuit 241
In the same way as above, of the codes that two paths reach from each state on the trellis to the state at the next time,
It has log-sum operation circuits 286 _n of the maximum number of states of the code to be decoded. Here, it is assumed that the addition / comparison / selection circuit 283 decodes a code having a maximum of 16 states, and 16 log-s
um operation circuits 286 ₁ , 286 ₂ , 286 ₃ ,..., 2
86 ₁₆ .

The log-sum operation circuit 28
6₁, 286_Two, 286_Three, ..., 286₁₆In it
The output on the trellis, based on the transition on the trellis, respectively
The log likelihood Iγ of the branch corresponding to the pattern and
The log likelihood Iβ0 one time before is supplied. Sand
The log-sum operation circuit 286₁, 286_Two, 286
_Three, ..., 286₁₆Contains the log likelihood DGB
0, a pair of branches corresponding to the output pattern on the trellis
Equivalent to number likelihood Iγ and calculated logarithm one hour before
Of likelihood BTT, log likelihood Iβ0 in each state
Is supplied. And log-su
m operation circuit 286₁, 286_Two, 286_Three, ..., 28
6₁₆Is the log likelihood in each state at the next time.
The degree Iβ is obtained as a log likelihood BTT. Each log-su
m operation circuit 286₁, 286_Two, 286 _Three, ..., 28
6₁₆Distribution of log likelihood BTT for
Here, the illustration is based on the memory number information MN.
It is determined by a selector or the like that does not. This log likelihood BT
The distribution of T will be described later.

More specifically, the log-sum operation circuit 28
6 ₁ has three adders 287 ₁ , 287 ₂ , 290 and l
It has a correction term calculation circuit 288 for calculating the value of the correction term in the og-sum correction, a selector 289, and an Iβ0 normalization circuit 291.

The adder 287 ₁ receives the log likelihood DGB00 of the log likelihood DGB0 and, among the log likelihood BTT calculated one time before, applies the log likelihood BTT corresponding to the sign to the log likelihood. B0, and these log likelihoods DGB00 and B0 are added. The adder 287 ₁ outputs the data AM0 indicating the sum of the log likelihood Iβ and the log likelihood Iγ obtained by the addition to the correction term calculation circuit 288 and the selector 2
89.

[0411] The adder 287 ₂ receives the log likelihood DGB01 of the log likelihood DGB0 and outputs the log likelihood BTT calculated one time earlier corresponding to the sign according to the sign. B1 and add these log likelihoods DGB01 and BGB1. The adder 287 ₂ supplies the data AM1 indicating Iβ0 + Iγ obtained by the addition to the correction term calculation circuit 288 and the selector 289.

Since the correction term calculation circuit 288 has the same configuration as the correction term calculation circuit 247 shown in FIG.
Here, although not described in detail, the data AM0 supplied from the adder 287 ₁ and the data AM1 supplied from the adder 287 ₂ are input, and data DM indicating the value of the correction term is calculated. At this time, similarly to the correction term calculation circuit 247, the correction term calculation circuit 288 does not calculate the absolute value of the difference value between the two pieces of input data and then obtains the value of the correction term. Calculate the values and select the appropriate one. In the correction term calculation circuit 288,
The data AM0, supplied from the adders 287 ₁ and 287 ₂
The difference between the data with “1” or “0” added to the most significant bit of the lower bits of AM1 is taken and the data AM
0 and AM1 are compared at high speed. Correction term calculation circuit 2
88 supplies the calculated data DM to the adder 290. Further, the correction term calculation circuit 288 generates a control signal SEL for controlling the selection operation by the selector 289.

[0413] The selector 289 is provided with a correction term calculation circuit 288.
Based on the control signal SEL supplied from the
A smaller value is selected from 0 and AM1. The selector 289 outputs the selected data SAM to the adder 2
90.

The adder 290 adds the data SAM supplied from the selector 289 and the data DM supplied from the correction term calculation circuit 288 to calculate the log likelihood Iβ0. The adder 290 supplies the calculated log likelihood Iβ0 as a log likelihood CM to the Iβ0 normalization circuit 291.

[0415] The Iβ0 normalizing circuit 291 calculates the Iα
Similarly to the normalization circuit 250, normalization for correcting the bias of the distribution of the log likelihood CM supplied from the adder 290 is performed. Also, the Iβ0 normalization circuit 291 outputs the termination information TB
A termination process is also performed using 0D. Iβ0 normalization circuit 29
1 performs clipping of the normalized log likelihood Iβ0 according to a required dynamic range, and performs log likelihood BT0
0, a predetermined log-sum operation circuit 286 ₁ , 2
86 _2, 286 _3,..., To be supplied to 286 _16. At this time, the log likelihood BT00 is set to 1 by a register (not shown).
After a delay time amount has been made, predetermined log-sum operation circuit 286 _1, 286 _2, 286 _3, ..., is supplied to 286 _16.

[0416] Such a log-sum operation circuit 286
₁ calculates and outputs the log likelihood BT00. That is,
The log-sum operation circuit 286 ₁ calculates the log likelihood B
In order to use T00 for calculating the log likelihood Iβ0 at the next time, a predetermined log-sum operation circuit 286 ₁ , 2
86 _2, 286 _3, ..., and supplies to 286 _16, and outputs to the outside.

Log-sum operation circuit 286_TwoIs lo
g-sum operation circuit 286₁Has the same configuration as
Therefore, although detailed description is omitted, the log likelihood DGB0
Log-likelihood DGB02, DGB03 and calculated one time before
Of the log likelihood BTTs that are
Are input as log-likelihoods B0 and B1, and these log-likelihoods are input.
Logarithm using the degrees DGB02, DGB03, B0, B1
The likelihood Iβ0 is calculated, and a predetermined log likelihood BT01 is calculated.
log-sum operation circuit 286₁, 286_Two, 286 _Three,
..., 286₁₆And output to the outside.
You.

Also, the log-sum operation circuit 286
₃ also, for the same configuration as the log-sum operation circuit 286 _1, although a detailed description is omitted, the log likelihood DGB0
Of the log likelihoods DGB04 and DGB05 and the log likelihood BTT calculated one time before, those corresponding to the sign are input as log likelihoods B0 and B1, and these log likelihoods DGB04 and DGB05 are input. The log likelihood Iβ0 is calculated by using DGB05, B0, and B1, and a predetermined log-sum operation circuit 286 ₁ , 286 ₂ ,
286 _3, ..., and supplies to 286 _16, and outputs to the outside.

Further, the log-sum operation circuit 286₁₆
Is also a log-sum operation circuit 286 ₁From the same configuration as
Therefore, although detailed description is omitted, the log likelihood DGB0
Log likelihood DGB30, DGB31, and one hour before
Of the log likelihood BTT calculated according to the sign
Are input as log likelihoods B0 and B1,
Using log likelihood DGB30, DGB31, B0, B1
Then, log likelihood Iβ0 is calculated and set as log likelihood BT15.
A predetermined log-sum operation circuit 286₁, 286_Two,
286_Three, ..., 286₁₆Supply to the outside
Output to

The addition / comparison / selection circuit 283 provides the log likelihood Iβ in a code such that two paths reach from each state on the trellis to the state at the next time.
Calculate 0. The addition / comparison / selection circuit 283 performs log-s
um operation circuits 286 ₁ , 286 ₂ , 286 ₃ ,..., 2
86 ₁₆ Data obtained by the respective BT00, B
, BT15 are supplied to the selector 285 as log likelihood BTT.

The addition / comparison / selection circuit 284 performs the addition / comparison / selection processing and log processing for a code such that four paths, or depending on the code, eight paths arrive from each state on the trellis to the state at the next time. By performing a process of adding a correction term by −sum correction, log−
Perform a sum operation.

More specifically, the addition / comparison / selection circuit 284
As shown in FIG. 40, the above-described addition / comparison / selection circuit 242
Similarly to the above, the maximum of the number of states of the code to be decoded among the codes in which four paths or eight paths depending on the code arrive from each state on the trellis to the state at the next time. It has a log-sum operation circuit 292 _n for the number of values. Here, the addition / comparison / selection circuit 284
Performs decoding of a code having a maximum of eight states, and includes eight log-sum operation circuits 292 ₁ ,.
It shall have a 292 _8.

The log-sum operation circuit 29
2 _1, ..., the 292 _8, respectively, log-sum in the ACS circuit 283 described above arithmetic circuit 28
6 _1, 286 _2, 286 _3, ..., as with 286 _16,
Based on the transition on the trellis, the log likelihood Iγ of the branch corresponding to the output pattern on the trellis and the log likelihood Iβ0 one time before in each state are supplied. That is, l
og-sum operation circuit 292 _1,..., and 292 _8,
Each of the log likelihood DGB0 corresponds to the log likelihood Iγ of the branch corresponding to the output pattern on the trellis, and the calculated log likelihood BTF one time earlier, the log likelihood Iβ0 in each state. The equivalent is supplied. Then, the log-sum operation circuit 292 ₁ ,.
-, 292 _8, respectively, determines the log likelihood Iβ0 in each state of the next time as the log likelihood BTF. Each l
og-sum operation circuit 292 _1, ..., distribution of the log likelihood BTF for 292 _8, depends on the code structure,
Here, it is determined by a selector or the like (not shown) based on the control signal NST. The distribution of the log likelihood BTF will be further described later.

More specifically, the log-sum operation circuit 29
2 ₁ has five adders 293 ₁ , 293 ₂ , 293 ₃ , 29
3 ₄ , 307, and six correction term calculation circuits 294 ₁ , 294 ₂ , which calculate the value of the correction term in the log-sum correction
294 ₃ , 294 ₄ , 294 ₅ , 294 ₆ and 11 selectors 295, 296, 297, 298, 299, 30
0, 301, 302, 303, 304, and 305, a selection control signal generation circuit 306 that generates a control signal for controlling the selection operation by the selector 305, and an Iβ0 normalization circuit 308.

The adder 293 ₁ receives the log likelihood DGB 00 of the log likelihood DGB 0, and outputs the log likelihood BTF calculated one time earlier corresponding to the sign according to the sign. B0, and these log likelihoods DGB00 and B0 are added. The adder 293 _1, correction term calculation circuit 294 ₁ data AM0 indicating the sum of log likelihood Iβ0 and log likelihood Iγ obtained by the addition, 294 _3,
294 ₅ and supplied to the selector 295.

[0426] The adder 293 ₂ receives the log likelihood DGB01 of the log likelihood DGB0 and, among the log likelihood BTF calculated one time ago, applies the log likelihood BTF corresponding to the sign to the log likelihood. B1 and add these log likelihoods DGB01 and BGB1. The adder 293 ₂ converts the data AM1 representing Iβ0 + Iγ obtained by the addition into the correction term calculation circuits 294 ₁ , 294 ₄ , 294 ₆ and the selector 2
95.

[0427] Adder 293 ₃ inputs the log likelihood DGB02 of log likelihood DGB0, of log likelihood BTF computed one time before, the log likelihood that apply in accordance with the code B2, and these log likelihoods DGB02 and BGB are added. The adder 293 ₃ converts the data AM2 indicating Iβ0 + Iγ obtained by the addition into the correction term calculation circuits 294 ₂ , 294 ₃ , 294 ₄ and the selector 2
96.

The adder 293 ₄ receives the log likelihood DGB03 of the log likelihood DGB0 and, among the log likelihood BTFs calculated one time before, applies the log likelihood BTF corresponding to the sign to the log likelihood. B3, and these log likelihoods DGB03 and B3 are added. The adder 293 ₄ converts the data AM3 indicating Iβ0 + Iγ obtained by the addition into the correction term calculation circuits 294 ₂ , 294 ₅ , 294 ₆ and the selector 2
96.

[0429] correction term calculation circuit 294 _1, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM0 supplied from the adder 293 ₁ , The data AM1 supplied from the adder 293 _2, and the data D indicating the value of the correction term.
Calculate M0. At this time, the correction term calculation circuit 294 ₁
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, in the correction term calculation circuit 294 ₁ , the data AM0 and AM1 supplied from the adders 293 ₁ and 293 ₂ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the magnitudes of the data AM0 and AM1 are compared at high speed. The correction term calculation circuit 294 ₁ outputs the calculated data DM0 to the selector 3
04. The correction term computation circuit 294 ₁ generates a control signal SEL0 for controlling the selecting operation of the selector 295,297,298,299,300.

[0430] correction term calculation circuit 294 _2, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM2 supplied from the adder 293 ₃ inputs the data AM3 supplied from the adder 293 _4, data indicating the value of the correction term D
Calculate M1. At this time, the correction term calculation circuit 294 ₂
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, in the correction term calculation circuit 294 ₂ , the data AM2 and AM3 supplied from the adders 293 ₃ and 293 _{4 are} provided with data “1” or “0” added to the most significant bit of the lower bit. By taking the difference, the data AM2 and AM3 are compared at high speed. The correction term calculation circuit 294 ₂ outputs the calculated data DM1 to the selector 3
04. Further, the correction term calculation circuit 294 ₂ generates a control signal SEL1 for controlling the selection operation by the selectors 296, 301, 302.

[0431] correction term calculation circuit 294 _3, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM0 supplied from the adder 293 ₁ inputs the data AM2 supplied from the adder 293 _3, data indicating the value of the correction term D
Calculate M2. At this time, the correction term calculation circuit 294 ₃
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, in the correction term calculation circuit 294 ₃ , the data AM0 and AM2 supplied from the adders 293 ₁ and 293 ₃ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the magnitudes of the data AM0 and AM2 are compared at high speed. The correction term calculation circuit 294 ₃ outputs the calculated data DM2 to the selector 2
Supply 99. Further, the correction term calculation circuit 294 ₃ generates a control signal SEL2 which is finally a control signal SEL8 for controlling the selection operation by the selectors 303 and 304, and generates the control signal SEL2 by the selector 297 and the selection control signal generation. The signal is supplied to a circuit 306.

[0432] correction term calculation circuit 294 _4, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM1 supplied from the adder 293 ₂ inputs the data AM2 supplied from the adder 293 _3, data indicating the value of the correction term D
Calculate M3. At this time, the correction term calculation circuit 294 ₄
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, in the correction term calculation circuit 294 ₄ , the data AM 1 and AM ₂ supplied from the adders 293 ₂ and 293 ₃ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the data AM1 and AM2 are compared with each other at high speed. The correction term calculation circuit 294 ₄ outputs the calculated data DM3 to the selector 2
Supply 99. Further, the correction term calculation circuit 294 ₄ finally generates a control signal SEL3 serving as a control signal SEL8 for controlling the selection operation by the selectors 303 and 304, and outputs the control signal SEL3 to the selector 297 and the control signal for selection. The signal is supplied to a circuit 306.

[0433] The correction term computation circuit 294 _5, for the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM0 supplied from the adder 293 ₁ inputs the data AM3 supplied from the adder 293 _4, data indicating the value of the correction term D
Calculate M4. At this time, the correction term calculation circuit 294 ₅
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Also, in the correction term calculation circuit 294 ₅ , the data AM 0 and AM 3 supplied from the adders 293 ₁ and 293 ₄ have data between “1” and “0” added to the most significant bit of the lower bit. By taking the difference, the magnitudes of the data AM0 and AM3 are compared at high speed. The correction term calculation circuit 294 ₅ outputs the calculated data DM4 to the selector 3
Supply to 00. Further, the correction term calculation circuit 294 ₅ generates a control signal SEL4, which finally becomes a control signal SEL8 for controlling the selection operation by the selectors 303 and 304, and uses this control signal SEL4 as the selector 298 and the selection control signal generation. The signal is supplied to a circuit 306.

[0434] correction term calculation circuit 294 _6, since the same configuration as the correction term calculation circuit 247 shown in FIG. 35 earlier, here it is not described in detail, the data AM1 supplied from the adder 293 ₂ inputs the data AM3 supplied from the adder 293 _4, data indicating the value of the correction term D
Calculate M5. In this case, the correction term computation circuit 294 _6,
Similarly to the correction term calculation circuit 247, instead of calculating the absolute value of the difference value between the two pieces of input data and then calculating the value of the correction term, the values of a plurality of correction terms are calculated, and an appropriate Choose one. Further, the correction term computation circuit 294 _6, adder 293 _2, 293 ₄ between the most significant bit of the lower bits of the data AM1, AM3 supplied "1" or "0" is assigned data from By taking the difference, the magnitudes of the data AM1 and AM3 are compared at high speed. The correction term calculation circuit 294 ₆ outputs the calculated data DM5 to the selector 3
Supply to 00. The correction term computation circuit 294 ₆ finally generates the control signal SEL5 to be a control signal SEL8 for controlling the selecting operation of the selectors 303 and 304, the control signal generating the control signal SEL5 selector 298 and selected The signal is supplied to a circuit 306.

The selector 295 includes a correction term calculation circuit 294
Based on the control signal SEL0 supplied from ₁ , data AM0 and AM1 are selected with a smaller value. The selector 295 supplies the selected data SAM0 to the selector 303.

The selector 296 includes a correction term calculation circuit 294
Based on the control signal SEL1 supplied from ₂ , data AM2 and AM3 are selected with a smaller value. The selector 296 supplies the selected data SAM1 to the selector 303.

The selector 297 includes a correction term calculation circuit 294
_{One of} the control signals SEL2 and SEL3 is selected based on the control signal SEL0 supplied from ₁ . Specifically, when the data AM0 has a larger value than the data AM1, the selector 297 outputs the control signal S
Select EL3. The selector 297 supplies the selected control signal SEL6 to the selector 301.

The selector 298 includes a correction term calculation circuit 294
_{One of} the control signals SEL4 and SEL5 is selected based on the control signal SEL0 supplied from ₁ . Specifically, when data AM0 has a larger value than data AM1, selector 298 outputs control signal S
Select EL5. The selector 298 supplies the selected control signal SEL7 to the selector 301.

The selector 299 includes a correction term calculation circuit 294
Based on the control signal SEL0 supplied from _{1, one of} the data DM2 and DM3 is selected. Specifically, the selector 299 selects the data DM3 when the data AM0 has a larger value than the data AM1. The selector 299 selects the data DS obtained by the selection.
0 is supplied to the selector 302.

The selector 300 includes a correction term calculation circuit 294
_{One of} the data DM4 and DM5 is selected based on the control signal SEL0 supplied from ₁ . Specifically, the selector 300 selects the data DM5 when the data AM0 has a larger value than the data AM1. The selector 300 selects the data DS obtained by the selection.
1 is supplied to the selector 302.

The selector 301 includes a correction term calculation circuit 294
Based on the control signal SEL1 supplied from ₂ , any one of the control signals SEL6 and SEL7 is selected. Specifically, when the value of the data AM2 is larger than that of the data AM3, the selector 301 controls the control signal S
Select EL7. The selector 301 supplies the control signal SEL8 obtained by selection as a control signal for selection in the selectors 303 and 304.

The selector 302 includes a correction term calculation circuit 294
Based on the control signal SEL1 supplied from ₂ , any one of the data DS0 and DS1 is selected. Specifically, the selector 302 selects the data DS1 when the data AM2 has a larger value than the data AM3. The selector 302 selects the data DS obtained by the selection.
2 is supplied to the selector 305.

The selector 303 selects one of the data SAM0 and SAM1 based on the control signal SEL8. Specifically, when the control signal SEL8 is the control signal SEL7, the selector 303 selects the data SAM1. The selector 303 supplies the selected data SAM2 to the adder 307.

The selector 304 selects one of the data DM0 and DM1 based on the control signal SEL8. Specifically, the selector 304 controls the control signal S
When EL8 is the control signal SEL7, the data D
Select M1. The selector 304 supplies the selected data DS3 to the selector 305.

[0445] The selector 305 is based on the control signal SEL9 supplied from the selection control signal generation circuit 306.
One of the data DS2 and DS3 is selected. The selector 305 selects the data RDM obtained by the selection.
Is supplied to the adder 307.

The selection control signal generation circuit 306 generates a control signal SEL9 for controlling the selection operation by the selector 305 based on the control signals SEL2, SEL3, SEL4 and SEL5. Specifically, the selection control signal generation circuit 306 controls the control signals SEL2, SEL3, S
The logical product of EL4 and SEL5 and the control signals SEL2 and SE
The control signal SEL9 is generated by taking the logical sum of the logical product of L3, SEL4, and SEL5 with the negation.

The adder 307 adds the data SAM2 supplied from the selector 303 and the data RDM supplied from the selector 305 to calculate a log likelihood Iβ0. The adder 307 supplies the calculated log likelihood Iβ0 to the Iβ0 normalization circuit 308 as log likelihood CM.

The Iβ0 normalization circuit 308
Similarly to the 0 normalization circuit 291, normalization is performed to correct the distribution bias of the log likelihood CM supplied from the adder 307. Further, the Iβ0 normalization circuit 308 calculates the termination information T
Termination processing is also performed using B0D. Iβ0 normalization circuit 3
08 performs clipping of the normalized log likelihood Iβ0 in accordance with a required dynamic range, and performs log likelihood BT
00, a predetermined log-sum operation circuit 292 ₁ ,
..., and supplies to 292 _8. At this time, the log likelihood BT
00 is a predetermined log-sum operation circuit 292 ₁ ,.
..., it is supplied to the 292 _8.

The log-sum operation circuit 292
₁ calculates and outputs the log likelihood BT00. That is,
The log-sum operation circuit 292 ₁ calculates the log likelihood B
In order to use T00 for calculating the log likelihood Iβ0 at the next time, a predetermined log-sum operation circuit 202 ₁ ,.
..., and supplies to 292 _8, and outputs it to the outside.

At this time, the log-sum operation circuit 292 ₁
Is selected from data AM0, AM1, AM2, and AM3 indicating likelihoods corresponding to four paths that have reached each state, or four sets of paths obtained by bundling eight paths depending on codes. By comparing the magnitude of likelihood for all combinations of data corresponding to two paths,
Among these data AM0, AM1, AM2 and AM3, data corresponding to at least two or more paths having high likelihood is obtained, and from the data corresponding to these paths,
The data corresponding to the highest likelihood path which is the path with the highest likelihood is selected. More specifically, the log-sum operation circuit 2
92 _1, the data AM0, AM1, AM2, AM3, so to speak by performing an operation to be likened to the tournament, compared value of the data AM0, the value of the data AM1, the magnitude of the value of the value and data AM3 data AM2 , The data corresponding to the maximum likelihood path is selected.

The log-sum operation circuit 292
₈ has the same configuration as the log-sum operation circuit 292 _1, and therefore detailed description is omitted, but the log likelihood DGB 0
Log likelihood DGB28, DGB29, DGB3
0, DGB31 and log likelihood BT calculated one time ago
Among F, those corresponding to the sign are represented by log likelihood B0,
B1, B2, B3, and their log likelihood DG
B28, DGB29, DGB30, DGB31, B0,
Using B1, B2, and B3, log likelihood Iβ0 is calculated,
As a log likelihood BT07, predetermined log-sum operation circuit 292 _1, ..., and supplies to 292 _8, and outputs to the outside.

The addition / comparison / selection circuit 284 calculates the log likelihood Iβ0 of a code such that four paths or eight paths depending on the code arrive from each state on the trellis to the state at the next time. I do. The addition / comparison / selection circuit 284 includes a log-sum operation circuit 292 ₁ ,.
..., data BT obtained by each of the 292 ₈
, BT07 are supplied to the selector 285 as data BTF. Note that the addition / comparison / selection circuit 28
4 is provided for calculating the log likelihood Iβ0 in a code such that four paths reach from each state on the trellis to the state at the next time, similarly to the above-described addition / comparison / selection circuit 242. However, as described above, the log likelihood Iβ0 of a code that can reach eight paths can be obtained depending on the code.
This is described in detail in “5-5-3” and “5-5-5”.

The selector 285 has the input bit number information IN
, And a log likelihood BTT indicating the log likelihood Iβ0 supplied from the addition / comparison / selection circuit 283 and data B indicating the log likelihood Iβ0 supplied from the addition / comparison / selection circuit 284.
One of the TFs is selected. In particular,
The selector 285 determines that the code by the element encoder in the encoding device 1 is such that no parallel path exists on the trellis and two paths reach from each state to the state at the next time. Contains the log likelihood B
TT is selected, and the code by the element encoder in the encoding device 1 is such that no parallel path exists on the trellis and four paths reach from each state to the state at the next time. In the case, log likelihood BTF
Select That is, here, the input bit number information IN is used as a control signal for controlling the selection operation by the selector 285, but actually, a control signal indicating a code configuration is input to the selector 285.

The Iβ0 addition / comparison / selection circuit 28
1 calculates log likelihood Iβ0, and outputs the calculated log likelihood Iβ0 as log likelihood B0. This log likelihood B0 is supplied to the Iβ storage circuit 160.

On the other hand, Iβ1 addition / comparison / selection circuit 282
Is provided to calculate the log likelihood Iβ1. The Iβ1 addition / comparison / selection circuit 282 has the same configuration as the Iβ0 addition / comparison / selection circuit 281, and thus detailed description is omitted, but the log likelihood DGB0 and the termination information T
Log likelihood DGB1 and termination information TB1 instead of B0D
D is input to calculate log likelihood Iβ1, and the calculated log likelihood Iβ1 is output as log likelihood B1. This log likelihood B1 is supplied to the Iβ storage circuit 160.

The Iβ calculating circuit 159 calculates the log likelihoods Iβ0 and Iβ1 of the two systems in parallel, and uses these calculated log likelihoods Iβ0 and Iβ1 as log likelihoods B0 and B1, respectively. The data is supplied to the storage circuit 160.

Although not shown, the Iβ storage circuit 160 has, for example, a plurality of banks of RAM, a control circuit, and a selection circuit. The Iβ storage circuit 160 includes an Iβ calculation circuit 159
Are stored as log likelihoods B0 and B1. Then, under control of the internal control circuit, the Iβ storage circuit 160 selects predetermined information from the stored log likelihoods B0 and B1 by using the selection circuit, and uses the logarithm used to calculate the log soft output Iλ. As the likelihood BT, the soft output calculation circuit 16
Feed to 1. Note that, as described above, the element decoder 50 performs a memory management method in the Iβ storage circuit 160 when performing the sliding window process as follows.
The one described in International Publication No. WO 99/62183 is adopted, and by performing the memory management for the received data and delay storage circuit 155 and the memory management for the Iβ storage circuit 160, the final The logarithmic soft output Iλ can be obtained in the original chronological order.

The soft output calculation circuit 161 is provided by the Iα calculation circuit 1
The data AGD supplied from the memory 58 and the Iβ storage circuit 16
The log soft output Iλ is calculated using the log likelihood BT supplied from 0. Specifically, the soft output calculation circuit 161
Is based on the notation described at the beginning of “2.”, performs the operation shown in the following equation (55) using the log likelihood Iγ, the log likelihood Iα and the log likelihood Iβ, and calculates the logarithm at each time t. Calculate the soft output Iλ. Note that the operator “# に お け る” in the following equation (55) is a log-log represented by the above-described operator “#”.
It shows a cumulative addition operation of a sum operation.

[0459]

[Equation 55]

The soft output calculation circuit 161 can also calculate the log soft output Iλ in symbol units or bit units. The soft output calculation circuit 161 includes an output data selection control signal CITM supplied from the outside, prior probability information format information CAPP supplied from the control circuit 60, input bit number information IN supplied from the code information generation circuit 151,
Based on memory number information MN and branch input / output information BIO, log soft output Iλ corresponding to posterior probability information for information symbols or information bits, or log soft output Iλ corresponding to posterior probability information for code symbols or code bits.
Calculate λ. The soft output calculation circuit 161 converts a log soft output Iλ calculated in a symbol unit or a log soft output Iλ calculated in a bit unit into log soft outputs SLM and BLM, respectively.
Are supplied to the external information calculation circuit 163, the amplitude adjustment and clipping circuit 164, and the hard decision circuit 165.

Specifically, as shown in FIG. 41, for example, the soft output calculation circuit 161 calculates the log likelihood Iα and the log likelihood Iγ
A log-likelihood I beta sum and Iα + Iγ + Iβ computation circuit 310 for calculating a, the enable signal generating circuit 311 generates an enable signal, for example, six log-sum operation circuit 312 _1, 312 _2, 312 _3, 312 _4, 312 _5,
312 and _6, Iλ calculation circuit 3 for calculating a log soft-output Airamuda
13 can be realized.

The Iα + Iγ + Iβ calculation circuit 310 includes an Iβ distribution circuit 314 for distributing the log likelihood Iβ, and a maximum value among the number of states of the code to be decoded, here 32
Adders 315 ₁ , 315 ₂ , 315 ₃ , 315 ₄ , 31
5 _5, 315 _6, ..., and a 315 _31, 315 _32.

The Iβ distribution circuit 314 includes the Iβ storage circuit 16
The log likelihood BT supplied from 0 is distributed according to the code configuration. That is, Iβ distribution circuit 314 distributes log likelihood BT so as to correspond to a trellis corresponding to the code configuration. At this time, the Iβ distribution circuit 314 distributes the log likelihood BT based on the input bit number information IN supplied from the code information generation circuit 151. The Iβ distribution circuit 314
The log likelihood Iβ obtained by the distribution is added to adders 315 ₁ and 31 ₁
5 _2, 315 _3, 315 _4, 315 _5, 315 _6, ...,
315 ₃₁ and 315 ₃₂ . That is, Iβ distribution circuit 314 calculates log likelihood I used for calculation of log soft output Iλ.
β is a log likelihood BTD and adders 315 ₁ , 315 ₂ , 3
15 _3, 315 _4, 315 _5, 315 _6, ..., 31
5 _31, 315 ₃ supplies _2.

The adder 315 ₁ receives the data AG00 of the data AGD indicating the sum of the log likelihood Iα and the log likelihood Iγ supplied from the Iα calculation circuit 158 and the log likelihood supplied from the Iβ distribution circuit 314. The log likelihood BTD00 of the degrees BTD is added. The adder 315 ₁ outputs the sum of the log likelihood Iα, the log likelihood Iγ, and the log likelihood Iβ obtained by the addition as data AGB00.

[0465] Adder 315 ₂ includes data AG01 of data AGD supplied from Iα calculation circuit 158, and
The log likelihood BTD00 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₂
Outputs the sum of the log likelihood Iα, Iγ and Iβ obtained as a result as data AGB01.

[0466] Adder 315 ₃ includes data AG02 of data AGD supplied from Iα calculation circuit 158,
The log likelihood BTD01 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₃
Outputs the sum of the log likelihood Iα, Iγ, and Iβ obtained by the addition as data AGB02.

[0467] Adder 315 ₄ includes a data AG03 of the data AGD supplied from Iα computation circuit 158,
The log likelihood BTD01 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₄
Outputs the sum of the log likelihood Iα, Iγ, and Iβ obtained by the addition as data AGB03.

The adder 315 ₅ includes the data AG04 of the data AGD supplied from the Iα calculation circuit 158,
The log likelihood BTD02 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₅
Outputs the sum of the log likelihood Iα, Iγ, and Iβ obtained by the addition as data AGB04.

[0469] The adder 315 ₆ outputs the data AG05 of the data AGD supplied from the Iα calculation circuit 158,
The log likelihood BTD02 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₆
Outputs the sum of the log likelihood Iα, Iγ, and Iβ obtained as the addition as data AGB05.

[0470] Adder 315 ₃₁ includes a data AG30 of the data AGD supplied from Iα computation circuit 158,
The log likelihood BTD 15 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₃₁
Outputs the sum of the log likelihood Iα, Iγ, and Iβ obtained as a result as data AGB30.

[0471] The adder 315 ₃₂ includes the data AG31 of the data AGD supplied from the Iα calculation circuit 158,
The log likelihood BTD 15 of the log likelihood BTD supplied from the Iβ distribution circuit 314 is added. Adder 315 ₃₂
Outputs, as data AGB31, the sum of log likelihood Iα, Iγ, and Iβ obtained by the addition.

[0472] Such an Iα + Iγ + Iβ calculation circuit 31
0 is the sum of the log likelihood Iα, the log likelihood Iγ, and the log likelihood Iβ, and the calculated data AGB00, AGB01,
AGB02, AGB03, AGB04, AGB05,
··, AGB30, AGB31 bundling, log-sum operation circuit 312 as data AGB _1, 312 _2, 312
_3, 312 _4, 312 _5, 312 supplies to _6.

The enable signal generation circuit 311 includes a selection control signal generation circuit 316 for generating a control signal for controlling the selection operation by the selectors 323 ₁ , 323 ₂ , 323 ₃ , and 323 ₄ , and a symbol corresponding branch selection circuit 319. And an effective branch selection circuit 317 for selecting a branch to be selected by the bit corresponding branch selection circuits 320, 321 and 322.
An output data selection circuit 318 for selecting branch input / output information BIO to be referred to when calculating log soft output Iλ, and a symbol for selecting a branch corresponding to the symbol when calculating log soft output Iλ in symbol units. Branch selection circuit 319
And a bit-corresponding branch selection circuit 32 for selecting a branch corresponding to the bit when calculating the logarithmic soft output Iλ in bit units.
0, 321, 322 and selectors 323 ₁ , 323 ₂ , 3
And a 23 _3, 323 _4.

The selection control signal generation circuit 316 outputs the output data selection control signal CITM supplied from the outside and the prior probability information format information CAPP supplied from the control circuit 60.
, The selectors 323 ₁ , 323 ₂ , 323 ₃ ,
Control signal AP for controlling the selecting operation of 323 ₄
Generate

[0475] The valid branch selection circuit 317 determines the symbol corresponding branch selection circuit 31 based on the input bit number information IN and the memory number information MN supplied from the code information generation circuit 151.
9 and control signals M1, M2, and M3 indicating whether the branch input / output information BIO input to each of the branch selection circuits 320, 321, and 322 are valid. That is, the valid branch selection circuit 317 includes a symbol corresponding branch selection circuit 319 and a bit corresponding branch selection circuits 320, 321,
322 generate control signals M1, M2 and M3 for selecting a branch to be selected. The valid branch selection circuit 317 supplies the generated control signals M1 and M2 to the bit corresponding branch selection circuits 320, 321 and 322, and also supplies the control signal M3 to the symbol corresponding branch selection circuit 319 and the bit corresponding branch selection circuits 320 and 321. 322.

The output data selection circuit 318 is supplied from the code information generation circuit 151 based on the output data selection control signal CITM supplied from outside and the input bit number information IN supplied from the code information generation circuit 151. From the branch input / output information BIO, the one corresponding to the branch corresponding to the code configuration is selected. The output data selection circuit 318 converts the selected branch input / output information BIO0 into the bit corresponding branch selection circuit 3
20 and the selected branch input / output information BIO
1 is supplied to the bit corresponding branch selection circuit 321 and
The selected branch input / output information BIO2 is supplied to the bit corresponding branch selection circuit 322.

The symbol corresponding branch selection circuit 319 is provided for calculating the log soft output Iλ in symbol units. Using the branch input / output information BIO supplied from the code information generation circuit 151, the symbol corresponding branch selection circuit 319 selects a branch corresponding to the symbol. At this time, the symbol corresponding branch selection circuit 319 selects a branch based on the control signal M3 supplied from the valid branch selection circuit 317. The symbol corresponding branch selection circuit 319 outputs enable signals SEN0, SEN1, SEN2, SEN3 indicating whether the input corresponding to the selected branch is “0” or “1”.
And the enable signal SEN0 is supplied to the selector 323 ₁
Supplies to supplies an enable signal SEN1 to the selector 323 _2, the enable signal SEN
2 is supplied to the selector 323 ₃ , and the enable signal SEN ₃ is supplied to the selector 323 ₄ .

The bit corresponding branch selection circuit 320 is provided for calculating the log soft output Iλ in bit units. The bit corresponding branch selection circuit 320 uses the branch input / output information BIO0 supplied from the output data selection circuit 318 to select a branch corresponding to the bit. At this time, the bit corresponding branch selection circuit 320 selects a branch based on the control signals M1, M2, and M3 supplied from the valid branch selection circuit 317. Bits corresponding branch selection circuit 320 generates the enable signal EN00, EN01 indicating whether input corresponding to branches were selected is "0" or "1", and supplies the enable signal EN00 to the selector 323 ₁ , supplies the enable signal EN01 to the selector 323 _2.

The bit corresponding branch selection circuit 321 is provided for calculating the logarithmic soft output Iλ in bit units, similarly to the bit corresponding branch selection circuit 320. The bit corresponding branch selection circuit 321 selects a branch corresponding to the bit by using the branch input / output information BIO1 supplied from the output data selection circuit 318. At this time, the bit corresponding branch selection circuit 321 selects a branch based on the control signals M1, M2, and M3 supplied from the valid branch selection circuit 317. The bit corresponding branch selection circuit 321 generates enable signals EN10 and EN11 indicating whether an input corresponding to the selected branch is “0” or “1”, and generates an enable signal EN10.
Is supplied to the selector 323 ₃ and the enable signal EN11 is supplied to the selector 323 ₄ .

The bit-corresponding branch selection circuit 322 is provided for calculating the logarithmic soft output Iλ in bit units, similarly to the bit-corresponding branch selection circuit 320. The bit corresponding branch selection circuit 322 selects a branch corresponding to the bit using the branch input / output information BIO2 supplied from the output data selection circuit 318. At this time, the bit corresponding branch selection circuit 322 selects a branch based on the control signals M1, M2, and M3 supplied from the valid branch selection circuit 317. The bit corresponding branch selection circuit 322 generates enable signals EN20 and EN21 indicating whether the input corresponding to the selected branch is “0” or “1”, and generates the enable signal EN20.
The supplies to log-sum operation circuit 312 ₅ supplies the enable signal EN21 to log-sum operation circuit 312 _6.

The selector 323 ₁ is supplied from the enable signal SEN0 supplied from the symbol corresponding branch selection circuit 319 and the bit corresponding branch selection circuit 320 based on the control signal AP supplied from the selection control signal generation circuit 316. One of the enable signals EN00 to be selected. Specifically, the selector 323 _1, the control signal AP is, the effect of outputting the information for the information symbols or information bits shown are the output data selection control signal CITM,
In addition, the prior probability information format information C
If the signal is indicated by APP, the enable signal SEN0 supplied from the symbol corresponding branch selection circuit 319 is selected. The selector 323 ₁ supplies the enable signal ENS0 selected to log-sum operation circuit 312 _1.

The selector 323 ₂ is supplied from the enable signal SEN1 supplied from the symbol corresponding branch selection circuit 319 and the bit corresponding branch selection circuit 320 based on the control signal AP supplied from the selection control signal generation circuit 316. One of the enable signals EN01 to be selected. Specifically, the selector 323 _2, control signals the AP, the effect of outputting the information for the information symbols or information bits shown are the output data selection control signal CITM,
In addition, the prior probability information format information C
When the signal is indicated by APP, the enable signal SEN1 supplied from the symbol corresponding branch selection circuit 319 is selected. The selector 323 ₂ supplies the enable signal ENS1 selected to log-sum operation circuit 312 _2.

The selector 323 ₃ is supplied based on the control signal AP supplied from the selection control signal generation circuit 316 and the enable signal SEN 2 supplied from the symbol corresponding branch selection circuit 319 and the bit corresponding branch selection circuit 321. One of the enable signals EN10. Specifically, the selector 323 _3, the control signal AP is, the effect of outputting the information for the information symbols or information bits shown are the output data selection control signal CITM,
In addition, the prior probability information format information C
When the signal is indicated by APP, the enable signal SEN2 supplied from the symbol corresponding branch selection circuit 319 is selected. The selector 323 ₃ supplies the enable signal ENS2 selected to log-sum operation circuit 312 _3.

The selector 323 ₄ is supplied based on the control signal AP supplied from the selection control signal generation circuit 316, the enable signal SEN3 supplied from the symbol corresponding branch selecting circuit 319, and the enable signal SEN3 supplied from the bit corresponding branch selecting circuit 321. One of the enable signals EN11 to be selected. Specifically, the selector 323 _4, control signals the AP, the effect of outputting the information for the information symbols or information bits shown are the output data selection control signal CITM,
In addition, the prior probability information format information C
If the signal indicates APP, the enable signal SEN3 supplied from the symbol corresponding branch selection circuit 319 is selected. The selector 323 ₄ supplies the enable signal ENS3 selected to log-sum operation circuit 312 _4.

[0485] Such an enable signal generation circuit 311
Are output data selection control signal CITM, prior probability information format information CAPP, memory number information MN, and branch input / output information B
Using IO, an enable signal E corresponding to the selected branch
NS0, ENS1, ENS2, ENS3, EN20, E
N21 is generated, and the log-sum operation circuit 312 ₁ , 3
12 _2, 312 _3, 312 _4, 312 _5, 312 supplies to _6.

The log-sum operation circuit 312 ₁ is shown in FIG.
As shown in FIG. 2, when the maximum value of the number of states of the code to be decoded is M, the number of log-sum operation cell circuits 325 _n represented by M × 2-1 is provided. Here, it is assumed that the log-sum operation circuit 312 ₁ decodes a code having a maximum of 16 states, and that 31 l
og-sum operation cell circuit 325 ₁ ,..., 325 ₃₁
Shall be provided.

The log-sum operation cell circuit 325 ₁
Two differentiators 326 ₁ and 326 ₂ and six selectors 32
7, 328, 329, 332, 336, 338 and a selection control signal generation circuit 33 for generating a control signal for controlling the selection operation by the selectors 327, 328, 329.
0, a selection control signal generation circuit 331 that generates a control signal for controlling the selection operation by the selector 332,
AND gate 333, OR gate 334, log-
It has a lookup table 335 that stores the value of the correction term in the sum correction as a table, and an adder 337.

The differentiator 326 ₁ outputs predetermined data AGB000, AGB00 corresponding to the code among the data AGB supplied from the Iα + Iγ + Iβ calculation circuit 310.
Take the difference of 1. Strictly speaking, the differentiator 326 ₁ outputs the data AGB000 and AGB001 to, for example, 13
The data AGB000 has a lower 6-bit data with "1" added to the most significant bit and the data AGB001 has a lower 6-bit data with "0" added to the most significant bit. And take the difference. The differentiator 326 ₁ outputs the calculated difference value DA1 to the selector 327.
And a control signal generation circuit 330 for selection.

[0489] The differentiator 326 ₂ outputs predetermined data AGB001 and AGB00 corresponding to the sign of the data AGB supplied from the Iα + Iγ + Iβ calculation circuit 310.
Take the difference of 0. Strictly speaking, the differentiator 326 ₂ outputs the data AGB000 and AGB001 to, for example, 13
If the data AGB001 has the highest order bit of data AGB001, the most significant bit of the lower order 6 bits of the data AGB001 has "1" added thereto, and the lower order 6 bits of data AGB000 has the highest order bit of data "0" added. And take the difference. The differentiator 326 ₂ outputs the calculated difference value DA0 to the selector 328.
And a control signal generation circuit 330 for selection.

[0490] The selector 327, based on the control signal SL1 supplied from the selection control signal generating circuit 330, a difference value DA1 supplied from differentiator 326 _1, among the data having the predetermined value N1, any Select one or the other. Specifically, the value of the correction term for the difference value DA1 is
Since the value of the difference value DA1 exceeds the predetermined value N1, the selector 327 selects data having the predetermined value N1 because it has the property of asymptotically approaching the predetermined value. The selector 327 selects the data SDA obtained by the selection.
1 is supplied to the selector 329.

The selector 328 determines which of the difference value DA0 supplied from the differentiator 326 ₂ and the data having the predetermined value N1 based on the control signal SL1 supplied from the selection control signal generation circuit 330. Select one or the other. Specifically, the value of the correction term for the difference value DA0 is
Since the value of the difference value DA0 exceeds the predetermined value N1, the selector 328 selects data having the predetermined value N1 because of the property of asymptotically approaching the predetermined value. The selector 328 selects the data SDA obtained by the selection.
0 is supplied to the selector 329.

The selector 329 selects one of the data SDA1 supplied from the selector 327 and the data SDA0 supplied from the selector 328 based on the control signal SL2 supplied from the selection control signal generation circuit 330. Select Specifically, the selector 329
If the value of data AGB000 is larger than the value of data AGB001, data SDA1 supplied from selector 327 is selected. The selector 329 supplies the data DM obtained by the selection to the look-up table 335.

The selection control signal generation circuit 330 generates a control signal SL1 for controlling the selection operation by the selectors 327 and 328 based on the data AGB00 and AGB01 and the difference values DA1 and DA0, and also selects the selector 329. Control signal S for controlling the selection operation by
Generate L2. The selection control signal generation circuit 330 converts the generated control signal SL2 into the selection control signal generation circuit 331.
Also supply. At this time, the selection control signal generation circuit 330
Is similar to the selection control signal generation circuit 232 described above.
Based on the data AGB00 and AGB01, the upper bits and the lower bits of the metric are divided to generate control signals SL1 and SL2 indicating a determination sentence for selection, which will be described later.

The selection control signal generation circuit 331 outputs the enable signals EN000 and EN00 of the enable signals ENS0 supplied from the enable signal generation circuit 311.
1 and a control signal SL2 for controlling the selection operation by the selector 332 based on the control signal SL2.

The selector 332 selects one of the data AGB000 and AGB001 based on the control signal SEL supplied from the selection control signal generation circuit 331. The selector 332 supplies the selected data DAG to the adder 337.

The AND gate 333 outputs the enable signal E
The logical product of N000 and EN001 is calculated. AND gate 3
33 supplies the obtained logical product ENA to the selector 336 as a control signal for selection.

The OR gate 334 outputs the enable signal EN
000, EN001 is ORed. OR gate 334
Supplies the obtained logical sum EN to the selector 338 as a control signal for selection, and supplies the enable signal EN1
00 supplies the log-sum operation cell circuit 325 ₁₇ as.

The look-up table 335 stores the log-
The value of the correction term in the sum correction is stored as a table. The look-up table 335 reads the value of the correction term corresponding to the value of the data DM supplied from the selector 329 from the table, and as the data RDM,
6

The selector 336 selects one of the data RDM supplied from the look-up table 335 and the data having a predetermined value N2 based on the logical product ENA supplied from the AND gate 333. . Specifically, if the logical product ENA is “1”, the selector 336 selects the data RDM. The selector 336 supplies the selected data SDM to the adder 337. The predetermined value N2 is an offset value added to unify the positive / negative identification code of the data CAG described later. That is, the data AGB000,
Data DAG which is one of AGB001
Can take a value that crosses positive and negative, but expressing both positive and negative values causes an increase in circuit scale. Therefore, in the log-sum operation cell circuit 325 ₁ ,
A predetermined value N2 to be added by an adder 337 described later is introduced so as to unify the positive / negative identification code of the data DAG.

The adder 337 adds the data DAG supplied from the selector 332 and the data SDM supplied from the selector 336. The adder 337 supplies the calculated data CAG to the selector 338.

The selector 338 selects one of the data CAG supplied from the adder 337 and the data having a predetermined value N3 based on the logical sum EN supplied from the OR gate 334. Specifically, when the logical sum EN is “1”, the selector 338
Select the data CAG. The selector 338 converts the data AGL obtained by the selection into the log-sum operation cell circuit 3.
25 ₁₇

The log-sum operation circuit 325 as described above
₁ is the data AGB000 and the data AGB001 supplied from the Iα + Iγ + Iβ calculation circuit 310, and
Using the enable signal EN000 and the enable signal EN001 supplied from the enable signal generation circuit 311, as described later, by performing an operation analogous to the first round in the winning match, the log soft output I
One log-sum operation in the cumulative addition operation of the log-sum operation performed when calculating λ is performed. log
-Sum operation circuit 325 _1, a computed data AGL as data AGB100, supplies to the log-sum operation cell circuit 325 ₁₇ to perform an operation to be likened to a second round of the tournament, the enable signal EN10
0 supplied to the log-sum operation cell circuit 325 _17.

The log-sum operation circuit 325 ₂ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB002 and AGB003 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN002 and the enable signal EN003 supplied from the log-su.
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₂ uses the calculated data AGL as data AGB101,
supplies to um operation cell circuit 325 _17, the enable signal EN101 log-sum operation cell circuit 32
5 ₁₇

The log-sum operation circuit 325 ₃ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB004 and the data AGB005 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN004 and the enable signal EN005 supplied from the first game in the win-out game.
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum arithmetic circuit 325 ₃ uses the calculated data AGL as the data AGB 102 to perform an operation analogous to the second round in the winning game.
supplies the m operation cell circuit 325 _18, the enable signal EN102 log-sum operation cell circuit 325
Supply ₁₈

The log-sum operation circuit 325 ₄ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB006 and AGB007 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN006 and the enable signal EN007 supplied from the first game in the win-out game.
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₄ uses the calculated data AGL as data AGB103,
supplies to um operation cell circuit 325 _18, the enable signal EN103 log-sum operation cell circuit 32
Supplied to the 5 _18.

The log-sum operation circuit 325 ₅ is
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB008 and AGB009 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN008 and the enable signal EN009 supplied from the
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₅ uses the calculated data AGL as the data AGB 104 to perform an operation analogous to the second round in the winning game.
supplies the m operation cell circuit 325 _19, the enable signal EN104 log-sum operation cell circuit 325
Supply ₁₉

The log-sum operation circuit 325 ₆ calculates
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB010 and AGB011 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN010 and the enable signal EN011 supplied from the first game in the winning match, and log-su
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₆ uses the calculated data AGL as the data AGB 105 to log-s
supplies to um operation cell circuit 325 _19, the enable signal EN105 log-sum operation cell circuit 32
5 is supplied to the _19.

[0508] The log-sum operation circuit 325 ₇ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB012 and AGB013 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN012 and the enable signal EN013 supplied from the
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₇ uses the calculated data AGL as the data AGB 106 to perform an operation analogous to the second match in the winning match.
supplies the m operation cell circuit 325 _20, the enable signal EN106 log-sum operation cell circuit 325
Supply ₂₀ .

The log-sum operation circuit 325 ₈ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB014 and AGB015 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN014 and the enable signal EN015 supplied from the terminal device, and performing an operation analogous to the first match in the winning match.
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₈ uses the calculated data AGL as the data AGB 107 to log-s
supplies to um operation cell circuit 325 _20, the enable signal EN107 log-sum operation cell circuit 32
Supplied to the 5 _20.

The log-sum operation circuit 325 ₉ is
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB016 and AGB017 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
By using the enable signal EN016 and the enable signal EN017 supplied from the CPU, an operation analogous to the first match in the winning match is performed, and the log-su
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₉ uses the calculated data AGL as the data AGB 108 to perform an operation analogous to the second round in the winning game.
supplies the m operation cell circuit 325 _21, the enable signal EN108 log-sum operation cell circuit 325
Supply ₂₁ .

[0511] The log-sum operation circuit 325 ₁₀
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB018 and AGB019 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN018 and the enable signal EN019 supplied from the first game in the win game.
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₁₀ uses the calculated data AGL as data AGB 109 to log-s
The um operation cell circuit 325 ₂₁ and the enable signal EN109 are supplied to the log-sum operation cell circuit 32.
5 Supply to ₂₁ .

The log-sum operation circuit 325 ₁₁ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB020 and AGB021 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN020 and the enable signal EN021 supplied from the PC to perform an operation analogous to the first round in the winning game.
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₁₁ uses the calculated data AGL as the data AGB 110 to perform an operation analogous to the second match in the winning match.
supplies the m operation cell circuit 325 _22, the enable signal EN110 log-sum operation cell circuit 325
Supply ₂₂ .

The log-sum operation circuit 325 ₁₂ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB022 and AGB023 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN022 and the enable signal EN023 supplied from the
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₁₂ uses the calculated data AGL as the data AGB 111 to log-s
supplies to um operation cell circuit 325 _22, the enable signal EN111 log-sum operation cell circuit 32
5 Supply to ₂₂ .

The log-sum operation circuit 325 ₁₃ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , detailed description is omitted, but the data AGB024 and the data AGB025 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN024 and the enable signal EN025 supplied from
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₁₃ uses the calculated data AGL as the data AGB 112 to perform an operation analogous to the second match in the winning match.
supplies the m operation cell circuit 325 _23, the enable signal EN112 log-sum operation cell circuit 325
Supply ₂₃ .

[0515] The log-sum operation circuit 325 ₁₄ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB026 and AGB027 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
By using the enable signal EN026 and the enable signal EN027 supplied from the PC, an operation analogous to the first match in the winning match is performed, and the log-su
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₁₄ uses the calculated data AGL as data AGB 113 to log-s
um operation cell circuit 325 _23, and supplies enable signal EN 113 to log-sum operation cell circuit 32.
5 to ₂₃ .

[0516] The log-sum operation circuit 325 ₁₅
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , detailed description is omitted, but the data AGB028 and AGB029 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN028 and the enable signal EN029 supplied from the
One log-sum operation in the cumulative addition operation of the m operation is performed. log-sum operation circuit 325 ₁₅ is a computed data AGL as data AGB114, log-su performing an operation to be likened to a second round of the tournament
supplies the m operation cell circuit 325 _24, the enable signal EN114 log-sum operation cell circuit 325
Supply ₂₄ .

The log-sum operation circuit 325 ₁₆ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB030 and the data AGB031 supplied from the Iα + Iγ + Iβ calculation circuit 310 and the enable signal generation circuit 311
Is performed by using the enable signal EN030 and the enable signal EN031 supplied from the
One log-sum operation in the cumulative addition operation of the m operation is performed. The log-sum operation circuit 325 ₁₆ uses the calculated data AGL as the data AGB 115 to log-s
um operation cell circuit 325 ₂₄ and supplies enable signal EN115 to log-sum operation cell circuit 32.
Supply to ₂₄ .

[0518] log-sum operation circuit 325 _17, lo
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB100 and the enable signal EN100 supplied from the log-sum operation cell circuit 325 ₁ and the log-sum operation cell circuit By using the data AGB101 and the enable signal EN101 supplied from 325 ₂ and performing an operation analogous to the second match in the winning match, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
_17, the computed data AGL as data AGB200, supplies to the log-sum operation cell circuit 325 ₂₅ to perform an operation to be likened to the third round of the tournament, the enable signal EN200 to log-sum operation cell circuit 325 ₂₅ Supply.

The log-sum operation circuit 325 ₁₈ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB 102 and the enable signal EN 102 supplied from the log-sum operation cell circuit 325 ₃ and the log-sum operation cell circuit 325 ₄ using data AGB103 and enable signals EN103 supplied from, by performing an operation to be likened to a second round of the tournament, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₁₈ supplies the computed data AGL as data AGB201, supplies to the log-sum operation cell circuit 325 _25, the enable signal EN201 to log-sum operation cell circuit 325 _25.

The log-sum operation circuit 325 ₁₉ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB104 and enable signals EN104 supplied from log-sum operation cell circuit 325 _5, and, log-sum operation cell circuit 325 ₆ by using the data AGB105 and enable signals EN105 supplied from, by performing an operation to be likened to a second round of the tournament, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
_19, the computed data AGL as data AGB202, supplies to the log-sum operation cell circuit 325 ₂₆ to perform an operation to be likened to the third round of the tournament, the enable signal EN202 to log-sum operation cell circuit 325 ₂₆ Supply.

The log-sum operation circuit 325 ₂₀ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB106 and enable signals EN106 supplied from log-sum operation cell circuit 325 _7, and, log-sum operation cell circuit By using the data AGB 107 and the enable signal EN 107 supplied from 325 ₈ to perform an operation analogous to the second round in the winning game, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₂₀ supplies the computed data AGL as data AGB203, supplies to the log-sum operation cell circuit 325 _26, the enable signal EN203 to log-sum operation cell circuit 325 _26.

The log-sum operation circuit 325 ₂₁ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB108 and enable signals EN108 supplied from log-sum operation cell circuit 325 _9, and, log-sum operation cell circuit By using the data AGB109 and the enable signal EN109 supplied from the 325 ₁₀ to perform an operation analogous to the second round in the winning game, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
_21, the computed data AGL as data AGB204, supplies to the log-sum operation cell circuit 325 ₂₇ to perform the operation to be likened to the third round of the tournament, the enable signal EN204 to log-sum operation cell circuit 325 ₂₇ Supply.

The log-sum operation circuit 325 ₂₂ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB 110 and the enable signal EN 110 supplied from the log-sum operation cell circuit 325 ₁₁ and the log-sum operation cell circuit By using the data AGB111 and the enable signal EN111 supplied from the 325 ₁₂ to perform an operation analogous to the second round in the winning game, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₂₂ supplies the computed data AGL as data AGB205, supplies to the log-sum operation cell circuit 325 _27, the enable signal EN205 to log-sum operation cell circuit 325 _27.

[0524] The log-sum operation circuit 325 ₂₃ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB 112 and the enable signal EN 112 supplied from the log-sum operation cell circuit 325 ₁₃ and the log-sum operation cell circuit By using the data AGB 113 and the enable signal EN 113 supplied from 325 ₁₄ to perform an operation analogous to the second round in the winning game, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
_23, the computed data AGL as data AGB206, supplies to the log-sum operation cell circuit 325 ₂₈ to perform an operation to be likened to the third round of the tournament, the enable signal EN206 to log-sum operation cell circuit 325 ₂₈ Supply.

[0525] The log-sum operation circuit 325 ₂₄ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB114 and the enable signal EN114 supplied from the log-sum operation cell circuit 325 ₁₅ and the log-sum operation cell circuit By using the data AGB 115 and the enable signal EN 115 supplied from 325 ₁₆ to perform an operation analogous to the second round in the winning game, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₂₄ supplies the computed data AGL as data AGB207, supplies to the log-sum operation cell circuit 325 _28, the enable signal EN207 to log-sum operation cell circuit 325 _28.

The log-sum operation circuit 325 ₂₅ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB200 and enable signals EN200 supplied from log-sum operation cell circuit 325 _17, and, log-sum operation cell circuit 325 ₁₈ using data AGB201 and enable signals EN201 supplied from, by performing an operation to be likened to the third round of the tournament, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
_25, the computed data AGL as data AGB300, supplies to the log-sum operation cell circuit 325 ₂₉ to perform the operation to be likened to the fourth round of the tournament, the enable signal EN300 to log-sum operation cell circuit 325 ₂₉ Supply.

[0527] log-sum operation circuit 325 _26, lo
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB 202 and the enable signal EN 202 supplied from the log-sum operation cell circuit 325 ₁₉ and the log-sum operation cell circuit By using the data AGB 203 and the enable signal EN 203 supplied from the 325 ₂₀ to perform an operation analogous to the third match in the winning match,
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₂₆ supplies the computed data AGL as data AGB301, supplies to the log-sum operation cell circuit 325 _29, the enable signal EN301 to log-sum operation cell circuit 325 _29.

The log-sum operation circuit 325 ₂₇ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB 204 and the enable signal EN 204 supplied from the log-sum operation cell circuit 325 ₂₁ and the log-sum operation cell circuit By using the data AGB 205 and the enable signal EN205 supplied from the 325 ₂₂ to perform an operation analogous to the third match in the winning match,
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
_27, the computed data AGL as data AGB302, supplies to the log-sum operation cell circuit 325 ₃₀ to perform the operation to be likened to the fourth round of the tournament, the enable signal EN302 to log-sum operation cell circuit 325 ₃₀ Supply.

The log-sum operation circuit 325 ₂₈ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB206 and enable signals EN206 supplied from log-sum operation cell circuit 325 _23, and, log-sum operation cell circuit By using the data AGB 207 and the enable signal EN 207 supplied from 325 ₂₄ to perform an operation analogous to the third match in the winning match,
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₂₈ supplies the computed data AGL as data AGB303, supplies to the log-sum operation cell circuit 325 _30, the enable signal EN303 to log-sum operation cell circuit 325 _30.

The log-sum operation circuit 325 ₂₉ outputs
Since the configuration is the same as that of the g-sum operation circuit 325 ₁ , the detailed description is omitted, but the data AGB300 and the enable signal EN300 supplied from the log-sum operation cell circuit 325 ₂₅ and the log-sum operation cell circuit 325 ₂₆ using data AGB301 and enable signals EN301 supplied from, by performing an operation to be likened to the fourth round of the tournament, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₂₉ is a log-sum operation cell circuit 325 that performs an operation analogous to the fifth round in the winning match, here the final match, using the calculated data AGL as data AGB400.
₃₁ and the enable signal EN400
It is supplied to the og-sum operation cell circuit 325 ₃₁ .

The log-sum operation circuit 325 ₃₀ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB302 and enable signals EN302 supplied from log-sum operation cell circuit 325 _27, and, log-sum operation cell circuit 325 ₂₈ using data AGB303 and enable signals EN303 supplied from, by performing an operation to be likened to the fourth round of the tournament, l
One log- in the cumulative addition operation of the og-sum operation
Perform a sum operation. log-sum operation circuit 325
₃₀ supplies the computed data AGL as data AGB401, supplies to the log-sum operation cell circuit 325 _31, the enable signal EN401 to log-sum operation cell circuit 325 _31.

The log-sum operation circuit 325 ₃₁ outputs
Since the same configuration as the g-sum operation circuit 325 _1, although a detailed description is omitted, the data AGB400 and enable signals EN400 supplied from log-sum operation cell circuit 325 _29, and, log-sum operation cell circuit By using the data AGB 401 and the enable signal EN 401 supplied from the 325 ₃₀ to perform an operation analogous to the final game in the winning game, lo
One log-s in the cumulative addition operation of the g-sum operation
Perform um operation. The log-sum operation circuit 325 ₃₁
The calculated enable signal EN500 is not output, but the calculated data AGL is output as data AGB500. Note that the data AGB500 is the data L0
It is supplied to the Iλ calculation circuit 313 as 0.

The log-sum operation circuit 312 as described above
₁ uses the data AGB and the enable signal ENS0 to perform an operation analogous to a winning game based on an enable signal corresponding to each branch on the trellis,
For example, log-s where the input of the branch on the trellis is “0”
The data L00 is calculated by performing a cumulative addition operation of the um operation.

[0534] log-sum operation circuit 312 _2, lo
Since the same configuration as the g-sum operation circuit 312 _1, it is omitted a detailed description, with reference to the data AGB and enable signal ENS1, log-sum operation circuit 3
Like the 12 _1, by performing the operation to be likened to the tournament based on an enable signal corresponding to each branch of the trellis, for instance cumulative addition of log-sum operation input branch in the trellis is "1" Calculate and calculate data L
01 is calculated. log-sum operation circuit 312 _2,
The calculated data L01 is supplied to the Iλ calculation circuit 313.

Also, the log-sum operation circuit 312
₃ also, for the same configuration as the log-sum operation circuit 312 _1, is omitted a detailed description, with reference to the data AGB and enable signal ENS2, similarly to the log-sum operation circuit 312 _1, the trellis By performing an operation analogous to a winning match based on an enable signal corresponding to each branch of the above, for example, a cumulative addition operation of a log-sum operation in which an input of a branch on the trellis is “0” is performed, and data L10 is calculated. I do. log-sum operation circuit 312 _3, Airamuda calculation circuit 31 and the calculated data L10
Supply 3

[0536] In addition, log-sum operation circuit 312 ₄
Also, since the same configuration as the log-sum operation circuit 312 _1, it is omitted a detailed description, with reference to the data AGB and enable signal ENS3, similarly to the log-sum operation circuit 312 _1, in the trellis By performing an operation analogous to a winning match based on an enable signal corresponding to each branch, for example, a cumulative addition operation of a log-sum operation in which an input of a branch on the trellis is “1” is performed, and data L11 is calculated. . log-sum operation circuit 312 _4, Airamuda calculation circuit 31 data L11 calculated
Supply 3

Further, the log-sum operation circuit 31
2 ₅ also, for the same configuration as the log-sum operation circuit 312 _1, is omitted a detailed description, with reference to the data AGB and enable signal ENS20, log-sum
Like the arithmetic circuits 312 _1, by performing the operation to be likened to the tournament based on an enable signal corresponding to each branch of the trellis, for example, an input branch on the trellis is log-sum operation is "0" A cumulative addition operation is performed to calculate data L20. log-sum operation circuit 312 _5, Airamuda calculation circuit 31 and the calculated data L20
Supply 3

The log-sum operation circuit 312
₆ also, for the same configuration as the log-sum operation circuit 312 _1, is omitted a detailed description, with reference to the data AGB and enable signal ENS21, similarly to the log-sum operation circuit 312 _1, the trellis By performing an operation analogous to a winning match based on an enable signal corresponding to each branch of the above, for example, a cumulative addition operation of a log-sum operation in which an input of a branch on the trellis is “1” is performed, and data L21 is calculated. I do. log-sum operation circuit 312 _6, Airamuda calculation circuit 31 calculates the data L21
Supply 3

[0539] The Iλ calculating circuit 313 includes three differentiators 32.
With 4 _1, 324 _2, 324 _3.

[0540] The differentiator 324 _1, the data L00 supplied from log-sum operation circuit 312 _1, log-s
um taking the difference between the data L01 supplied from the arithmetic circuit 312 _2. Data L calculated by the differentiator 324 ₁
M0 is subjected to, for example, 2's complement notation conversion.

[0541] The differentiator 324 _2, the data L10 supplied from log-sum operation circuit 312 _3, log-s
um taking the difference between the data L11 supplied from the arithmetic circuit 312 _4. Data L calculated by the differentiator 324 ₂
M1 is subjected to, for example, two's complement notation conversion.

[0542] differentiator 324 _3, a data L20 supplied from log-sum operation circuit 312 _4, log-s
um taking the difference between the data L21 supplied from the arithmetic circuit 312 _6. Data L calculated by differentiator 324 ₃
M2 is subjected to, for example, two's complement notation conversion.

The Iλ calculation circuit 313 performs log
-Sum operation circuit 312 _1, 312 _2, 312 _3, 312 ₄
L00, L0 supplied from each of the so-called straight binary notations.
1, L10, and L11 are bundled and output as a logarithmic soft output SLM calculated in symbol units. Also, the Iλ calculation circuit 3
Reference numeral 13 denotes data LM0, L2 expressed as two's complement notation calculated by each of the differentiators 324 ₁ , 324 ₂ , and 324 _3.
M1 and LM2 are bundled and output as a logarithmic soft output BLM calculated in bit units.

The soft output calculation circuit 1 configured as described above
61 realizes a cumulative addition operation of a log-sum operation according to an input of each branch on the trellis by performing an operation analogous to a winning game using an enable signal, and performs logarithmic soft output in a symbol unit or a bit unit. Iλ can be calculated and output as log soft outputs SLM and BLM, respectively. These log soft outputs SLM and BLM are supplied to an external information calculation circuit 163, an amplitude adjustment and clip circuit 16
4 and the hard decision circuit 165.

The received value or prior probability information separating circuit 162
Is output from the reception data and delay storage circuit 155 and is delayed from the delayed reception data DAD subjected to a predetermined delay.
The received value or the prior probability information is separated and extracted. The reception value or prior probability information separation circuit 162 includes the reception value format information CRTY supplied from the control circuit 60 and the input bit number information I supplied from the code information generation circuit 151.
N, the input delayed reception data DAD is separated.

[0546] Specifically, the reception value or prior probability information separation circuit 162 can be realized as having four selectors 341, 342, 343, and 344, for example, as shown in FIG.

[0547] The selector 341 has the input bit number information IN
, One of the delayed reception data DAD3 and DAD4 of the delay reception data DAD is selected. Specifically, when the number of input bits to the element encoder is “1”, the selector 341 selects the delayed reception data DAD4. The selector 341 outputs the selected data as delayed reception data DAS.

The selector 342 receives the reception value format information CRT
Based on Y, one of the delay reception data DAD0 of the delay reception data DAD and the delay reception data DAS supplied from the selector 341 is selected.
Specifically, the selector 342 sets the reception value format information CRT
When Y indicates external information, the delay reception data DAD0 is selected. Selector 342 outputs the selected data as delayed received data PD0.

The selector 343 receives the reception value format information CRT.
Based on Y, one of the delay reception data DAD1 and DAD4 of the delay reception data DAD is selected. Specifically, when the received value format information CRTY indicates external information, the selector 343 selects the delayed received data DAD1. Selector 343 outputs the selected data as delayed reception data PD1.

The selector 344 receives the reception value format information CRT
Based on Y, one of the delay reception data DAD2 and DAD5 of the delay reception data DAD is selected. Specifically, when the received value format information CRTY indicates external information, the selector 344 selects the delayed received data DAD2. Selector 344 outputs the selected data as delayed reception data PD2.

The received value or prior probability information separating circuit 162 outputs the delayed received data DAD0, DAD1, DAD2, and DAD3 of the input delayed received data DAD.
Bundled into a so-called offset binary
y) Output as a delayed reception value DRC expressed as a notation, delay output data DAS, DAD4, and DAD5 are bundled and output as delay advance probability information DAP;
The delay reception data PD0, PD1, and PD2 are bundled and output as delay external information DEX. The delayed reception value DRC is supplied to the external information calculation circuit 163 and the hard decision circuit 165, and the delay prior probability information DAP is supplied to the external information calculation circuit 16
Is supplied to the 3, delay extrinsic information DEX is directly supplied to the selector 120 ₂ as delayed extrinsic information sdex.

The external information calculation circuit 163 includes a logarithmic soft output SLM or log soft output BLM supplied from the soft output calculation circuit 161 and a delayed reception value DRC or delay advance supplied from the reception value or prior probability information separation circuit 162. Probability information D
The external information OE is calculated using the AP.

Specifically, the external information calculation circuit 163
For example, as shown in FIG. 44, an information bit external information calculation circuit 350 for calculating external information for information bits, an information symbol external information calculation circuit 351 for calculating external information for information symbols, and a code for calculating external information for codes External information calculation circuit 352 and two selectors 3
53, 354.

The information bit external information calculation circuit 350 includes, for example, three external information calculation cell circuits 355 ₁ , 355 ₂ , and 3
With a 55 _3. These external information calculation cell circuits 35
5 _1, 355 _2, 355 _3, respectively, substantially consists differentiator (not shown) taking the difference between the logarithmic soft-output BLM and delayed a priori probability information DAP.

[0555] The external information calculation cell circuit 355 ₁ calculates the difference between the log soft output BLM0 of the log soft output BLM and the delayed prior probability information DAP0 of the delayed prior probability information DAP. After performing amplitude adjustment and clipping, and further performing offset binary notation conversion and the like, the information is output as external information EX0.

The external information calculation cell circuit 355 ₂ calculates the difference between the log soft output BLM1 of the log soft output BLM and the delay prior probability information DAP1 of the delay prior probability information DAP, and calculates the difference value. After performing amplitude adjustment and clipping, and further performing offset binary notation conversion and the like, the information is output as external information EX1.

The external information calculation cell circuit 355 ₃ calculates the difference between the log soft output BLM2 of the log soft output BLM and the delay prior probability information DAP2 of the delay prior probability information DAP. After performing amplitude adjustment and clipping, and further performing offset binary notation conversion and the like, the information is output as external information EX2.

The information bit external information calculation circuit 3
50 is, for example, three systems of external information EX0, EX1, EX
2 in bit units, and these external information EX0, E
X1 and EX2 are bundled as external information EXB and the selector 3
53.

The information symbol external information calculation circuit 351 is
For example, four external information calculation cell circuits 356 ₁ , 356 ₂ ,
It has 356 ₃ , 356 ₄ and a normalization circuit 357. Of these parts, the external information calculation cell circuits 356 ₁ , 3 6
56 ₂ , 356 ₃ , and 356 ₄ , as in the case of the external information calculation cell circuits 355 ₁ , 355 ₂ , and 355 ₃ , respectively, substantially take the difference between the log soft output SLM and the delayed prior probability information DAP. It consists of a differentiator.

The external information calculation cell circuit 356 ₁ calculates the logarithmic soft output SLM0 of the logarithmic soft output SLM and a predetermined value M
Is calculated, and the difference value is subjected to amplitude adjustment and clipping.
It is supplied to the normalization circuit 357 as D0.

The external information calculation cell circuit 356 ₂ calculates the difference between the log soft output SLM1 of the log soft output SLM and the delay prior probability information DAP0 of the delay prior probability information DAP. After performing amplitude adjustment and clipping, the normalization circuit 3
57.

The external information calculation cell circuit 356 ₃ calculates the difference between the log soft output SLM2 of the log soft output SLM and the delay prior probability information DAP1 of the delay prior probability information DAP. After performing amplitude adjustment and clipping, the normalizing circuit 3
57.

The external information calculation cell circuit 356 ₄ calculates the difference between the log soft output SLM3 of the log soft output SLM and the delay advance probability information DAP2 of the delay advance probability information DAP, and calculates the difference value. After performing amplitude adjustment and clipping, the normalization circuit 3
57.

[0564] The normalization circuit 357 includes external information calculation cell circuits 356 ₁ , 356 ₂ , 356 ₃ , and 35 as described later.
External information calculated by 6 ₄ ED0, ED1, ED
2. Normalization is performed to correct the bias of the distribution of ED3 and reduce the amount of information. Specifically, the normalization circuit 357
Are the external information calculation cell circuits 356 ₁ , 356 ₂ , 35
External information ED0, ED calculated by 6 ₃ , 356 ₄
After adding a predetermined value to each of the external information ED0, ED1, ED2, and ED3 so that the one having the maximum value among 1, 1, ED2, and ED3 is adjusted to a predetermined value such as "0", Clipping is performed according to the required dynamic range, and further, normalization is performed so that the value of the external information for one certain symbol is different from the values of the external information for all other symbols. The normalization circuit 357 converts the normalized external information into the external information EX0,
Output as EX1 and EX2.

[0565] Such an information symbol external information calculation circuit 351 includes, for example, three systems of external information EX0, EX1, and E.
X2 is calculated for each symbol, and these external information EX is calculated.
0, EX1 and EX2 are bundled and supplied to the selector 353 as external information EXS.

[0566] The code external information calculation circuit 352 includes, for example, 3
External information calculation cell circuits 358 ₁ , 358 ₂ , 358 ₃
Having. These external information calculation cell circuits 358 ₁ , 3
58 ₂ and 358 ₃ are external information calculation cell circuits 3 respectively.
Like 55 ₁ , 355 ₂ , and 355 ₃ , it is substantially composed of a differentiator (not shown) that calculates the difference between the logarithmic soft output BLM and the delayed reception value DRC.

The external information calculation cell circuit 358 ₁ calculates the difference between the log soft output BLM0 of the log soft output BLM and the delayed received value APS0 of the delayed received value DRC,
After performing amplitude adjustment and clipping on this difference value and further performing offset binary notation conversion and the like,
Output as external information EX0.

The external information calculation cell circuit 358 ₂ calculates the difference between the log soft output BLM1 of the log soft output BLM and the delayed received value APS1 of the delayed received value DRC.
After performing amplitude adjustment and clipping on this difference value and further performing offset binary notation conversion and the like,
Output as external information EX1.

The external information calculation cell circuit 358 ₃ calculates the difference between the log soft output BLM2 of the log soft output BLM and the delayed received value APS2 of the delayed received value DRC,
The difference value is subjected to amplitude adjustment and clipping, subjected to offset binary notation conversion and the like, and then output as external information EX2.

[0570] Such a code external information calculation circuit 352
Calculates, for example, three systems of external information EX0, EX1, and EX2, bundles these pieces of external information EX0, EX1, and EX2, and supplies them to the selector 354 as external information EXC.

[0571] The selector 353 is based on the prior probability information format information CAPP, and the information bit external information calculation circuit 35
One of the external information EXB supplied from 0 and the external information EXS supplied from the information symbol external information calculation circuit 351 is selected. Specifically, when the prior probability information format information CAPP indicates that the information is in symbol units, the selector 353 outputs the external information EAPP.
Select XS. The selector 353 supplies the selected external information ES to the selector 354.

The selector 354 selects one of the external information ES supplied from the selector 353 and the external information EXC supplied from the code external information calculation circuit 352, based on the output data selection control signal CITM. I do. Specifically, the selector 354 selects the external information EXC when the output data selection control signal CITM indicates that information on the code is to be output. The selector 354 outputs the external information OE obtained by the selection to the outside.

The external information calculation circuit 163 uses the input logarithmic soft output SLM or logarithmic soft output BLM and the delay reception value DCR or the delay prior probability information DAP,
Calculating extrinsic information OE, the external information OE, as it is to the selector 120 ₁ as the external information SOE.

[0574] Although not shown, the amplitude adjustment and clipping circuit 164 adjusts the amplitude of the logarithmic soft output SLM in symbol units and clips to a predetermined dynamic range, and adjusts the amplitude of the logarithmic soft output BLM in bit units. And a circuit for clipping to a predetermined dynamic range. At this time, based on the output data selection control signal CITM supplied from the outside and the prior probability information format information CAPP supplied from the control circuit 60, the amplitude adjustment and clipping circuit 164 performs logarithmic soft output SLM, B
The amplitude of each LM is adjusted, and one of the data clipped to a predetermined dynamic range is output as a logarithmic soft output OL after the amplitude adjustment. The logarithmic soft-output OL is directly supplied to the selector 120 ₁ as soft-output SOL.

The hard decision circuit 165 makes a hard decision on the logarithmic soft outputs SLM and BLM, which are decoded values, and makes a hard decision on the delayed received value DRC. At this time, the hard decision circuit 165
Output data selection control signal CITM supplied from outside
And received value format information CRT supplied from the control circuit 60
Based on Y, the prior probability information format information CAPP and the signal point arrangement information CSIG, the log soft outputs SLM and BLM and the delayed reception value DRC are hard-decided. Here, in the case where the coding apparatus 1 performs coding by TTCM or SCTCM, the coding apparatus 1 performs modulation by the 8PSK modulation method, and the signal point arrangement information CS
IG includes eight sets of signal point arrangement information CSIG0 and CSIG.
1, CSIG2, CSIG3, CSIG4, CSIG
5, CSIG6 and CSIG7.

Specifically, as shown in FIG. 45, for example, the hard decision circuit 165 includes an inverter 360 and a minimum symbol calculation circuit 361 for calculating a symbol having the minimum value.
And a selection control signal generation circuit 36 for generating a control signal for controlling a selection operation by a selector 369 described later.
8, the selectors 369 and 371, and the encoding device 1
An I / Q demapping circuit 370 that performs I / Q value demapping in the case where coding by CM or SCTCM is performed can be realized.

The inverter 360 is connected to the soft output calculation circuit 16
Logarithmic soft output BL supplied from 1 and represented in 2's complement notation
A predetermined bit group of M is inverted and output as decoded bit hard decision information BHD.

The minimum symbol calculation circuit 361 is, for example,
It can be realized as having three comparison circuits 362, 364, 366 and three selectors 363, 365, 367.

The comparison circuit 362 includes a soft output calculation circuit 161
And the log soft outputs SLM0 and SLM1 are compared among the log soft outputs SLM supplied as a straight binary notation. The comparison circuit 362 supplies a control signal SL0 indicating the obtained magnitude relationship to the selector 367 and also supplies the selector 363 as a control signal for selection.

The selector 363 determines the logarithmic soft output SLM based on the control signal SL0 supplied from the comparison circuit 362.
0, SLM1 with the smaller value is selected. The selector 363 supplies the selected data SSL0 to the comparison circuit 366.

The comparison circuit 364 includes a soft output calculation circuit 161
Soft output S of the log soft output SLM supplied from
The magnitude relationship between LM2 and SLM3 is compared. Comparison circuit 36
4 supplies the selector 367 with a control signal SL1 indicating the obtained magnitude relationship, and also supplies the selector 365 as a control signal for selection.

The selector 365 is based on the control signal SL1 supplied from the comparison circuit 364, and has a logarithmic soft output SLM.
2, SLM3 is selected with a smaller value. The selector 365 supplies the selected data SSL1 to the comparison circuit 366.

[0583] The comparing circuit 366 compares the magnitude relationship between the data SSL0 supplied from the selector 363 and the data SSL1 supplied from the selector 365. The comparison circuit 366 supplies the control signal SEL1 indicating the obtained magnitude relationship to the selector 367 as a control signal for selection.

[0583] The selector 367 determines whether the comparator 362 is in accordance with the control signal SEL1 supplied from the comparator 366.
, And one of the control signal SL1 supplied from the comparison circuit 364. Specifically, the selector 367 outputs the data SSL
When the value of 0 is larger than the value of the data SSL1, the control signal SL1 is selected. Selector 367 outputs the data obtained by selection as control signal SEL0.

The minimum symbol calculation circuit 361 as described above
Calculates the one having the smallest value among the logarithmic soft outputs SLM in symbol units, and generates the decoded symbol hard decision information SHD obtained by bundling the control signals SEL0 and SEL1 as the selector 3.
Supply to 69.

The selection control signal generation circuit 368 outputs the output data selection control signal CITM supplied from the outside and the prior probability information format information CAPP supplied from the control circuit 60.
, The control signal AIS for controlling the selection operation by the selector 369 is generated.

The selector 369 outputs the decoded bit hard decision information B supplied from the inverter 360 based on the control signal AIS supplied from the selection control signal generation circuit 368.
One of the HD and the decoded symbol hard decision information SHD supplied from the minimum symbol calculation circuit 361 is selected. Specifically, the selector 369 controls the control signal A
The output data selection control signal CITM indicates that the IS outputs information for the information symbol or the information bit, and the prior probability information format information CA indicates that the IS is for each symbol.
If the PP indicates, the decoded symbol hard decision information SHD is selected. The selector 369 outputs the selected data as decoded value hard decision information DHD1.

[0588] The hard decision circuit 165 obtains decoded bit hard decision information BHD and decoded symbol hard decision information SHD from these units, and converts the decoded value hard decision information DHD1 selected by the selector 369 into the decoded value hard decision information. DHD
Output as The decoded value hard decision information DHD is output to the outside as decoded value hard decision information SDH.

The hard decision circuit 165 determines the decoded bit hard decision information BHD by using the inverter 360
Is used because of the notation of data. That is, the decoded bit hard decision information BHD is
As described above, the logarithmic soft output BL expressed in two's complement notation
M is required. Therefore, the hard decision circuit 165 outputs the logarithmic soft output B
By making a determination using a predetermined bit group, specifically, an inverted bit obtained by inverting the most significant bit of the LM, the logarithmic soft output BLM calculated in bit units can be hard-determined.

In the hard decision circuit 165, the I / Q
The demapping circuit 370 includes, for example, a look-up table 372 that stores a demapping table, and seven selectors 373, 374, 375, 376, 377, and 3
79, 380 and a selection control signal generation circuit 378 that generates a control signal for controlling the selection operation by the selectors 379, 380.

The lookup table 372 stores a table for demapping received values. Specifically, the lookup table 372 stores the I / Q
The boundary values for the I axis in the plane are stored as a table. The look-up table 372 stores a boundary corresponding to a combination of the value of the delayed received value IR corresponding to the in-phase component and the value of the delayed received value QR corresponding to the quadrature component among the delayed received values DRC expressed in offset binary notation. The values are read from the table and, for example, four-system boundary value data BD
The signals are supplied to the selection control signal generation circuit 378 as R0, BDR1, BDR2, and BDR3.

[0592] The selector 373 selects one of the signal point arrangement information CSIG2 and CSIG6 based on the delayed reception value QR.
Select one of them. Specifically, the selector 373
Selects the signal point arrangement information CSIG2 when the delayed reception value QR indicates a positive value. Selector 3
73 supplies the selected data to the selector 380 as signal point arrangement information SSSS0.

[0593] Based on the delayed reception value QR, the selector 374 selects one of the signal point arrangement information CSIG3 and CSIG5.
Select one of them. Specifically, the selector 374
Selects the signal point arrangement information CSIG3 when the delayed reception value QR indicates a positive value. Selector 3
74 supplies the selected data to the selector 376 as signal point arrangement information SS0.

[0594] The selector 375 determines the signal point arrangement information CSIG1 or CSIG7 based on the delayed reception value QR.
Select one of them. Specifically, the selector 375
Selects the signal point arrangement information CSIG1 when the delayed reception value QR indicates a positive value. Selector 3
75 supplies the selected data to the selector 376 as signal point arrangement information SS1.

[0595] The selector 376 determines the signal point arrangement information S supplied from the selector 374 based on the delayed reception value IR.
Either S0 or the signal point arrangement information SS1 supplied from the selector 375 is selected. Specifically, when the delayed reception value IR indicates a positive value, the selector 376 selects the signal point arrangement information SS1. The selector 376 supplies the selected data to the selector 379 as signal point arrangement information SSS0.

The selector 377 determines, based on the delayed reception value IR, data having a predetermined value M and signal point arrangement information C
One of SIG4 is selected. Specifically, when the delayed reception value IR indicates a positive value, the selector 377 selects data having a predetermined value M. The selector 377 supplies the selected data to the selector 379 as signal point arrangement information SSS1.

The selection control signal generation circuit 378 calculates the delay reception value QR and the boundary value data BDR0, BDR1, BDR2, BDR supplied from the look-up table 372.
3 to generate a control signal SEL5 for controlling the selection operation by the selector 379, and a control signal S for controlling the selection operation by the selector 380.
Generate EL6.

The selector 379 operates based on the control signal SEL5 supplied from the selection control signal generation circuit 378.
One of the signal point arrangement information SSS0 and SSS1 is selected. The selector 379 supplies the selected data to the selector 380 as the signal point arrangement information SSSS1.

The selector 380 operates based on the control signal SEL6 supplied from the selection control signal generation circuit 378.
One of the signal point arrangement information SSSS0 and SSSS1 is selected. The selector 380 supplies the selected data to the selector 371 as the received value hard decision information IRH.

[0600] Such an I / Q demapping circuit 370 includes:
The received value hard decision information IRH is obtained when the encoding device 1 performs encoding by TTCM or SCTCM.

[0601] Further, in the hard decision circuit 165, the selector 371 is composed of a predetermined bit group of the delayed received value DCR, the received value hard decision information BRH indicating the hard decision result in the offset binary notation, and the I / Q demapping information. Circuit 37
One of the received value hard decision information IRH supplied from 0 is selected. Specifically, the selector 371
If the received value format information CRTY indicates that the encoding apparatus 1 performs encoding by TTCM or SCTCM, the received value hard decision information IRH is selected. The selector 371 outputs the selected data as the received value hard decision information RHD. This received value hard decision information R
HD is output to the outside as received value hard decision information SRH.

The hard decision circuit 165 does not perform the bit inversion processing to obtain the received value hard decision information BRH as in the case of obtaining the decoded bit hard decision information BHD described above. It is caused by That is, as described above, the received value hard decision information BRH includes the delayed received value D expressed in offset binary notation.
It is required on the premise of RC. Therefore, the hard decision circuit 165 can make a hard decision on the delayed received value DRC by making a decision using a predetermined bit group, specifically, the most significant bit, of the delayed received value DRC.

The hard decision circuit 165 makes a hard decision on the logarithmic soft outputs SLM and BLM as decoded values to obtain decoded value hard decision information SDH, and makes a hard decision on the delayed received value DRC to make the received value hard decision. Find information SRH. These decoded value hard decision information SDH and received value hard decision information SRH are
These are output to the outside as decoded value hard decision information DHD and received value hard decision information RHD, respectively, and are monitored as necessary.

The soft output decoding circuit 90 described above receives the soft input decoded received value TSR,
6 and the Iγ distribution circuit 157, every time a received value is received, the log likelihood Iγ is calculated. After the Iα calculation circuit 158 calculates the log likelihood Iα, when all the received values are received, the Iβ calculation circuit 159, the log likelihood Iβ is calculated for each state at all times. The element decoder 50 calculates the log soft output Iλ at each time using the log likelihoods Iα, Iβ, and Iγ calculated by the soft output calculation circuit 161 and outputs the log soft output Iλ to the outside. Alternatively, the information is supplied to the external information calculation circuit 163. Further, the element decoder 50 calculates the external information at each time by the external information calculation circuit 163. As described above, the element decoder 50 outputs the decoded reception value T
Using the SR and the external information or the interleaved data TEXT, soft output decoding to which the Log-BCJR algorithm is applied can be performed. In particular, the soft output decoding circuit 90
Can perform soft-output decoding on an arbitrary code regardless of the code configuration of the elementary encoder in PCCC, SCCC, TTCM, or SCTCM.

[0605] Various features relating to the soft output decoding circuit 90 will be further described in "5."

2-3 Details of Interleaver Next, the interleaver 100 will be described in detail. Prior to a description of a specific configuration, a basic design concept of the interleaver 100 will be described.

[0606] The interleaver 100 can perform an interleave process and a deinterleave process as described later, and can also delay an input received value. Therefore, it is assumed that interleaver 100 includes a RAM for delaying an input received value and a RAM for interleaving input data.
Note that these RAMs are actually used as described later.
They are shared and are used by being switched according to the mode indicating the code configuration including the type of interleaving to be performed.

As shown in FIG. 46, for example, the delay RAM is configured to appear as a dual-port RAM composed of banks A and B to a control circuit of the interleaver 100, which will be described later. Here, it is assumed that the control circuit cannot simultaneously access the even-numbered address or the odd-numbered address by the write address used for writing data to the RAM and the read address used for reading data. In the interleaver 100, when an even-length delay is performed using the delay RAM, for example, 0, 1, 2, 3,
4, ..., DL-2, DL-1,0,1,2, ...
Based on the write address, data is stored at each address in the RAM. Then, in the interleaver 100, for example, 1, 2, 3, 4, 5,
, DL-1, 0, 1, 2, 3,..., Data is read from each address in the RAM. Also, interleaver 10
0 is realized by holding an output delayed by an even number length in a register or the like when delaying by an odd number length. In practice, the delay RAM is, for example, as shown in FIG.
Each of the banks A and B includes a plurality of RAMs for upper addresses and lower addresses. Therefore, in the interleaver 100, for example, as shown in FIG. 48, it is necessary to appropriately convert the address generated by the control circuit and give it to each RAM. In FIG. 47,
The reason for inverting the most significant bit of the address is to simplify the designation of the address when inputting / outputting a plurality of symbols, as described later.

On the other hand, as shown in FIG. 49, for example, as shown in FIG.
It is configured to look like two RAMs. The interleaver 100 can switch between the interleave processing and the deinterleave processing as described above. Therefore, in the interleaver 100, when performing the interleave processing, usually, for example, 0, 1,
Count up like 2, 3, ..., or
.., 3, 2, 1, 0, the data is stored at each address in the RAM as the write bank A based on the sequential write address generated by counting down. Then, in the interleaver 100, data is read from each address in the RAM as the read bank B based on the random read address. On the other hand, in the interleaver 100, when the deinterleave processing is performed, the data is stored in each address in the RAM as the write bank A based on the random write address, contrary to the interleave processing. , R as a read bank B based on a sequential read address.
Data is read from each address in the AM. In the interleaver 100, for example, as shown in FIG. 50, based on a sequential write address and a random read address, the address is converted into an address to be used for each of the banks A and B, and given to each RAM.

Next, the input / output to / from the address storage circuit 110 as viewed from the interleaver 100 will be described.

The address storage circuit 110 basically has
On the basis of the sequential address data IAA supplied from the interleaver 100, for example, read address data A which is three-system random address data
DA0, ADA1, and ADA2 are output. In this way, the interleaver 100 is supplied with the read address data ADA of a plurality of systems from the address storage circuit 110, so that the interleaver 10
A value of 0 can perform a plurality of types of interleaving on data of up to three symbols.

For example, the interleaver 100 operates as shown in FIG.
As shown in (A), when random interleaving is performed on input data of one symbol, the read address data ADA0, ADA1, and ADA2 of the three systems from the address storage circuit 110 are read address data. Interleaving is performed using ADA0. In the following description, random interleaving is referred to as random interleaving.

[0613] When random interleaving is performed on the input data of two symbols, as shown in FIG. 6B, the interleaver 100 reads the three sets of address data from the address storage circuit 110. Interleaving is performed using read address data ADA0 and ADA1 among ADA0, ADA1 and ADA2.

Further, as shown in FIG. (C), when interleaving is performed on input data of two symbols individually based on mutually different addresses, the interleaver 100 stores the address storage circuit 110. Read address data ADA0, ADA from
1, ADA2, read address data ADA
0, interleaving is performed using ADA1. In addition,
In the following description, such interleaving is referred to as inline interleaving.

Further, the interleaver 100 holds the combination of each bit with respect to the input data of two symbols, that is, the same address for each symbol as shown in FIG. In the case of performing interleaving based on
Read address data ADA0, AD
A1, ADA2, read address data ADA
0, interleaving is performed using ADA1. In addition,
In the following description, such interleaving will be referred to as pair wise interleaving.

[0616] When random interleaving is performed on the input data of three symbols as shown in Fig. 47 (E), the interleaver 100 reads the three sets of address data from the address storage circuit 110. Interleaving is performed using all of ADA0, ADA1, and ADA2.

[0617] Further, as shown in Fig. 47 (F), when performing inline interleaving on input data of three symbols, the interleaver 100 reads out three systems of address data from the address storage circuit 110. Interleaving is performed using all of ADA0, ADA1, and ADA2.

[0618] Furthermore, as shown in Fig. 47 (G), when performing pairwise interleaving on input data of three symbols, the interleaver 100 reads three systems of read addresses from the address storage circuit 110. Interleaving is performed using all of the data ADA0, ADA1, and ADA2.

[0619] As described above, the interleaver 100 can perform a plurality of types of interleaving using a plurality of systems of read address data ADA provided from the address storage circuit 110. Note that the plurality of types of interleaving includes, of course, a plurality of types of deinterleaving that performs the reverse of the interleaving. The interleaver 100 has a plurality of RAMs, and implements a plurality of types of interleaving by appropriately selecting and switching a RAM to be used according to the type of interleaving.

The specific use of the plurality of RAMs will be described later.

The interleaver 100 capable of performing such interleaving or deinterleaving is configured as shown in FIG. 52, for example. The interleaver 100 includes a control circuit 400 for performing various processes such as address generation, a delay address generation circuit 401 for generating a delay address, an odd length delay compensation circuit 402 for compensating for an odd length delay, and input address data. Address conversion circuit 403 for converting the address data into interleave address data, a delay address conversion circuit 404 for converting the input address data into delay address data, and a storage circuit 407 ₁ , described later.
407 _2, ..., an address selection circuit 405 for selecting the address data to be distributed to 407 _16, the storage circuit 407
_1, 407 _2, ..., select the input data selecting circuit 406 for selecting data to be distributed to 407 _16, for example, 16 pieces of the storage circuits 407 _1, 407 _2, ..., and 407 _16, the data to be output And an output data selection circuit 408 that performs the operation.

The control circuit 400 includes a storage circuit 40 described later.
7 _1, 407 _2, ..., be one that controls the writing and / or reading data to 407 _16, entering interleave start position signal TIS supplied from the selector 120 _5, when the interleaving or deinterleaving And a write address and a read address used for the operation are generated. At this time, the control circuit 400 outputs the interleaved mode signal CDIN supplied from the outside,
Interleave length information CI supplied from control circuit 60
A write address and a read address are generated based on the NL and the operation mode information CBF indicating that the data should be delayed by the interleave length. The control circuit 400 supplies the generated write address data IWA, which is sequential address data, to the interleave address conversion circuit 403. Further, the control circuit 400 supplies the generated sequential address data IAA to the address storage circuit 110 and also supplies the generated sequential address data IAA to the interleave address conversion circuit 403 as interleave long delay read address data IRA.

Further, as will be described later, the control circuit 400 outputs the end position information CNFT supplied from the control circuit 60.
, Termination period information CNFL, and termination state information CNF
When D, puncture cycle information CNEL, and puncture pattern information CNEP are input, interleaver non-output position information CNO and delay interleave start position signal CDS are generated based on interleave length information CINL, and termination time information is generated. It generates CGT, termination state information CGS, and erase position information CGE. The control circuit 400, after the lapse of the time corresponding to the interleave length, outputs the generated information as the interleaver non-output position information INO, the delay interleave start position signal IDS, the end time information IGT, and the end state information IGS, respectively. as an erasure position information IGE, to the selector 120 ₁₀ in synchronization with the beginning of the frame. The control circuit 400 also supplies the generated interleaver non-output position information CNO to the address selection circuit 405.

As will be described later, the write address data IWA, which is sequential address data generated by the control circuit 400, indicates that the interleave mode signal CDIN indicates that the interleaver 100 performs the interleave processing. If the the storage circuits 407 _1, 407 _2, ..., but the address data used for writing data to 407 _16, the interleave mode signal CDIN is, instructs the relevant interleaver 100 performs deinterleaving , The storage circuits 407 ₁ , 407 ₂ ,.
-, the address data is used for reading data from 407 _16. Similarly, the sequential address data IAA generated by the control circuit 400 corresponds to the interleaver mode
If 0 indicates that interleave processing is to be performed, the storage circuits 407 ₁ , 407 ₂ ,.
Although the intended for reading a random address data from the address storage circuit 110 used for reading data from 7 _16, interleave mode signal CDIN
Indicates that the interleaver 100 performs the deinterleave processing,
07 _1, 407 _2, ..., it becomes for reading random address data used for writing data to 407 ₁₆ from the address storage circuit 110.

The control circuit 400 counts up by a counter (not shown) when generating a write address and a read address.
Although sequential address data is generated, a write address counter and a read address counter are individually provided, as will be described later.

The delay address generation circuit 401 generates delay address data based on the interleave length information CINL supplied from the control circuit 60. The delay address generation circuit 401 includes delay write address data DWA, which is the generated write address data,
The delay read address data DRA that is the read address data is supplied to the delay address conversion circuit 404.

The odd length delay compensation circuit 402 is provided to compensate for odd length delay. That is, as described above, the interleaver 100 is configured using two banks of RAMs when performing the delay. As described later, the interleaver 100 switches between writing and reading of data for each time slot between the banks, so that the delay length, that is, the RAM of the number of words corresponding to half the time slot of the interleave length is used. Can be realized by using two banks. However, interleaver 100
In this case, the delay length is limited to an even length. Therefore, the odd-length delay compensation circuit 402 is provided to cope with the odd-length delay, and when performing even-length delay based on the interleave length information CINL supplied from the control circuit 60, In the case where only the delay by the RAM is performed on the TDI and the odd-length delay is performed, the delay of the data TDI by the delay length of −1 and the delay of the register by one time slot are performed. , The data TDI which is the data to be delayed is selected.

Specifically, the odd-length delay compensation circuit 402
Are data TDI0 and TDI of 6 systems
1, TDI2, TDI3, TDI4 and TDI5, for example, as shown in FIG. 53, six registers 410 ₁ , 410 ₂ , 410 ₃ , 410 ₄ , 410 ₅ ,
410 ₆ and six selectors 411 ₁ , 411 ₂ , 41
1 _3, 411 _4, 411 _5, 411 ₆ and can be implemented as having.

[0628] When data TDI0 is input, register 410 ₁ holds data TDI0 for one time slot. The register 410 ₁ stores the held data DD
D0 and supplies to the selector 411 _1.

[0630] Upon receiving the data TDI1, the register 410 ₂ holds the data TDI1 for one time slot. The register 410 ₂ stores the held data DD
D1 and supplies to the selector 411 _2.

When data TDI2 is input, register 410 ₃ holds data TDI2 for one time slot. The register 410 ₃ stores the held data DD
D2 and supplies to the selector 411 _3.

The register 410 ₄ receives the data TDI3 and holds the data TDI3 for one time slot. The register 410 ₄ stores the held data DD
D3 and supplied to the selector 411 _4.

The register 410 ₅ receives the data TDI4 and holds the data TDI4 for one time slot. The register 410 ₅ stores the held data DD.
D4 and supplies to the selector 411 _5.

[0634] Register 410 ₆ inputs the data TDI5, holds this data TDI5 only one time slot. Register 410 ₆ holds data DD
D5 supplies to the selector 411 _6.

[0635] The selector 411 _1, based on the interleaving length information CINL, the data DDD0 supplied from the register 410 _1, of the data TDI0, selects either. Specifically, the selector 411 ₁
If the interleave length is even, the data T
Select DI0. The selector 411 ₁ uses the selected data DS0 as the data D0,
6 Needless to say, the interleave length information CINL input to the selector 411 ₁ is actually the least significant bit of the bit string representing the interleave length information CINL.

[0636] The selector 411 _2, based on the interleaving length information CINL, the data DDD1 supplied from the register 410 _2, of the data TDI1, selects either. Specifically, the selector 411 ₂
If the interleave length is even, the data T
Select DI1. The selector 411 ₂ converts the selected data DS1 into the input data selection circuit 40 as the data D1.
6 Incidentally, the interleaving length information CINL inputted to the selector 411 _2, in fact, it is needless to say that sufficient least significant bit of the bit string indicating the interleaving length information CINL.

[0637] The selector 411 ₃ based on the interleaving length information CINL, the data DDD2 supplied from the register 410 _3, out of the data TDI2, selects either. Specifically, the selector 411 ₃
If the interleave length is even, the data T
Select DI2. The selector 411 ₃ uses the selected data DS2 as the data D2 as input data selection circuit 40.
6 Incidentally, the interleaving length information CINL inputted to the selector 411 _3, in fact, it is needless to say that sufficient least significant bit of the bit string indicating the interleaving length information CINL.

[0638] The selector 411 ₄ selects one of the data DDD3 and the data TDI3 supplied from the register 410 ₄ based on the interleave length information CINL. Specifically, the selector 411 ₄
If the interleave length is even, the data T
Select DI3. The selector 411 ₄ converts the selected data DS3 into the input data selection circuit 40 as the data D3.
6 Incidentally, the interleaving length information CINL inputted to the selector 411 ₄ is in fact, it is needless to say that sufficient least significant bit of the bit string indicating the interleaving length information CINL.

[0639] The selector 411 ₅ selects one of the data DDD4 and the data TDI4 supplied from the register 410 ₅ based on the interleave length information CINL. Specifically, the selector 411 ₅
If the interleave length is even, the data T
Select DI4. The selector 411 ₅ converts the selected data DS4 into the input data selection circuit 40 as data D4.
6 Note that it goes without saying that the interleave length information CINL input to the selector 411 ₅ is actually the least significant bit of the bit string representing the interleave length information CINL.

[0640] The selector 411 ₆ selects one of the data DDD5 and the data TDI5 supplied from the register 410 ₆ based on the interleave length information CINL. Specifically, the selector 411 ₆
If the interleave length is even, the data T
Select DI5. The selector 411 ₆ converts the selected data DS5 as the data D5 into the input data selection circuit 40.
6 Needless to say, the interleave length information CINL input to the selector 411 ₆ is actually the least significant bit of the bit string representing the interleave length information CINL.

The odd-length delay compensating circuit 402 has the following construction.
When the data TDI is input, the data TDI is output without passing through the register in the case of an even-length delay, and the data TDI is output after being held for one time slot by a register in the case of an odd-length delay.

[0642] Interleave address conversion circuit 403
Is an externally supplied interleaved mode signal CD
Write address data, which is sequential address data supplied from the control circuit 400, based on the IN, the interleaver type information CINT supplied from the control circuit 60, and the operation mode information CBF indicating that the delay should be delayed by the interleave length. Of the IWA and interleave length delayed read address data IRA and the read address data ADA which is random address data supplied from the address storage circuit 110, desired address data is selected and converted to interleave address data. . The interleave address conversion circuit 403 converts, for example, six systems of address data AA0, BA0, AA1, BA1, AA2, and BA2 obtained by the conversion.
Is supplied to the address selection circuit 405. Further, the interleave address conversion circuit 403 outputs, for example, four control signals IOBS and IOB for instructing a selection operation in the output data selection circuit 408 based on the input information.
P0, IOBP1, and IOBP2 are generated, and these control signals are supplied to the output data selection circuit 408.

The delay address conversion circuit 404 includes a delay write address data DWA supplied from the delay address generation circuit 401 and a delay read address data DWA.
The desired address data is selected from the RA and converted to delay address data. Delay address conversion circuit 4
04 supplies the converted address data DAA and DBA to the address selection circuit 405, for example. In addition, the delay address conversion circuit 404 is, for example, a two-system control signal DOB for instructing a selection operation in the output data selection circuit 408 based on the input information.
S, DOBP are generated, and these control signals are supplied to the output data selection circuit 408.

[0644] The address selection circuit 405
Interleaver type information CINT supplied from
Based on the interleaver non-output position information CNO supplied from the control circuit 400, the address data AA0 and B supplied from the interleave address conversion circuit 403 are used.
A0, AA1, BA1, AA2, and BA2, and address data DA supplied from the delay address conversion circuit 404.
A and DBA, storage circuits 407 ₁ , 407 ₂ ,.
· To select the address data to be distributed to 407 _16. The address selection circuit 405 outputs the selected address data AR
00, AR01, ..., the AR15, respectively, the memory circuits 407 _1, 407 _2, ..., and supplies the 407 _16.

The address selection circuit 405 includes, in addition to the interleaver type information CINT and the interleaver non-output position information CNO, a control circuit 4 (not shown).
00 a control signal input through the generated and interleave address conversion circuit 405, the memory circuit 407 ₁ at the time of performing the interleaving or de-interleaving, 407 _2, ..., the write enable signal and a write to 407 ₁₆ And a control signal generated by the delay address conversion circuit 404, the storage circuits 407 ₁ , 407 ₂ ,.
..., and a signal indicating the bank of write enable signal and for writing to 407 ₁₆ is input. The address selection circuit 405, based on this information,
_1, 407 _2, ..., a write enable signal XWE for 407 _16, storage circuit 407 _1, 407 _2, ..., 40
7 ₁₆ clock inhibit for blocking the clock signal to the (clock inhibit) signal the IH, storage circuits 407 _1, 4
07 _2, ..., to generate a partial write control signal PW for causing writing of data to 407 ₁₆ as a so-called partial write (partial write). The address selection circuit 405 converts these write enable signal XWE, clock block signal IH and partial write control signal PW into storage circuits 407 ₁ , 407 ₂ ,.
- and supplies to 407 _16.

The input data selection circuit 406 has a selector
120_Four, For example, three systems of data TII supplied from
0, TII1, and TII2 are data I0, I1, and I2.
And from the odd-length delay compensation circuit 402
Data D0, D1, D2, D3, D4, D5 supplied
Is entered. The input data selection circuit 406
Supplied interleave mode signal CDIN and control
Interleaver type information CI supplied from circuit 60
Based on NT and interleaver input / output replacement information CIPT
Then, data I0, I1, I2, D0, D1, D2
Of the D3, D4, and D5, the storage circuit 407₁, 407_Two,
..., 407₁₆Select the data to be distributed to In particular,
The input data selection circuit 406 interpolates the input data.
When performing interleaving or deinterleaving, the data
I0, I1, and I2 are input and these data I0, I2
1, I2, the storage circuit 407₁, 407_Two, ...,
407 ₁₆Select the data to be distributed to Also, input data
The data selection circuit 406 delays the input data
Include delay data D0, D1, D2, D3, D4.
D5, and these data D0, D1, D2, D
3, D4 and D5, the storage circuit 407₁, 407_Two,
.., 407₁₆Select the data to be distributed to Input data
The data selection circuit 406 outputs the selected data IR00, IR0
,..., IR15 are stored in the storage circuit 40, respectively.
7₁, 407_Two, ..., 407₁₆To supply.

[0647] The input data selection circuit 406
As will be described later, when interleaving is performed on a plurality of symbols, it has a function of replacing each symbol with each other. That is, the input data selection circuit 406 has a function of changing the order of each symbol for the input data I0, I1, and I2 based on the interleaver input / output replacement information CIPT.

The storage circuits 407 ₁ , 407 ₂ ,..., 40
RAs ₁₆ each having a partial write function
M and a plurality of selectors and the like. Storage circuit 40
7 _1, 407 _2, ..., 407 _16, respectively, the address data AR0 supplied from the address selection circuit 405
The data IR00, IR01,..., IR15 supplied from the input data selection circuit 406 are written and stored at the addresses specified by 0, AR01,. Then, the storage circuits 407 ₁ , 407 ₂ ,
, 407 ₁₆ are address selection circuits 40
5, the address data AR00, AR01,
.., Read stored data from the address specified by AR15, and read data OR00, OR0
Output data selection circuit 408 as OR15
To supply. At this time, the storage circuits 407 ₁ , 407 ₂ ,.
.., 407 ₁₆ are address selection circuits 405, respectively.
Starts writing data based on the write enable signal XWE supplied from the device. Further, the storage circuits 407 ₁ ,
407 _2, ..., 407 _16, respectively, based on the clock inhibit signal the IH, can also stop any operation, including writing and / or reading.

Further, storage circuits 407 ₁ , 407 ₂ ,.
-, 407 _16, respectively, on the basis of the partial write control signal PW, it is also possible to perform writing of data by the partial write function. That is, a normal RAM
In, the write operation is performed by, when a certain address is specified, selecting memory cells for the number of bits corresponding to this address and writing information to all of these memory cells at once. On the other hand, in a partial write RAM, the write operation does not write information to all the selected memory cells at once, but only writes to an arbitrary bit of the memory cells selected by the address. This is done by: Storage circuits 407 ₁ , 407 ₂ ,..., 40
7 _16, respectively, has a RAM having such a partial write function, based on the partial write control signal PW, it is also possible to write information to a portion of the specified address.

[0650] interleaver 100, these storage circuits 407 _1, 407 _2, ..., by controlling the writing and / or reading data to 407 _16, interleaving and deinterleaving, as well, the received value Delay processing can be realized.

Specifically, the storage circuits 407 ₁ , 407 ₂ ,
, 407 ₁₆ are an inverter 420 and five selectors 421, 4 as shown in FIG. 54, for example.
22, 423, 425, 426 and a RAM 424 with a partial write function. Note that, in FIG. Further, in FIG.
Address data AR00, AR0 supplied from the
, AR15 are collectively referred to as address data AR, and data IR00, IR01,.
R, and the output data selection circuit 4
08, data OR00, OR01,.
R15 is generically called data OR.

[0652] The inverter 420 has the address data AR
, And inverts the most significant bit. The inverter 420 supplies the inverted bit IAR obtained by inversion to the selector 421.

The selector 421 is connected to the address selection circuit 40
5 based on the partial write control signal PW supplied from the inverter 420, and the inverted bit IA supplied from the inverter 420.
One of R and a bit whose value is "0" is selected and output as 1-bit data HPW. Specifically, when the partial write control signal PW instructs data writing by the partial write function, the selector 421 outputs the inverted bit IAR.
Select The data HPW selected by the selector 421 is parallel-converted into, for example, 8 bits and supplied to the RAM 424 as data VIH.

[0654] The selector 422 is connected to the address selection circuit 40.
5 selects one of the most significant bit of the address data AR and the bit whose value is “0” based on the partial write control signal PW supplied from
Output as 1-bit data LPW. In particular,
The selector 422 determines whether the partial write control signal PW
If the instruction is to instruct data writing by the partial write function, the most significant bit of the address data AR is selected. The data LPW selected by the selector 422 is parallel-converted into, for example, 8 bits and supplied to the RAM 424 as data VIL.

[0655] Data IR is divided into upper bits and lower bits and input to selector 423. For example,
When the data IR consists of 16 bits, the selector 423 provides the upper 8 bits of data IR [15: 8],
Lower eight bits of data IR [7: 0] are input. The selector 423 outputs the data I based on the partial write control signal PW supplied from the address selection circuit 405.
Either the upper bit or the lower bit of R is selected. Specifically, when the partial write control signal PW instructs data writing by the partial write function, the selector 423 selects the lower bits of the data IR. The data IR1 selected by the selector 423 is bundled with the lower-order data IR0 of the data IR, and the data I (= ｛IR1,
IR0 #) is supplied to the RAM 424.

The RAM 424 simply writes the data IR and reads the data OR based on the address data AR. However, as described above, the RAM 424 has a partial write function.
Address data AR and data IR are input, and data O
It is not configured to output R.

The RAM 424 has the address selection circuit 40
5, a write enable signal XWE and a clock blocking signal IH. When the write permission signal XWE is input, the RAM 424 enters a state in which data can be written. The RAM 424 stores address data A
R based on address data IA, which is data excluding the most significant bit of R, and data VIH and VIL.
(= {IR1, IR0}) is written. Also, RA
From M424, the address data IA and the data VI
Data OH and OL are read based on H and VIL. These data OH and OL are both supplied to the selectors 425 and 426. Also, the RAM 424
When the clock blocking signal IH is input, the write and / or
Alternatively, stop all operations including reading.

[0658] Details of each data input / output to / from the RAM 424 will be described later.

[0659] The selector 425 outputs the data L obtained by delaying the data LPW supplied from the selector 422 with a predetermined delay.
The data O supplied from the RAM 424 based on the PD
H or OL is selected, and the data SOH
Output as Specifically, the selector 425 selects the data OH when the data LPD is “0”, and selects the data O when the data LPD is “1”.
Select L. That is, the selector 425 is provided to determine which of the higher-order bit data and the lower-order bit data should be output in the address direction in consideration of data writing and reading by the partial write function. .

[0660] The selector 426 outputs data LW obtained by delaying the data LPW supplied from the selector 422 by a predetermined delay.
The data O supplied from the RAM 424 based on the PD
One of H and OL is selected, and data SOL is selected.
Output as Specifically, the selector 426 selects the data OL when the data LPD is “0”, and selects the data OL when the data LPD is “1”.
Select H. That is, similarly to the selector 425, the selector 426 determines whether to output higher-order bit data or lower-order bit data in the address direction in consideration of data writing and reading by the partial write function. It is provided in.

The data SOH selected by the selector 425 and the data SOL selected by the selector 426 are supplied to the output data selection circuit 408 as data OR (= {SOH, SOL}).

[0660] Such storage circuits 407 ₁ , 407 ₂ ,.
.., 407 ₁₆ are address data AR0, respectively.
0, AR01,..., AR15.
, IR15, and reading of data OR00, OR01, ..., OR15.

[0663] Note that the storage circuits 407 ₁ , 407 ₂ , ...
, 407 ₁₆ enable data writing by the partial write function, as described above.
This will be described later.

The output data selection circuit 408 has an interleave mode signal CDIN supplied from the outside and interleaver type information CIN supplied from the control circuit 60.
T and interleaver input / output replacement information CIPT, and control signals IOBS, IOBP0, IOBP1, IOBP2 supplied from the interleave address conversion circuit 403.
And the control signals DOBS, DOBP supplied from the delay address conversion circuit 404,
7 _1, 407 _2, ..., 407 ₁₆ of the data supplied from the respective OR00, OR01, ..., of OR15, selects data to be output. When the input data is interleaved or deinterleaved, the output data selection circuit 408 converts the selected data into, for example, three-system interleaver output data IIO0, IIO.
1, as IIO2, respectively, to the selector 120 _7. Further, when the input data is delayed, the output data selection circuit 408 converts the selected data into, for example, six-system interleave length delayed reception values IDO0, IDO.
O1, IDO2, IDO3, IDO4, as IDO5, respectively, to the selector 120 _6.

The output data selection circuit 408 is
As will be described later, when deinterleaving is performed on a plurality of symbols, it has a function of replacing each symbol with each other. That is, output data selection circuit 408 outputs interleaver output data IIO0, IIO1, II based on interleaver input / output replacement information CIPT.
O2 has a function of changing the order of each symbol.

The interleaver 100 described above is
When performing the interleaving process, the control circuit 400
Write that is sequential address data
Address selecting circuit using embedded address data IWA
405 allows the appropriate storage circuit 407₁, 407_Two,
.., 407₁₆Address, and input data.
The data I0, I1, I2
The appropriate storage circuit 407₁, 407_Two, ..., 407₁₆
To the storage circuits 407 ₁, 40
7_Two, ..., 407₁₆Write data to On the other hand,
The interleaver 100 is generated by the control circuit 400
Address based on sequential address data IAA
Random address read from the
Using the read address data ADA
And an appropriate storage circuit by the address selection circuit 405.
407₁, 407_Two, ..., 407₁₆Distribute addresses to
And the storage circuit 407₁, 407_Two, ..., 407₁₆Written in
Read the stored data. And interleaving
The output data selection circuit 408
Storage circuit 407₁, 407_Two, ..., 407₁₆Out of
Select the data to be input and select the interleaver output data I
Output as IO0, IIO1, IIO2. like this
In this way, the interleaver 100
Leave processing can be performed.

[0667] When performing the deinterleave processing, the interleaver 100 reads random address data read from the address storage circuit 110 based on the sequential address data IAA generated by the control circuit 400. Address data ADA
, And 407 ₁₆ are distributed by the address selection circuit 405 to appropriate storage circuits 407 ₁ , 407 ₂ ,. Circuit 40
7 _1, 407 _2, ..., distributing addresses to 407 _16,
These storage circuits 407 ₁ , 407 ₂ ,..., 407 ₁₆
Write data to On the other hand, the interleaver 100
Using a sequential address data generated by the control circuit 400 write address data IWA, the address selection circuit 405, the appropriate storage circuits 407 _1, 407 _2, ..., distributing addresses to 407 _16, the memory circuit 407 _1, 407 _2, ..., it reads the data stored in the 407 _16. Then, the interleaver 100, by the output data selection circuit 408, the appropriate storage circuits 407 _1, 407 _2, ..., select the data output from the 407 _16, interleaver output data I
Output as IO0, IIO1, IIO2. By doing so, the interleaver 100 can perform the deinterleave processing.

Further, when delaying the input data, the interleaver 100 uses the write address data IWA generated by the control circuit 400 to generate an appropriate storage circuit 40
7 _1, 407 _2, ..., 407 as well as distributing the address _16, the input data selecting circuit 406, the data D0, D1, D2, D3, D4, D5 appropriate storage circuits 407 _1, 407 _2, · .., 407 ₁₆ and distribute the addresses to these storage circuits 407 ₁ , 407 ₂ ,.
7 Write data to ₁₆ . On the other hand, interleaver 100
, 4 using the interleave-length-delayed read address data IRA, which is sequential address data generated by the control circuit 400, by the address selection circuit 405 and appropriate storage circuits 407 ₁ , 407 ₂ ,.
07 ₁₆ distributes an address, the memory circuit 407 _1, 40
7 _2, ..., it reads the data stored in the 407 _16. Then, the interleaver 100 uses the output data selection circuit 408 to store the appropriate storage circuits 407 ₁ and 4071.
7 _2, ..., select the data output from the 407 _16, interleaving length delayed received value IDO 0, IDO1,
Output as IDO2, IDO3, IDO4, IDO5. By doing so, the interleaver 10
A value of 0 can delay input data.

Next, R in interleaver 100
A specific example of a method of using AM will be described.

[0670] The element decoder 50 serves as a data RAM, and stores the storage circuits 407 ₁ ,
407 _2, ..., includes 16 RAM, each having a 407 _16, as the RAM address, it comprises a plurality of RAM included in the address storage circuit 110. Here, the 16 RAMs of each of the storage circuits 407 ₁ , 407 ₂ ,..., 407 ₁₆ are 16 bits × 40
It is assumed that the memory has a storage capacity of 96 words, and the address storage circuit 110 includes six RAMs each having a storage capacity of 14 bits × 4096 words. In addition, R in the memory circuit 407 _1, 407 _2, ..., 407 ₁₆
AM, RAMD01, D02,..., D
16, and the RAM in the address storage circuit 110 is referred to as RAMA.

First, for one symbol of input data,
An example in which random interleaving is performed will be described. Here, it is assumed that the encoding device 1 performs PCCC with an encoding rate of “1/6 or more” and that the capacity of input data is “16 kilowords or less”.

In this case, the interleaver 100 needs to interleave the data of one symbol and delay the data of six symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
.., D16, 12 RAMs D01, D0
2, D03, D04, D05, D06, D07, D0
8, D09, D10, D11, and D12 are used for delay, and as shown in FIG.
D13, D14, D15, and D16 are used for interleaving. As the RAM for the address, FIG.
As shown in FIG. 7, out of the six RAMAs, any four R
AMA may be used. Therefore, interleaver 1
00 and the address storage circuit 110 do not use two RAMAs as shown in FIG.

More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D06, D09, D10, D1
3 and D14 are used as the above-mentioned bank A (A ₀ , A ₁ ), and the RAMs D03, D04, D07, D08, D11,
D12, D15 and D16 are connected to the above-mentioned bank B (B ₀ ,
B ₁ ). That is, the interleaver 100
Are RAMD01, D02, D05, D06, D09,
When data is written to D10, D13, and D14, the RAMs D03, D04, D07, D08,
Data is read from D11, D12, D15, D16, and RAMD03, D04, D07, D08, D11,
When data is written to D12, D15, and D16, the RAMs D01, D02, D05, D06,
Data is read from D09, D10, D13, D14.

The RAMs D01 and D02 store the address data A supplied from the address selection circuit 405, respectively.
Based on R00 and AR01, the input data selection circuit 40
6, delay data D0 and D1 are supplied and written as data IR00 and IR01. At this time, R
The data of 0 to 4 kilowords of the data D0 and D1 is written in the AMD01, and the RAMD02 is written in the RAMD02.
Four to eight kilowords of data are written. Also,
Address data AR04 and AR data supplied from the address selection circuit 405 are stored in the RAMs D05 and D06, respectively.
Based on the data D05, the input data selection circuit 406 outputs data IR04 and IR05 as delay data D2 and D3.
Is supplied and written. At this time, data of 0 to 4 kilowords of the data D2 and D3 is written to the RAM D05, and data of 4 to 8 kilowords is written to the RAM D06. Further, RAMD0
9 and D10, the data IR08, IR08, from the input data selection circuit 406 based on the address data AR08, AR09 supplied from the address selection circuit 405, respectively.
Delay data D4 and D5 are supplied and written as IR09. At this time, data of 0 to 4 kilowords of the data D4 and D5 is written to the RAM D09, and data of 4 to 8 kilowords is written to the RAM D10.

At the same time, RAMD03, D04, D
From 07, D08, D11, and D12, stored data are data OR02, OR03, and OR0, respectively.
6, OR07, OR10, OR11,
The data is supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR02 and AR03 supplied from the address selection circuit 405, the data D0 and D1 for the delay are input from the input data selection circuit 406 to the RAMs D03 and D04, respectively. Is supplied and written. At this time, the RAM D03 stores 0 of the data D0 and D1.
To 4 kilowords of data are written into RAMD0
4 is written with 4 to 8 kilowords of data. The RAMs D07 and D08 have address data AR supplied from the address selection circuit 405, respectively.
06, AR07, the input data selection circuit 406
, Delay data D2 and D3 are supplied and written as data IR06 and IR07. At this time, RA
Of the data D2 and D3, data of 0 to 4 kilowords is written into MD07, and 4D is written into RAMD08.
To 8 kilowords of data are written. further,
The RAMs D11 and D12 have address data AR10 and AR supplied from the address selection circuit 405, respectively.
11, delay data D 4, D 5 as data IR 10, IR 11 from input data selection circuit 406.
Is supplied and written. At this time, data of 0 to 4 kilowords of the data D4 and D5 is written to the RAMD11, and data of 4 to 8 kilowords is written to the RAMD12.

At the same time, RAM D01, D02, D
From 05, D06, D09, and D10, stored data are data OR00, OR01, and OR0, respectively.
4, OR05, OR08, OR09,
The data is supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Also, RAMD13, D14, D15, D
RAs 16 each function as a partial write RAM based on the partial write control signal PW, and have a pseudo 8 bit × 8192 word storage capacity.
Acts as M.

[0679] The RAMs D13 and D14 have the address data A supplied from the address selection circuit 405, respectively.
Based on R12 and AR13, the input data selection circuit 40
6, data I0 for interleaving is supplied and written as data IR12 and IR13. At this time, data of 0 to 8 kilowords of the data I0 is written to the RAMD13, and
Data for 8 to 16 kilowords is written.

At the same time, the stored data is read from the RAMs D15 and D16, respectively, by the data OR1.
4, the output data selection circuit 4
08. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR14 and AR15 supplied from the address selection circuit 405, the interleave data I0 is supplied as data IR15 and IR16 from the input data selection circuit 406 to the RAMs D15 and D16, respectively. Is written.
At this time, data of 0 to 8 kilowords of the data I0 is written to the RAMD15,
Is written with data of 8 to 16 kilowords.

At the same time, the stored data is read from the RAMs D13 and D14 by the data OR1.
2, the output data selection circuit 4
08. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0684] By doing so, the interleaver 100 allows the coding apparatus 1 to set the coding rate to "1".
/ 6 or more ”is performed, and the data capacity becomes“ 16 ”.
Random interleaving and delay can be applied to input data of one symbol which is equal to or less than a kiloword.

Next, an example in which random interleaving is performed on input data of two symbols will be described. Here, it is assumed that the coding apparatus 1 performs SCCC with a coding rate of “１ ／ or more” and that the capacity of input data is “8 kwords or less”.

In this case, the interleaver 100 needs to interleave the data of two symbols and delay the data of six symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
, D16, six RAMs D01, D02,
D03, D04, D05, and D07 are used for delay, and as shown in FIG.
10, D11, D12, D13, D14, D15, D1
6 is used for interleaving. In addition, RA for address
As M, as shown in FIG.
Of these, any four RAMAs may be used. Therefore, the interleaver 100 and the address storage circuit 1
Reference numeral 10 denotes two RAMs D0 as shown in FIG.
6, D08 and two RAMAs are not used.

More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D09, D10, D13, D1
4 is used as the above-described bank A (A ₀ ), and RAMD
03, D04, D07, D11, D12, D15, D1
6 is used as the above-mentioned bank B (B ₀ ). That is, the interleaver 100 includes the RAMs D01, D02,
When data is written to D05, D09, D10, D13, and D14, the RAMs D03, D04,
Data is read from D07, D11, D12, D15, and D16, and RAM D03, D04, D07, D11, D
12, D15 and D16, the data is written in the RAMs D01, D02, D05, D09, D
Data is read from 10, D13, and D14.

The RAMD01 has an address selection circuit 40
5 based on the address data AR00 supplied from
As data IR00 from the input data selection circuit 406,
Delay data D0 and D1 are supplied and written.
At this time, data D0 and D1 for 0 to 4 kilowords are written to the RAM D01. Also, RAMD05
Input data selection circuit 406 based on address data AR04 supplied from address selection circuit 405.
To the data IR04, the delay data D2, D3
Is supplied and written. At this time, data D2 and D3 for 0 to 4 kilowords are written to the RAM D05. Further, based on the address data AR01 supplied from the address selection circuit 405, delay data D4 and D5 are supplied and written as data IR01 from the input data selection circuit 406 to the RAM D02. At this time, data D4 and D5 for 0 to 4 kilowords are written to the RAM D02.

At the same time, RAMD03, D04, D
From 07, the stored data is read out as data OR02, OR03, and OR06, respectively, and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, RAMD03 receives data IR02 from input data selection circuit 406 based on address data AR02 supplied from address selection circuit 405.
, The delay data D0 and D1 are supplied and written. At this time, data D0 and D1 for 0 to 4 kilowords are written to the RAM D03. Also, RA
Based on the address data AR06 supplied from the address selection circuit 405, the MD07 receives the delay data D06 as data IR06 from the input data selection circuit 406.
2, D3 are supplied and written. At this time, RAM
D07 contains data D2 and D3 for 0 to 4 kilowords.
Is written. Further, the RAMD04 includes the address data AR03 supplied from the address selection circuit 405.
From the input data selection circuit 406 based on
As 03, delay data D4 and D5 are supplied and written. At this time, data D4 and D5 for 0 to 4 kilowords are written to the RAM D04.

At the same time, RAMs D01, D02, D
From 05, the stored data is read as data OR00, OR01, and OR04, respectively, and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Also, RAMs D09, D10, D11, D
12, D13, D14, D15, D16 are respectively
Based on the partial write control signal PW, it functions as a RAM for partial write and simulates 8 bits × 81
It acts as a RAM with a storage capacity of 92 words.

The RAMD 13 has an address selection circuit 40
5 based on the address data AR12 supplied from
As the data IR12 from the input data selection circuit 406,
Data I0 for interleaving is supplied and written. At this time, data I0 for 0 to 8 kilowords is written to the RAMD13. Similarly to RAMD13, interleave data I0 is supplied as data IR13 from input data selection circuit 406 and written into RAMD14, based on address data AR13 supplied from address selection circuit 405.
At this time, data I0 for 0 to 8 kilowords is written to RAMD14. Further, based on the address data AR08 supplied from the address selection circuit 405, the RAMD09 stores the data I08 for interleaving as data IR08 from the input data selection circuit 406.
1 is supplied and written. At this time, RAMD09
Is written with data I1 for 0 to 8 kilowords. Also, in RAMD10, similarly to RAMD09,
Based on the address data AR09 supplied from the address selection circuit 405, interleave data I1 is supplied and written as data IR09 from the input data selection circuit 406. At this time, data I1 for 0 to 8 kilowords is written to the RAMD10.

At the same time, the stored data is read from the data OR1 from the RAMs D11 and D15.
0, OR14, and is supplied to the output data selection circuit 408 as one-system symbol data out of the two-symbol data. RAMD12, D16
, The stored data is the data OR
11, and read as OR15, and supplied to the output data selection circuit 408 as another one-system symbol data of the two-symbol data. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR14 supplied from the address selection circuit 405, the RAMD15 receives the data IR14 from the input data selection circuit 406.
The data I0 for interleaving is supplied and written. At this time, data I0 for 0 to 8 kilowords is written to the RAMD15. Also, RAM
Similarly to the RAM D15, the interleave data I0 is supplied to the D16 as the data IR15 from the input data selection circuit 406 based on the address data AR15 supplied from the address selection circuit 405, and is written. At this time, data I0 for 0 to 8 kilowords is written to the RAMD16. Furthermore, RAMD
11, the input data selection circuit 4 based on the address data AR10 supplied from the address selection circuit 405.
From 06, data I1 for interleaving is supplied and written as data IR10. At this time, RAM
Data I1 for 0 to 8 kilowords is written to D11. Also, in the RAMD12, similarly to the RAMD11, the input data selection circuit 406 based on the address data AR11 supplied from the address selection circuit 405.
, Data I1 for interleaving is supplied and written as data IR11. At this time, RAMD1
2 is written with data I1 for 0 to 8 kilowords.

At the same time, the stored data is read from the data OR0 from the RAMs D09 and D13, respectively.
8, and read out as OR12 and supplied to the output data selection circuit 408 as one system of symbol data out of the data of two symbols. RAMD10, D14
, The stored data is the data OR
09, OR13, and supplied to the output data selection circuit 408 as another one-system symbol data of the two-symbol data. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0696] By doing so, the coding apparatus 1 allows the interleaver 100 to set the coding rate to "1".
SCCC of 以上 or more ”is performed, and random interleaving and delay can be applied to input data of two symbols having a data capacity of“ 8 kilowords or less ”.

Next, an example in which inline interleaving is performed on input data of two symbols will be described. In this case, the encoding apparatus 1 determines that the punctured SC
CC, and the input data capacity is “1”.
2 kilowords or less ".

In this case, the interleaver 100 needs to interleave the data of two symbols and delay the data of four symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
, D16, eight RAMs D01, D02,
D03, D04, D05, D06, D07, and D08 are used for delay, and as shown in FIG. 4B, eight RAMs D09, D10, D11, D12, D13, and D1 are used.
4, D15 and D16 are used for interleaving. Also,
As the address RAM, all six RAMs A are used, as shown in FIG.

[0699] More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D06, D09, D10, D1
3 and D14 are used as the above-mentioned bank A (A ₀ , A ₁ ), and the RAMs D03, D04, D07, D08, D11,
D12, D15 and D16 are connected to the above-mentioned bank B (B ₀ ,
B ₁ ). That is, the interleaver 100
Are RAMD01, D02, D05, D06, D09,
When data is written to D10, D13, and D14, the RAMs D03, D04, D07, D08,
Data is read from D11, D12, D15, D16, and RAMD03, D04, D07, D08, D11,
When data is written to D12, D15, and D16, the RAMs D01, D02, D05, D06,
Data is read from D09, D10, D13, D14.

The RAMs D01 and D02 store the address data A supplied from the address selection circuit 405, respectively.
Based on R00 and AR01, the input data selection circuit 40
6, delay data D0 and D1 are supplied and written as data IR00 and IR01. At this time, R
The AMD02 stores the data D0 and D1 only in a half storage area in the word direction as shown by the hatched portion in FIG. 9A, and does not store data in the remaining storage areas. That is, data of 0 to 4 kilowords out of the data D0 and D1 is written into the RAM D01,
In AMD02, data for 4 to 6 kilowords is written. Further, based on the address data AR04 and AR05 supplied from the address selection circuit 405, delay data D2 and D3 are supplied as data IR04 and IR05 from the input data selection circuit 406 to the RAMs D05 and D06, respectively. Written. At this time, the RAM D06 stores the data D2 and D3 only in the half storage area in the word direction, as shown by the hatched portion in FIG. I don't remember. That is, RAMD
05 is written with data of 0 to 4 kilowords out of the data D2 and D3, and RAMD06 is written with data of 4 to 6 kilowords.

At the same time, RAMD03, D04, D
From 07 and D08, the stored data is read out as data OR02, OR03, OR06 and OR07, respectively, and supplied to the output data selection circuit 408. At this time, the RAMs D04 and D08 each store data only in a half storage area in the word direction, as indicated by the hatched portion in FIG. Not. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR02 and AR03 supplied from the address selection circuit 405, the data D0 and D1 for the delay are input to the RAMs D03 and D04 as the data IR02 and IR03 from the input data selection circuit 406, respectively. Is supplied and written. At this time, the RAM D04 stores data D0 and D only in half the storage area in the word direction, as indicated by the hatched area in FIG.
1 and no data is stored in the remaining storage areas. That is, the data D0,
Data of 0 to 4 kilowords is written in D1, and data of 4 to 6 kilowords is written in RAM D04. Further, based on the address data AR06 and AR07 supplied from the address selection circuit 405, delay data D2 and D3 are supplied as data IR06 and IR07 from the input data selection circuit 406 to the RAMs D07 and D08, respectively. Written. At this time, the RAM D08 stores the data D2 and D3 only in a half storage area in the word direction as in the case of the RAM D04, as indicated by the hatched portion in FIG. I don't remember. That is, RAM
D07 is written with data of 0 to 4 kilowords out of the data D2 and D3, and RAMD08 is written with data of 4 to 6 kilowords.

At the same time, RAMs D01, D02, D
05 and D06, the stored data is read out as data OR00, OR01, OR04, and OR05, respectively, and supplied to the output data selection circuit 408. At this time, each of the RAMs D02 and D06 stores data only in a half storage area in the word direction, as indicated by hatching in FIG. 2A, and stores data in the remaining storage areas. Not. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Also, the RAM D09, D10, D11, D
12, D13, D14, D15, D16 are respectively
Based on the partial write control signal PW, it functions as a RAM for partial write and simulates 8 bits × 81
It acts as a RAM with a storage capacity of 92 words.

The RAMs D13 and D14 have the address data A supplied from the address selection circuit 405, respectively.
Based on R12 and AR13, the input data selection circuit 40
6, data I0 for interleaving is supplied and written as data IR12 and IR13. At this time, the RAMD 14 stores the data I0 only in a half storage area in the word direction, and does not store the data in the remaining storage areas, as indicated by the hatched portion in FIG. That is, in the RAMD13, of the data I0,
Data of 0 to 8 kilowords is written, RAMD
14 is written with 8 to 12 kilowords of data. The RAMs D09 and D10 respectively store the address data A supplied from the address selection circuit 405.
Based on R08 and AR09, input data selection circuit 40
6, data I1 for interleaving is supplied and written as data IR08 and IR09. At this time, the RAMD10 stores the data I1 only in the half storage area in the word direction and stores the data in the remaining storage area, as shown by the hatched portion in FIG. Never. That is, data of 0 to 8 kilowords of the data I1 is written to the RAMD09, and data of 8 to 12 kilowords is written to the RAMD10.

At the same time, the stored data is read from the RAMs D15 and D16, respectively, from the data OR1.
4, OR15, and is supplied to the output data selection circuit 408 as one-system symbol data of the two-symbol data. At this time, RAMD16
As shown by the hatched portion in FIG. 3B, data is stored only in a half storage area in the word direction, and no data is stored in the remaining storage areas. RAMD1
From D1 and D12, the stored data is
The data is read as data OR10 and OR11, and is supplied to the output data selection circuit 408 as another one-system symbol data of the two-symbol data. At this time, the RAMD12 stores data only in a half storage area in the word direction as in the RAMD16, as indicated by the hatched portion in FIG.
No data is stored. Note that the data reading is performed in the same manner as in the data writing, as in the address selection circuit 4.
This is performed based on the address data supplied from 05.

Similarly, based on the address data AR14 and AR15 supplied from the address selection circuit 405, the interleave data I0 is supplied as data IR14 and IR15 from the input data selection circuit 406 to the RAMs D15 and D16, respectively. Is written.
At this time, the RAMD16 stores the data I0 only in a half storage area in the word direction, as indicated by the hatched portion in FIG.
And no data is stored in the remaining storage area. That is, data of 0 to 8 kilowords out of the data I0 is written into the RAM D15,
Data of 8 to 12 kilowords are written in the MD 16. Also, based on the address data AR10 and AR11 supplied from the address selection circuit 405, interleave data I1 is supplied and written as data IR10 and IR11 from the input data selection circuit 406 to the RAMs D11 and D12, respectively. . At this time, the RAMD12 stores the data I1 only in a half storage area in the word direction as in the case of the RAMD16, as indicated by the hatched portion in FIG.
No data is stored. That is, RAMD11
Of the data I1, 0 to 8 kilowords of data are written into the RAM 11, and 8 to 12 kilowords of data are written into the RAMD12.

At the same time, the stored data is read from the RAMs D13 and D14 by the data OR1.
2, and read as OR13, and supplied to the output data selection circuit 408 as one-system symbol data of the two-symbol data. At this time, RAMD14
As shown by the hatched portion in FIG. 3B, data is stored only in a half storage area in the word direction, and no data is stored in the remaining storage areas. RAMD0
From 9 and D10, the stored data is
The data is read as data OR08 and OR09, and is supplied to the output data selection circuit 408 as another one-system symbol data of the two-symbol data. At this time, the RAMD10 stores data only in a half storage area in the word direction as in the case of the RAMD14, as indicated by the hatched portion in FIG.
No data is stored. Note that the data reading is performed in the same manner as in the data writing, as in the address selection circuit 4.
This is performed based on the address data supplied from 05.

[0709] By doing so, interleaver 100 performs inline SCCC on punctured SCCC by coding apparatus 1 and performs inline processing on input data of two symbols having a data capacity of "12 kilowords or less". Interleaving and delay can be applied.

Next, an example in which pair-wise interleaving is performed on input data of two symbols will be described. Here, it is assumed that the encoding device 1 performs SCCC.

In this case, the interleaver 100 needs to interleave the data of two symbols and delay the data of four symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
, D16, eight RAMs D01, D02,
D03, D04, D05, D06, and D07D08 are used for delay, and as shown in FIG.
AMD09, D10, D11, D12, D13, D1
4, D15 and D16 are used for interleaving. Also,
As the RAM for the address, as shown in FIG. 3C, any four of the six RAMs may be used. Therefore, the interleaver 100 and the address storage circuit 110 are, as shown in FIG.
Two RAMAs will not be used.

More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D06, D09, D10, D1
3 and D14 are used as the above-mentioned bank A (A ₀ , A ₁ ), and the RAMs D03, D04, D07, D08, D11,
D12, D15 and D16 are connected to the above-mentioned bank B (B ₀ ,
B ₁ ). That is, the interleaver 100
Are RAMD01, D02, D05, D06, D09,
When data is written to D10, D13, and D14, the RAMs D03, D04, D07, D08,
Data is read from D11, D12, D15, D16, and RAMD03, D04, D07, D08, D11,
When data is written to D12, D15, and D16, the RAMs D01, D02, D05, D06,
Data is read from D09, D10, D13, D14. At this time, RAMD13, D14 and RAMD0
9 and D10 operate based on the same address.
The AMDs 15 and D16 and the RAMs D11 and D12 operate based on the same address.

[0713] In the RAMs D01 and D02, the address data A supplied from the address selection circuit 405 are respectively stored.
Based on R00 and AR01, the input data selection circuit 40
6, delay data D0 and D1 are supplied and written as data IR00 and IR01. At this time, R
The data of 0 to 4 kilowords of the data D0 and D1 is written in the AMD01, and the RAMD02 is written in the RAMD02.
Four to eight kilowords of data are written. Also,
Address data AR04 and AR data supplied from the address selection circuit 405 are stored in the RAMs D05 and D06, respectively.
Based on the data D05, the input data selection circuit 406 outputs data IR04 and IR05 as delay data D2 and D3.
Is supplied and written. At this time, data of 0 to 4 kilowords of the data D2 and D3 is written to the RAM D05, and data of 4 to 8 kilowords is written to the RAM D06.

At the same time, RAMD03, D04, D
From 07 and D08, the stored data is read out as data OR02, OR03, OR06 and OR07, respectively, and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0715] Similarly, based on the address data AR02 and AR03 supplied from the address selection circuit 405, delay data D0 and D1 are input to the RAMs D03 and D04, respectively, as data IR02 and IR03 from the input data selection circuit 406. Is supplied and written. At this time, the RAM D03 stores 0 of the data D0 and D1.
To 4 kilowords of data are written into RAMD0
4 is written with 4 to 8 kilowords of data. The RAMs D07 and D08 have address data AR supplied from the address selection circuit 405, respectively.
06, AR07, the input data selection circuit 406
, Delay data D2 and D3 are supplied and written as data IR06 and IR07. At this time, RA
Of the data D2 and D3, data of 0 to 4 kilowords is written into MD07, and 4D is written into RAMD08.
To 8 kilowords of data are written.

At the same time, RAMs D01, D02, D
05 and D06, the stored data is read out as data OR00, OR01, OR04, and OR05, respectively, and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Also, the RAMs D09, D10, D11, D
12, D13, D14, D15, D16 are respectively
Based on the partial write control signal PW, it functions as a RAM for partial write and simulates 8 bits × 81
It acts as a RAM with a storage capacity of 92 words.

The RAMs D13 and D14 have the address data A supplied from the address selection circuit 405, respectively.
Based on R12 and AR13, the input data selection circuit 40
6, data I0 for interleaving is supplied and written as data IR12 and IR13. At this time, data of 0 to 8 kilowords of the data I0 is written to the RAMD13, and
Data for 8 to 16 kilowords is written. Also, the address data AR08, AR08, supplied from the address selection circuit 405 are stored in the RAMs D09, D10, respectively.
Based on AR09, interleave data I1 is supplied and written as data IR08 and IR09 from input data selection circuit 406. At this time, RAM
In D09, data of 0 to 8 kilowords of the data I1 is written, and in RAM D10, 8 to 16 kilowords are written.
Kiloword data is written.

At the same time, the stored data is read from the RAMs D15 and D16, respectively, by the data OR1.
4, OR15, and is supplied to the output data selection circuit 408 as one-system symbol data of the two-symbol data. RAMD11, D12
, The stored data is the data OR
10, and read as OR11, and supplied to the output data selection circuit 408 as another one-system symbol data of the two-symbol data. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR14, AR15 supplied from the address selection circuit 405, the interleave data I0 is supplied as data IR14, IR15 from the input data selection circuit 406 to the RAMs D15, D16, respectively. Is written.
At this time, data of 0 to 8 kilowords of the data I0 is written to the RAMD15,
Is written with data of 8 to 16 kilowords. The RAMs D11 and D12 have address data AR supplied from the address selection circuit 405, respectively.
10, an input data selection circuit 406 based on AR11.
Supplies data I1 for interleaving as data IR10 and IR11, and is written. At this time,
Data of 0 to 8 kilowords of the data I1 is written to the RAMD11, and data of 8 to 16 kilowords is written to the RAMD12.

At the same time, the stored data is read from the RAMs D13 and D14, respectively, as the data OR1.
2, and read as OR13, and supplied to the output data selection circuit 408 as one-system symbol data of the two-symbol data. In addition, RAMD09, D10
, The stored data is the data OR
08, OR09, and supplied to the output data selection circuit 408 as another one-system symbol data of the two-symbol data. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0722] In this way, interleaver 100 can perform pair-wise interleaving and delay on input data of two symbols on which SCCC has been performed by coding apparatus 1.

Next, an example in which random interleaving is performed on input data of three symbols will be described. Here, it is assumed that the coding apparatus 1 performs SCCC with a coding rate of “１ ／ or more” and that the capacity of input data is “4 kwords or less”.

[0724] In this case, the interleaver 100 needs to interleave data of three symbols and delay data of four symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
, D16, four RAMs D01, D03,
D05 and D07 are used for delay, and 12 RAMs D02, D04, D06 and D06 are used as shown in FIG.
D08, D09, D10, D11, D12, D13, D
14, D15 and D16 are used for interleaving. As the address RAM, any three of the six RAMs may be used as shown in FIG. Therefore, the interleaver 100 and the address storage circuit 110 do not use three RAMAs as shown in FIG.

More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D06, D09, D10, D1
3, D14 is used as the above-mentioned bank A (A ₀ ),
RAM D03, D04, D07, D08, D11, D1
2, D15 and D16 are used as the above-mentioned bank B (B ₀ ). That is, the interleaver 100 has a RAM
D01, D02, D05, D06, D09, D10, D
13, when writing data to D14, RAM D03, D04, D07, D08, D11,
Read data from D12, D15, D16
D03, D04, D07, D08, D11, D12, D
15, when writing data to D16, the RAMs D01, D02, D05, D06, D09,
Data is read from D10, D13, and D14.

[0726] The RAMD01 has an address selection circuit 40
5 based on the address data AR00 supplied from
As data IR00 from the input data selection circuit 406,
Delay data D0 and D1 are supplied and written.
At this time, the RAM D01 stores the data D only in a half storage area in the word direction, as indicated by the hatched portion in FIG.
0 and D1 are stored, and no data is stored in the remaining storage areas. That is, data D0 and D1 for 0 to 2 kilowords are written in the RAM D01. Further, based on the address data AR04 supplied from the address selection circuit 405, delay data D2 and D3 are supplied and written as data IR04 from the input data selection circuit 406 to the RAMD05. At this time, the RAM D05 stores the data D2 and D3 only in a half storage area in the word direction as in the case of the RAM D01, as indicated by the hatched portion in FIG. I don't remember. That is, RAMD
In 05, data D2 and D3 for 0 to 2 kilowords are written.

[0727] At the same time, the stored data is read from the data OR0 from the RAMs D03 and D07, respectively.
2, OR06 and output data selection circuit 4
08. At this time, RAMD03, D07
Respectively store data only in a half storage area in the word direction, as indicated by hatched portions in FIG.
No data is stored in the remaining storage areas. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, RAMD03 receives data IR02 from input data selection circuit 406 based on address data AR02 supplied from address selection circuit 405.
, The delay data D0 and D1 are supplied and written. At this time, the RAM D03 stores the data D2 and D3 only in a half storage area in the word direction and does not store the data in the remaining storage areas, as indicated by the hatched portion in FIG. . That is, in RAMD03,
Data D0 and D1 for 0 to 2 kilowords are written. The RAMD07 includes an address selection circuit 405.
, Delay data D2 and D3 are supplied and written as data IR06 from the input data selection circuit 406 based on the address data AR06 supplied from. At this time, the RAM D07 stores the data D2 and D3 only in a half storage area in the word direction as in the case of the RAM D03, as indicated by the hatched portion in FIG. I don't remember. That is, RAM
D07 contains data D2 and D3 for 0 to 2 kilowords.
Is written.

At the same time, the stored data is read from the RAMs D01 and D05, respectively, from the data OR0.
0, OR04 and output data selection circuit 4
08. At this time, RAMD01, D05
Respectively store data only in a half storage area in the word direction, as indicated by hatched portions in FIG.
No data is stored in the remaining storage areas. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Also, RAMs D02, D04, D06, D
08, D09, D10, D11, D12, D13, D1
4, D15 and D16 do not function as a partial write RAM, and have a normal storage capacity.
Act as

The RAMD 13 includes an address selection circuit 40
5 based on the address data AR12 supplied from
As the data IR12 from the input data selection circuit 406,
Data I0 for interleaving is supplied and written. At this time, the RAMD 13 stores the data I0 only in a half storage area in the bit direction and does not store the data in the remaining storage area, as shown by the hatched portion in FIG. I0 is stored. Also, RA
Based on the address data AR08 supplied from the address selection circuit 405, interleave data I1 and I2 are supplied and written as data IR08 from the input data selection circuit 406 to the MD09. Further, based on the address data AR13 supplied from the address selection circuit 405, the interleave data I0 is supplied from the input data selection circuit 406 to the RAMD14 as data IR13 and written. At this time, the RAMD14 stores the data I0 only in the half storage area in the bit direction and does not store the data in the remaining storage areas, as shown by the hatched portion in FIG. Alternatively, the same data I0 is stored. The RAMD 10 has an address selection circuit 405
And interleave data I1 and I2 are supplied and written as data IR09 from the input data selection circuit 406 based on the address data AR09 supplied from. Furthermore, based on the address data AR05 supplied from the address selection circuit 405, the data IR05 is supplied from the input data selection circuit 406 to the RAMD06.
The data I0 for interleaving is supplied and written. At this time, the RAM D06 stores the data I0 only in a half storage area in the bit direction, and does not store the data in the remaining storage areas, like the RAMD13, as indicated by the hatched portion in FIG. Alternatively, the same data I0 is stored. Further, the RAMD02 stores the address data AR0 supplied from the address selection circuit 405.
1 based on the data I from the input data selection circuit 406.
As R01, interleaving data I1 and I2 are supplied and written.

[0732] At the same time, the stored data is output from the data OR1 from the RAMs D11 and D15, respectively.
The data is read as 0 or OR 14 and supplied to the output data selection circuit 408 as one system of symbol data among the data of three symbols. At this time, RAMD15
As shown by the hatched portion in FIG. 9B, data is stored only in a half storage area in the bit direction, and no data is stored in the remaining storage areas, or the same data is stored. ing. The RAMD 11 outputs two types of data. One of these data is selected by a selector (not shown) and supplied to the output data selection circuit 408. Further, RAMD12, D16
, The stored data is the data OR
11, and read out as OR15, and supplied to the output data selection circuit 408 as symbol data of another one of the three symbol data. At this time, RAMD1
6 is a RAMD15 as indicated by the hatched portion in FIG.
Similarly to the above, data is stored only in a half storage area in the bit direction, and no data is stored in the remaining storage areas, or the same data is stored. The RAMD 12 outputs two types of data. One of these data is selected by a selector (not shown) and supplied to the output data selection circuit 408.
Furthermore, from RAMD04 and D08,
The stored data is read out as data OR03 and OR07, and among the three symbol data, the output data selection circuit 4 outputs the symbol data of another one system.
08. At this time, as indicated by the hatched portion in FIG.
Data is stored only in half the storage area in the bit direction, and no data is stored in the remaining storage areas.
Alternatively, the same data is stored. Also, RAM
D04 outputs two systems of data. One of these data is selected by a selector (not shown) and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0733] Similarly, the RAMD15 receives the data IR14 from the input data selection circuit 406 based on the address data AR14 supplied from the address selection circuit 405.
The data I0 for interleaving is supplied and written. At this time, the RAMD15 stores the data I0 only in a half storage area in the bit direction and does not store the data in the remaining storage area, as shown by the hatched portion in FIG. I0 is stored. Also, based on the address data AR10 supplied from the address selection circuit 405, interleave data I1 and I2 are supplied and written as data IR10 from the input data selection circuit 406 to the RAMD11. Further, the RAMD 16 includes an address selection circuit 40.
5 based on the address data AR15 supplied from
As the data IR15 from the input data selection circuit 406,
Data I0 for interleaving is supplied and written. At this time, the RAMD 16 stores the data I0 only in the half storage area in the bit direction and does not store the data in the remaining storage areas, as shown by the hatched portion in FIG. Or the same data I0
Is stored. Further, based on the address data AR11 supplied from the address selection circuit 405, interleave data I1 and I2 are supplied and written as data IR11 from the input data selection circuit 406 to the RAMD12. Furthermore, the address data A supplied from the address selection circuit 405 is stored in the RAMD08.
Based on R07, interleave data I0 is supplied and written as data IR07 from input data selection circuit 406. At this time, the RAMD08 stores data I0 only in a half storage area in the bit direction and does not store data in the remaining storage areas, as indicated by the hatched portion in FIG. Alternatively, the same data I0 is stored. Also, RAMD04
Input data selection circuit 406 based on address data AR03 supplied from address selection circuit 405.
, Data I1 and I2 for interleaving are supplied and written as data IR03.

At the same time, the stored data is read from the RAMs D11 and D15, respectively, as the data OR1.
The data is read as 0 or OR 14 and supplied to the output data selection circuit 408 as one system of symbol data among the data of three symbols. At this time, RAMD15
As shown by the hatched portion in FIG. 9B, data is stored only in a half storage area in the bit direction, and no data is stored in the remaining storage areas, or the same data is stored. ing. The RAMD 11 outputs two types of data. One of these data is selected by a selector (not shown) and supplied to the output data selection circuit 408. Further, RAMD12, D16
, The stored data is the data OR
11, and read out as OR15, and supplied to the output data selection circuit 408 as symbol data of another one of the three symbol data. At this time, RAMD1
6 is a RAMD15 as indicated by the hatched portion in FIG.
Similarly to the above, data is stored only in a half storage area in the bit direction, and no data is stored in the remaining storage areas, or the same data is stored. The RAMD 12 outputs two types of data. One of these data is selected by a selector (not shown) and supplied to the output data selection circuit 408.
Furthermore, from RAMD04 and D08,
The stored data is read out as data OR03 and OR07, and among the three symbol data, the output data selection circuit 4 outputs the symbol data of another one system.
08. At this time, as indicated by the hatched portion in FIG.
Data is stored only in half the storage area in the bit direction, and no data is stored in the remaining storage areas.
Alternatively, the same data is stored. Also, RAM
D04 outputs two systems of data. One of these data is selected by a selector (not shown) and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0735] By doing so, the interleaver 100 allows the coding apparatus 1 to set the coding rate to "1".
SCCC of "/ 3 or more" is performed, and random interleaving and delay can be applied to input data of three symbols having a data capacity of "4 kilowords or less".

Next, an example of performing inline interleaving on input data of three symbols will be described. Here, the coding apparatus 1 determines that the coding rate is “2/3”.
And the capacity of the input data is "16 kilowords or less".

In this case, interleaver 100 needs to interleave data of three symbols and delay data of six symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
, D16, six RAMs D01, D02,
D03, D04, D05, and D07 are used for delay, and as shown in FIG.
11, D13, D14, D15 and D16 are used for interleaving. In addition, as the address RAM, all six RAMs A are used, as shown in FIG. However, these six RAMs each have 1 bit in the bit direction as shown by the hatched portion in FIG.
Of the 4-bit storage area, only the 13-bit storage area is used. Therefore, the interleaver 100
The address storage circuit 110 does not use the four RAMs D06, D08, D10, and D12 as shown in FIG.

More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D09, D13, and D14 are used as the above-described bank A (A ₀ ), and the RAMs D03 and D
04, D07, D11, D15, and D16 are used as the above-described bank B (B ₀ ). That is, the interleaver 100 includes the RAMs D01, D02, D05, D09,
When data is written to D13 and D14, RAMs D03, D04, D07, D11, D15,
Data is read from D16, and RAMD03, D04,
When data is written to D07, D11, D15, D16, the RAMs D01, D02, D05,
Data is read from D09, D13, and D14.

[0739] The RAMD01 includes an address selection circuit 40.
5 based on the address data AR00 supplied from
As data IR00 from the input data selection circuit 406,
Delay data D0 and D1 are supplied and written.
At this time, data D0 and D1 for 0 to 4 kilowords are written to the RAM D01. Also, RAMD05
Input data selection circuit 406 based on address data AR04 supplied from address selection circuit 405.
To the data IR04, the delay data D2, D3
Is supplied and written. At this time, data D2 and D3 for 0 to 4 kilowords are written to the RAM D05. Further, based on the address data AR01 supplied from the address selection circuit 405, delay data D4 and D5 are supplied and written as data IR01 from the input data selection circuit 406 to the RAM D02. At this time, data D4 and D5 for 0 to 4 kilowords are written to the RAM D02.

At the same time, RAMD03, D04, D
From 07, the stored data is read out as data OR02, OR03, and OR06, respectively, and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0741] Similarly, the RAMD03 receives the data IR02 from the input data selection circuit 406 based on the address data AR02 supplied from the address selection circuit 405.
, The delay data D0 and D1 are supplied and written. At this time, data D0 and D1 for 0 to 4 kilowords are written to the RAM D03. Also, RA
Based on the address data AR06 supplied from the address selection circuit 405, the MD07 receives the delay data D06 as data IR06 from the input data selection circuit 406.
2, D3 are supplied and written. At this time, RAM
D07 contains data D2 and D3 for 0 to 4 kilowords.
Is written. Further, the RAMD04 includes the address data AR03 supplied from the address selection circuit 405.
From the input data selection circuit 406 based on
As 03, delay data D4 and D5 are supplied and written. At this time, data D4 and D5 for 0 to 4 kilowords are written to the RAM D04.

At the same time, RAM D01, D02, D
From 05, the stored data is read as data OR00, OR01, and OR04, respectively, and supplied to the output data selection circuit 408. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0743] Also, the RAMs D09, D11, D13, D
Based on the partial write control signal PW, 14, D15, and D16 each function as a partial write RAM, and act as a RAM having a storage capacity of 8 bits × 8192 words in a pseudo manner.

The RAMD 13 has an address selection circuit 40
5 based on the address data AR12 supplied from
As the data IR12 from the input data selection circuit 406,
Data I0 for interleaving is supplied and written. At this time, data I0 for 0 to 8 kilowords is written to the RAMD13. Further, based on the address data AR08 supplied from the address selection circuit 405, the RAMD09 stores the data I08 for interleaving as data IR08 from the input data selection circuit 406.
1 is supplied and written. At this time, RAMD09
Is written with data I1 for 0 to 8 kilowords. Further, the RAMD 14 has an address selection circuit 40
5 based on the address data AR13 supplied from
As the data IR13 from the input data selection circuit 406,
Interleave data I2 is supplied and written. At this time, data I2 for 0 to 8 kilowords is written to RAMD14.

At the same time, the stored data is read out from RAMD 15 as data OR 14,
The data is supplied to the output data selection circuit 408 as one system of symbol data among the data of three symbols. Also,
From the RAMD11, the stored data is the data O
Read as R10, and among the data of three symbols,
The data is supplied to the output data selection circuit 408 as another one-system symbol data. Furthermore, from RAMD16,
The stored data is read as the data OR15, and is supplied to the output data selection circuit 408 as another one-system symbol data out of the three-symbol data. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0746] Similarly, based on the address data AR14 supplied from the address selection circuit 405, the data IR14 is supplied from the input data selection circuit 406 to the RAMD15.
The data I0 for interleaving is supplied and written. At this time, data I0 for 0 to 8 kilowords is written to the RAMD15. Also, RAM
D11 is supplied with interleave data I1 as data IR10 from the input data selection circuit 406 based on the address data AR10 supplied from the address selection circuit 405, and is written. At this time, RA
Data I1 for 0 to 8 kilowords is written to MD11. Further, based on the address data AR15 supplied from the address selection circuit 405, the RAMD16 receives the data IR15 from the input data selection circuit 406.
, Data for interleaving I2 is supplied and written. At this time, data I2 for 0 to 8 kilowords is written to the RAMD16.

[0747] At the same time, the stored data is read out from RAMD13 as data OR12,
The data is supplied to the output data selection circuit 408 as one system of symbol data among the data of three symbols. Also,
From RAMD09, the stored data is data O
Read out as R08, and among the data of three symbols,
The data is supplied to the output data selection circuit 408 as another one-system symbol data. Furthermore, from RAMD14,
The stored data is read as the data OR13, and is supplied to the output data selection circuit 408 as another one-system symbol data among the three-symbol data. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0748] By doing so, the interleaver 100 allows the coding apparatus 1 to set the coding rate to "2".
/ 3 "is performed, and inline interleaving and delay can be applied to input data of three symbols whose data capacity is" 16 kilowords or less ".

Next, an example in which pair-wise interleaving is performed on input data of three symbols will be described. Here, the encoding device 1 performs TTCM, and the capacity of input data is “32 kilowords or less”.
It is assumed that

In this case, interleaver 100 needs to interleave data of three symbols and delay data of two symbols. Therefore, the interleaver 100 is, for example, shown in FIG.
As shown in (A), 16 RAMs D01, D02,
, D16, four RAMs D01, D02,
D03 and D04 are used for delay, and 12 RAMs D05, D06, D07,
D08, D09, D10, D11, D12, D13, D
14, D15 and D16 are used for interleaving. Further, as the RAM for the address, as shown in FIG. 3C, any four of the six RAMs may be used. Therefore, the interleaver 100 and the address storage circuit 110 do not use two RAMAs as shown in FIG.

More specifically, the interleaver 100
Is a RAMD as shown in FIGS.
01, D02, D05, D06, D09, D10, D1
3 and D14 are used as the above-mentioned bank A (A ₀ , A ₁ ), and the RAMs D03, D04, D07, D08, D11,
D12, D15 and D16 are connected to the above-mentioned bank B (B ₀ ,
B ₁ ). That is, the interleaver 100
Are RAMD01, D02, D05, D06, D09,
When data is written to D10, D13, and D14, the RAMs D03, D04, D07, D08,
Data is read from D11, D12, D15, D16, and RAMD03, D04, D07, D08, D11,
When data is written to D12, D15, and D16, the RAMs D01, D02, D05, D06,
Data is read from D09, D10, D13, D14. At this time, RAMD13, D14 and RAMD0
9, D10 and the RAMs D05, D06 operate based on the same address, and the RAMs D15, D16, RA
MD11, D12 and RAM D07, D08 operate based on the same address.

The RAMs D01 and D02 store the address data A supplied from the address selection circuit 405, respectively.
Based on R00 and AR01, the input data selection circuit 40
6, delay data D0 and D1 are supplied and written as data IR00 and IR01. At this time, R
The data of 0 to 4 kilowords of the data D0 and D1 is written in the AMD01, and the RAMD02 is written in the RAMD02.
Four to eight kilowords of data are written.

At the same time, the stored data is read from the data OR0 from the RAMs D03 and D04, respectively.
2, read as OR03 and output data selection circuit 4
08. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR02 and AR03 supplied from the address selection circuit 405, the RAMs D03 and D04 receive the delay data D0 and D1 as the data IR02 and IR03 from the input data selection circuit 406, respectively. Is supplied and written. At this time, the RAM D03 stores 0 of the data D0 and D1.
To 4 kilowords of data are written into RAMD0
4 is written with 4 to 8 kilowords of data.

[0755] At the same time, the stored data is read from the data OR0 from the RAMs D01 and D02, respectively.
0, OR01 and output data selection circuit 4
08. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Also, the RAMs D05, D06, D07, D
08, D09, D10, D11, D12, D13, D1
4, D15 and D16 each function as a partial write RAM based on the partial write control signal PW, and function as a RAM having a storage capacity of 8 bits × 8192 words in a simulated manner.

The RAMs D13 and D14 have the address data A supplied from the address selection circuit 405, respectively.
Based on R12 and AR13, the input data selection circuit 40
6, data I0 for interleaving is supplied and written as data IR12 and IR13. At this time, data of 0 to 8 kilowords of the data I0 is written to the RAMD13, and
Data for 8 to 16 kilowords is written. Also, the address data AR08, AR08, supplied from the address selection circuit 405 are stored in the RAMs D09, D10, respectively.
Based on AR09, interleave data I1 is supplied and written as data IR08 and IR09 from input data selection circuit 406. At this time, RAM
In D09, data of 0 to 8 kilowords of the data I1 is written, and in RAM D10, 8 to 16 kilowords are written.
Kiloword data is written. Furthermore, RAM
D05 and D06 respectively have an address selection circuit 40
5 from the input data selection circuit 406 based on the address data AR04 and AR05 supplied from
4, IR05, interleaving data I2 is supplied and written. At this time, data of 0 to 8 kilowords of the data I2 is written to the RAMD05, and data of 8 to 16 kilowords is written to the RAMD06.

At the same time, the stored data is read from the RAMs D15 and D16, respectively, from the data OR1.
4, read as OR15, and supplied to the output data selection circuit 408 as one system of symbol data among the data of three symbols. RAMD11, D12
, The stored data is the data OR
10, and read as OR11, and supplied to the output data selection circuit 408 as another one-system symbol data out of the three-symbol data. Further, RAMD0
7, D08, respectively, the stored data is
The data is read as data OR06 and OR07, and is supplied to the output data selection circuit 408 as another one-system symbol data among the data of three symbols. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

Similarly, based on the address data AR14, AR15 supplied from the address selection circuit 405, the interleave data I0 is supplied as data IR14, IR15 from the input data selection circuit 406 to the RAMs D15, D16, respectively. Is written.
At this time, data of 0 to 8 kilowords of the data I0 is written to the RAMD15,
Is written with data of 8 to 16 kilowords. The RAMs D11 and D12 have address data AR supplied from the address selection circuit 405, respectively.
10, an input data selection circuit 406 based on AR11.
Supplies data I1 for interleaving as data IR10 and IR11, and is written. At this time,
Data of 0 to 8 kilowords of the data I1 is written to the RAMD11, and data of 8 to 16 kilowords is written to the RAMD12. further,
The RAMs D07 and D08 have address data AR06 and AR supplied from the address selection circuit 405, respectively.
07, the interleave data I2 is supplied and written as data IR06 and IR07 from the input data selection circuit 406. At this time, RAMD0
7, data of 0 to 8 kilowords of the data I2 is written, and RAMD08 is written of data of 8 to 16 kilowords.

At the same time, the stored data is read from the RAMs D13 and D14, respectively, as the data OR1.
2, and read as OR13, and supplied to the output data selection circuit 408 as one-system symbol data out of the three-symbol data. In addition, RAMD09, D10
, The stored data is the data OR
08, OR09, and is supplied to the output data selection circuit 408 as symbol data of another one of the three symbol data. Further, RAMD0
From 5, D06, the stored data is
The data is read out as data OR04 and OR05, and is supplied to the output data selection circuit 408 as another one-system symbol data among the data of three symbols. Note that the data reading is performed based on the address data supplied from the address selection circuit 405, as in the data writing.

[0764] By doing so, interleaver 100 performs pairwise interleave and delay processing on input data of three symbols having a data capacity of "32 kilowords or less" by TTCM performed by encoding apparatus 1. Can be applied.

As described above, the interleaver 100
Sharing the RAM for delay and the RAM for interleaving, switching the RAM to be used in accordance with the mode indicating the code configuration including the type of interleaving to be performed, and writing and / or reading data to and from the appropriate RAM Thus, a plurality of types of interleave processing and delay processing can be performed, and can be used for decoding various codes.

[0764] Various features of the interleaver 100 will be further described in "6."

[0764] 3. A decoder constructed by concatenating element decoders
No. Device Next, the decoding device 3 capable of performing iterative decoding is described by connecting the element decoders 50 described above.

As described above, the decoding device 3 is constituted by connecting a plurality of element decoders 50, and the PCCC, SCCC, TTCM and SCTCM
Can be repeatedly decoded.

As shown in FIG. 62, the decoding device 3 multiplies the product of the number of element codes and at least the number of repetitions N of iterative decoding, for example, 2 × N element decoders 50 ₁₁ , 50 ₁₂ ,
.., 50 _N1 and 50 _N2 . This decoding device 3
Is for estimating input data in the encoding device 1 by obtaining decoded data DEC by iterative decoding from a received value that is softly input due to the influence of noise generated on the memoryless communication channel 2. In this decoding device 3, the two consecutive element decoders 50 ₁₁ and 50 ₁₂ and the element decoders 50 _N1 and 50 _N2 respectively include the decoding device 3 shown in FIG. 3 or FIG. In the case of configuring ', 3'', iterative decoding for one time is realized. That is, when the encoding device 1 is the encoding device 1 ′ shown in FIG. 2 earlier, the element decoders 50 ₁₁ , 5
0 ₁₂ ,..., 50 _M1 , 50 _M2
The one represented by _i1 indicates that it is provided corresponding to the convolutional encoder 12 and performs the decoding process for the i-th iteration, and the one represented by the element decoder 50 _i2 is the convolutional encoder. 2 is provided corresponding to the decoding unit 14 and performs decoding processing for the i-th iteration. Also,
If the encoding device 1 is the encoding device 1 ″ shown in FIG. 4 earlier, the element decoders 50 ₁₁ , 50 ₁₂ ,.
Among _M1 and 50 _M2, the one represented by the element decoder 50 _i1 is provided corresponding to the convolutional encoder 33 that encodes the inner code and performs the i-th iteration of the decoding process. And the one represented by the element decoder 50 _i2 is
The figure shows that it is provided corresponding to the convolutional encoder 31 that encodes the outer code and performs the decoding process for the i-th iteration.

[0767] Specifically, the element decoder 50 _11, and a received value R, together with and the extrinsic information or interleaved data EXT as priori probability information is input, the erase information E
RS, prior probability information erasure information EAP, end time information TN
P, termination state information TNS, and an interleave start position signal ILS are input. Also, the element decoder 50
₁₁ , an output data selection control signal ITM and an interleave mode signal DIN are input.

[0768] Element decoder 50 ₁₁ outputs the delayed received value RN and soft-output INT obtained by performing the processing described above, the next stage erasure locator information ERSN next stage a priori probability information erasure information EAPN, Next stage end time information TNP
N, next stage termination state information TNSN, and next stage interleave start position signal ILSN. At this time,
Element decoder 50 _11, when the decoding apparatus 3 was previously decoder 3 shown in FIG. 3 ', based on the interleave mode signal DIN, the interleaver 100, to function as performing interleave processing . Further, the element decoder 50 _11, when the decoding apparatus 3 was previously decoder 3 shown in FIG. 5 '', based on the interleave mode signal DIN, the interleaver 100 performs deinterleaving Function as things. Further, the element decoder 50 ₁₁ selects one of the soft output SOL that is the log soft output Iλ output from the soft output decoding circuit 90 and the external information SOE based on the output data selection control signal ITM. , Data finally output as the soft output INT can be determined. Here, the soft output INT is assumed to be external information. Furthermore,
Element decoder 50 _11, if desired, can also output a decoded value hard decision information DHD and received value hard decision information RHD.

[0769] Further, the element decoder 50 _12, delayed received value outputted from the preceding element decoder 50 ₁₁ RN, soft-output I
NT, next-stage erasure position information ERSN, next-stage prior probability information erasure information EAPN, next-stage end time information TNPN, next-stage end state information TNSN, and next-stage interleave start position signal ILSN are received value R and external, respectively. Information or interleave data EXT, erasure information ERS, prior probability information erasure information EAP, termination time information TNP, termination state information TNS, and an interleave start position signal ILS are input. Further, the element decoder 50 _12, the output data selection control signal ITM and interleaving mode signal DIN is input.

[0770] Element decoder 50 _12, similarly to the element decoder 50 ₁₁ outputs the resultant delayed received value RN and the soft-output INT by performing the processing described above, the next stage erasure locator information ERSN, Next stage prior probability information deletion information EAP
N, next stage end time information TNPN, next stage end state information TNSN, and next stage interleave start position signal IL
Output SN. At this time, when the decoding device 3 is the decoding device 3 ′ shown in FIG. 3 earlier, the element decoder 50 ₁₂ performs the deinterleaving process on the interleaver 100 based on the interleave mode signal DIN. Function as things. Further, the element decoder 50 _12, when the decoding apparatus 3 was previously decoder 3 shown in FIG. 5 '', based on the interleave mode signal DIN, an interleaver 100, performs interleaving Function as Further, the element decoder 50 ₁₂ outputs the soft output decoding circuit 9 based on the output data selection control signal ITM.
By selecting one of the soft output SOL, which is the log soft output Iλ output from 0, and the external information SOE, the data finally output as the soft output INT can be determined. Here, the soft output INT is assumed to be external information. Furthermore, the element decoder 50 _12, if desired, can also output a decoded value hard decision information DHD and received value hard decision information RHD.

[0771] Such element decoder 50 _12, delayed received value RN, soft-output INT, next-stage erasure position information ERSN, next-stage a priori probability information erasure information EAPN, next-stage termination time information T
NPN, next-stage termination state information TNSN, and the next-stage interleave start position signal ILSN, respectively, and outputs to the next element decoder 50 _21, not shown.

Further, in the element decoder 50 _{N 1} , the delayed reception value RN output from the preceding element decoder 50 _N-12 (not shown), the soft output INT, the next-stage erasure position information ERSN, and the next-stage prior probability information are erased. Information EAPN, next stage end time information TN
PN, next-stage termination state information TNSN, and next-stage interleave start position signal ILSN are received value R, external information or interleave data EXT, erasure information ERS, prior probability information erasure information EAP, ending time information TNP, and ending, respectively. The state information TNS and the interleave start position signal ILS are input. Further, the output data selection control signal ITM and the interleave mode signal DIN are input to the element decoder 50 _N1 .

[0773] Element decoder 50 _N1, like element decoder 50 ₁₁ outputs the resultant delayed received value RN and the soft-output INT by performing the processing described above, the next stage erasure locator information ERSN, Next stage prior probability information deletion information EAP
N, next stage end time information TNPN, next stage end state information TNSN, and next stage interleave start position signal IL
Output SN. At this time, when the decoding device 3 is the decoding device 3 ′ shown in FIG. 3 earlier, the element decoder 50 _N1 performs an interleave process on the interleaver 100 based on the interleave mode signal DIN. Function as In addition, when the decoding device 3 is the decoding device 3 ″ illustrated in FIG. 5 earlier, the element decoder 50 _N1 performs the deinterleaving process on the interleaver 100 based on the interleave mode signal DIN. Function as things. Further, based on the output data selection control signal ITM, the element decoder 50 _N1 outputs a soft output SOL which is a log soft output Iλ output from the soft output decoding circuit 90.
Alternatively, by selecting one of the external information SOEs, the data finally output as the soft output INT can be determined. Here, the soft output INT is assumed to be external information. Furthermore, the element decoder 50 _N1 can output the decoded value hard decision information DHD and the received value hard decision information RHD as necessary.

[0774] Then, the final stage element decoder 50 _N2 has:
Delayed received value R output from preceding element decoder 50 _N1
N, soft output INT, next-stage erasure position information ERSN, next-stage prior probability information erasure information EAPN, next-stage end time information TNP
N, next-stage termination state information TNSN, and next-stage interleave start position signal ILSN are received value R, external information or interleaved data EXT, erasure information ERS, prior probability information erasure information EAP, termination time information TNP, and termination, respectively. The state information TNS and the interleave start position signal ILS are input. Also, the output data selection control signal ITM and the interleave mode signal DIN are input to the element decoder 50 _N2 .

The element decoder 50 _N2 outputs the soft output INT obtained by performing the above-described processing,
It outputs decoded value hard decision information DHD and received value hard decision information RHD as necessary. At this time, the element decoder 50 _N2
Causes the interleaver 100 to function as a device that performs deinterleaving processing based on the interleave mode signal DIN when the decoding device 3 is the decoding device 3 ′ shown in FIG. Also, the element decoder 50
_When the decoding device 3 is the decoding device 3 ″ shown in FIG. 5 earlier, _N2 causes the interleaver 100 to function as a device that performs an interleave process based on the interleave mode signal DIN. Further, the element decoder 50
_N2 selects a soft output INT and a log soft output Iλ as data to be output based on the output data selection control signal ITM, and outputs the log soft output Iλ as decoded data DEC as a final result. Note that the element decoder 50 _N2
If necessary, the delayed reception value RN and the soft output INT, the next-stage erasure position information ERSN, and the next-stage prior probability information erasure information EAP
N, next stage end time information TNPN, next stage end state information TNSN, and next stage interleave start position signal IL
SN can also be output.

[0776] Such a decoding device 3 includes element decoders 50 _i1 , 5 _i corresponding to each element encoder in the encoding device 1.
By providing 0 _i2 , a code having high decoding complexity is decomposed into elements having low complexity, and the element decoders 50 _i1 and 50 _i2 are decomposed.
The characteristics can be sequentially improved by the interaction between. Upon receiving the received value, the decoding device 3 receives 2 × N element decoders 50 ₁₁ , 50 ₁₂ ,..., 50 _N1 , 50 _N2.
Thus, the iterative decoding is performed with the maximum number of repetitions being N, and the decoded data DEC is output.

The decoding apparatus 3 performs iterative decoding with a maximum number of repetitions of N by connecting 2 × N element decoders 50 ₁₁ , 50 ₁₂ ,..., 50 _N1 , 50 _N2. However, the element decoders 50 ₁₁ , 50 ₁₂ ,.
By using the delay function provided in 50 _N1 and 50 _N2 , iterative decoding in which the number of repetitions is N or less can be performed as described later.

[0778] The decoding apparatus for decoding codes according to the TTCM method and the SCTCM method is the same as the decoding apparatus 3 described above.
In this case, the symbols of the in-phase component and the quadrature component are directly input as the reception values.

[0779] 4. Next, features of the element decoder 50 will be described for each feature.
The following features are provided as functions of the element decoder 50, and will be described using appropriately simplified drawings to clarify the concept of the features.

4-1 Code Likelihood Switching Function This is a feature of the above-described received value and prior probability information selection circuit 154. Receiving value and prior probability information selection circuit 154
Is provided for decoding an arbitrary code as described above.

[0781] For example, if the encoding device 1 uses PCCC or TT
In the case of performing coding by CM, as shown in FIG. 3, information to be input for performing soft output decoding includes a received value and a preceding interleaver or deinterleaver. External information supplied from the Also, for example, when the encoding device 1 performs encoding by SCCC or SCTCM, as shown in FIG. 5, information to be input to perform soft-output decoding of an inner code. Is the received value and the external information supplied from the preceding interleaver. The information to be input to perform the soft-output decoding of the outer code is the external information supplied from the deinterleaver and the value “0”. Is the prior probability information. Further, when the encoding device 1 performs puncturing, it is necessary to input information indicating that fact as prior probability information. As described above, in order to decode an arbitrary code, the element decoder 50 needs to select information necessary for performing soft-output decoding according to each code.

[0782] Therefore, the element decoder 50 is provided with the received value and prior probability information selection circuit 154, so that the information to be input to perform the soft output decoding among the input received value and the prior probability information is provided. Is appropriately selected according to the sign. By doing so, the element decoder 50
Is a versatile structure that can decode any code such as PCCC, SCCC, TTCM or SCTCM.

[0783] That is, the decoding device 3 sets the PCCC, SC
Any code such as CC, TTCM or SCTCM,
Decoding can be repeatedly performed only by connecting a plurality of element decoders 50 composed of LSIs having the same wiring. Therefore, the decoding device 3 can provide the user with high convenience even when performing an experiment, for example.

[0784] The element decoder 50 does not necessarily include the received value and prior probability information selection circuit 154 as the soft output decoding circuit 9
It is not necessary to provide inside or before 0. That is, the element decoder 50 determines, from the information from the preceding element decoder,
It is not necessary to adopt a configuration for selecting information necessary for soft output decoding. For example, the element decoder 50 selects the selectors 120 ₈ , 1
20 _9, 120 ₁₀ subsequent to providing the received value and a priori probability information selection circuit 154, delayed received value TRN and soft-output TINT
May be switched as the code likelihood to select information necessary for performing soft output decoding in the next-stage element decoder.

In the case of the reception value and prior probability information selection circuit 154 described with reference to FIG. 28, the two adjacent element decoders 50 _A and 50 _B constituting the decoding device 3 are simplified, for example, as shown in FIG. Can be represented as a configuration shown in FIG.
That is, the element decoder 50 _B is front element decoder 50 _A
And the soft output INT is input as external information or interleaved data EXT, and the received value TR is used as a signal line for delay and a decoded received value TSR. And a signal line of the same. In this case, the element decoder 5
Receiving value and prior probability information selection circuit 15 provided for 0 _B
4 is a selector 501 for selectively outputting the decoded reception value TSR and external information or interleaved data TEXT, and a selector 501 for selectively outputting the external information or interleaved data TELT.
This is represented as having a selector 502 that selectively outputs XT and prior probability information whose value is “0”.

[0786] On the other hand, the selectors 120 ₈ , 12
When the received value and prior probability information selection circuit 154 is provided at the subsequent stage of 0 ₉ and 120 ₁₀ , the two adjacent element decoders 50 _C and 50 _D constituting the decoding device 3 are simplified, for example, as shown in FIG. It can be represented as the configuration shown. That is, the reception value and prior probability information selection circuit 154 provided in the element decoder 50 _C substantially includes the delay reception value TRN
Selector 503 for selectively outputting the soft output TINT
And a selector 504 for selectively outputting the soft output TINT and the prior probability information whose value is “0”. In this case, the element decoder 50 _D, inputs the delayed received value RN outputted from the selector 503 in the preceding stage of the element decoder 50 _C as a received value R, a soft-output INT output from the selector 504 or the external information Input as interleaved data EXT,
The delay reception value TRN is input. In this case, the reception value and prior probability information selection circuit 154
3, 504 may be provided inside the interleaver 100.

As described above, the position where the element decoder 50 is provided with the reception value and prior probability information selection circuit 154 is not limited. However, as shown in FIG.
The configuration in which the information required for soft-output decoding in the next-stage element decoder is selected by the previous-stage element decoder is because it is necessary to separately input and output the received value delayed between the two element decoders. Requires a large number of pins.

4-2 Delay Function of Received Value This is a feature relating to the above-described received data and delay storage circuit 155 and interleaver 100.

[0789] For example, if the encoding device 1 is PCCC or TT
When coding by CM is performed, a received value needs to be input as information necessary for performing soft output decoding as shown in FIG. Also, for example, when the encoding device 1 performs encoding by SCCC or SCTCM, as shown in FIG. 5, as information necessary for performing soft-output decoding of an inner code, Received values need to be entered.

[0790] Therefore, as described above, the element decoder 50 includes the reception data and delay storage circuit 155, so that all the reception values TR including the reception values other than the decoding reception value TSR to be decoded are included. And delays at least the same time as the processing time required by the soft-output decoding circuit 90, and the interleaver 100 converts the data TDI, which is one of the received value TR or the delayed received value SDR, into at least the Lever 100
Is delayed by the same time as the required processing time, that is,
Delay by interleave length.

[0790] By doing so, the decoding device 3
Since there is no need to externally provide a delay circuit such as a RAM or a FIFO (First In First Out), the circuit scale can be reduced, and PCCC, SCCC, TTCM
Or an arbitrary code such as SCTCM,
It is possible to perform iterative decoding only by connecting a plurality of element decoders 50 made of I.

The element decoder 50 does not need to use the reception data and delay storage circuit 155 in order to delay the reception value by the same time as the processing time required by the soft output decoding circuit 90. May be separately provided. In this case, the element decoder 50 does not need to include a delay circuit in the soft output decoding circuit 90.

[0793] That is, two element decoders 50 _E and 50 _F adjacent to each other constituting the decoding device 3 can be simplified, for example, as shown in FIG. 65, in addition to the soft output decoding circuit 90 and the interleaver 100. , Delay circuit 5 for delaying the received value
10 are represented. Of course, the delay circuit 510 may be separated into a storage circuit that delays by the same time as the processing time required by the soft output decoding circuit 90 and a storage circuit that delays by the same time as the processing time required by the interleaver 100. . Thus, the element decoder 50
What is necessary is just to provide a delay line for delaying all the received values.

Of course, the element decoder 50 actually employs a method described later using the interleave 100 in order to realize the processing time required by the interleaver 100 and the simultaneous delay. Will be described later.

4-3 Decoded Received Value Selection Function This is a feature related to the decoded received value selection circuit 70 described above.
The decoded received value selection circuit 70 is provided for decoding an arbitrary code as described above.

[0796] The received value required for performing the soft output decoding differs depending on the code. Therefore, the element decoder 50
By providing the decoded reception value selection circuit 70, the reception value TSR to be decoded is appropriately selected from all the reception values TR according to the code. In other words, the decryption device 3
Are adjacent two element decoders 50 _G and 50 _H
In a simplified manner, for example, as shown in FIG. 66, in addition to the soft output decoding circuit 90, the interleaver 100, and the delay circuit 510 for delaying the received value, a predetermined delay line for delaying all the received values is used. Is provided as a decoded reception value selection circuit 70 for selectively extracting the signal line of FIG.

As described above, by selectively extracting a predetermined reception value from the reception values input to the delay circuit 510, the decoding device 3 can perform the PCCC, SCCC, TTC
Any symbol, such as M or SCTCM, is
It is possible to repeatedly perform decoding only by connecting a plurality of element decoders 50 made of SI.

[0798] 4-4 Decoding Storage Circuit and Delay Storage
Circuit sharing This is a feature of the above-described received data and delay storage circuit 155.

[0799] The reception data and delay storage circuit 155
As described above, the selected reception value and the prior probability information RAP, which are reception data used for decoding, and the reception value TR, which is delay data, are both stored. That is, the reception data and delay storage circuit 155 has a RAM having a capacity capable of storing both the selected reception value and the prior probability information RAP and the reception value TR, and is controlled by a control circuit (not shown). Then, writing and / or reading of each information is selectively performed. At this time, the reception data and delay storage circuit 155 writes the reception data DA used in the Iα calculation circuit 158 and the reception value TR in the same word, and stores them in synchronization with the timing at which the reception data DA is read. The received reception value TR is output as a delayed reception value PDR.

As described above, the decoding device 3 can reduce the circuit scale by sharing the storage circuits having different purposes of storage, and can reduce the PCCC, SCCC, and TTCM.
Or an arbitrary code such as SCTCM,
It is possible to perform iterative decoding only by connecting a plurality of element decoders 50 made of I.

4-5 Delay Function of Frame Head Information This is a feature relating to the above-described received data and delay storage circuit 155.

The edge signal TEILS indicating the head of the frame detected by the edge detection circuit 80 indicates the interleave start position. Therefore, the interleaver 100 needs to input a signal corresponding to the edge signal TEILS in synchronization with input of information obtained as a result of soft output decoding by the soft output decoding circuit 90.
Therefore, the edge signal TEILS is output to the soft output decoding circuit 9.
It must be delayed by the same time as the processing time required by 0.

Therefore, as described above, the element decoder 50 includes the reception data and delay storage circuit 155, and synchronizes the edge signal TEILS with the soft output decoding circuit 90 at the beginning of the frame of the information to be decoded. The input is delayed by the same time as the processing time required by the soft output decoding circuit 90. At this time, the reception data and delay storage circuit 155 writes the reception data DA used in the Iα calculation circuit 158 and the edge signal TEILS in the same word, and stores them in synchronization with the timing at which the reception data DA is read. The output edge signal TEILS is output as the delayed edge signal PDIL.

[0804] By doing so, the decoding device 3
Eliminates the need for externally providing a delay circuit for delaying an edge signal, and can share a circuit for delay and a circuit for storing received data, thereby reducing the circuit scale and improving convenience. PCCC, SCC
An arbitrary code such as C, TTCM or SCTCM can be repeatedly decoded only by connecting a plurality of element decoders 50 composed of LSIs having the same wiring.

The element decoder 50 receives the received data and the delay storage circuit 155 in order to delay the edge signal.
It is not necessary to use a soft output decoding circuit 9
0 may be separately provided. That is, the element decoder 50 may have a delay line for delaying the edge signal.

If the frame length of the information to be decoded is longer than the processing time required by the soft output decoding circuit 90, the element decoder 50 delays the edge signal based on a counter (not shown) for counting the decoding delay. Alternatively, it may be generated and output to the interleaver 100.

4-6 Soft Output Decoding Circuit or Interleave
A feature about the selector 120 _4, 120 ₇ was server standalone operation function described above, incidentally, the selector 120 ₃ described above, 120 _5, 1
To 20 ₆ is a characteristic related.

[0808] As described above, the element decoder 50 corresponds to the element encoder when the code is repeatedly decoded by the encoding apparatus 1. Decoding circuit 90 or interleaver 100
Has the function of switching the operation mode so as to perform only the above function. That is, as described above, the element decoder 50 generates the operation mode information CBF by the control circuit 60, and based on the operation mode information CBF, the selector 1
By performing the selecting operation of 20 _3, 120 _4, 120 _5, 120 _6, 120 _7, the soft-output decoding circuit 90 and interleaver 100, respectively, a mode for the ordinary soft-output decoding and interleaving, A mode in which only the soft output decoding circuit 90 performs normal soft output decoding processing and a mode in which only the interleaver 100 performs normal interleaving processing are realized.

[0809] Specifically, the selector 120 _3, as described above, on the basis of the operation mode information CBF, received value T
R and the delayed received value S supplied from the soft output decoding circuit 90.
One of DR and DR is selected. That is, the element decoder 50 determines whether the soft output decoding processing by the soft output decoding circuit 90 or the soft output decoding circuit 9 is to be performed by the selector 120 ₃ as a received value input to the interleaver 100.
It is possible to determine whether or not to use a delay that is the same as the processing time required by 0.

[0810] The selector 120 _4, as described above, on the basis of the operation mode information CBF, and external information or interleaved data TEXT, among the data TDLX supplied from the selector 120 _2, selects either . That is, the element decoder 50 selects the selector 1
20 by _4, as the external information or soft output is input to the interleaver 100, or used after subjected to soft-output decoding or soft-output decoding circuit 90 takes processing time and the time delay due to the soft-output decoding circuit 90 Can be determined.

[0811] Furthermore, the selector 120 _5, as described above, on the basis of the operation mode information CBF, the edge signal TEILS supplied from the edge detection circuit 80, the delay edge signal SDILS supplied from the soft-output decoding circuit 90
And one of them is selected. In other words, the element decoder 50 uses the soft output decoding circuit 90 or the soft output decoding circuit 9 as the edge signal input to the interleaver 100 by the selector 120 ₅ as an edge signal.
It is possible to determine whether or not to use a delay that is the same as the processing time required by 0.

Further, as described above, the selector 120 ₆ determines whether or not the delayed reception value SDR supplied from the soft output decoding circuit 90 and the interleave length delay reception supplied from the interleaver 100 are based on the operation mode information CBF. One of the values IDO is selected. That is, the element decoder 50, the selector 120 _6, as a received value to be output, whether to use those subjected to interleaving processing or the interleaver 100 takes processing time and the time delay by the interleaver 100 Can be determined.

[0813] The selector 120 _7, as described above, on the basis of the operation mode information CBF, the interleaver output data IIO supplied from the interleaver 100
When, among the data TDLX supplied from the selector 120 _2, selects either. That is, the element decoder 50, either by the selector 120 _7, as the external information or the soft output to be output, use having been subjected to the interleave processing or the interleaver 100 is the processing time and the time required delay due interleaver 100 Can be determined.

[0814] By doing so, the element decoder 50 can operate only the soft-output decoding circuit 90 in a mode requiring only soft-output decoding, for example. In a mode requiring only processing, only the interleaver 100 can be operated.

[0815] If the mode in which only the interleaver 100 performs the normal interleave processing is used, the element decoder 50 can also be used as an encoding device. This is because an element encoder in an encoding device usually includes a delay element and a combinational circuit, and can be easily realized by a so-called FPGA or the like. Accordingly, for example, when the encoding device 1 ′ shown in FIG. 2 is realized, the element decoder 50 can realize the convolutional encoders 12 and 14 by the control circuit 60 or the like. In addition, as described above, since the interleaver 100 also has a function as a delay circuit, the element decoder 50 implements the functions of the interleaver 13 and the delay unit 11 in the encoding device 1 'by the interleaver 100. be able to. Similarly, the element decoder 50 first has the configuration shown in FIG.
It is also possible to easily realize an encoding device that performs encoding by SCCC, such as the encoding device 1 ″ shown in FIG.

[0816] As described above, the element decoder 50 can switch the operation mode, and can provide abundant uses and excellent convenience besides iterative decoding.

[0817] Note that the element decoder 50 includes a selector 120
_3, 120 _4, 120 _5, 120 _6, 120 ₇ instead of switching the operation mode only, as and using the other selectors may be realized a wide operating mode of a different configuration.

[0818] is a 4-7 delay mode switching function above the selector 120 ₂ and features of the interleaver 100.

As shown in FIG. 3 or FIG. 5, iterative decoding is a single decoding with a combination of the same number of element decoders as the number of element encoders in the encoding device 1. That is, in the iterative decoding, at least two or more element decoders are set as one set, and decoding is performed once. In the iterative decoding, a final decoding result is obtained by setting the number of repetitions to a plurality.

Here, in order to determine the optimum number of repetitions for various codes, it is usually necessary to perform an experiment in which the number of repetitions is changed. In this case, an experiment can be performed if a plurality of decoding devices are configured by connecting a number of element decoders corresponding to the number of repetitions. Further, one decoding device is configured by connecting a number of element decoders capable of performing iterative decoding with an arbitrary number of repetitions, and taps are performed from the element decoders corresponding to a desired number of repetitions equal to or less than the number of repetitions. It is also possible to conduct an experiment by pulling out.

[0821] However, to perform the former experiment, it is necessary to construct a huge number of decoding devices, which may require a great deal of labor. Also, when performing the latter experiment, the circuit scale of the decoding device increases,
Since the decoding delay changes according to the number of repetitions, it is not desirable to compare the decoding results according to the change in the number of repetitions.

[0822] Therefore, as described above, the element decoder 50 generates the operation mode information CBF by the control circuit 60 and, based on the operation mode information CBF, selects the selector 1
Together to perform selecting operation of 20 _2, by causing the address control by the interleaver 100, the input data, at least the soft-output decoding circuit 90
Is the delay between the processing time and the simultaneous delay required, at least the delay between the processing time required by the interleaver 100 and the simultaneous delay, or
At least soft output decoding circuit 90 and interleaver 10
A plurality of delay modes for delaying the processing time required simultaneously with zero are realized.

[0823] Specifically, the selector 120 _2, as described above, the operation mode information CBF is, at least the soft-output decoding circuit 90 takes processing time and delay of the same time, the same as the processing time at least the interleaver 100 is required If the delay mode indicates at least one of the delay of the time and the delay at the same time as the processing time required by the soft output decoding circuit 90 and the interleaver 100, the delay external information SDEX is selected. And output the operation mode information CBF at least in the soft output decoding circuit 90 and / or
Alternatively, when the normal mode in which the processing by the soft output decoding circuit 90 and / or the interleaver 100 is performed without delay by the interleaver 100 is indicated, the data TLX, that is, the decoding result by the soft output decoding circuit 90 Select and output. In other words, the element decoder 50 uses the selector 120 _{2 to} output at least the soft output decoding circuit 90 and / or
Alternatively, it is possible to determine whether or not to delay the processing time required by the interleaver 100 at the same time.

Also, as described above, when the operation mode information CBF indicating the delay mode is input, the interleaver 100 performs address control, thereby
It can function as a delay circuit. This will be described later.

[0825] By doing so, the decoding device 3
As a concatenated number of element decoders that can perform iterative decoding for a possible number of repetitions,
It is possible to perform iterative decoding with an arbitrary number of repetitions. For example, if the encoding device 1 is the encoding device 1 ′, 1 ″ previously shown in FIG. 2 or FIG. 4 and the decoding device 3 is configured by connecting 200 elementary decoders, The device 3 can perform iterative decoding with a maximum of 100 repetitions. In the decoding device 3, when performing the iterative decoding with the number of repetitions of 20, the 40th element decoder from the head performs ordinary soft output decoding processing and interleaving processing, and the remaining 160 element decodings. The device may perform the operation in the delay mode that delays at least the processing time required by the soft output decoding circuit 90 and the interleaver 100 at the same time.

[0827] As described above, the decoding device 3 has a plurality of delay modes, and by switching between these delay modes, the element decoder 50 composed of LSIs with the same wiring is used.
, It is possible to perform iterative decoding with the number of repetitions changed without changing the overall decoding delay, and to perform PCCC, SCCC, TTCM or SCC.
An arbitrary code such as CTCM can be repeatedly decoded at a desired number of repetitions.

[0827] Note that the element decoder 50 includes a selector 120
Rather than switching the delay mode by only ₂ , the selector 120 that performs a selection operation based on the operation mode information CBF in order to operate the soft output decoding circuit 90 or the interleaver 100 alone as shown in, for example, “4-6”. ₄ ,
120 ₇ , and additionally, selectors 120 ₃ , 120
By using multiple selectors such as ₅ , 120 ₆
Various delay modes may be realized.

4-8 Next-Stage Information Generation Function This is a feature related to the control circuit 400 in the control circuit 60 and the interleaver 100 described above.

In the case where the decoding device 3 is configured by connecting a plurality of element decoders, it is necessary that each element decoder is provided with various kinds of information regarding codes. The various types of information include a termination time and a termination state as termination information, a puncture pattern as erasure information, and head information of a frame. In order to provide such information to each element decoder, it is conceivable to generate necessary information by an external control circuit or the like, but this leads to an increase in the number of components and an increase in the board area.

[0832] Therefore, the element decoder 50 generates and outputs necessary information for the next-stage element decoder by using the interleaver 100 capable of grasping information such as the head information of the frame and the interleave length. I do. That is, as described above, the element decoder 50 uses the control circuit 60 to control the end position information C which is static information.
It generates NFT, termination period information CNFL, termination state information CNFD, puncturing cycle information CNEL, and puncturing pattern information CNEP. Then, the element decoder 50 outputs the termination position information CNFT, termination period information CNFL, termination state information CNFD, and puncture cycle information CNEL generated by the control circuit 60.
And puncturing pattern information CNEP are input to interleaver 100,
And the termination time information IGS and the termination state information IGS based on these information.
, Erase position information IGE and interleaver non-output position information INO. And interleaver 10
0 is the control circuit 60 under the control of the control circuit 400.
After the time corresponding to the interleave length elapses after the information is input, the generated end time information IGT, end state information IGS, erase position information IGE, and interleaver non-output position information INO are output. Also, interleaver 1
00, the interleave start position signal TIS supplied from the selector 120 _5, interleaving length fraction, i.e., delayed by the processing time and the same time interleaver 100 is required to generate and output a delayed interleave start position signal IDS to.

[0831] By doing so, the element decoder 50 outputs the generated termination time information IGT, termination state information IGS, erasure position information IGE, interleaver non-output position information INO, and delay interleave start position signal IDS. Can be easily output in synchronization with the beginning of the frame.

[0832] As described above, the decoding device 3 does not need to externally provide a control circuit for generating various types of information, can reduce the number of components, and can use the PCCC, SCCC, and TCC.
An arbitrary code such as TCM or SCTCM can be repeatedly decoded only by connecting a plurality of element decoders 50 composed of LSIs having the same wiring.

[0832] The element decoder 50 does not generate various kinds of information by the control circuit 400 in the interleaver 100 and outputs it in synchronization with the head of the frame. May be generated. That is, the decoding device 3 includes a control circuit in which each element decoder generates various information such as termination information and erasure information, instead of generating information necessary for the next-stage element decoder in the preceding element decoder. The information may be generated in synchronization with the head of the frame of the input data.

4-9 System Verification Function This is a feature related to the selectors 120 ₈ , 120 ₉ , 120 ₁₀ and the signal line 130 described above.

The element decoder 50 has a huge number of pins, for example, several hundreds. Therefore, when the decoding device 3 is configured by connecting a plurality of the element decoders 50, a state of conduction failure due to, for example, a solder failure or the like is likely to occur.

[0832] Therefore, the element decoder 50 receives the externally input received value TR, external information or interleaved data TEXT, erasure information TERS, and prior probability information erasure information T.
EAP, termination time information TTNP, termination state information TT
NS and a signal line 130 for bundling a signal line for transmitting each of the interleave start position signal TILS and communicating with the outside. By transmitting a through signal through the signal line 130, system verification such as continuity inspection can be performed. Do.

At this time, the element decoder 50 controls the control circuit 6
0, the verification mode information CTHR is generated, and based on the verification mode information CTHR, the selectors 120 ₈ , 12
By performing the selecting operation of the 0 _9, 120 _10, to switch to the verification mode for performing verification of the system.

[0838] Specifically, the selector 120 _8, as described above, when verification mode information CTHR were indicates the verification mode, select the through signal transmitted by the signal line 130, delay The received value RN is output as a received value RN to a terminal to which the received value R is input in a subsequent element decoder.

[0839] The selector 120 _9, as described above, when verification mode information CTHR were indicates the verification mode, select the through signal transmitted by the signal line 130, as soft-output INT , External information or interleaved data EXT at the next element decoder.
Is output to the input terminal.

[0840] Furthermore, the selector 120 _10, as described above, when verification mode information CTHR were indicates the verification mode, select the through signal transmitted by the signal line 130, the next stage termination time Information TNPN, next stage termination state information TNSN, next stage erase position information ERS
N, the next-stage prior probability information erasure information EAPN, and the next-stage interleave start position signal ILSN in the next-stage element decoder, the termination time information TNP, the termination state information TNS, the erasure information TERS, and the prior probability information erasure information TE
The AP and the interleave start position signal ILS are output to terminals to which they are input.

[0841] As described above, the decoding device 3 has a function of outputting an input signal from the outside to the outside as it is, and by inputting / outputting a through signal in the verification mode, easily determines a conduction failure portion. Therefore, even when a plurality of element decoders having a large number of pins are connected, the system can be easily verified, and excellent convenience can be provided.

[0842] 5. Features of Soft Output Decoding Circuit Next, features of the soft output decoding circuit 90 will be described. The following features are provided as functions of the soft-output decoding circuit 90, and will be described with reference to appropriately simplified drawings in order to clarify the concept of the features.

5-1 How to Provide Code Information This is a feature of the code information generation circuit 151 described above.
The element decoder 50 is capable of soft-output decoding a code by an arbitrary element encoder such as the convolutional encoder shown in FIGS. 14 to 17 with the same configuration regardless of the code. . To this end, the element decoder 50 has the following four features.

[0844] 5-1-1 Input / output parameters of all branches on the trellis
Turn calculation example of the trellis in the previously indicated convolutional encoder 14, as shown in an example in FIG. 19, a structure in which two paths to reach from each state to the state at the next time, It has a structure having a total of 32 branches. The trellis in the convolutional encoder shown in FIG. 15 has a structure in which four paths reach from each state to the state at the next time, as shown in FIG. Will be obtained. Further, the trellis in the convolutional encoder shown in FIG. 16 has a structure in which four paths reach from each state to the state at the next time, as shown in FIG. Will be obtained. Furthermore, the trellis in the convolutional encoder previously shown in FIG. 17 has a structure in which four sets of parallel paths arrive from each state to the state at the next time, as shown in FIG. It will have 32 branches. In addition, these convolutional encoders have a variable number of memories depending on the connection method, but are trellises having 32 or less branches.

The soft output decoding circuit 90 focuses on the fact that the number of branches on the trellis is equal to or less than a predetermined value, and considers the branches on the trellis mainly without considering the code configuration. The input / output pattern of the branch is calculated, and this information is used in calculating the log likelihood Iγ and the log soft output Iλ. Specifically, the soft output decoding circuit 90 calculates the input / output patterns of all the branches on the trellis by the code information generation circuit 151, and uses this information as the branch input / output information BIO and the Iγ distribution circuit 157 and the soft output. It is supplied to the calculation circuit 161.

[0846] The branch input / output information BIO contains the log likelihood I
This is information calculated along the time axis from the transition source state to the transition destination state in order to calculate α. That is, the branch input / output information BIO is information based on the branch input as viewed from the state of the transition destination. On the other hand, in the soft output decoding circuit 90, in order to calculate the log likelihood Iβ, branch input / output information is calculated from the state of the transition destination to the state of the transition source along the time axis in reverse order. This is necessary, but this is determined by the branch input / output information calculation circuit 223 in the Iγ distribution circuit 157.
It is calculated as I. That is, the branch input / output information BI is
This information is based on the branch output from the state of the transition source.

[0849] By doing so, the element decoder 50 can decode an arbitrary trellis code having a predetermined number of branches or less with the same configuration. That is, the element decoder 50 normally performs decoding based on a unique trellis corresponding to each code configuration.
By paying attention to the branches on the trellis, it is possible to decode an arbitrary code regardless of the code configuration. At this time, the element decoder 50 can decode even when the element encoder is a non-linear code.

[0848] Here, a case has been described in which a code having a trellis structure having 32 branches or less is decoded. However, it is needless to say that the element decoder 50 is not limited to the number of branches. Nor.

[0849] Hereinafter, three specific examples will be given as branch numbering in the method shown here.

[0850]5-1-2 Transition source state and transition destination state
Numbering to and from states In a Bozencraft convolutional encoder, the delay is
Since the data is stored in time series for the extension element,
The transition destination state is limited. To explain specifically
Using the convolutional encoder shown in FIG.
If the state of the transition source is “0000”,
Shift register 201_Three, Shift register 201_TwoAnd sif
Register 201₁Will be the next time
201 _Four, Shift register 201_ThreeAnd shift register
201_TwoTransition to the contents of the
Ports are limited to “0000” and “0001”. This
Like the convolutional encoder of the Bozencraft type.
State when the number of memories is determined.
Is determined. Therefore, the bozen craft type convolution
In a coder only, an arbitrary stage can be used regardless of the code configuration.
Easily finds the presence or absence of a branch connecting a state with any state
be able to.

The soft output decoding circuit 90 uses the code information generation circuit 151 to uniquely number the branch connecting the transition source state and the transition destination state. That is, when decoding a Bosencraft type convolutional code, the soft output decoding circuit 90 performs branch numbering using the uniqueness of the trellis. Then, the soft output decoding circuit 90 calculates the input / output pattern of each numbered branch, and uses this information as the branch input / output information BIO obtained along the time axis, the Iγ distribution circuit 157 and the soft output calculation circuit 161. To supply. Also, the soft output decoding circuit 90 calculates Iγ
The branch input / output information calculation circuit 223 in the distribution circuit 157 calculates the branch input / output information BI obtained in the reverse order to the time axis based on at least the memory number information MN and the branch input / output information BIO, and obtains Iγ for Iβ0. Distribution circuit 22
4 ₁ and Iγ is supplied to the distribution circuit 224 ₂ for Aibeta1.

[0852] More specifically, the soft output decoding circuit 90 performs the decoding of the Bozencraft convolutional encoder whose coding rate is represented by "1 / n" shown in FIG. 67, each branch is uniquely numbered according to the number of memories, and branch input / output information BIO along the time axis is calculated, as shown in FIG. 67, for example. That is, when decoding the convolutional encoder having the number of memories of “4” by the code information generation circuit 151, the soft output decoding circuit 90 performs numbering as shown in FIG. When decoding the convolutional encoder having the number "3", numbering is performed as shown in FIG. 3B, and when decoding the convolutional encoder having the memory number "2", Numbering is performed as shown in FIG. 3C, and when decoding is performed by a convolutional encoder having a memory number of “1”, numbering is performed as shown in FIG. In the figure, for example, numbers “0” and “1” are assigned to two branches input to a state having a state number “0”, and input to a state having a state number “1”. The numbers "2" and "3" are assigned to the two branches.

On the other hand, the soft-output decoding circuit 90 uses the branch input / output information calculation circuit 223 to uniquely number each branch according to the number of memories, as shown in FIG. 68, for example. The branch input / output information BI along the reverse order is calculated. That is, when decoding the convolutional encoder having the number of memories of “4” by the branch input / output information calculation circuit 223, the soft output decoding circuit 90 performs numbering as shown in FIG. When decoding the convolutional encoder having the number of memories of "3", the numbering is performed as shown in FIG. 2B, and decoding of the convolutional encoder having the number of memories of "2" is performed. Are numbered as shown in FIG. 11C, and when decoding is performed by a convolutional encoder having a memory number of "1", numbering is performed as shown in FIG. In the figure, for example, numbers “0” and “1” are assigned to two branches that are output from the state with the state number “0”, and output from the state with the state number “1”. The numbers “2” and “3” are assigned to each of the two branches.

[0854] Also, the soft output decoding circuit 90 first
When decoding the Bozencraft type convolutional encoder whose coding rate is represented by “2/3” as shown in FIG. 69, for example, as shown in FIG. Accordingly, each branch is uniquely numbered, and branch input / output information BIO is calculated along the time axis. That is, the soft output decoding circuit 90
When decoding is performed by the convolutional encoder having the number of memories of "3", the numbering is performed as shown in FIG. 2A, and decoding of the convolutional encoder having the number of memories of "2" is performed. If so, numbering is performed as shown in FIG.
In the figure, for example, “0”, “1”,
Numbers “2” and “3” are assigned, and “4”, “5”, and “4” are assigned to each of the four branches input to the state having the state number “1”.
Numbers “6” and “7” are assigned.

On the other hand, the soft-output decoding circuit 90 uses the branch input / output information calculation circuit 223 to uniquely number each branch according to the number of memories, as shown in FIG. 70, for example. The branch input / output information BI along the reverse order is calculated. That is, when decoding the convolutional encoder with the number of memories of “3” by the branch input / output information calculation circuit 223, the soft output decoding circuit 90 performs numbering as shown in FIG. When decoding the convolutional encoder having the number of memories of "2", numbering is performed as shown in FIG. In the figure, for example, numbers “0”, “1”, “2”, and “3” are assigned to four branches output from the state with the state number “0”, and the state number is changed. Numbers “4”, “5”, “6”, and “7” are assigned to the four branches output from the state “1”.

[0856] By doing so, the soft output decoding circuit 90 can uniquely grasp the transition source state and the transition destination state from the branch numbers, regardless of the code configuration. Therefore, for example, when numbering is performed depending on the sign, such as numbering of branches when a certain input is made in a certain state, the transition source state and the transition destination state need to be uniquely determined. However, the soft-output decoding circuit 90 uses the uniqueness of the trellis to number the branches depending on the state, so that the relationship between the branch numbers and the input / output patterns is uniquely determined. Decoding can be performed with a simple control.

[0857] Specific examples of branch numbering according to this method include those shown in Figs. 67 to 70. The branch connecting the transition source state and the transition destination state is uniquely numbered. If given, specific numbers are not limited to those shown in FIG.

5-1-3 Numbering along Time Axis and
For numbers other than the Bozencraft type convolutional encoder such as the Massy type, the data is arranged in a time series with respect to the delay element, like the Bozencraft type convolutional encoder. Since the state is not held, the state of the transition destination is not limited. To illustrate, the use of convolutional encoder previously shown in FIG. 22, when the source state is "000", the contents of the shift register 205 ₃ in the next time, before not the contents of the shift register 205 ₂ is directly shifts at time, also, the shift register 205 at the next time ₂
The contents, the contents of the shift register 205 ₁ is not intended to be directly proceeds before time. For this reason, the state of the transition destination is not limited to the number of memories, but varies according to the code configuration.

The soft-output decoding circuit 90 uses the code information generation circuit 151 to perform numbering on the basis of the branch input as viewed from the transition destination state, and to perform the input / output pattern for each numbered branch. And supplies this information to the Iγ distribution circuit 157 and the soft output calculation circuit 161 as branch input / output information BIO obtained along the time axis. Then, the soft output decoding circuit 90 separately calculates the transition source state based on the code configuration by the control signal generation circuit 240 in the Iα calculation circuit 158, and supplies the transition source state to the addition / comparison / selection circuit 242 as the control signal PST. Further, the soft-output decoding circuit 90 outputs the output from the state of the transition source by the branch input / output information calculation circuit 223 in the Iγ distribution circuit 157 based on at least the generation matrix information CG affecting the output at each time. Numbering is performed on the basis of the number of branches, and an input / output pattern for each numbered branch is calculated. This information is used as branch input / output information BI obtained along the time axis in the reverse order.
Iγ distribution circuit 224 ₁ for Iβ1 and Iγ distribution circuit 22 for Iβ1
4 for supplying _2. Then, the soft output decoding circuit 90 calculates Iβ
The state of the transition destination is separately calculated based on the code configuration by the control signal generation circuit 280 in the calculation circuit 159, and the Iβ0 addition / comparison / selection circuit 2 is used as the control signal NST.
81 and an Iβ1 addition / comparison / selection circuit 282.

[0859] Specifically, the soft-output decoding circuit 90 performs decoding of the Massy-type convolutional encoder whose coding rate is represented by "2/3" shown in FIG. For example, as shown in FIG. 71, the code information generating circuit 151 numbers each branch according to the number of memories and calculates branch input / output information BIO along the time axis. That is, when decoding the convolutional encoder having the number of memories of “3” by the code information generation circuit 151, the soft output decoding circuit 90 performs numbering as shown in FIG. When decoding the convolutional encoder having the number "2", numbering is performed as shown in FIG. In the figure, for example, “0”, “1”,
Numbers “2” and “3” are assigned, and “4”, “5”, and “4” are assigned to each of the four branches input to the state having the state number “1”.
Numbers “6” and “7” are assigned. Here,
Although a specific example of the numbering method for the four branches input to each state is not described in detail, the soft output decoding circuit 9
For 0, for example, a unique number can be assigned to each branch using the information of the input pattern and, if necessary, the information of the state of the transition source.

On the other hand, in the soft output decoding circuit 90, the branch input / output information calculation circuit 223 numbers each branch according to the number of memories, for example, as shown in FIG. The branch input / output information BI is calculated. That is, when decoding the convolutional encoder with the number of memories of “3” by the branch input / output information calculation circuit 223, the soft output decoding circuit 90 performs numbering as shown in FIG. When decoding the convolutional encoder having the number of memories of "2", numbering is performed as shown in FIG. In the figure, for example, “0”, “0” is assigned to each of the four branches output from the state having the state number “0”.
Numbers “1”, “2”, and “3” are assigned, and “4”, “5”, “6”, and “7” are assigned to four branches output from the state with the state number “1”. "Number.
Although a specific example of the numbering method for the four branches input to each state is not described in detail here,
The soft output decoding circuit 90 can perform unique numbering for each branch using, for example, only information on the input pattern.

[0832] As described above, the soft output decoding circuit 90 separately performs numbering along the time axis and numbering along the reverse order of the time axis for each state to calculate an input / output pattern. At the same time, the state of the transition source and the state of the transition destination are calculated based on the code configuration. By doing so, the soft-output decoding circuit 90 can decode even a Massy-type convolutional code in which the shape of the trellis changes according to the parameter of the element code.

[0863] Specific examples of branch numbering by this method include those shown in Figs. 71 and 72, but the specific numbers are not limited to those shown in Fig. 71. In addition, here, the case where the decoding of the Massy-type convolutional encoder is performed has been described.
The present invention can be applied to any code including a non-linear code other than the Massy type convolutional code. Of course, this method can also be applied to a Bozencraft type convolutional code.

5-1-4 Based on Uniqueness of Entire Trellis
If the number of input bits in the numbering code is less than the number of memories,
There may be a trellis structure in which a path arrives from each state on the trellis to all states at the next time. In other words, when the trellis has a structure in which the path reaches from each state to all the states at the next time, the state number of the transition source and the state number of the transition destination are uniquely grasped regardless of the code configuration. be able to.

[0865] The soft output decoding circuit 90 uses the code information generation circuit 151 to number all branches in consideration of the entire trellis based on the uniqueness of the entire trellis structure. Then, the soft output decoding circuit 90
An input / output pattern for each numbered branch is calculated, and this information is supplied to the Iγ distribution circuit 157 and the soft output calculation circuit 161 as branch input / output information BIO obtained along the time axis. Further, the soft output decoding circuit 90 includes the Iγ distribution circuit 1
The branch input / output information calculation circuit 223 calculates the branch input / output information BI obtained in the reverse order to the time axis based on at least the memory number information MN and the branch input / output information BIO, and outputs the Iγ distribution circuit for Iβ0. 224 ₁ and I
It is supplied to the β1 Iγ distribution circuit 224 ₂ .

[0866] More specifically, the soft output decoding circuit 90 performs the decoding of the Massy type convolutional encoder whose coding rate is "3/3" shown in FIG. As shown in, for example, FIG. 73, the code information generation circuit 151 uniquely numbers each branch according to the number of memories, and calculates branch input / output information BIO along the time axis. That is, the soft output decoding circuit 90
When decoding is performed by the convolutional encoder having the number of memories of "2", the numbering is performed as shown in FIG. 2A, and decoding of the convolutional encoder having the number of memories of "1" is performed. If so, numbering is performed as shown in FIG.
In FIG. 9A, for example, the state number is “0”.
, "0, 1", "2, 3", "4"
5 ”and“ 6, 7 ”, and the state number is“ 1 ”.
, "8, 9", "10, 11",
The numbers “12, 13” and “14, 15” are assigned.
Here, a specific example of the numbering method for a plurality of sets of branches input to each state and the numbering method for each parallel path in one set of branches will not be described in detail. For example, the unit 90 can perform a case classification based on the generation matrix information CG, and in each case, can use the information of the input pattern and the information of the state of the transition source to perform unique numbering for each branch.

On the other hand, the soft-output decoding circuit 90 uses the branch input / output information calculation circuit 223 to uniquely number each branch according to the number of memories, as shown in FIG. 74, for example. The branch input / output information BI along the reverse order is calculated. That is, when decoding the convolutional encoder having the number of memories of “2” by the branch input / output information calculation circuit 223, the soft output decoding circuit 90 performs numbering as shown in FIG. When decoding a convolutional encoder having a memory number of "1", numbering is performed as shown in FIG. In FIG. 1A, for example, each of the eight branches output from the state with the state number “0” is represented by 2.
"0, 1", "2,
Numbers 3 ”,“ 4, 5 ”,“ 6, 7 ”are assigned, and four sets of each branch obtained by bundling each of the eight branches output from the state with the state number“ 1 ”are obtained. "8, 9", "1" on the branch
Numbers 0, 11 "," 12, 13 "," 14, 15 "are given here. Here, a numbering method for a plurality of sets of branches input to each state, and a set of Although a specific example of the numbering method for each parallel path in the branch is not described in detail, the soft-output decoding circuit 90 performs, for example, classification based on the generator matrix information CG, and in each case, the input pattern information and the transition. By using the information of the original state, a unique number can be assigned to each branch.

As described above, when the trellis has a trellis structure in which a path reaches from each state to all the states at the next time, the soft output decoding circuit 90 determines based on the uniqueness of the entire structure of the trellis. By performing numbering for all the branches, the transition source state and the transition destination state can be uniquely grasped from the branch numbers regardless of the code configuration. Therefore, the soft output decoding circuit 90 can uniquely grasp the state number of the transition source and the state number of the transition destination, and can perform decoding with simple control.

[0869] Specific examples of branch numbering according to this method include those shown in Figs. 73 and 74. The branches connecting the transition source state and the transition destination state are uniquely numbered. If given, specific numbers are not limited to those shown in FIG.

5-2 Termination Information Input Method This is a feature of the termination information generation circuit 153 described above.
When codes based on PCCC, SCCC, TTCM, and SCTCM are repeatedly decoded, a termination process is indispensable. Therefore, the element decoder 50 generates termination information by the following two methods.

5-2-1 Termination of Information for the Number of Input Bits
As you enter the above-mentioned period, at the bow Zen Craft-type convolutional encoder, destination state is limited. Therefore, as described above, when terminating a Bozencraft type convolutional code, the soft output decoding circuit 90 inputs information corresponding to the number of input bits to the convolutional encoder for the termination period as termination information. Specifies the termination state.

Specifically, when the number of input bits is “1” and the code of the Bozencraft convolutional encoder having the number of memories of “2” ends in the state represented by “00”, , The soft output decoding circuit 90 generates one bit “0” corresponding to the number of input bits as termination state information TSM in one time slot by the termination information generation circuit 153, as shown in FIG. By generating the termination state information TSM for two time slots, ie, two minutes, the termination state “00” can be specified.

[0873] In this way, the element decoder 50 can perform termination processing of an arbitrary Bozencraft convolutional code whose coding rate is represented by k / n. The element decoder 50 can be configured to minimize the number of pins for inputting termination information. For example, even when the termination pattern is long and continuous termination processing is required,
Termination information can be appropriately generated, and inconsistency in termination information input can be avoided.

[0887] 5-2-2 Information 1 indicating termination state
As you enter the above-mentioned time slot, for example, in the Massey-type convolution encoder such baud Zen Crafts type convolutional encoder other elements encoder, as the convolutional encoder for Beau Zen craft type, the transition destination Is not limited. Therefore, when a code other than the Bozencraft type convolutional code is terminated, it is not possible to input information for the number of input bits for the termination period as termination information.

[0875] Thus, as described above, the soft output decoding circuit 90 sets the information indicating the termination state to 1 as termination information.
The closing state is specified by inputting in the time slot.

[0876] Specifically, when the number of input bits is "1" and the code of the Massy convolutional encoder having the number of memories of "2" is terminated to the state represented by "00", The soft-output decoding circuit 90 includes a termination information generation circuit 15.
3, for example, as shown in FIG. 76, two bits “00” indicating the termination state are generated as termination state information TSM in one time slot, thereby obtaining “0”.
A termination state of "0" can be specified.

[0887] By doing so, the element decoder 50 can perform termination processing for any trellis code including a Massy convolutional code whose trellis structure changes according to the code configuration. Of course, the element decoder 50 can also perform termination processing of the Bozencraft type convolutional code using this method. This method is also applicable to decoding other than soft output decoding such as so-called Viterbi decoding.

5-3 Processing of Erase Position This is a feature of the above-described received value and prior probability information selection circuit 154.

In soft output decoding, it is usually necessary to separately store information indicating a position where no code output exists due to puncturing, at least until the calculation of the log likelihood Iγ, and a storage circuit for storing this information. It was necessary to take measures such as providing

[0880] Therefore, as described above, the soft output decoding circuit 90 outputs the code output by the received value and prior probability information selection circuit 154 based on the internal erasure position information IERS supplied from the internal erasure information generation circuit 152. The non-existing position is replaced with a symbol whose likelihood is “0”. That is, the soft output decoding circuit 90 determines that the probability of whether the bit corresponding to the position where no code output exists is “0” or “1” is “１ ／”, and thereby the decoding operation is performed. Produces a situation equivalent to being erased without affecting.

[0881] By doing so, the element decoder 50 does not need to separately include a storage circuit for holding information indicating a position where no code output exists, and thus the circuit scale can be reduced.

5-4 Calculation and Distribution of Log Likelihood Iγ This is a feature of the above-mentioned Iγ calculation circuit 156 and Iγ distribution circuit 157. As described above, the element decoder 50
Can soft-decode a code by an arbitrary element encoder such as the convolutional encoder previously shown in FIGS. 14 to 17 with the same configuration regardless of the code. To this end, the element decoder 50 is
The calculation and distribution of the log likelihood Iγ have the following four features.

5-4-1 Log Likelihood for All Input / Output Patterns
The calculation / distribution soft output decoding circuit 90 of the degree Iγ calculates the log likelihood Iγ of all possible input / output patterns by the Iγ calculation circuit 156 in order to realize decoding of an arbitrary code. By 157, distribution is performed according to the input / output pattern determined according to the code configuration.

Here, consider the case where the convolutional encoder shown in FIGS. 14 to 17 is decoded first. The trellis in each of these convolutional encoders has a structure having 32 or less branches, and has at most 32 input / output patterns. Therefore, the soft output decoding circuit 9
0 is an Iγ calculation circuit 156 as schematically shown in FIG.
The information / sign Iγ calculation circuit 221 in
All the input / output patterns are calculated. Note that, in the figure, “Iγ (00/000)” indicates the log likelihood Iγ corresponding to the branch whose input data / output data is “00/000” in the elementary encoder. The soft-output decoding circuit 90 outputs the Iγ distribution circuit 224 ₃ for Iα, the Iγ distribution circuit 224 ₁ for Iβ0, or the Iγ for Iβ1 in the above-mentioned Iγ distribution circuit 157 according to the input / output pattern determined according to the code configuration. 32 selectors 520 ₁ , 520 ₂ ,... Corresponding to the respective distribution circuits 224 _2.
, 520 ₃₂ , 32 types of log likelihood Iγ (00/000), Iγ (01/000),.
, Iγ (11/111), one log likelihood Iγ is selected, and a predetermined process is performed on the 32 types of log likelihood Iγ obtained by selection. 1, ...
·, Log likelihood Iγ (0), Iγ (1),
.., And distributed and output as Iγ (31).

[0885] In this way, the element decoder 50 can decode an arbitrary trellis code having a predetermined number of branches or less with the same configuration. In particular, this method is effective when the number of input / output patterns is small and the number of branches on the trellis is large.

5-4-2 At least a part of input / output patterns
Calculation and distribution of the log likelihood Iγ of the I / N circuit In the case of the method shown in “5-4-1”, the Iγ distribution circuit 224 ₃ for Iα in the Iγ distribution circuit 157 and Iγ
The β0 Iγ distribution circuit 224 ₁ or the Iβ1 Iγ distribution circuit 224 ₂ selects one signal from 32 signals.
In other words, there will be at least 32 selectors for performing a 32-to-1 selection, and the circuit scale may be enormous.

The soft output decoding circuit 90 calculates the log likelihood Iγ of at least a part of the input / output patterns, instead of calculating all of the 32 input / output patterns by the Iγ calculation circuit 156. After the desired log likelihood Iγ is selected by the Iγ distribution circuit 157, each selected log likelihood Iγ is added.

[0888] For concrete description, here again, the case of decoding the convolutional encoder shown in Figs. 14 to 17 first will be considered. In this case, the convolutional encoder shown in FIG. 14 has at most 16 input / output patterns, and the convolutional encoder shown in FIG.
The convolutional encoder shown in FIG. 16 has at most eight input / output patterns,
The convolutional encoder shown in FIG. 17 has at most 16 input / output patterns. Here, the convolutional encoder shown in FIG. 15 having the largest number of input / output patterns has at most four types of input patterns and at most eight types of output patterns. Therefore, the soft-output decoding circuit 90 outputs the information and information in the Iγ calculation circuit 156 as schematically shown in FIG.
The code Iγ calculation circuit 221 calculates the log likelihood Iγ according to the four input patterns and the eight output patterns. Then, the soft output decoding circuit 90 selects one of four log likelihoods Iγ corresponding to the four input patterns by the selector 530 ₁ in the Iγ distribution circuit 157 according to the input / output pattern determined according to the code configuration. , A log likelihood Iγ is selected from the
The selector 530 ₂ at 7, selects one log likelihood Iγ from the eight log likelihood Iγ corresponding to the input pattern of eight, by adder 531 in the Iγ distribution circuit 157, obtained by the selected Log likelihood I
After adding γ and performing predetermined processing, it is distributed and output as log likelihood Iγ corresponding to the branch number. Iγ distribution circuit 1
57 is such two selectors 530 ₁ , 530
₂ and an adder 531 at most 32, so that the Iα distribution circuit 224 for Iα described above is provided.
_{3. The} Iγ distribution circuit 224 ₁ for Iβ0 or the Iγ distribution circuit 224 ₂ for Iβ1 is configured.

[0889] By doing so, the element decoder 50 does not need to have a selector having a huge circuit scale such as a selector for selecting 32: 1, and performs 4-to-1 selection and 8-to-1 selection. It is sufficient to provide a selector such as a selector having a small circuit scale and an adder, and it is possible to decode an arbitrary trellis code having a branch of a predetermined number or less with the same configuration with a small circuit scale. In particular, this method is effective when there are many input / output patterns for the number of branches on the trellis. Also, this technique
For example, when the encoding device 1 performs encoding by TTCM or SCTCM, or when input data and output data in the encoding device 1 are decoded in symbol units, input bits and output bits are encoded in bit units. If they cannot be separated, they will be very effective.

5-4-3 Log Likelihood for All Input / Output Patterns
In the one-time normalized Log-BCJR algorithm for the degree Iγ , generally, only the difference value between the log likelihoods affects the result, and the greater the value of the log likelihood, the higher the importance.

However, in the calculation process, the distribution of the values of the log likelihood Iγ is deviated with the passage of time, and after a lapse of a predetermined time, the value that can be expressed by the system for calculating the log likelihood Iγ is obtained. The range may be exceeded.

For example, when the log likelihood Iγ is calculated by a system that handles only positive values like hardware, the value of the log likelihood Iγ gradually increases, and after a certain period of time, The hardware exceeds the range of values that can be represented. Also, considering a case where the log likelihood Iγ is calculated by a system that handles only negative values, such as a system that performs a floating-point operation, in this case, the value of the log likelihood Iγ gradually decreases, After a certain period of time, the range of values that can be expressed as software is exceeded. As described above, the log likelihood Iγ exceeds the range of expressible values, and the log likelihood Iγ that exceeds the range of expressible values is clipped.

[0893] Therefore, the soft output decoding circuit 90 calculates the distribution of the log likelihood Iγ in order to avoid that the log likelihood Iγ is clipped and it becomes difficult to express an appropriate difference between the log likelihoods. Perform normalization to correct the bias.

[0894] Specifically, the soft output decoding circuit 90 outputs "5
In the case of calculating the log likelihood Iγ for all possible input / output patterns by the method shown in FIG. 4-1, normalization is performed as follows.
A plurality of log likelihoods Iγ (00/000) and Iγ (01/0) calculated by the information / code Iγ calculation circuit 221 by the Iγ normalization circuit 222 in the Iγ calculation circuit 156.
00),..., Iγ (11/111)
Log likelihood Iγ (00/000), Iγ (01/0) such that the log likelihood Iγ corresponding to the one having the maximum value is matched with the log likelihood corresponding to the maximum possible probability.
00),..., Iγ (11/111).

[0895] Specifically, when the element decoder 50 treats the log likelihood as a negative value, that is, when the above-mentioned constant sgn is "+1", the soft-output decoding circuit 90 will
As schematically shown in FIG.
The information / sign Iγ calculation circuit 2
21 are calculated based on a plurality of log likelihoods Iγ (00/00
0), Iγ (01/000), ..., Iγ (11/1
11) The one having the maximum value is assigned to the element decoder 50.
Are adjusted to the maximum value that can be represented by a plurality of log likelihoods Iγ (00/000), Iγ (01/000),.
., Iγ (11/111) is added with a predetermined value.

[0896] For example, the Iγ normalizing circuit 222 calculates a plurality of log likelihoods Iγ (00/000),
Iγ (01/000), ..., Iγ (11/111)
Are assumed to have the distributions shown in FIG. 80 (A), respectively, and as shown in FIG. 80 (B), these log likelihoods Iγ (00/000), Iγ (01/000),・
.., a plurality of log likelihoods Iγ (00/000), Iγ (11/111), so that log likelihood Iγ (11/111) indicated by plot x which is the maximum value is set to “0”. I
A predetermined value is added to each of γ (01/000),..., Iγ (11/111).

[0897] When the element decoder 50 treats the log likelihood as a positive value, that is, when the above-mentioned constant sgn is "-1", the soft output decoding circuit 90 outputs
56, a plurality of log likelihoods Iγ (00/000), Iγ (01/000),... Calculated by the information / code Iγ calculation circuit 221.
, Iγ (11/111), a plurality of log likelihoods Iγ (00/000), Iγ (01) so that the one having the minimum value matches the minimum value that can be represented by the element decoder 50.
/ 000),..., Iγ (11/111).

For example, the Iγ normalization circuit 222 calculates a plurality of log likelihoods Iγ (00/000),
Iγ (01/000), ..., Iγ (11/111)
Are assumed to have the distributions shown in FIG. 81 (A), respectively, and as shown in FIG. 81 (B), these log likelihoods Iγ (00/000), Iγ (01/000),・
.., Iγ (11/111), a plurality of log likelihoods Iγ (00/000), I
A predetermined value is subtracted from each of γ (01/000),..., Iγ (11/111).

[0899] The soft-output decoding circuit 90 includes the Iγ normalizing circuit 2
After performing such normalization by 22, clipping is performed in accordance with the required dynamic range, and the result is supplied to the Iγ distribution circuit 157 as log likelihood GA, GB0, GB1.

[0900] The element decoder 50 includes an Iγ normalizing circuit 222.
By performing such normalization every time,
The number of bits of the log likelihood GA, GB0, GB1 supplied from the Iγ calculation circuit 156 to the Iγ distribution circuit 157 can be reduced. In addition, the element decoder 50 can express a difference between log likelihoods appropriately without causing a situation in which a logarithmic likelihood having a large value and a high degree of importance is clipped. It can be carried out.

[0991] The element decoder 50 does not necessarily need to include the Iγ normalization circuit 222 inside the Iγ calculation circuit 156. For example, the element decoder 50 includes the Iγ distribution circuit 1
An Iγ normalization circuit 222 may be provided at a stage subsequent to 57. Of course, this method is effective not only when decoding an arbitrary code but also when decoding a fixed code.

5-4-4 At least Part of Input / Output Pattern
The normalized soft-output decoding circuit 90 for the log likelihood Iγ of the input / output pattern has the log likelihood Iγ of at least a part of the input / output pattern by the method shown in “5-4-2”.
Is calculated, the following normalization is performed. That is, the soft output decoding circuit 90 has the maximum probability γ among the plurality of log likelihoods Iγ corresponding to the input pattern calculated by the information / code Iγ calculation circuit 221 by the Iγ normalization circuit 222 in the Iγ calculation circuit 156. A predetermined operation is performed on each log likelihood Iγ so as to match the log likelihood Iγ corresponding to the one having a value to the log likelihood corresponding to the maximum value of the possible probability.

[0993] Specifically, when the element decoder 50 treats the log likelihood as a negative value, that is, when the above-described constant sgn is "+1", the soft output decoding circuit 90 shown in FIG.
As schematically shown in FIG.
The information / sign Iγ calculation circuit 2
Of the plurality of log likelihoods Iγ corresponding to the input pattern calculated by the element decoder 5
A predetermined value is added to each of the plurality of log likelihoods Iγ so that 0 is adjusted to the maximum representable value, and a plurality of logarithms according to the output pattern calculated by the information / code Iγ calculation circuit 221 are added. Among the likelihoods Iγ, a predetermined value is added to each of the plurality of log likelihoods Iγ to perform normalization so that the one having the maximum value matches the maximum value that can be expressed by the element decoder 50. .

[0904] If the element decoder 50 treats the log likelihood as a positive value, that is, if the above-described constant sgn is "-1", the soft output decoding circuit 90 outputs
56, the one having the minimum value among the plurality of log likelihoods Iγ corresponding to the input pattern calculated by the information / code Iγ calculation circuit 221 by the element / decoder 50 A predetermined value is added to each of the plurality of log likelihoods Iγ so as to match the value, and a plurality of log likelihoods Iγ corresponding to the output pattern calculated by the information / code Iγ calculation circuit 221 are added.
Among them, a predetermined value is added to each of the plurality of log likelihoods Iγ, and normalization is performed so that the one having the minimum value matches the minimum value that can be represented by the element decoder 50.

[0905] That is, the soft output decoding circuit 90 normalizes the log likelihood Iγ according to the input pattern and the log likelihood Iγ according to the output pattern.

[0906] The soft-output decoding circuit 90 includes the Iγ normalizing circuit 2
After performing such normalization by 22, clipping is performed in accordance with the required dynamic range, and the result is supplied to the Iγ distribution circuit 157 as log likelihood GA, GB0, GB1.

[0907] The element decoder 50 includes an Iγ normalizing circuit 222.
By performing such normalization every time,
The scale of searching for the log likelihood Iγ having the maximum value or the minimum value can be reduced, and the processing speed can be increased and the circuit size can be reduced. Then, the element decoder 50
It is possible to reduce the number of bits of the log likelihood GA, GB0, and GB1 supplied from the Iγ calculation circuit 156 to the Iγ distribution circuit 157, and the log likelihood having a large value and high importance is clipped. Therefore, it is possible to express an appropriate difference between log likelihoods, and to perform highly accurate decoding.

However, in this case, depending on the code configuration,
Although the final maximum or minimum value of the log likelihood Iγ does not necessarily match the maximum or minimum value that can be represented by the element decoder 50, when all input / output patterns appear,
The performance is not degraded because it is equivalent to the normalization by the method shown in “5-4-3”.

Note that, even in this case, the element decoder 50 does not necessarily require the Iγ normalization circuit 222
It is not necessary to provide inside 56.

5-5 Calculation of Log Likelihood Iα, Iβ This is a feature of the Iα calculation circuit 158 and the Iβ calculation circuit 159 described above. Further, depending on the feature, there is also one related to the Iγ distribution circuit 157. The element decoder 50 has the following nine features in calculating the log likelihoods Iα and Iβ.

5-5-1 Log Likelihood Iα and Log Likelihood Iγ
When calculating the log soft output Iλ in the soft output decoding, it is necessary to previously obtain the sum of the log likelihood Iα and the log likelihood Iγ as shown in the above equation (55). . That is, in soft output decoding, it is usually necessary to separately provide a circuit for calculating the sum of log likelihood Iα and log likelihood Iγ in order to calculate log soft output Iλ. Therefore, the log soft output I
There is a possibility that the scale of the circuit for calculating λ increases.

[0912] Therefore, the soft output decoding circuit 90 diverts the sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ obtained in the process of calculating the log likelihood Iα to calculate the log soft output Iλ. Specifically, as described above, the soft output decoding circuit 90 outputs the log likelihood Iα and the log likelihood Iγ calculated by the Iα calculation circuit 158 instead of outputting the log likelihood Iα as it is. Output the sum. That is, I
The α calculation circuit 158 includes the addition / comparison / selection circuits 241 and 242
Then, the sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ obtained in the process of calculating the log likelihood Iα is output.

[0913] By doing so, the element decoder 50 does not need to include a circuit for calculating the sum of the log likelihood Iα and the log likelihood Iγ required to calculate the log soft output Iλ. The circuit scale can be reduced.

[0914] 5-5-2 Pre-processing for parallel path There is a case where it is desired to decode a code having a parallel path on a trellis, such as a code by the convolutional encoder shown in Fig. 17 earlier. Here, taking the case of the convolutional encoder shown in FIG. 17 as an example, the trellis is shown in FIG.
As shown in an example in FIG. 5, a structure in which four sets of two parallel paths arrive from each state to the state at the next time is adopted. That is, the trellis in this case has a structure in which eight paths reach each state.

Here, the parallel path focuses on the fact that the state of the transition source is the same and the state of the transition destination is the same. That is, it is noted that the parallel path can be simulated as one path. By paying attention to this point, when decoding a code in which a parallel path exists on the trellis, the soft output decoding circuit 90 can obtain the log likelihood I
Before calculating α and Iβ, a log-sum operation is performed on the log likelihood Iγ corresponding to the parallel path in advance. More specifically, the soft-output decoding circuit 90 is connected to the Iβ0 parallel path processing circuit 22 in the Iγ distribution circuit 157 described above.
5 _1, provided with a parallel path processing circuit 225 ₂ and the parallel path processing circuit 225 ₃ for Iα for Aibeta1, perform log-sum operation on log likelihood Iγ corresponding to parallel paths, bundling parallel paths.

[0916] By doing so, the element decoder 50 can reduce the processing load of the Iα calculation circuit 158 and the Iβ calculation circuit 159, and can speed up the processing without deteriorating the performance. it can.

[0971] The element decoder 50 is provided with the Iγ distribution circuit 1
Although 57 has a function of bundling parallel paths, it need not be limited to this configuration. That is, the element decoder 50 may bundle the log likelihood Iγ corresponding to the parallel path before calculating the log likelihoods Iα and Iβ. Also,
Here, two parallel paths are described as being bundled into one set, but an arbitrary number of parallel paths, for example, four, may be bundled into one set.

[0918] 5-5-3 The shared element decoder 50 of the addition / comparison / selection circuit is capable of decoding an arbitrary code. However, when the number of input bits is k, it is necessary to decode each code. is log likelihood I.alpha, as ACS circuit for performing a process of adding a correction term by the ACS processing and log-sum correction in order to calculate the I beta, the trellis 2 ^k the path reaches each state It is necessary to prepare corresponding things individually. In general, as for such an addition / comparison / selection circuit, a circuit corresponding to a code having a large number k of input bits to the element encoder increases in circuit scale and processing load.

[0926] Here, the 4 shown in FIGS.
Consider a case where a code is decoded by various kinds of convolutional encoders. In this case, the addition / comparison / selection processing circuit corresponding to the code by the convolutional encoder shown in FIG. 14 corresponds to a trellis having a structure in which 2 ¹ = 2 paths arrive from each state to the state at the next time. You need something to do. Further, FIGS. 15 and as the ACS processing circuit corresponding to the code by convolutional encoder shown in FIG. 16, from the state to the state at the next time 2 ²
= A trellis having a structure in which four paths arrive is required. Further, the addition / comparison / selection processing circuit corresponding to the code by the convolutional encoder shown in FIG.
A trellis having a structure in which ³ = 8 paths arrive is required.

[0920] The code by the convolutional encoder shown in Fig. 17 has a parallel path on the trellis. At this time, when the parallel paths are bundled by the method shown in “5-5-2”, the trellis of this code is calculated from each state at the next time using the number of memories ν = 2 in the convolutional encoder. To the state 2ν =
It can be simulated as having a structure in which 2 ² = 4 paths arrive.

[0921] Therefore, the soft output decoding circuit 90 does not include an addition / comparison / selection circuit corresponding to a code in which the number of input bits to the element encoder is k = 3, and the number of input bits to the element encoder is k = 2. = Ν is shared with the addition / comparison / selection circuit corresponding to the sign of ν.

[0922] Specifically, the soft-output decoding circuit 90 calculates Iα
As an addition / comparison / selection circuit in the calculation circuit 158, only the addition / comparison / selection circuits 241 and 242 corresponding to codes having k = 1, 2 as the number of input bits to the element encoder are provided. As a circuit, the number of input bits to the element encoder is k
Addition / comparison / selection circuit 28 corresponding to the code of = 1,2
3, 284, and the number of input bits to the element encoder is k = 3. That is, the soft output decoding circuit 90 sets the number of input bits to the element encoder to k =
3 and the number of memories is ν = 2 <k, and instead of the addition / comparison / selection circuit corresponding to the code having a parallel path on the trellis, the number of input bits to the element encoder is k = The addition / comparison / selection circuit corresponding to the code of 2 = ν is shared.

[0923] In this way, the element decoder 50 does not need to include an addition / comparison / selection circuit corresponding to a code having k = 3 input bits to the element encoder, thereby reducing the circuit scale. be able to.

[0924] Here, the addition / comparison / selection circuit corresponding to the code having the number of input bits k = 3 to the elementary encoder corresponds to the code having the number of input bits k = 2 to the elementary encoder. Although an example in which the addition and selection circuit is shared with the addition and comparison selection circuit has been described, depending on the code configuration, for example, an addition and comparison and selection circuit corresponding to a code having k = 2 input bits to the element encoder may be used as the element decoder 50. , And the number of input bits to the element encoder is shared with an addition / comparison / selection circuit corresponding to a code having k = 1.
It can be shared with an addition / comparison / selection circuit corresponding to a code having a small number of input bits to the element encoder. For example, in a code in which the number of input bits to the elementary encoder is k = 3 and two sets of four parallel paths arrive from each state to an arbitrary state,
When these four parallel paths are bundled into one set,
It can be shared with an addition / comparison / selection circuit corresponding to a code in which the number of input bits to the element encoder is k = 1.
That is, the element decoder 50 is a code whose input bit number to the element encoder is k ₁ and whose number of memories is ν <k ₁ , and corresponds to a code having a parallel path on the trellis. The selection circuit can be shared with an addition / comparison / selection circuit corresponding to a code in which the number of input bits to the element encoder is k ₂ <k ₁ and the number of memories is ν.

5-5-4 Pair for Calculation of Log Soft Output Iλ
Output of the number likelihood Iγ If the parallel paths are bundled by the method shown in “5-5-2”, the processing of the addition / comparison / selection circuit in the Iα calculation circuit 158 and the Iβ calculation circuit 159 becomes simple. As described above, it is effective in terms of speeding up the processing. However, in order to calculate the logarithmic soft output Iλ which is the finally required result, the individual metric corresponding to each parallel path is Required. That is, in the soft output decoding, when calculating the log soft output Iλ, the log likelihood Iγ when the parallel paths are bundled cannot be used as it is.

[0926] Therefore, the soft output decoding circuit 90 decodes a code having a parallel path on the trellis. If the parallel paths are bundled, the log likelihood used to calculate the log soft output Iλ is used. The degree Iγ is separately output. Specifically, the soft output decoding circuit 90 includes an Iγ distribution circuit 157
Log likelihood PGA obtained by distributing the I.alpha for Iγ distribution circuit 224 ₃ in the supplies to the parallel path processing circuit 225 ₃ for I.alpha, separately output as a log likelihood DGAB.

[0927] By doing so, the element decoder 50 can bundle the parallel paths without affecting the decoding result, and as a result, the processing load of the Iα calculation circuit 158 and the Iβ calculation circuit 159. , And the processing speed can be increased without deteriorating the performance. That is, when bundling the parallel paths, the element decoder 50 inevitably separately outputs the log likelihood Iγ used for calculating the log soft output Iλ.

5-5-5 Log Likelihood for Parallel Path
Calculation of the sum of the degree Iα and the log likelihood Iγ As shown in “5-5-1”, the log likelihood Iα obtained in the process of calculating the log likelihood Iα to calculate the log soft output Iλ. Outputting the sum Iα + Iγ of the log likelihood Iγ and the log likelihood Iγ is effective from the viewpoint of reducing the circuit scale. However, when decoding a code having a parallel path on the trellis, it is necessary to output “5-5-1” The sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ obtained by the method shown cannot be output as it is.

[0929] Therefore, the soft output decoding circuit 90 decodes a code having a parallel path on the trellis. When the parallel paths are bundled, the soft output decoding circuit 90 performs addition comparison selection for calculating the log likelihood Iα. Separately from the circuit, the log likelihood Iα
And a circuit for calculating a sum Iα + Iγ of the logarithmic likelihood Iγ and using the calculation result to calculate a logarithmic soft output Iλ. Specifically, the soft output decoding circuit 90 includes an Iα calculation circuit 158
, An Iα + Iγ calculation circuit 243 is provided.
The Iγ calculation circuit 243 allows the addition / comparison / selection circuit 242
And the Iγ distribution circuit 157
, The log likelihood Iγ obtained in a state where the parallel paths are not bundled, and the sum is used for calculating a log soft output Iλ.

[0930] By doing so, the element decoder 50 can bundle the parallel paths without affecting the decoding result, and as a result, the processing load of the Iα calculation circuit 158 and the Iβ calculation circuit 159. , And the processing speed can be increased without deteriorating the performance. That is, when bundling the parallel paths, the element decoder 50 inevitably separately calculates the sum of the log likelihood Iα and the log likelihood Iγ used for calculating the log soft output Iλ.

5-5-6 Log Likelihood According to Code Configuration
As shown in "5-1-2" as the selection destination, in the Bozencraft convolutional encoder, since the data is held in time series with respect to the delay element, the state of the transition destination is limited. , The trellis has uniqueness.

[0932] Therefore, when decoding a Bozencraft convolutional code, the soft output decoding circuit 90 can easily utilize the uniqueness of the trellis even when the number of memories of the convolutional encoder becomes variable. It has a decryption function. More specifically, the soft-output decoding circuit 90 is the same as that shown in FIG.
Although not shown in FIGS. 36, 39 and 40, Iα
Addition / comparison / selection circuits 241, 24 in calculation circuit 158
2 and the addition / comparison / selection circuit 2 in the Iβ calculation circuit 159
83, 284, the log likelihood Iα, I
a selector for selecting β.

For example, as in the convolutional encoder shown in FIG. 14, the number of memories is "1", "2", "3",
FIG. 83 shows an example of a trellis in a convolutional encoder that is variable between “4” in accordance with the number of memories.
(A), (B), (C) and (D) show. That is, the trellis shown in FIG. 3A is an example when the number of memories is “1”, and the trellis shown in FIG. 3B is an example when the number of memories is “2”. The trellis shown in (C) is an example when the number of memories is "3", and FIG.
Is an example when the number of memories is "4".

[0932] In these four trellises, the state of which the state number is "0" is matched, and each trellis is superimposed, as shown in FIG. In the figure, the branch indicated by the solid line is the branch on the trellis shown in FIG.
The branch indicated by the broken line is a branch on the trellis illustrated in FIG. 83 (B), the branch indicated by a dashed line is a branch on the trellis illustrated in FIG. 83 (C), and the branch indicated by a two-dot chain line is 83
It is a branch on the trellis shown in (D).

As can be seen from FIG. 84, the branches that reach the states with the state numbers “0” and “1” are those in which four branches overlap and those in which four branches arrive from different states. There is. Therefore, when the number of memories of the convolutional encoder is made variable, one of the four branches arriving from different states may be selected according to the number of memories.

Also, the branches that reach the states with the state numbers “2” and “3” are the ones in which the three branches overlap,
Some branches come from different states. Therefore, when the number of memories of the convolutional encoder is made variable, one of three branches arriving from different states may be selected according to the number of memories.

[0937] Furthermore, state numbers "4", "5",
The branches reaching the states “6” and “7” include a branch in which two branches overlap and a branch in which two branches arrive from different states. Therefore, when the number of memories of the convolutional encoder is made variable, one of two branches arriving from different states may be selected according to the number of memories.

[0938] Since the branch reaching the state having the state number "8" or later is only the branch by the convolutional encoder shown in Fig. 83 (D), it is not necessary to perform the branch selecting operation.

[0939] In consideration of these facts, the above-mentioned 16
Log-sum operation circuits 245 _nAddition comparison with
FIG. 85 schematically shows the selection circuit 241.
U, four selectors 540₁, 540_Two, 540_Three, 5
40_FourTo calculate the log likelihood AL at the next time
At this time, select the log likelihood AL calculated at the previous time.
It will be good.

[0939] That is, the addition / comparison / selection circuit 241 uses the selector 540 _{1 to} select the state in which the transition source state number is “1” in the log likelihood AL calculated at the previous time based on the memory number information MN , The log likelihood AL02 corresponding to the state whose transition source state number is “2”, and the log likelihood A corresponding to the state whose transition source state number is “4”.
L04: One of the log likelihoods AL08 corresponding to the state whose transition source state number is "8" is selected. For example, when the element encoder has one memory, the selector 540 ₁ outputs the log likelihood A
If L01 is selected and the element coder has the number of memories of "2", the log likelihood AL02 is selected and the element coder has the number of memories of "3" In
The log likelihood AL04 is selected, and if the element encoder has four memories, the log likelihood AL08 is selected. The log-sum operation circuits 245 ₁ and 245 ₂ are supplied with the log likelihood AL00 as the log likelihood A0, and are supplied with the log likelihood selected by the selector 540 ₁ as the log likelihood A1.

[0941] The addition / comparison / selection circuit 241 uses the selector 540 _{2 to} select the state of the log likelihood AL calculated at the previous time based on the memory number information MN whose transition source state number is “3”. , The log likelihood AL05 corresponding to the state whose transition source state number is “5”, and the log likelihood AL09 corresponding to the state whose transition source state number is “9”.
Log likelihood is selected. Selector 540
₂ is, for example, when the element coder has a memory number of “2”, the log likelihood AL03 is selected, and when the element coder has a memory number of “3”, , The log likelihood AL05 is selected, and when the number of memories in the element encoder is “4”, the log likelihood AL09 is selected. The log-sum operation circuits 245 ₃ and 245 ₄ are supplied with the log likelihood AL01 as the log likelihood A0 and the log likelihood selected by the selector 540 ₂ as the log likelihood A1.

[0942] In addition, ACS circuit 241, the selector 540 _3, based on the memory number information MN,
Of the log likelihood AL calculated at the previous time, the log likelihood AL06 corresponding to the state whose transition source state number is “6” and the log likelihood corresponding to the state whose transition source state number is “10” One log likelihood of the degree AL10 is selected. For example, when the element encoder has a memory number of “3”, the selector 540 ₃
If L06 is selected and the element encoder has four memories, AL10 is selected. log-s
The um operation circuits 245 ₅ and 245 ₆ have a log likelihood AL02
Is supplied as the log likelihood A0, and the selector 5
40 log likelihood selected by ₃ is supplied as a log likelihood A1.

[0931] Further, the addition / comparison / selection circuit 241
The selector 540 ₄ , based on the memory number information MN, of the log likelihood AL calculated at the previous time, the log likelihood AL07 corresponding to the state with the state number “7” of the transition source and the state of the transition source One of the log likelihoods AL11 corresponding to the state with the number “11” is selected. For example, the selector 540 ₄ selects AL07 when the element coder has a memory number of “3”, and selects the AL07 when the element coder has a memory number of “4”. Selects AL11.
The log-sum operation circuits 245 ₇ and 245 ₈ are supplied with the log likelihood AL03 as the log likelihood A0,
The log likelihood selected by the selector 540 ₄ is supplied as the log likelihood A1.

As described above, the soft output decoding circuit 90 can decode a Bozencraft type convolutional code in which the number of memories is variable by providing the selector in the addition / comparison / selection circuit. That is, the soft output decoding circuit 90
Is an element that enables efficient decoding of trellises of codes corresponding to the number of memories by utilizing the uniqueness of the trellis of a Bozencraft type convolutional code, thereby enabling the decoding of codes having a variable number of memories. Decoder 5
0 can be easily realized.

[0945] Here, the addition / comparison / selection circuit 241 in the Iα calculation circuit 158 has been described as an example.
The element decoder 50 includes an addition / comparison / selection circuit 242 and an addition / comparison / selection circuit 283, 284 in the Iβ calculation circuit 159.
Also have the same function.

Also, in the above-described example, the description has been made assuming that the selector is provided for selecting at most 4: 1. However, the trellis can be arbitrarily overlapped. It is also possible.

5-5-7 For Log Likelihood Iα and Iβ
The normalized log likelihoods Iα and Iβ produce a bias in the distribution of values as time elapses in the calculation process, similarly to the above-described log likelihood Iγ, and after a certain period of time , the log likelihood Iα
The system for calculating α and Iβ may exceed the range of values that can be expressed.

[0948] Therefore, the soft output decoding circuit 90 performs normalization to correct the bias of the distribution of the log likelihoods Iα and Iβ.

The first method of this normalization is “5-
Similarly to the normalization method for the log likelihood Iγ shown in 4-3 ", when the element decoder 50 treats the log likelihood as a negative value, that is, when the above-described constant sgn is" +1 ", Iα Iα normalization circuit 25 in calculation circuit 158
0, 272 and the Iβ0 normalization circuits 291 and 308 in the Iβ calculation circuit 159 and the like. It is conceivable to add a predetermined value to each of the plurality of log likelihoods Iα and Iβ so as to match the maximum value that can be expressed. Also, as a first method of normalization, when the element decoder 50 treats the log likelihood as a positive value, that is, when the above-described constant sgn is "-
In the case of “1”, a plurality of log likelihoods Iα, Iα, calculated for each time by the Iα normalization circuits 250 and 272 in the Iα calculation circuit 158 and the Iβ0 normalization circuits 291 and 308 in the Iβ calculation circuit 159. It is conceivable that a predetermined value is subtracted from each of the plurality of log likelihoods Iα and Iβ so that the one having the minimum value among Iβ is adjusted to the minimum value that can be represented by the element decoder 50.

[0950] The log-sum operation circuit 24 in the Iα calculation circuit 158 for performing normalization according to the first method.
5 _n , 256 _n and log−
The sum operation circuits 286 _n and 292 _n can be represented as a log-sum operation circuit 550 schematically shown in FIG. That is, the log-sum operation circuit 550
Log likelihood Iγ and log likelihood Iα, I calculated one time ago
is added by an adder 551, and a correction term value is calculated by a correction term calculation circuit 552 from the obtained data.
Then, the log-sum operation circuit 550 includes the adder 53
3, the data from the adder 551 and the data from the correction term calculation circuit 552 are added, and the normalization circuit 554 determines the judgment information J based on the data from the adder 553.
The above-described normalization is performed based on D. The normalized data is delayed by one time by the register 555,
The log likelihood Iα and Iβ are supplied to the adder 551 and output to the outside.

Here, in order to explain the case where the log likelihood Iα is normalized, the dynamic ranges of the log likelihood Iα and the log likelihood Iγ calculated one time before are denoted by a and g, respectively. Assuming that the normalization circuit 554
Normalization as shown in FIG. 87 is performed. Here, the maximum value or the minimum value that can be represented by the element decoder 50 is “0”.

At this time, the dynamic range of the sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ calculated by the adder 551 is represented by a + g as shown in FIG. Sum Iα of log likelihood Iα and log likelihood Iγ at this time
The maximum value or the minimum value of + Iγ is represented as M1. Subsequently, the dynamic range of the data after the log-sum operation obtained through the processing by the correction term calculation circuit 552 and the adder 553 is represented by a + g because the dynamic range by the log-sum operation does not increase. The maximum value or the minimum value of the data at this time is represented as M2.

[0953] The normalization circuit 554 performs normalization so that the maximum value or the minimum value M2 of the data after log-sum operation is set to "0", and clips a value whose dynamic range is equal to or more than a. At this time, the normalization circuit 554
Based on the determination information JD, a value to be added or subtracted from the data after the log-sum operation is obtained, and normalization is performed. Further, the normalization circuit 554 performs the same normalization on the log likelihood Iβ.

[0954] By performing such normalization for each time, the soft-output decoding circuit 90 does not cause logarithmic likelihood having a large value to be clipped and has an appropriate log likelihood. It is possible to express the difference between
High-precision decoding can be performed. In particular, when performing normalization to set the maximum or minimum log-likelihood to “0”, the soft-output decoding circuit 90 assumes that the log-likelihood takes only a negative value or a positive value. No need for negative expressions,
The required dynamic range can be minimized, and the circuit size can be reduced.

[0955] The soft output decoding circuit 90 can also use another normalization method. That is, as a second method, the soft output decoding circuit 90 uses the Iα normalization circuits 250 and 272 and the Iβ calculation circuit 15 in the Iα calculation circuit 158 as a second method.
9, among the plurality of log likelihoods Iα and Iβ calculated by the Iβ0 normalization circuits 291 and 308, when the log likelihood Iα and Iβ corresponding to the metric having the largest probability exceed a predetermined value, An operation using the predetermined value is performed on each of the plurality of log likelihoods Iα and Iβ.

[0956] Specifically, when the element decoder 50 treats the log likelihood as a negative value, that is, when the above-mentioned constant sgn is "+1", the soft-output decoding circuit 90 The Iβ0 normalization circuit 29 in the Iα normalization circuits 250 and 272 and the Iβ calculation circuit 159
1,308 etc., the plurality of log likelihoods I calculated
When the maximum value of α and Iβ exceeds a predetermined value, a predetermined value is added to each of the plurality of log likelihoods Iα and Iβ, and the element decoder 50 calculates the log likelihood. When it is treated as a positive value, that is, when the above-described constant sgn is “−1”, Iα in the Iα calculation circuit 158
When a plurality of log likelihoods Iα and Iβ calculated by the normalization circuits 250 and 272 and the Iβ0 normalization circuits 291 and 308 in the Iβ calculation circuit 159 exceed a predetermined value. , A plurality of log likelihoods I
A predetermined value is subtracted from each of α and Iβ.

[0957] In particular, the soft output decoding circuit 90 can simplify the normalization processing by adopting 1/2 of the dynamic range as the predetermined value.

[0958] Regarding this, the log shown in FIG.
Description will be made using the −sum operation circuit 550. Here, the dynamic range of log likelihood Iγ is represented by g, the dynamic range of log likelihood Iα calculated one time ago is represented by a, and the dynamic range of log likelihood Iα is x> a Log likelihood I having the maximum or minimum value corresponding to the metric with the highest probability
If the value of α is expressed as z <x / 2, the normalization circuit 5
54 performs normalization as shown in FIG.

At this time, the dynamic range of the sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ calculated by the adder 551 is represented by x + g, as described above.
In addition, the sum I of the log likelihood Iα and the log likelihood Iγ at this time is
The maximum value or the minimum value of α + Iγ is represented by min (z + g, x), which is the smaller of z + g and x.
Subsequently, the dynamic range of the data after the log-sum operation obtained through the processing by the correction term calculation circuit 552 and the adder 553 is represented by x + g because the dynamic range by the log-sum operation does not increase. Since the maximum value or the minimum value of the data at this time changes by log2 (the natural logarithm of 2) which is the maximum value of the correction term at the maximum, it is represented by min (z + g, x) + log2.

The normalization circuit 554 calculates min (z + g,
If it is determined that the value of x) + log2 exceeds x / 2 which is 1/2 of the dynamic range x of the log likelihood Iα, x / 2 is subtracted from the data after log-sum operation. Normalization is performed, and values whose dynamic range is equal to or larger than x are clipped. The maximum or minimum value of the data at this time is min (z + g, x) + log2-x /
It is represented by 2. The normalization circuit 554 performs the same normalization on the log likelihood Iβ.

Here, subtracting half the value of the dynamic range of log likelihood Iα from the data after log-sum operation means that the most significant bit of the data after log-sum operation is inverted. Nothing else. That is,
The normalization circuit 554 determines that the most significant bit is “1”
By performing a process of inverting the most significant bit to “0” for the data after the og-sum operation,
Normalization can be performed.

[0932] As described above, the soft output decoding circuit 90 determines that among the plurality of calculated log likelihoods Iα and Iβ, the log likelihoods Iα and Iβ corresponding to the metric having the largest probability exceed a predetermined value. When it is determined, a plurality of log likelihoods Iα, Iβ
, A calculation using the predetermined value may be performed to perform normalization. In this case, the soft-output decoding circuit 90 only needs to invert the most significant bit by setting the predetermined value to a value of ダ イ ナ ミ ッ ク of the dynamic range of the log likelihood Iα, Iβ. A normalization can be performed below.

[0964] Further, the soft output decoding circuit 90 can use still another normalization method. That is, the soft output decoding circuit 90 uses the Iα calculation circuit 15 as a third method.
Of the plurality of log likelihoods Iα and Iβ calculated by the Iα normalization circuits 250 and 272 in I.8 and the Iβ0 normalization circuits 291 and 308 in the Iβ calculation circuit 159, respectively. Iα,
When Iβ exceeds a predetermined value, in the next time slot, as in the second method described above, for each of the plurality of log likelihoods Iα and Iβ, addition using the predetermined value or Perform subtraction.

[0964] The log-sum operation circuit 24 in the Iα calculation circuit 158 for performing normalization according to the third method.
5 _n , 256 _n and log−
The sum operation circuits 286 _n and 292 _n can be represented as a log-sum operation circuit 560 schematically shown in FIG. That is, the log-sum operation circuit 560
Log likelihood Iγ and log likelihood Iα, I calculated one time ago
is added by an adder 561, the value of the correction term is calculated by a correction term calculation circuit 562 from the obtained data, and the data from the adder 561 and the data from the correction term calculation circuit 562 are calculated by an adder 563. And are added. And
The log-sum operation circuit 560 performs the above-described normalization by the normalization circuit 564 based on the determination information JD based on the data from the register 565. The normalized data is delayed by one time by the register 565, supplied to the adder 561 as log likelihoods Iα and Iβ, and output to the outside. That is, log-
When it is determined that the data read from the register 565 exceeds the predetermined value, the sum operation circuit 560 performs normalization by the normalization circuit 564 in the next time slot.

Here, the dynamic range of the log likelihood Iγ is represented by g, and the dynamic range of the log likelihood Iα calculated one time before is represented by a.
Assuming that the dynamic range of α is secured by x> a and the value of the log likelihood Iα having the maximum value or the minimum value corresponding to the metric having the largest probability is represented by z <x / 2, The conversion circuit 564 performs normalization as shown in FIG.

At this time, the dynamic range of the sum Iα + Iγ of the log likelihood Iα and the log likelihood Iγ calculated by the adder 561 is represented by x + g as described above.
In addition, the sum I of the log likelihood Iα and the log likelihood Iγ at this time is
The maximum or minimum value of α + Iγ is also mi as described above.
It is represented by n (z + g, x). Subsequently, lo obtained through the processing by the correction term calculation circuit 562 and the adder 563 is obtained.
The dynamic range of the data after the g-sum operation is l
Since the dynamic range by the og-sum operation does not increase, it is represented by x + g. The maximum value or the minimum value of the data at this time is log, which is the maximum value of the correction term at the maximum.
Since it changes by 2, min (z + g, x) + lo
g2.

[0967] The normalizing circuit 564 calculates min (z + g,
x) + log2 is a predetermined value, for example, log likelihood Iα
Is determined to have exceeded x / 2, which is の of the dynamic range x, of l in the next time slot.
Normalization is performed by subtracting x / 2 from the data after the og-sum operation. The maximum or minimum value of the data at this time is represented by min (z + g, x) + log2. The normalization circuit 564 performs the same normalization on the log likelihood Iβ.

[0968] By performing such normalization, the soft output decoding circuit 90 determines whether or not to perform normalization by logarithm.
It is not necessary to perform the operation immediately after the −sum operation, and the speed of the normalization process can be increased.

[0969] 5-5-8 In log-sum correction
Calculation of Correction Term When calculating the correction term in log-sum correction,
Usually, the absolute value of the difference value is calculated by comparing the magnitude of the difference value between the two input data, and the value of the correction term corresponding to the absolute value is calculated. That is, log-sum
As schematically shown in FIG. 91, the log-sum operation circuit 570 that performs the operation calculates the difference value between the input data AM0 and the data AM1 by using a differentiator 571 ₁ and also outputs the data AM1 by using a differentiator 571 ₂ . A difference value between the data and the data AM0 is calculated.
72, the data AM0 is compared with the data AM1 in magnitude. Based on the comparison result, the selector 573 selects one of the two data from the differentiators 571 ₁ and 571 ₂ and selects this data. The value of the correction term corresponding to the obtained data is read from the look-up table 574. Then, the log-sum operation circuit 570 uses the adder 575 to output data DM indicating the value of the correction term,
One of the data AM0 and the data AM1 is added to the data SAM.

In the log-sum operation circuit 570, since the magnitude comparison between the data AM0 and the data AM1 by the comparison circuit 572 usually requires more time than the processing of other units, the result is large. In addition, it takes more time to obtain the data DM than to obtain the data SAM, which may cause a large delay.

[0971] Therefore, the soft output decoding circuit 90 first
As shown in FIG. 5, instead of calculating the absolute value of the difference value between the two input data and then calculating the value of the correction term, 2
The value of a plurality of correction terms corresponding to one difference value is calculated, and an appropriate one is selected from the calculated values. That is, the soft output decoding circuit 90 performs the magnitude comparison of the difference value between the two input data and the calculation of the value of the correction term in parallel.

[0972] Such log-sum operation is performed by
As schematically shown in FIG. 92, the g-sum operation circuit 580 calculates a difference value between the input data AM0 and the data AM1 by using a differentiator 581 ₁ , and
The difference value between the data AM1 and the data AM0 is calculated by 81 ₂ , the value of the correction term corresponding to the data from the differentiator 581 _{1 is} read from the look-up table 582 _1, and the correction value corresponding to the data from the differentiator 581 ₂ It reads the value of the correction term to the look-up table 582 _2.
At the same time, the log-sum operation circuit 580 outputs the data A by the comparison circuit 583 corresponding to the selection control signal generation circuit 253 in the Iα calculation circuit 158 described above.
M0 and data AM1 are compared in magnitude, and either one of the two data from the look-up tables 582 ₁ and 582 ₂ is selected by the selector 584 based on the comparison result, and the adder 585 selects The selected data DM is added to the data SAM, which is one of the data AM0 and the data AM1.

[0973] As described above, the soft-output decoding circuit 90 calculates the values of a plurality of correction terms corresponding to the two difference values, and selects an appropriate one from among them to obtain the log likelihood I.
α and Iβ can be obtained at high speed.

[0974] 5-5-9 In log-sum operation
When calculating a correction term in generation of a control signal for selection log-sum correction,
As in the case of the selection control signal generation circuit 253 in the Iα calculation circuit 158 described above, it is necessary to generate a determination statement for comparing the magnitudes of two data to generate a selection control signal. Specifically, the determination sentence of the control signal SEL generated by the selection control signal generation circuit 253 indicates the magnitude relationship between the data AM0 and AM1, as shown in the following equation (56).

[0975]

[Equation 56]

[0976] Since the correction term in the log-sum correction has the property of asymptotically approaching a predetermined value, as described above, the absolute value of the difference value between the two data as variables is determined by the predetermined value. Should be clipped to value. Specifically, as shown in the following expression (57), the determination statement of the control signal SL created by the selection control signal generation circuit 253 includes the absolute value of the difference value between the data AM0 and AM1 and a predetermined value. It indicates the magnitude relation of.

[0977]

[Equation 57]

[0978] If the data AM0 and AM1 each consist of 12 bits, the selection control signal generation circuit 253 has at least a 12-bit comparison circuit, which leads to an increase in circuit scale. This causes a delay in processing.

[0979] Therefore, the selection control signal generation circuit 253
Divides the upper and lower bits of the metric based on at least the data AM0 and AM1 and creates a decision sentence for selection, thereby controlling the control signals SEL and S
Generate L. That is, the selection control signal generation circuit 25
No. 3 divides each of the data AM0 and AM1 into upper bits and lower bits, and creates a decision sentence for comparing the magnitudes of the data AM0 and AM1.

[0980] First, consider the generation of a control signal SEL consisting of the decision statement shown in the above equation (56).

[0981] The correction term calculation circuit 247 outputs the data AM0,
If AM1 is composed of, for example, 12 bits, "1" is added to the most significant bit of the lower 6 bits of data AM0, and "0" is added to the most significant bit of the lower 6 bits of data AM1. The difference from the attached one is taken. At the same time, the correction term calculation circuit 247 sets “0” to the most significant bit of the lower 6 bits of the data AM0.
And the difference between the lower 6 bits of the data AM1 and the uppermost bit of the data AM1 with "1" added.
The selection control signal generation circuit 253 outputs the data AM0, AM
1, a decision statement as shown in the following equation (58) is created using these difference values DA1 and DA0, and the control signal SE
Generate L.

[0982]

[Equation 58]

First, the correction term calculation circuit 247 uses the selection control signal generation circuit 253 to output data AM0 and AM1.
6 bits AM0 [11: 6] and AM1 [11:
6], the data AM0, A
The magnitude relationship of M1 is determined. That is, the data AM0,
Upper six bits AM0 [11: 6] and AM1 [1 of AM1
1: 6], the data AM0, AM
It is nothing but the one that represents the magnitude relation of 1. Therefore, the selection control signal generation circuit 253 outputs (AM0 [11: 6]>
AM1 [11: 6]) is created.

[0984] The correction term calculation circuit 247 calculates the difference value D
By determining A1, the magnitude relationship of the lower 6 bits of the data AM0 and AM1 can be determined. That is, the fact that the most significant bit of the difference value DA1 is "1" is nothing less than that the lower 6 bits of the data AM0 are larger than the lower 6 bits of the data AM1. Considering the case where AM1 ≦ AM0 is satisfied under this condition, the upper 6 bits of data AM0 are higher than the upper 6 bits of data AM1.
In some cases, the upper 6 bits of data AM0 are equal to the upper 6 bits of data AM1. Therefore, the selection control signal generation circuit 253
((AM0 [11: 6] == AM1 [11: 6]) & D
A determination statement A1 [6] == 1) is created.

[0985] Therefore, the selection control signal generation circuit 25
3 can realize the determination statement shown in the above equation (56) by creating the determination statement shown in the above equation (58). That is, the selection control signal generation circuit 253
This can be realized only by having a bit comparison circuit and an equal (=) determination circuit, so that the circuit scale can be reduced and the processing speed can be increased.

Next, consider the generation of a control signal SL consisting of the decision statement shown in the above equation (57).

[0987] The correction term calculation circuit 247 outputs the data AM0,
Assuming that AM1 consists of, for example, 12 bits, as described above, "1" is added to the most significant bit of the lower 6 bits of data AM0 and the most significant bit of the lower 6 bits of data AM1. The difference from the one in which “0” is added to is taken. At the same time, the correction term calculation circuit 24
7 is the difference between the lower 6-bit data of data AM0 with "0" added to the most significant bit and the lower 6-bit data of data AM1 with "1" added to the most significant bit. . The selection control signal generation circuit 253 generates the difference values DA1 and DA0 in addition to the data AM0 and AM1.
Is used to create a decision statement as shown in the following equation (59),
A control signal SL is generated.

[0988]

[Equation 59]

First, the correction term calculation circuit 247 uses the selection control signal generation circuit 253 to output the data AM0 and AM1.
6 bits AM0 [11: 6] and AM1 [11:
6] are equal to each other. That is, the data AM
0, the upper 6 bits AM0 [11: 6] of AM1, AM1
If [11: 6] are equal, the data AM0, AM1
Is less than a predetermined value, here less than 64. Therefore, the selection control signal generation circuit 253
A determination sentence (AM0 [11: 6] == AM1 [11: 6]) is created.

[0990] Also, the upper 6 bits AM0 of data AM0
[11: 6] is the upper 6 bits AM1 of data AM1
Data “1” larger than [11: 6] and data A
The lower 6 bits AM0 [5: 0] of M0 are the data AM1
Is smaller than the lower 6 bits AM1 [5: 0] of the data, the absolute value of the difference value between the data AM0 and AM1 is smaller than a predetermined value, here, smaller than 64. Here, data AM
The case where the lower 6 bits AM0 [5: 0] of 0 is smaller than the lower 6 bits AM1 [5: 0] of the data AM1 is as follows.
Considering the above, there is a case where the most significant bit DA1 [6] of the difference value DA1 is “0”. for that reason,
The selection control signal generation circuit 253 calculates ((｛1′b0, A
M0 [11: 6]｝ == {1′b0, AM1 [11:
6] Create a judgment sentence of + 7′d1) & DA1 [6] == 0).

Similarly, upper 6 bits AM of data AM1
1 [11: 6] is the upper 6 bits AM0 of data AM0
Data “1” larger than [11: 6] and data A
The lower 6 bits AM1 [5: 0] of M1 are the data AM0
Is smaller than the lower 6 bits AM0 [5: 0], the absolute value of the difference between the data AM0 and AM1 is less than a predetermined value, here less than 64. Therefore, the selection control signal generation circuit 253 generates ((｛1′b0, AM1 [1
1: 6]｝ == {1′b0, AM0 [11: 6]} +
7'd1) & DA0 [6] == 0) is created.

[0992] Therefore, the selection control signal generation circuit 25
3 can realize the determination statement shown in the above equation (57) by creating the determination statement shown in the above equation (59). That is, the selection control signal generation circuit 253 can be realized only by having the equal (=) determination circuit, so that the circuit scale can be reduced and the processing can be speeded up.

As described above, the soft output decoding circuit 90
When calculating the correction term in the g-sum correction, a control signal for selection for comparing the magnitude of two data and clipping the absolute value of the difference between the two data as a variable to a predetermined value Can be reduced, and the processing speed can be increased.

Although the selection control signal generation circuit 253 has been described here, the selection control signal generation circuit 232 and the soft output calculation circuit 16 in the Iγ distribution circuit 157 have been described.
1, the control signal generation circuit 330 for selection
A control signal can be generated by a similar method.

5-6 Calculation of Log Soft Output Iλ This is a feature of the soft output calculation circuit 161 described above. The element decoder 50 has the following two features in calculating the log soft output Iλ.

[0996] 5-6-1 lo using enable signal
When calculating the log soft output Iλ of the cumulative addition operation of the g-sum operation, the cumulative addition operation of the log-sum operation according to the input of each branch on the trellis is performed and the input corresponding to the branch of “0” is performed. The result of the cumulative addition of the log-sum operation and the log-sum corresponding to the branch whose input is “1”
It is necessary to take the difference from the summation result of the sum operation.

[0997] Therefore, in the soft output decoding circuit 90,
In order to enable decoding of an arbitrary code, log likelihood Iα, log likelihood Iγ and log likelihood Iγ corresponding to each branch on the trellis are used.
In addition to calculating the sum with β, an enable signal indicating the input of each branch is generated, and based on the enable signal, an operation analogous to a winning game is performed, thereby realizing the calculation of the log soft output Iλ.

[0998] Here, log-sum operation circuit 312 ₁ of the soft-output computation circuit 161 described above, it is assumed that the accumulated addition of the log-sum computation in accordance with the branch input is "0". log-sum operation cell circuit 325 ₁ in log-sum operation circuit 312 _1, ...,
325 ₃₁ is the input data of 32 systems AG, respectively.
B, two data AGBs are input,
2 corresponding to each of these two systems of data AGB
A system enable signal EN is input.

[0999] For example, the log-sum operation cell circuit 32
5₁, Two enable signals EN000,
Both of EN001 indicate that the input is "0".
, The log-sum operation cell circuit 32
5₁Is the data of two systems AGB000 and AGB001.
The log-sum operation used is performed, and the result is referred to as data A
Output as GB100. Also, log-sum operation
Cell circuit 325₁Two enable signals input to
Of the EN000 and EN001, the enable signal EN0
Only 00 indicates that the input is "0".
, The log-sum operation cell circuit 325₁Is
Of the two systems of data AGB000 and AGB001,
Data AGB000 with a predetermined offset value N2.
And outputs the result as data AGB100. Similarly, l
og-sum operation cell circuit 325 ₁2 systems input to
Of the enable signals EN000 and EN001 of
Only the cable signal EN001 has an input of “0”
, The log-sum operation cell
Circuit 325₁Is a predetermined type for the data AGB001.
The offset value N2 is added and output as data AGB100.
Power. Further, the log-sum operation cell circuit 325₁
Enable signals EN000, EN input to the
001 indicate that the input is “1”.
If there is, the log-sum operation cell circuit 325₁
Uses two sets of data AGB000 and AGB001
Log-sum operation result or data AGB000, A
GB001 does not output itself and has a predetermined value
Is output as data AGB100. Also,
log-sum operation cell circuit 325_Two, ..., 325_Three
1Is also a log-sum operation cell circuit 325₁Processing similar to
To selectively output data AGB.

[1000] By doing so, log-s
um operation circuit 312 ₁ is capable of performing cumulative addition of the log-sum computation using only data AGB corresponding branches of the input is "0".

[1001] Similarly, the log-sum operation circuit 31
2 _2, ..., 312 ₆ performs cumulative addition of the log-sum computation using only data AGB corresponding branches of the input is "0" or "1".

In this way, the soft output decoding circuit 90 can calculate the log soft output Iλ for an arbitrary trellis code having a predetermined number of branches or less.

[1003] Here, the case where decoding of a code having a trellis structure having 32 or less branches has been described, but the soft output decoding circuit 90 is not limited to the number of branches. Not even.

5-6-2 l without using enable signal
Incidentally, in the case of the method shown in “5-6-1” in the cumulative addition operation of the og-sum operation , each lo
g-sum operation circuit 312 _1, ..., 312 _6, respectively, 32 of the data AGB lines, select the data AGB 16 strains input is "0" or "1", these 16 strains Is a cumulative addition operation of the log-sum operation using the data AGB. for that reason,
Each log-sum operation circuit 312 _1,..., In 312 _6, in fact, among the 31 pieces of log-sum operation cell circuit, will not only work of about half,
There is a possibility that the efficiency may be reduced.

[1005] Therefore, the soft output decoding circuit 90 sets "5-6
The logarithmic soft output Iλ can be calculated by the following method other than the method shown in FIG.

In other words, as schematically shown in FIG. 93, the soft output calculation circuit 161 'is selected by the selection circuit 590 in advance from the data AGB of 32 systems according to the input / output pattern of each branch on the trellis. , And the eight log-sum operation circuits 591 ₁ ,.
By 91 ₈ each, performs log-sum operation using data AGB selected 16 strains. Although not shown, the soft output calculation circuit 161 ′ has four logarithms.
-8 log-
sum operation circuit 591 _1, log-su using data AGB eight lines are output from the respective ... 591 ₈
The m-operation is performed, and the log-sum operation is performed by each of the two log-sum operation circuits using the four systems of data AGB output from each of the four log-sum operation circuits. Then, the soft output calculation circuit 1
61 'is the log-sum operation circuit 591 _15,
A log-sum operation is performed using two systems of data AGB output from each of the two log-sum operation circuits.

[1007] The soft output calculation circuit 161 'performs such processing for each case where the input is "0" or "1".

[1008] As described above, the soft output calculating circuit 161 '
The data AGB of 32 systems is previously set by the selection circuit 590.
Are selected in accordance with the input / output pattern of each branch on the trellis, and an operation which can be compared to a winning battle is performed by ₁₅ log-sum arithmetic circuits 591 ₁ ,. Then, the cumulative addition operation of the log-sum operation can be realized.

[1009] Even with such a technique, the soft output decoding circuit 90 can calculate the log soft output Iλ for an arbitrary trellis code having a predetermined number of branches or less.

[1010] Here, the case of decoding a code having a trellis structure having 32 or less branches has been described, but the soft output decoding circuit 90 is not limited to the number of branches. Not even.

5-7 Normalization for External Information This is a feature of the external information calculation circuit 163 described above.

[1012] The soft output decoding circuit 90, as described above,
The external information calculation circuit 163 can calculate external information in symbol units and external information in bit units. Here, when calculating the external information on a symbol basis, for example, if two bits and one symbol are used, four pieces of external information are calculated.

[1013] Therefore, the soft-output decoding circuit 90 performs normalization to correct the bias of the distribution of the external information in symbol units and reduce the amount of information, and outputs the external information for all symbols to the prior probability information in the next stage. , And outputs the number of external information of “the number of symbols−1”.

[1014] More specifically, the soft output decoding circuit 90
4 (A), for example, four symbols “0”
Assuming that the external information ED0, ED1, ED2, and ED3 corresponding to each of "0", "01", "10", and "11" have been calculated, as shown in FIG. Of the four pieces of external information ED0, ED1, ED2, and ED3 so that the external information ED1 having the maximum value is adjusted to a predetermined value such as “0” by the normalization circuit 357.
A predetermined value is added to each of ED2 and ED3,
The external information EA0, EA1, EA2, and EA3 are obtained. The soft output decoding circuit 90 can correct the bias of the distribution of the external information by performing such normalization.

[1015] Subsequently, the soft output decoding circuit 90 uses the normalizing circuit 357 to output the four pieces of normalized external information EA0, EA1, EA2, and EA3 as shown in FIG.
Is clipped according to the required dynamic range, and external information EN0, EN1, EN2, EN3
Ask for. By performing such clipping, the soft-output decoding circuit 90 can hold a value difference between external information having a large value and a high degree of importance.

[1016] Then, the soft output decoding circuit 90 uses the normalization circuit 357 to output, for example, the four pieces of external information EN0, EN1, and EN after clipping, as shown in FIG.
2 and EN3, the value of the external information EN0 for the symbol “00” is changed to the values of all other symbols “01” and “1”.
External information EN1, E for each of "0" and "11"
A difference is made from the values of N2 and EN3. Soft output decoding circuit 90
By performing such normalization, it is possible to output the ratio of the three external information as the external information EX0, EX1, and EX2, instead of outputting the four external information.

By doing so, the soft-output decoding circuit 90 does not need to output external information for one symbol, and can reduce the number of external input / output pins. Also, the soft output decoding circuit 90 performs the clipping shown in FIG. 10C before performing the normalization shown in FIG. The difference can be retained, and highly accurate decoding can be performed.

[1018] Here, the case has been described where the extrinsic information for four symbols is calculated and normalized, but the soft output decoding circuit 90 normalizes the extrinsic information for symbols other than four. You can also.

5-8 Hard Decision of Received Value This is a feature of the hard decision circuit 165 described above.

[1020] When the received value is hard-determined, I / O
The tangent of the received value on the Q plane is obtained. However, in this case, for example,
Assuming that the in-phase component and the quadrature component are each represented by 8 bits, it is necessary to divide 8-bit data, which causes an increase in circuit scale and a delay in processing.

As an alternative method, assuming that the in-phase component and the quadrature component are each represented by 8 bits, a total of 16536 = 65536 cases are classified, and hard decision in each case is performed. It is conceivable to delineate the values. However, this method is not realistic because it requires a huge amount of processing time.

[1022] As another method, in order to compare the angle of the received value on the I / Q plane with the boundary of the hard decision area, the received value is divided and compared with the tangent of the angle of the boundary. Conceivable. However, also in this method, division between 8-bit data is required, and since the boundary of the area is generally given by an irrational number, further examination of accuracy is required.

The soft output decoding circuit 90 obtains a boundary value for either the in-phase component or the quadrature component of the received value by lookup, and obtains a hard decision value according to the value of the other component.

[1024] More specifically, if the encoding device 1 performs modulation by the 8PSK modulation method, the soft output decoding circuit 90 converts the I / Q plane into eight signals as shown in FIG. In order to divide into eight regions according to points, four boundary lines (boundary value data) BDR0, BDR1, BDR2, and BDR3 for either the I axis or the Q axis are provided,
These boundary value data BDR0, BDR1, BDR2,
The BDR 3 is stored as a table in the lookup table 372 in the hard decision circuit 165 described above. In the figure, the in-phase component and the quadrature component are each represented by 5 bits, and each dot represents each bit. Also, areas 0, 1,
The values of the signal points mapped to 2, 3, 4, 5, 6, and 7 are respectively the above-mentioned signal point arrangement information CSIG.
0, CSIG1, CSIG2, CSIG3, CSIG
4, CSIG5, CSIG6, and CSIG7.

[1025] As described above, the soft output decoding circuit 90
By the hard decision circuit 165, four boundary value data BDR0, BDR1, BDR for either the I axis or the Q axis
2, BDR3 and the value of the other component are compared, it is determined to which region the signal point of the received value belongs, and a hard decision value is obtained.

[1026] By doing so, the soft-output decoding circuit 90 can reduce the capacity of the table stored in the look-up table 372, and it is not necessary to consider the accuracy, thereby reducing the circuit scale. At the same time, the processing speed can be increased.

[1027] Although the case has been described above where signal points are demapped by the 8PSK modulation method, this method can be applied to demapping of signal points by any PSK modulation method.

[1028] 6. Next, features of the interleaver 100 will be described. The following features are provided as functions of the interleaver 100, but will be described with reference to appropriately simplified drawings in order to clarify the concept of the features.

[1029] 6-1 a plurality of types of interleaving functions described above the storage circuit 407 _1, 407 _2, ..., 407 ₁₆
This is a feature relating to the control of writing and / or reading data to and from the memory.

[1030] As described above, the interleaver 100 stores a plurality of storage circuits 407 ₁ , 407 ₂ , and 407 according to the mode indicating the code configuration including the type of interleave to be performed.
..., from the 407 _16, select the appropriate be subjected to writing and / or reading data, switch the memory circuit to be used, to achieve a plurality of types of interleaving.

[1031] Specifically, when the control circuit 400 generates the write address and the read address, the interleaver 100 uses the address selection circuit 405 based on the interleaver type information CINT and the interleaver non-output position information CNO. , address data AA0, BA0, AA1, BA1, AA2, among the BA2, storage circuits 407 _1, 407 _2, ..., and select the address data to be distributed to 407 _16. Further, the interleaver 100 uses the input data selection circuit 406 to output the interleave mode signal CDIN, the interleaver type information CINT and the interleaver input / output replacement information CINT.
Based on the PT, the data for interleaving I0, I
1, I2 and delay data D0, D1, D2, D
3, D4 and D5, the storage circuits 407 ₁ , 407 ₂ ,.
..., selects the data to be distributed to 407 _16.

[1032] As a specific example, first, Figs.
1 is conceivable. That is, after the interleaver 100 generates an address by the control circuit 400 irrespective of the type of interleaving to be performed, the address selection circuit 405 and the input data selection circuit 406 change the code configuration including the type of interleaving to be performed. The storage circuits 407 ₁ , 407 ₂ ,.
.., address and data are distributed to 407 ₁₆
Storing data circuit 407 _1, 407 _2, ..., 407 ₁₆
To memorize.

[1033] Then, the interleaver 100, storage circuit 407 _1, 407 _2, ..., and supplied to the output data selection circuit 408 the data read from the 407 _16, by the output data selection circuit 408, interleave mode signal CDIN , Interleaver type information CINT, interleaver input / output replacement information CIPT, control signal IOB
S, IOBP0, IOBP1, IOBP2, DOBS,
Based on DOBP, data OR00, OR01,.
The data to be output is selected from the OR 15 and output as the interleaver output data IIO and the interleave length reception value IDO.

As described above, interleaver 100 implements a plurality of types of interleaving by switching the storage circuit to be used and distributing addresses and data in accordance with the mode indicating the code configuration including the type of interleaving to be performed. It can be versatile. Therefore, the element decoder 50 can perform decoding adaptively corresponding to various codes.

[1035] 6-2 Interleaving storage circuit and delay
A feature associated with the functions shown in shared "6-1" of the storage circuit for extending the storage circuit 407 _1, 407 _2, ..., the feature related to the control of the write and / or reading data to 407 ₁₆ is there.

In iterative decoding, it is necessary to delay the received value by the same time as the processing time required by the interleaver, that is, by the time corresponding to the interleave length. Here, when decoding a plurality of types of codes, the number of symbols to be delayed changes according to the code configuration, and the storage circuit (R
AM) also varies.

[1037] Therefore, the interleaver 100 is described above.
As mentioned above, the storage circuit for interleaving and the storage for delay
Circuit and a plurality of storage circuits 4 according to the code configuration.
07 ₁, 407_Two, ..., 407₁₆Use from
Switch storage circuit, do not use for interleave processing
Note that the memory circuit is used for delay processing and not used for delay processing.
The memory is used for interleaving.

[1038] As a specific example, FIGS.
1 is conceivable. That is, the interleaver 100 uses the address selection circuit 405 and the input data selection circuit 406 to consider both the interleave processing and the delay processing according to the code configuration, and
_1, 407 _2, ..., perform the distribution of address data and data for 407 _16, by the output data selection circuit 408, and outputs the desired data.

By doing so, it is not necessary for the interleaver 100 to separately include a memory circuit for interleaving and a memory circuit for delay, and it is sufficient to provide a minimum number of memory circuits, and the circuit scale is reduced. Reduction can be achieved.

[1040]6-3 Memory circuit using clock blocking signal
Operation control As described above, the interleaver 100 has at least
Plural storage circuits 407 having RAM₁, 407_Two, ...
・, 407₁₆And these storage circuits 407 ₁, 40
7_Two, ..., 407₁₆Interleave processing using
And delay processing. In this case, the storage circuit 407₁, 4
07_Two, ..., 407₁₆Are usually
Every time a clock signal is input, data is written and / or
An operation such as reading is performed.

[1041] In such an interleaver 100,
May actually have unused storage circuits.
You. Specifically, in the example shown in FIG.
407 ₆, 407₈RAMD06 and D08 are unused
For example, in the example shown in FIG.
Storage circuit 407₆, 407₈, 407_Ten, 407₁₂Smell
RAMs D06, D08, D10, and D12 are unused R
Exists as AM.

Therefore, interleaver 100 generates a clock blocking signal IH for blocking the input clock signal by address selecting circuit 405, and applies this clock blocking signal IH to an unused storage circuit. Writing and / or writing in the unused storage circuit
Alternatively, all operations including reading are stopped.

[1043] More specifically, in the interleaver 100, a plurality of storage circuits 407 ₁ , 407 ₂ ,.
407 ₁₆ Of, a storage circuit for use is determined by dividing the address direction. And the interleaver 100
The address selection circuit 405 generates a clock inhibition signal IH for a storage circuit that does not correspond to a write address and / or a read address, and applies the clock inhibition signal IH to the storage circuit.

As described above, the interleaver 100 can stop the operation of the unused storage circuit by dividing the storage circuit to be used in the address direction and providing the mechanism for activating the clock inhibition signal IH. . Therefore, the element decoder 50 can store all the storage circuits 4
07 _1, 407 _2, ..., it is not necessary to operate in accordance with any of the clock signals 407 _16, it is possible to lower the operating ratio of the memory circuit, as a result, it is possible to reduce the power consumption.

6-4 Deinterleaving Function As described above, the interleaver 100 can perform both the interleaving process and the deinterleaving process.

By the way, generally, when performing the interleaving process, data is written to the storage circuit using sequential address data, and data is read from the storage circuit using random address data. . On the other hand, when performing deinterleaving processing, in order to generate address data for reading,
It is necessary to reversely convert the address data used in the interleaving process. Therefore, when iterative decoding is performed, the address data used in the deinterleaving process is used for conversion in order to use the address data used in the interleaving process, and the address data used in the interleaving process is used for inverse conversion in order to use the address data in the deinterleaving process. It is necessary to hold two types of address data separately from each other, and there is a possibility that the circuit scale will be reduced.

[1047] Therefore, when performing the deinterleave processing, the interleaver 100 uses the read address data used for the interleave processing as the write address data, and reads out using the sequential address data, thereby interleaving. The same address data is shared between the processing and the deinterleaving processing.

[1048] Specifically, as described above, when performing the interleave processing, the interleaver 100 generates the write address data IWA which is sequential address data by the control circuit 400, and converts the write address data IWA. Using the storage circuit 40
7 _1, 407 _2, ..., performs writing of data to 407 _16, a sequential address data IAA generated by the control circuit 400, on the basis of the address data IAA, read address data is a random address data ADA is read from the address storage circuit 110, and the read address data AD is read.
A, the storage circuits 407 ₁ , 407 ₂ ,.
Reading data from 7 _16.

On the other hand, as described above, the interleaver 100 performs sequential address data IAA by the control circuit 400 when performing the deinterleave processing.
And the read address data A, which is random address data, is generated based on the address data IAA.
DA is read from the address storage circuit 110, and using the read address data ADA, the storage circuit 407 is read.
_1, 407 _2, ..., 407 performs writing of data to _16, the control circuit 400 is a sequential address data write address data IW
It generates A, by using the write address data IWA, performs the storage circuit 407 _1, 407 _2, ..., the read data from 407 _16.

[1050] As described above, the interleaver 100 shares the same address data between the interleave processing and the deinterleave processing, and switches the address data according to the interleave processing and the deinterleave processing. In other words, the interleaver 100 causes the control circuit 400 to switch the read address data used for the interleave process to be used as the write address data used for the deinterleave process, and to switch the read address data used for the deinterleave process. The address data is switched to be used as write address data used for the interleave processing.

[1051] The control circuit 400 for switching such address data can be represented, for example, as a configuration shown in FIG. 96 in a simplified manner. That is, the control circuit 40
0, the write address generator circuit 601 for generating address data for writing, a read address generating circuit 602 for generating address data for reading, expressed as having a ₂ and two selectors 603 _1, 603.

[1052] The control circuit 400, the write address generator circuit 601 generates sequential address data for writing, and supplies to the selector 603 _1, 603 _2, by the read address generating circuit 602, the sequential address for reading the data generated and supplied to the selector 603 _1, 603 _2. The selector 603 _1, 603 _2, based on the interleave mode signal CDIN, the address data supplied from the write address generating circuit 601, among the address data supplied from the read address generating circuit 602, selects one .

[1053] Specifically, the selector 603 _1, interleave mode signal CDIN is, the interleaver 1
When 00 indicates that interleave processing is to be performed, the address data supplied from the write address generation circuit 601 is selected, and as the write address data IWA, the interleave address conversion circuit 4
03. The selector 603 ₂ outputs the interleave mode signal CDIN to the interleaver 10.
If 0 indicates that interleave processing is to be performed, the address data supplied from the read address generation circuit 602 is selected, and the address data IAA is selected.
To the address storage circuit 110 and the interleave address conversion circuit 403.

[1054] On the other hand, the selector 603 _1, interleave mode signal CDIN is, when the interleaver 100 has been to instructs to perform deinterleaving, the address data supplied from the read address generating circuit 602 Selected, and as the write address data IWA, the interleave address conversion circuit 403
To supply. The selector 603 _2, interleave mode signal CDIN is, when the interleaver 100 has been to instructs the performing deinterleaving selects the address data supplied from the write address generating circuit 601, The address data IAA is supplied to the address storage circuit 110 and the interleave address conversion circuit 403.

As described above, the interleaver 100 can simplify the circuit and reduce the scale by switching the address data shared between the interleave processing and the deinterleave processing by the control circuit 400.

[1056] 6-5 Write Address and Read Address
When a write address and a read address are generated, sequential address data is usually generated by counting up with a counter. Here, when the write address counter and the read address counter are shared, data reading from the storage circuit cannot be started until writing of the next frame to the storage circuit is started.

In other words, when the interleaver shares the counter for the write address and the counter for the read address, as shown in FIG. 97, when the interleave start position signal indicated by A is input, the bank A Is written to the storage circuit of FIG. Subsequently, when the next interleave start position signal indicated by B is input, the interleaver reads data stored in the storage circuit of bank A and writes data to the storage circuit of bank B. Done.
Similarly, when the next interleave start position signal indicated by C is input, the interleaver reads out the data stored in the storage circuit of the bank B,
Data is written to the storage circuit of the bank A.

As described above, when the interleaver shares the counter for the write address and the counter for the read address, the interleaver reads the data from the storage circuit simultaneously with the start of writing the next frame to the storage circuit. To start.

Here, generally, the input timing of a frame input from the outside changes, and the frame is not always input to the interleaver at a constant interval. That is, the interleaver usually needs to operate without knowing the timing at which the next frame is input.

[1060] In consideration of performing repetitive decoding in such a situation, it is necessary to interleave the external information and delay the received value. However, in the interleaver, the input timing of the received value is required. Is different for each frame, so that a difference in delay amount may occur. That is, in the interleaver, the time between the two interleave start position signals indicated by A and B and the time between the two interleave start position signals indicated by B and C are different in FIG. The amount of delay may be different. In this case, since it is difficult for the interleaver to match the input timing of the reception value to be delayed, complicated processing is required to realize iterative decoding.

[1061] Therefore, the interleaver 100 has a configuration in which a counter for a write address and a counter for a read address are separately provided, and immediately after the data writing to the storage circuit is completed, the data reading is started. .

[1062] Specifically, as shown in Fig. 98, when the interleave start position signal TIS indicated by A is input, the interleaver 100 counts up the write address counter by the control circuit 400, and As soon as data is written to the storage circuit A, the read address counter is counted up and the stored data is read. Subsequently, when the next interleave start position signal TIS indicated by B is input, the interleaver 100 counts up a write address counter by the control circuit 400 and writes data to the storage circuit of the bank A. Then, the counter for the read address is immediately counted up and the stored data is read. Similarly,
When the next interleave start position signal TIS indicated by C is input, the interleaver 100 counts up the counter for the write address, and immediately writes the data to the storage circuit of the bank A. And the stored data is read out.

[1064] As described above, the interleaver 100 provides the counter for the write address and the counter for the read address separately, so that the data read can be started immediately after the data write to the storage circuit is completed. it can. That is, the interleaver 100 is configured such that even if the time between two interleave start position signals TIS indicated by A and B is different from the time between two interleave start position signals TIS indicated by B and C, The amount of delay can always be fixed to the interleave length, and it becomes easy to match the input timing of the received value to be delayed.

6-6. As shown in the delay function “6-5” for the interleave length , when the write address counter and the read address counter are separately provided, the interleaver 100 When the value is delayed, the order of reading data from the storage circuit is the same as the order of writing data to the storage circuit. That is, when delaying the received value, the interleaver 100 makes the read address the same as the write address.

[1064] By doing so, interleaver 100 can realize a delay corresponding to the interleave length. In particular, the interleaver 100 can easily realize a delay corresponding to the interleave length by counting up both a read address counter and a write address counter and generating sequential address data. .

The interleaver 100 adopts such an easy method. For example, when performing an experiment in which the number of repetitions is changed, the interleaver 100 changes the entire decoding delay only by connecting a plurality of element decoders. It is possible to perform iterative decoding in which the number of repetitions is changed without causing the repetition.

6-7 How to Use Address Space This is a feature relating to an address expression method when performing interleaving in which a plurality of symbols are input and a plurality of symbols are output.

Normally, a continuous address is assigned to the RAM in the storage circuit, and data is written using this continuous address space. Here, when performing interleaving in which a plurality of symbols are input and a plurality of symbols are output, it is considered that continuous addresses are assigned to RAMs in a plurality of storage circuits.

For example, in a case where interleaving is performed such that data of three symbols is input as input symbols and data of three symbols is output as output symbols, RAM0, RAM1, RAM2, and RAM9 of nine storage circuits are used.
RAM3, RAM4, RAM5, RAM6, RAM7,
When performing interleaving using the RAM 8, FIG.
As shown in FIG. 9, data I0 (= I0 [0], I0) of the 0th symbol is stored in RAM0, RAM3, and RAM6.
[1], I0 [2],..., I0 [31]) are sequentially written in the word direction for each time slot,
1, RAM4 and RAM7, data I1 of the first symbol (= I1 [0], I1 [1], I1 [2],.
.., I1 [31]) are sequentially written in the word direction for each time slot, and RAM2, RAM5, RAM8
, The data I2 of the second symbol (= I2
[0], I2 [1], I2 [2],..., I2 [3
1)) are sequentially written in the word direction for each time slot. Then, one system of interleaver output data IIO0 is read from RAM0, RAM1, and RAM2, and the other one is read from RAM3, RAM4, and RAM5.
The interleaver output data IIO1 of one system is read, and another interleaver output data IIO2 of another system is read from the RAM 6, RAM7, and RAM8.

At this time, as shown in FIG. 100, when writing data, it is assumed that continuous addresses from 0 to 31 are assigned to RAM0, RAM3, and RAM6, respectively. RAM
4 and RAM7 are assigned continuous addresses of 32 to 63, respectively.
The M5 and the RAM 8 are assigned continuous addresses from 64 to 95, respectively.

This is the same even when data is not stored in all storage areas of each RAM when the interleave length is made variable.

For example, RAM0, RAM1, RAM2,
RAM3, RAM4, RAM5, RAM6, RAM7,
In the example shown in the figure, the RAM 8 can perform interleaving with an interleave length of 32 time slots, but when the interleave length is set to 10 time slots, for example, as shown in FIG.
For RAM0, RAM3, and RAM6,
In the entire storage area for 32 time slots, data I0 of the 0th symbol (= I0 [0], I0 [1], I0
[2],..., I0 [9]) are sequentially written in the word direction for each time slot, and no data is written to the remaining storage areas. RAM1, RAM4, R
For AM7, the data I1 (= I1) of the first symbol in the entire storage area for 32 time slots, respectively.
[0], I1 [1], I1 [2],..., I1
[9]) is sequentially written in the word direction for each time slot, and no data is written to the remaining storage areas. Furthermore, for the RAM2, RAM5, and RAM8, the data I2 (= I2 [0], I2) of the second symbol in the entire storage area for 32 time slots, respectively.
[1], I2 [2],..., I2 [31]) are sequentially written in the word direction for each time slot, and no data is written to the remaining storage areas.

At this time, as shown in FIG. 102, when writing data, continuous addresses from 0 to 9 are assigned to RAM0, RAM3 and RAM6, respectively, Are assigned consecutive addresses from 10 to 19, respectively.
Are assigned continuous addresses across a plurality of physically different RAMs, such as 20 to 29 consecutive addresses.

However, when data is written to the RAM using such an address space, it is necessary to perform conversion to an address indicating a combination of a time slot and an input symbol when reading data. is there. For example, RAM0, RAM1, and R shown in FIG.
When reading data stored in the address space of “12” from AM2, the information indicating the address of “12” is used to read “2nd time slot of the first symbol”.
It is necessary to convert to information.

[1075] Therefore, when writing data by assigning continuous addresses to each RAM, it is necessary to provide a conversion circuit for converting addresses when reading data. In particular, if the number of symbols is not a power of 2, the address conversion operation becomes complicated.

The interleaver 100 gives the replacement destination address in combination with the input symbol information and the time slot information for each symbol.

[1077] More specifically, as described above, interleaver 100 performs interleaving in which, for example, data of three symbols is input as input symbols and data of three symbols is output as output symbols. , RAM0, RAM1, RAM2 of the nine storage circuits
RAM3, RAM4, RAM5, RAM6, RAM7,
When performing interleaving with an interleave length of 32 time slots using the RAM 8, the control circuit 400
For example, as shown in FIG. 103, when data is written, RAM 0, RAM 3 and RAM 6 are respectively written as 0-0, 0-1, 0-2,. A combination of information indicating each time slot and information indicating the 0th symbol is given as an address. Also, the interleaver 100 has a RAM
1, RAM4, and RAM7, respectively, 1-0,
A combination of information indicating each time slot and information indicating the first symbol, such as 1-1, 1-2,..., 1-31, is given as an address. Further, the interleaver 100 has RAM2, RAM5,
2-0, 2-1 and 2-
A combination of information indicating each time slot and information indicating the second symbol, such as 2, 2,..., 2-31, is given as an address.

[1078] In practice, the address assignment shown in the figure is equivalent to the address assignment shown in FIG. For example, RAM0, RAM1, RAM shown in FIG.
Consider a case where data stored in the address space of “34” is read out from the address space No. 2. In this case, the information indicating the address “34” is expressed in a 7-digit binary number.
It is represented as “0100010”. Here, it can be seen that the upper two bits “01” indicate the first symbol, and the lower five bits “00010” indicate the second time slot. That is, the address assignment shown in FIG. 103 is substantially equivalent to the address assignment shown in FIG. 100, and the operation of converting the address when reading data is unnecessary.

Also, when performing interleaving with an interleaving length of 10 time slots, for example, as shown in FIG.
When writing data, RAM0, RAM3, RAM6
, Respectively, 0-0, 0-1, 0-2,.
A combination of information indicating each time slot and information indicating the 0th symbol, such as 0-9, is given as an address. Also, interleaver 10
0 is information indicating each time slot and the first symbol, such as 1-0, 1-1, 1-2,..., 1-9, for RAM1, RAM4, and RAM7, respectively. Is given as an address. Further, the interleaver 100 has a RAM 2,
For RAM5 and RAM8, 2-0, 2-
A combination of information indicating each time slot and information indicating the second symbol, such as 1, 2,,..., 2-9, is given as an address.

The address assignment shown in FIG.
It can be seen that the assignment of addresses is substantially the same as that shown in FIG. Therefore, the interleaver 100
Is used when the interleave length is variable.
Even when data is not stored in all storage areas of the AM, it is possible to eliminate the need for address conversion work when reading data.

[1081] As described above, interleaver 100 always inputs a plurality of symbols by giving the address of the replacement destination in combination of the information of the input symbol and the information of the time slot for each symbol. Even when performing interleaving for output and changing the interleave length, there is no need to perform address conversion work when reading data, so it is necessary to provide a special address conversion circuit. Therefore, the circuit scale can be reduced.

[1082] The interleaver 100 is the same as that shown in FIG.
In addition to the address assignment shown in FIG. 104, any combination may be used as long as the combination can identify the time slot and the input symbol.

[1083] 6-8 Data by Partial Write Function
407 ₁₆ , writing and reading of the above-mentioned storage circuits 407 ₁ , 407 ₂ ,.
It is a feature about.

As described above, the storage circuit 407 has a partial write function based on the partial write control signal PW. For example, the storage circuit 407 normally includes (the number of bits B) × as shown in FIG.
B-bit data is input / output to / from the RAM 424 having a storage capacity of (the number of words W). When the B-bit data is used as a RAM for partial write, as shown in FIG. / 2) × (number of words 2 W) A RAM 424 having a storage capacity of B / 2 bits can be input and output in a pseudo manner.

This is because the interleave length is usually limited according to the number of words in the RAM when a RAM having both the number of bits and the number of words is limited as an interleaver. In other words, the interleaver 100
Operates the RAM 424 in the storage circuit 407 as a RAM for partial writes,
Interleave processing with an interleave length longer than the normal number of words in M424 can also be realized.

At this time, since the interleaver 100 receives the data of the number of bits in a normal state when the RAM is not in the partial write function, for example, 16 bits, the input 16-bit data is used in the partial write function. Among them, it is necessary to provide the data to the RAM 424 by switching every desired 8-bit data.

Therefore, in interleaver 100, the data input to storage circuit 407 is divided into upper bits and lower bits to form two-symbol data. When the partial write function is used, the data of these two symbols is Among them, the same data is always selected, and the data is selected such that the read data corresponding to the address is always at the same position of the output data.

[1088] Specifically, the storage circuit 407 writes and reads data in the partial write function as follows.

[1089] That is, the storage circuit 407 is provided with the selector 4
21 and 422, the address data AR
Of the most significant bit of the address data AR and the most significant bit of the address data AR. Thus, for example, when the most significant bit of the address data AR is “0”, the data VIH contains the 8-bit data “111”.
11111 ", and the data VIL becomes 8-bit data" 00000000. "Similarly, if the most significant bit of the address data AR is" 1 ", the data VIH becomes 8-bit data" 00000000. " The data VIL is 8-bit data “1111111”.
1 ".

Here, data VIH indicates whether or not to write data to the upper address in the bit direction in the storage area of RAM 424, and data VIL indicates the lower address in the bit direction in the storage area of RAM 424. This indicates whether data is to be written. The storage circuit 407 writes data to an address where each bit of the data VIH and VIL is “0”.

At the same time, the storage circuit 407 causes the selector 423 to always select the lower 8 bits of data IR [7: 0] of the data IR. Thereby, the data I
Is a repetition of data IR [7: 0], that is, I = {IR1, IR0} = {IR [7: 0], IR
[7: 0]}.

[1092] The storage circuit 407 stores the RA based on the address data IA, which is data obtained by removing the most significant bit of the address data AR, and the data VIH and VIL.
For M424, the data IR [7:
0] is written. That is, when the most significant bit of the address data AR is “0”, the storage circuit 407 writes the data IR [7: 0] to the lower address of a predetermined word in the RAM 424, and Is the most significant bit of "1",
The data IR [7: 0] is written into the RAM 424 at an upper address in a predetermined word.

As described above, the storage circuit 407 stores the data I in the RAM 424 during the partial write function.
Only the lower 8-bit data IR [7: 0] of R is written.

[1094] The storage circuit 407 stores the RA based on the address data IA, which is data obtained by removing the most significant bit of the address data AR, and the data VIH and VIL.
From M424, the data stored in the upper address is read out as data OH, and the data stored in the lower address is read out as data OL, and the selectors 425 and 426 select the data, thereby outputting the data OR.

At this time, the data OR is always stored in the RAM 4
Among the data OH and OL read from the data 24, the data corresponding to the address is configured to be at the same position of the data to be output. That is, the data OR is the data L
If PD is "0", the corresponding address is R
Since the address is the lower address in the AM 424, the data OL read from the lower address is set as the lower bit, the data OH read from the upper address is set as the upper bit, and OR = {SOH, SOL} = {OH, O
L｝. Similarly, when the data LPD is "1", the corresponding address is stored in the RAM4.
24, the data OH read from the upper address is set as the lower bit,
The data OL read from the lower address is the upper bit, and OR = {SOH, SOL} = {OL, OH}.

As described above, the storage circuit 407 always writes the lower bit data IR0 obtained by dividing the input data IR into the upper bit and the lower bit into the RAM 424 at the time of the partial write function, Of the data read from the RAM 424, the data corresponding to the address is set as the lower bits of the output data.

[1097] On the other hand, instead of using the partial write function,
Normally, the memory circuit 407 writes and reads data as follows.

[1098] That is, the storage circuit 407 is connected to the selector 4
A bit having a value of “0” is selected by each of 21 and 422. Thereby, for example, the data VIH,
VIL is always 8-bit data “00000000”.

At the same time, the storage circuit 407 causes the selector 423 to always select data IR [15: 8] of the upper 8 bits of the data IR. Thus, the data I becomes I = {IR1, IR0} = {IR [15: 8],
IR [7: 0]}, which is the data IR itself.

[1100] The storage circuit 407 stores the data VI
Since H and VIL are both “00000000”, the address data IA, which is the data excluding the most significant bit of the address data AR, and the data VIH and VI
Based on L, the data I is written into the RAM 424 at both the upper address and the lower address of a predetermined word. That is, the storage circuit 407
For 424, data IR [15: 8] is written to an upper address in a predetermined word, and data IR [7: 0] is written to a lower address.

As described above, the storage circuit 407 normally writes the data IR itself to the RAM 424.

[1102] The storage circuit 407 stores the RA based on the address data IA, which is data obtained by removing the most significant bit of the address data AR, and the data VIH and VIL.
From M424, the data stored in the upper address is read out as data OH, and the data stored in the lower address is read out as data OL, and the selectors 425 and 426 select the data, thereby outputting the data OR. At this time, since the data LPD is “0”, the data OR always uses the data OL read from the lower address in the RAM 424 as the lower bit and the data OH read from the upper address.
Is the upper bit, and OR = {SOH, SOL} = {O
H, OL}. That is, the data OR is stored in the RAM 4
24 is the data itself read from the predetermined word.

As described above, the storage circuit 407 normally writes the data IR to the RAM 424 and outputs it as the data OR.

[1104] By doing so, the interleaver 100 only needs to know the upper bit data or the lower bit data of the input / output multiple bit data, and which bit data is written or read. It is not necessary to be conscious of whether it is contributing to Therefore, the interleaver 100 normally includes a RAM having a storage capacity of (number of bits B) × (number of words W)
By acting as a RAM for partial write, it is easy to use it as a RAM of half the number of bits × double word.

[1105] Here, the storage capacity of the RAM 424 in the partial write function has been described as being half the number of bits x 2 times the word length as compared with the normal time, but this method is limited to this storage capacity. is not. This method uses the RAM 42 in the partial write function.
4 has a storage capacity of, for example, 1/3 several bits × 3 times long word, 1/4 several bits × 4 times long word, 1
The present invention can be applied to an arbitrary storage capacity such as a case of a word having a length of bits × bits.

[1106] That is, the interleaver divides the data input to the storage circuit into at least upper bits and lower bits to obtain data of at least two symbols. When the partial write function is used, the data of at least two symbols is used. Among them, the same data should always be selected, and the data should be selected so that the read data corresponding to the address is always at the same position of the data to be output.

[1107] 6-9 Pair to Even Length Delay and Odd Length Delay
The odd length delay compensation circuit 402 and the storage circuit 407 described above
₁ , 407 ₂ ,..., 407 ₁₆ .

[1108] When iterative decoding with variable code length is performed, it is necessary to perform variable length delay. Interleaver 1
00 uses a two-bank RAM to switch between writing and reading of data in one time slot, so that a delay length, that is, a RAM having a number of words corresponding to a half time slot of the interleave length is used. Delay can be realized.

[1109] To simplify and explain this operation, 3
An example in which an interleave length delay of six time slots is realized using two banks of RAMs each having the number of words of a time slot will be described with reference to FIG. Here, it is assumed that addresses 0, 1, and 2 are assigned to the RAMs of the banks A and B, respectively, for convenience. In the RAM of the bank A, data A, C, and E are stored in advance in the storage areas of the addresses 0, 1, and 2, and in the RAM of the bank B, the data of the addresses 1 and 2 are stored. It is assumed that data B and D are stored in advance in the area, and no data is stored in the storage area at address 0. Further, in the figure, data writing is represented by "W" and data reading is represented by "R".

[1110] First, in the 0th time slot, the interleaver 100 stores the address 0 in the RAM of the bank A.
, The data A is read from the storage area, and the data F is written to the storage area at the address 0 in the RAM of the bank B.

[1111] Subsequently, in the first time slot, the interleaver 100 stores the data G in the storage area of the address 0 in the RAM of the bank A, that is, the storage area from which the data A is read in the zeroth time slot. And the data B is read from the storage area of the address 1 in the RAM of the bank B.

Subsequently, in the second time slot, the interleaver 100 reads out the data C from the storage area of the address 1 in the RAM of the bank A, and reads the storage area of the address 1 in the RAM of the bank B, that is, one time. The data H is written to the storage area from which the data F was read in the slot.

Subsequently, in the third time slot, the interleaver 100 stores the data I in the storage area of the address 1 in the RAM of the bank A, that is, the storage area from which the data C is read in the second time slot. And the data D is read from the storage area at the address 2 in the RAM of the bank B.

Subsequently, in the fourth time slot, interleaver 100 reads data E from the storage area of address 2 in the RAM of bank A, and reads the storage area of address 2 in the RAM of bank B, that is, three times. The data J is written to the storage area from which the data D was read in the slot.

Subsequently, in the fifth time slot, the interleaver 100 stores the data K in the storage area of the address 2 in the RAM of the bank A, that is, the storage area from which the data E is read in the fourth time slot. And the data F is read from the storage area at the address 0 in the RAM of the bank B.

At the sixth time slot, the interleaver 100 reads out the data G from the storage area at the address 0 in the RAM of the bank A, and reads the storage area at the address 0 in the RAM of the bank B, that is, the fifth time slot. The data L is written into the storage area from which the data F has been read.

The interleaver 100 switches writing and reading of data in one time slot using the two banks of RAMs. FIG. 107 shows a timing chart of writing and reading data by such an operation. That is, the data F written to the bank B is read out after the lapse of the interleave length, and similarly, the data G written to the bank A is read out after the lapse of the interleave length. .

As described above, when data is written to one bank, interleaver 100 switches the operation of reading data from the other bank for each time slot, so that the interleaver 100 has a word slot equivalent to half the interleave length. The interleave length delay can be realized by using two banks of the number of RAMs.

By the way, in the case of the delay processing by this method, since the storage capacity of the RAM is small, the circuit scale can be reduced, but the delay length is limited to an even number.

[1120] Therefore, the interleaver 100 performs the above-described operation when the delay is even-numbered, so that the RAM
Only for the delay length, and for odd length delays,
By performing the above-described operation to delay the delay length by one minute, and by providing a switching function so as to delay by one time slot using a register, both the even-length delay and the odd-length delay are supported. .

[1121] Specifically, as described above, the interleaver 100 uses the odd-length delay compensation circuit 402 to output the interleave length information CIN supplied from the control circuit 60.
When an even-length delay is performed based on L, the data TD
When only the delay by the RAM is performed for I and the odd-length delay is performed, the delay of the RAM by the delay length of −1 and the delay of one time slot by the register are performed on the data TDI. , The data TDI which is the data to be delayed is selected.

In this way, the interleaver 100 can cope with both the even-length delay and the odd-length delay with a small circuit scale.

6-10. Input / Output Order Switching Function This is a feature of the input data selection circuit 406 and the output data selection circuit 408 described above.

[1124] As described above, the soft output decoding circuit 90
Although any code can be decoded, an input / output pattern corresponding to the code must be obtained in advance in order to decode any code. Therefore, it is very difficult for the soft output decoding circuit 90 to actually decode all codes by one circuit, and it is realistic to perform decoding for an arbitrarily assumed code. is there.

As described above, in addition to the soft output decoding circuit 90, a soft output decoding circuit having a limited code to be decoded generally has a soft output of an arbitrary code that inputs a plurality of symbols and outputs a plurality of symbols. When decoding, it may not be possible to decode a code that differs only in the order between input symbols and / or the order between output symbols for the given code.

[1126] For example, when the decoding device 3 is constructed by connecting the element decoders 50 and a code is decoded by a coding device that performs coding by SCCC, the coding device performs coding of an outer code. As a convolutional encoder, an arbitrary convolutional encoder that can be decoded by the soft-output decoding circuit 90 is provided. As an interleaver, one that performs inline interleaving is provided. Further, as a convolutional encoder that performs inner code encoding, And the convolutional encoder shown in FIG. 24 before the soft output decoding circuit 90 can decode. In this case, it goes without saying that the decoding device 3 can decode the code by the encoding device.

By the way, as shown in FIG. 108, the convolutional encoder for encoding the inner code in the encoding device is used, and when the soft output decoding circuit 90 does not target the convolutional code for decoding, the decoding device 3 Makes it impossible to decode codes by this encoding device.

[1128] Here, the convolutional encoder shown in FIG.
Assuming that the input data i ₀ , i ₁ , and i ₂ are the _0th , _1st , and _2nd symbols, respectively, the input data i1 of the _first symbol and the 2nd symbol of the convolutional encoder shown in FIG. It can be seen that the input data i ₂ is replaced. That is, in the encoding apparatus including the convolutional encoder shown in FIG. 108, as shown in FIG. 109, the 3-bit encoded data output from the convolutional encoder that encodes the outer code is input to the interleaver. In this case, the convolutional encoder shown in FIG. 24 is used as a convolutional encoder for performing coding of an inner code by exchanging the encoded data of the first symbol and the encoded data of the second symbol. It can be seen that this is equivalent to an encoding device.

[1129] As described above, the decoding device 3 determines the order between input symbols and / or the output between the input symbols for an encoding device that uses a code that is not to be decoded by the soft-output decoding circuit 90 as an element code. Even if only the order between symbols is different, decoding becomes impossible.

In other words, on the encoding side, when interleaving is performed individually for each symbol such as inline interleaving or pairwise interleaving, the positions of input and output symbols are uniquely determined. It is undeniable that there is a demand for performing a wide range of coding by performing coding with the position of the symbol changed. In particular, in the case of an encoding device using a Massey-type code as an element code, various encodings can be performed by exchanging the output positions of the tissue components. Therefore, it is necessary for the decoding device to cope with the decoding of such codes.

The interleaver 100 has a function of changing the order between input symbols and / or the order between output symbols when performing interleaving for inputting a plurality of symbols and outputting a plurality of symbols.
A plurality of types of interleaving based on the same address are realized.

[1132] Specifically, when performing interleaving processing, interleaver 100 uses interleaver input / output replacement information CIP by input data selection circuit 406.
Based on T, the input order between the symbols is replaced with each other, and the input position and the output position of each symbol are switched.

[1133] When performing the deinterleaving process, the interleaver 100 outputs the output data selection circuit 40
8, based on the interleaver input / output replacement information CIPT, the output order between the symbols is replaced with each other, and the input position and the output position of each symbol are switched.

[1134] In other words, assuming that the decoding device 3 decodes a code by SCCC, the two adjacent element decoders 50 _I and 50 _J constituting the decoding device 3 can be simplified, for example, as shown in FIG. It can be represented as the configuration shown. Here, a circuit having a function of switching the order between input symbols and / or the order between output symbols is referred to as a symbol switching circuit.

[1135] That is, the element decoder 50 _I outputs the data output from the soft output decoding circuit 90 to the interleaver 10.
When input to 0, deinterleave processing is performed by the interleaver 100. At this time, the element decoder 50
_I is a data OR consisting of a plurality of symbols that has been subjected to deinterleaving processing by passing through a storage circuit 407 in the interleaver 100.
Is input to the symbol exchange circuit 610 corresponding to the symbol interleaver output data IIO to be output by the symbol exchange circuit 610, and the interleaver output data IIO consisting of a plurality of symbols is selected according to the code configuration. Then, the input order between the symbols is replaced with each other, that is, the order of the symbols is changed, and the symbols are supplied to the element decoder 50 _J at the next stage.

On the other hand, the element decoder 50 _J
When the data supplied from 0 _I and subjected to the soft-output decoding process by the soft-output decoding circuit 90 is input to the interleaver 100, the interleaver 100 performs an interleave process. At this time, the element decoder 50 _J converts the data I composed of a plurality of symbols supplied from the soft output decoding circuit 90 and subjected to various processes by the symbol replacement circuit 611 corresponding to the input data selection circuit 406 in the interleaver 100. , Depending on the code configuration,
The order of each symbol is exchanged and supplied to the storage circuit 407 as data IR. The interleaved data is supplied to the next-stage element decoder (not shown).

By doing so, the interleaver 100 can change the order between input symbols and / or the order between output symbols, and realize a plurality of types of interleaving based on the same address. In particular, the interleaver 100 performs interleaving in which the number of input / output symbols is the same and the input position and the output position are determined one-to-one, such as a normal inline interleaver or a pair-wise interleaver. , It is possible to switch the connection between the position of the input symbol and the position of the output symbol.

[1138] Therefore, even when a general-purpose soft output decoding circuit having a limited code to be decoded is provided, the element decoder 50 applies an input to a code that can be decoded by the soft output decoding circuit. Codes that differ only in the order between symbols and / or the order between output symbols can be decoded. The element decoder 50 can limit the number of codes to be decoded by the soft-output decoding circuit 90, so that the circuit can be simplified and the scale can be reduced.

[1139] Here, an example in which the function of changing the order of each symbol is provided in interleaver 100 has been described. However, it is not always necessary to provide it as a function of interleaver 100. For example, it is provided as a function of soft output decoding circuit 90. You may do so.

[1140] In the case where the function of changing the order of each symbol is provided as a function of the soft output decoding circuit 90, if the decoding device 3 decodes a code according to SCCC, two adjacent element decoding units constituting the decoding device 3 are decoded. Vessel 50 _K ,
Simplified 50 _L can be represented, for example, as the configuration shown in FIG.

[1141] That is, the element decoder 50 _K, depending on the soft-output decoding circuit 90 and interleaver 100 performs the normal soft-output decoding, and deinterleaving, the data obtained to the next stage element decoder 50 _L Supply.

On the other hand, the element decoder 50 _L
When data consisting of a plurality of symbols supplied from 0 _K , that is, information necessary for soft output decoding processing such as external information or interleaved data TEXT is input to the soft output decoding circuit 90, the symbol exchange circuit According to 612, the order of each symbol is changed according to the code configuration. Further, the element decoder 50 _L performs various processing similar to that of the soft-output decoding circuit 90, and outputs the external information SOE composed of a plurality of symbols calculated by the external information calculation circuit 163 by the symbol replacement circuit 613 according to the code configuration. After changing the order of each symbol and performing various processes, the symbols are supplied to the interleaver 100 as data TII. And the element decoder 50
_L performs an interleaving process on the input data TII and supplies it to a next-stage element decoder (not shown).

By doing so, the soft output decoding circuit 90 can decode a code that differs only in the order between input symbols and / or the order between output symbols. Therefore, the element decoder 50 can limit the number of codes to be decoded by the soft-output decoding circuit 90, so that the circuit can be simplified and the scale can be reduced. In particular, when repeatedly decoding a Massy-type code, the element decoder 50 can decode a code in which the output position of a tissue component is replaced.

Note that the element decoder 50 _L shown in FIG.
Has been described as having the symbol exchange circuit 613 in the soft output decoding circuit 90, but the interleaver 100 may have the symbol exchange circuit 613. That is, the element decoder 50 only needs to include a symbol exchange circuit according to the code configuration in a stage subsequent to the interleaver 100 performing the deinterleaving process and in a stage preceding the interleaver 100 performing the interleaving process. Of course, even when the decoding device 3 decodes a code by PCCC, the element decoder 50
The subsequent stage of the interleaver 100 that performs the deinterleave processing, and the interleaver 1 that performs the interleave processing
A configuration may be adopted in which a symbol exchange circuit according to the code configuration is provided in a stage preceding 00.

[1145] 7. Summary As described above, in the data transmission / reception system configured using the encoding device 1 and the decoding device 3, the element decoder 50 configuring the decoding device 3 requires at least the processing time required by the soft output decoding circuit 90 and A plurality of delay modes for delaying at the same time, at least a delay at the same time as the processing time required by the interleaver 100, or at least a delay at the same time as the processing time required by the soft-output decoding circuit 90 and the interleaver 100; By switching between these delay modes, the decoding device 3 performs iterative decoding with the number of repetitions changed without changing the overall decoding delay, by merely connecting a plurality of element decoders 50 composed of LSIs having the same wiring. PCCC, SC
Any code such as CC, TTCM or SCTCM,
Decoding can be performed repeatedly with a desired number of repetitions.

[1146] That is, the data transmission / reception system configured by using the encoding apparatus 1 and the decoding apparatus 3 has a simple configuration and performs iterative decoding in which the number of repetitions is changed without changing the overall decoding delay. This can be performed and can provide high convenience to the user.

[1147] The present invention is not limited to the above embodiment. For example, in the above embodiment, the element decoder 50 uses the soft output decoding circuit 90, the interleaver 100, and the like as an LSI. Although the description has been given assuming that they are integrated, only the soft output decoding circuit 90 is
And a plurality of soft output decoding circuits 90 connected to each other.
The decoding device 3 may be configured by providing other units including as external devices. Similarly, in the present invention, only the interleaver 100 is configured as a single module such as an LSI, and a plurality of the interleavers 100 are connected, and other units including the soft output decoding circuit 90 are provided as external devices. May be configured as the decoding device 3. That is, according to the present invention, at least the soft output decoding circuit 90 or the interleaver 100
If it is configured as a single module, it can be applied to iterative decoding.

[1148] In the above-described embodiment, when the correction term is calculated by the soft output decoding circuit 90, the value of the correction term is read from the look-up table constituted by the ROM or the like. The present invention may be various memories such as a RAM, for example, instead of the ROM, and is also applicable to a case where a value of a correction term is calculated by providing a so-called linear approximation circuit or the like.

Further, in the above embodiment, the number of symbols input / output to / from interleaver 100 has been described as a maximum of three symbols.
The present invention can also be applied to a case where an arbitrary number of symbols of three or more is input / output.

[1150] Furthermore, in the above-described embodiment, interleaver 100 has 16 storage circuits 407 ₁ , 40 ₁
7 _2, ..., it has been described as having a 407 _16, but the present invention can, of course, be applied to a case of having any number of memory circuits according to the code structure.

[1151] In the above-described embodiment, random interleaving, inline interleaving, and pairwise interleaving have been described as types of interleaving that interleaver 100 can handle.
The present invention is not limited to these types of interleaving, but is applicable to other types of interleaving.

[1152] Furthermore, in the above-described embodiment, the decoding apparatus uses an MA based on the Log-BCJR algorithm.
Although it has been described that P decoding is performed,
-Log-BCJR algorithm or "Bahl, Cock
e, Jelinek and Raviv, “Optimal decoding of linear
codes for minimizing symbol error rate ”, IEEETra
ns. Inf. Theory, vol. IT-20, pp. 284-287, Mar. 197
M based on the BCJR algorithm described in "4."
The present invention is also applicable to a decoding device that performs AP decoding.

Further, in the above-described embodiment, the encoding device and the decoding device are applied to the transmission device and the reception device in the data transmission / reception system. However, the present invention relates to a floppy (registered trademark) disk, a CD, and the like. -R
The present invention can also be applied to a recording and / or reproducing apparatus that performs recording and / or reproduction on a recording medium such as a magnetic, optical or magneto-optical disk such as OM or MO (Magneto Optical). In this case, the data encoded by the encoding device is recorded on a recording medium equivalent to a memoryless communication channel,
The data is decoded and reproduced by the decoding device.

As described above, it goes without saying that the present invention can be appropriately changed without departing from the spirit of the present invention.

[1155]

As described in detail above, the decoding apparatus according to the present invention obtains the probability of passing through an arbitrary state based on a received value that is a soft input, and uses this probability to calculate
A decoding device corresponding to element codes for repeatedly decoding codes generated by concatenating a plurality of element codes via an interleaver, and performing soft output decoding by inputting received values and prior probability information. Soft output decoding means for generating soft output and / or external information at each time, and external information generated by the soft output decoding means, and inputting the external information based on the same replacement position information as the interleaver. Interleaving means for permuting and rearranging the order of the external information so as to rearrange the order of the information, or so as to restore the arrangement of the information rearranged by the interleaver, and at least soft-output decoding of the input data Delay at the same time as the processing time required by the means, at least the delay at the same time as the processing time required by the interleaving means, or at least the soft output decoding means and Interleave means and a switching means for switching a plurality of delay mode for the processing time of the same time delay required is.

Therefore, the decoding apparatus according to the present invention
By the switching means, at least the delay between the processing time required by the soft output decoding means and the delay at least simultaneously with the processing time required by the interleaving means, or at least the delay between the processing time required by the soft output decoding means and the interleaving means By switching a plurality of delay modes for delaying, it is possible to perform iterative decoding with a simple configuration and with a different number of repetitions without changing the overall decoding delay, thereby providing excellent convenience.

In the decoding method according to the present invention, a probability of passing through an arbitrary state is determined based on a received value that is a soft input, and a plurality of element codes are subjected to a first interleaving process using the probability. A decoding method corresponding to an element code for repeatedly decoding a code generated by concatenating through a plurality of elements, comprising: receiving a received value and prior probability information; performing soft output decoding; Or, a soft output decoding step of generating external information, and inputting the external information generated in the soft output decoding step, and replacing the order of the external information based on the same replacement position information as in the first interleaving step. And a second interleaving step of permuting and rearranging the order of the external information so that the arrangement of the information rearranged in the first interleaving step is restored. And the data of at least the soft-output decoding step takes processing time and the time delay, at least a second
Or a plurality of delay modes for delaying at least the same time as the processing time required for the interleaving step, or at least the processing time required for the soft output decoding step and the second interleaving step.

Therefore, the decoding method according to the present invention
At least the same delay as the processing time required for the soft output decoding step, the delay same as the processing time required for at least the second interleaving step, or at least the processing time required for the soft output decoding step and the second interleaving step. By switching a plurality of delay modes for delaying time, it is possible to perform iterative decoding with the number of repetitions changed without changing the overall decoding delay, and to provide excellent convenience.

Further, the decoding apparatus according to the present invention obtains a probability of passing through an arbitrary state based on a received value which is a soft input, and uses this probability to connect a plurality of element codes via an interleaver. Is a decoding device that repeatedly decodes the generated code, the decoding device includes a plurality of connected element decoders, these element decoders,
A soft output decoding means for inputting a received value and prior probability information and performing soft output decoding to generate soft output and / or external information at each time, and an external information generated by the soft output decoding means. Then, based on the same replacement position information as the interleaver, the order of the external information is replaced and rearranged, or the order of the external information is replaced so that the arrangement of the information rearranged by the interleaver is restored. Interleaving means for reordering and input data, at least a delay at the same time as the processing time required by the soft output decoding means, at least a delay at the same time as the processing time required by the interleaving means, or at least the soft output decoding means and the interleave Switching means for switching between a plurality of delay modes for simultaneously delaying the processing time required by the means.

Therefore, the decoding device according to the present invention
When performing iterative decoding, the switching means causes at least the delay between the processing time required by the soft output decoding means and the delay at least simultaneously with the processing time required by the interleaving means, or at least the soft output decoding means and the interleaving means By switching between a plurality of delay modes for delaying the required processing time and the simultaneous delay, it is possible to perform iterative decoding with a simple configuration and with a different number of repetitions without changing the overall decoding delay. Can be provided.

The decoding method according to the present invention further comprises:
A probability of passing through an arbitrary state is determined based on a received value that is a soft input, and using this probability, a code generated by connecting a plurality of element codes via a first interleaving process is repeatedly decoded. A decoding method, in which a plurality of element decoding steps are performed consecutively, and these element decoding steps perform soft output decoding by receiving a received value and prior probability information, respectively. A soft output decoding step of generating soft output and / or external information at each time, and the external information generated in the soft output decoding step are input, based on the same replacement position information as in the first interleaving step. A second input that replaces and rearranges the order of the external information, or rearranges and rearranges the order of the external information such that the arrangement of the information rearranged in the first interleaving step is restored. When the element decoding step is performed a plurality of times in succession, the input data is at least processed at the same time as the processing time required for the soft output decoding step, and at least the processing time required for the second interleaving step. Or a plurality of delay modes for delaying at least the processing time required for the soft-output decoding step and the second interleaving step at the same time.

Therefore, the decoding method according to the present invention
When performing iterative decoding, at least a delay at the same time as the processing time required for the soft output decoding step, at least a delay at the same time as the processing time required for the second interleaving step, or at least the soft output decoding step and the second interleave By switching between multiple delay modes that delay the processing time required by the process and simultaneously, it is possible to perform iterative decoding with the number of repetitions changed without changing the overall decoding delay, providing excellent convenience It is possible to do.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a communication model to which a data transmission / reception system shown as an embodiment of the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of an example of an encoding device in the data transmission / reception system, and is a block diagram illustrating a configuration of an encoding device that performs encoding by PCCC.

3 is a block diagram illustrating a configuration of an example of a decoding device in the data transmission / reception system, and is a block diagram illustrating a configuration of a decoding device that decodes a code by the encoding device illustrated in FIG. 2;

FIG. 4 is a block diagram illustrating a configuration of an example of an encoding device in the data transmission / reception system, and is a block diagram illustrating a configuration of an encoding device that performs encoding by SCCC.

5 is a block diagram illustrating a configuration of an example of a decoding device in the data transmission / reception system, and is a block diagram illustrating a configuration of a decoding device that decodes a code by the encoding device illustrated in FIG. 4;

FIG. 6 is a block diagram illustrating a schematic configuration of an element decoder.

FIG. 7 is a block diagram illustrating a detailed configuration of a left half portion of the same element decoder.

FIG. 8 is a block diagram illustrating a detailed configuration of a right half of the element decoder.

FIG. 9 is a block diagram illustrating a configuration of a decoded received value selection circuit included in the element decoder.

FIG. 10 is a block diagram illustrating a configuration of an edge detection circuit included in the element decoder.

FIG. 11 is a block diagram illustrating a schematic configuration of a soft output decoding circuit included in the element decoder.

FIG. 12 is a block diagram illustrating a detailed configuration of a left half portion of the soft output decoding circuit.

FIG. 13 is a block diagram illustrating a detailed configuration of a right half portion of the soft output decoding circuit.

FIG. 14 is a block diagram illustrating a configuration example of a Bozencraft convolutional encoder.

FIG. 15 is a block diagram illustrating another configuration example of the Bozencraft convolutional encoder.

FIG. 16 is a block diagram illustrating a configuration example of a Massy type convolutional encoder.

FIG. 17 is a block diagram illustrating another configuration example of the Massy type convolutional encoder.

18 is a block diagram illustrating a specific configuration example of the convolutional encoder illustrated in FIG.

19 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG.

20 is a block diagram illustrating a specific configuration example of the convolutional encoder illustrated in FIG.

21 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG.

22 is a block diagram illustrating a specific configuration example of the convolutional encoder illustrated in FIG.

23 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG.

24 is a block diagram illustrating a specific configuration example of the convolutional encoder illustrated in FIG.

25 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG.

FIG. 26 is a block diagram illustrating a configuration of an internal erasure information generation circuit included in the soft output decoding circuit.

FIG. 27 is a block diagram illustrating a configuration of a termination information generation circuit included in the soft output decoding circuit.

FIG. 28 is a block diagram illustrating a configuration of a received value and prior probability information selection circuit included in the soft output decoding circuit.

FIG. 29 is a block diagram illustrating a configuration of an Iγ calculation circuit included in the soft output decoding circuit.

FIG. 30 is a block diagram illustrating a configuration of an Iγ distribution circuit included in the soft output decoding circuit.

FIG. 31 is a block diagram illustrating a configuration of a parallel path processing circuit for Iβ0 included in the Iγ distribution circuit.

FIG. 32 is a block diagram illustrating a configuration of a log-sum operation circuit for a parallel path included in the parallel path processing circuit for Iβ0.

FIG. 33 is a block diagram illustrating a configuration of an Iα calculation circuit included in the soft output decoding circuit.

FIG. 34 is a block diagram illustrating a configuration of an addition / comparison / selection circuit included in the Iα calculation circuit, which is for a code such that two paths reach from each state on the trellis to the state at the next time. It is a block diagram explaining the composition of the addition comparison selection circuit which performs processing.

FIG. 35 is a block diagram illustrating a configuration of a correction term calculation circuit included in the addition / comparison / selection circuit.

FIG. 36 is a block diagram illustrating a configuration of an addition / comparison / selection circuit included in the Iα calculation circuit, which is for a code such that four paths reach from each state on the trellis to the state at the next time. It is a block diagram explaining the composition of the addition comparison selection circuit which performs processing.

FIG. 37 is a block diagram illustrating a configuration of an Iα + Iγ calculation circuit included in the Iα calculation circuit.

FIG. 38 is a block diagram illustrating a configuration of an Iβ calculation circuit included in the soft output decoding circuit.

FIG. 39 is a block diagram illustrating a configuration of an addition / comparison / selection circuit included in the Iβ calculation circuit, with respect to a code such that two paths arrive from each state on the trellis to the state at the next time. It is a block diagram explaining the composition of the addition comparison selection circuit which performs processing.

FIG. 40 is a block diagram illustrating a configuration of an addition / comparison / selection circuit included in the Iβ calculation circuit, with respect to a code such that four paths arrive from each state on the trellis to the state at the next time. It is a block diagram explaining the composition of the addition comparison selection circuit which performs processing.

FIG. 41 is a block diagram illustrating a configuration of a soft output calculation circuit included in the soft output decoding circuit.

FIG. 42 is a block diagram illustrating a configuration of a log-sum operation circuit included in the soft output calculation circuit.

FIG. 43 is a block diagram illustrating a configuration of a received value or prior probability information separation circuit included in the soft output decoding circuit.

FIG. 44 is a block diagram illustrating a configuration of an external information calculation circuit included in the soft output decoding circuit.

FIG. 45 is a block diagram illustrating a configuration of a hard decision circuit included in the soft output decoding circuit.

FIG. 46 is a block diagram for explaining the concept of a delay RAM in an interleaver provided in the same element decoder.

FIG. 47 is a block diagram for explaining the concept of a delay RAM, and is a block diagram for explaining that the RAM is constituted by a plurality of RAMs.

FIG. 48 is a block diagram for explaining the concept of a RAM for delay, and is a block diagram for explaining how an address generated by a control circuit of the interleaver is appropriately converted and given to each RAM; It is.

FIG. 49 is a block diagram for explaining the concept of an interleaving RAM in the interleaver.

FIG. 50 is a block diagram for explaining the concept of an interleaving RAM, which is based on a sequential write address and a random read address;
FIG. 3 is a block diagram for explaining how addresses are converted into addresses used for banks A and B and given to each RAM.

FIG. 51 is a diagram for explaining the types of interleaving performed by the interleaver, wherein (A) shows random interleaving for one symbol of input data;
(B) shows random interleaving for input data of two symbols, (C) shows inline interleaving for input data of two symbols, and (D)
Shows pairwise interleaving for input data of 2 symbols, (E) shows random interleaving for input data of 3 symbols, (F) shows inline interleaving for input data of 3 symbols, and (G) shows FIG. 6 is a diagram illustrating pairwise interleaving for input data of three symbols.

FIG. 52 is a block diagram illustrating a configuration of the interleaver.

FIG. 53 is a block diagram illustrating a configuration of an odd-length delay compensation circuit included in the interleaver.

FIG. 54 is a block diagram illustrating a configuration of a storage circuit included in the interleaver.

FIG. 55 is a diagram for explaining a method of using a RAM in the interleaver, wherein (A) shows a delay RAM when random interleaving is performed on one symbol of input data; (B) shows an interleave RAM, (C) shows an address RAM, and (D) shows an unused RAM.

FIG. 56 is a diagram for explaining a method of using a RAM in the interleaver, wherein (A) shows a delay RAM when random interleaving is performed on two-symbol input data; (B) shows an interleave RAM, (C) shows an address RAM, and (D) shows an unused RAM.

FIG. 57 is a diagram for explaining a method of using a RAM in the interleaver, in which inline interleaving is performed on input data of two symbols, (A) shows a RAM for delay, (B) is a diagram showing a RAM for interleaving, and (C) is a diagram showing a RAM for addresses.

FIG. 58 is a diagram for explaining a method of using a RAM in the interleaver, in which pair-wise interleaving is performed on two-symbol input data, (A) shows a delay RAM; (B) shows an interleave RAM, (C) shows an address RAM, and (D) shows an unused RAM.

FIG. 59 is a diagram for explaining a method of using a RAM in the interleaver, wherein (A) shows a delay RAM when random interleaving is performed on input data of three symbols; (B) shows an interleave RAM, (C) shows an address RAM, and (D) shows an unused RAM.

FIG. 60 is a diagram for explaining a method of using a RAM in the interleaver, in which inline interleaving is performed on input data of three symbols, (A) shows a delay RAM, (B) shows an interleave RAM, (C) shows an address RAM, and (D) shows an unused RAM.

FIG. 61 is a diagram for explaining a method of using a RAM in the interleaver, wherein (A) shows a delay RAM when performing pairwise interleaving on input data of three symbols; (B) shows an interleave RAM, (C) shows an address RAM, and (D) shows an unused RAM.

FIG. 62 is a block diagram illustrating a configuration of a decoding device that is configured by connecting the same element decoders.

FIG. 63 is a block diagram illustrating a simplified configuration of two adjacent element decoders that constitute the decoding device,
It is a block diagram explaining the structure which selects the information required for soft output decoding from the information from the element decoder of a preceding stage.

FIG. 64 is a block diagram illustrating a simplified configuration of two adjacent element decoders that constitute the decoding device,
FIG. 21 is a block diagram illustrating a configuration in which information necessary for soft-output decoding in a next-stage element decoder is selected by a previous-stage element decoder.

FIG. 65 is a block diagram illustrating a simplified configuration of two adjacent elementary decoders constituting the decoding device,
It is a block diagram explaining the structure provided with the delay circuit which delays a received value.

FIG. 66 is a block diagram for explaining a simplified configuration of two adjacent element decoders constituting the decoding apparatus,
It is a block diagram explaining the structure provided with the decoding reception value selection circuit which selects the reception value to decode.

67 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 14, and is a diagram illustrating numbering based on a branch input as viewed from a state of a transition destination; FIG. ) Shows the numbering when the number of memories is 4, (B) shows the numbering when the number of memories is 3, (C) shows the numbering when the number of memories is 2, D) is a diagram showing numbering when the number of memories is one.

68 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 14, and is a diagram illustrating numbering based on a branch output from the state of a transition source, and (A) shows the numbering when the number of memories is four, (B) shows the numbering when the number of memories is three, (C) shows the numbering when the number of memories is two, (D) is a diagram showing numbering when the number of memories is one.

69 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 15, and is a diagram illustrating numbering based on a branch input as viewed from a transition destination state; FIG. () Shows numbering when the number of memories is three, and (B) is a diagram showing numbering when the number of memories is two.

70 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 15, and is a diagram illustrating numbering based on a branch output from the state of the transition source, and 3A is a diagram showing numbering when the number of memories is three, and FIG. 3B is a diagram showing numbering when the number of memories is two.

71 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 16, and is a diagram illustrating numbering based on a branch input as viewed from a state of a transition destination; FIG. () Shows numbering when the number of memories is three, and (B) is a diagram showing numbering when the number of memories is two.

72 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 16, and illustrating numbering based on a branch output from the state of the transition source, and 3A is a diagram showing numbering when the number of memories is three, and FIG. 3B is a diagram showing numbering when the number of memories is two.

73 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 17, and is a diagram illustrating numbering based on a branch input as viewed from a transition destination state; FIG. () Shows numbering when the number of memories is two, and (B) is a diagram showing numbering when the number of memories is one.

74 is a diagram illustrating a trellis in the convolutional encoder illustrated in FIG. 17, and is a diagram illustrating numbering based on a branch output from the state of the transition source, and FIG. 4A is a diagram illustrating numbering when the number of memories is two, and FIG. 4B is a diagram illustrating numbering when the number of memories is one.

FIG. 75 is a diagram illustrating a trellis for describing an operation of generating termination information, and is a diagram illustrating an operation of inputting termination information for the number of input bits for a termination period.

FIG. 76 is a diagram illustrating a trellis for describing an operation of generating termination information, and is a diagram illustrating an operation of inputting termination information in one time slot.

FIG. 77 is a block diagram illustrating a schematic configuration of the Iγ calculation circuit and the Iγ distribution circuit, wherein log likelihood Iγ for all input / output patterns is calculated, and input / output determined according to a code configuration; It is a block diagram explaining the structure which distributes according to a pattern.

FIG. 78 is a block diagram illustrating a schematic configuration of the Iγ calculation circuit and the Iγ distribution circuit, and calculates a log likelihood Iγ for at least a part of input / output patterns and selects a desired log likelihood Iγ FIG. 3 is a block diagram illustrating a configuration for performing addition.

FIG. 79 is a block diagram illustrating a schematic configuration of the Iγ calculation circuit and the Iγ distribution circuit. In a case where the log likelihood Iγ for all input / output patterns is calculated, 1 is used for the log likelihood Iγ. It is a block diagram explaining the structure which performs normalization for every time.

FIG. 80 is a diagram for explaining normalization of the log likelihood Iγ when the same element decoder treats the log likelihood as a negative value. FIG. 80 (A) shows the log likelihood Iγ before normalization. FIG. 4B shows a distribution example, and FIG. 4B is a diagram showing a distribution example of the log likelihood Iγ after normalization.

FIG. 81 is a diagram for explaining normalization of the log likelihood Iγ when the same element decoder treats the log likelihood as a positive value. FIG. 81 (A) is a diagram illustrating the log likelihood Iγ before normalization. FIG. 4B shows a distribution example, and FIG. 4B is a diagram showing a distribution example of the log likelihood Iγ after normalization.

FIG. 82 is a block diagram illustrating a schematic configuration of the Iγ calculation circuit and the Iγ distribution circuit, and calculates a log likelihood Iγ for at least a part of input / output patterns; FIG. 3 is a block diagram illustrating a configuration for performing normalization at each time.

83A and 83B are diagrams illustrating an example of a trellis in a convolutional encoder. FIG. 83A illustrates an example in which the number of memories is “1”, and FIG. 83B illustrates an example in which the number of memories is “2”. (C) shows an example when the number of memories is "3", and (D) shows an example when the number of memories is "4".

FIG. 84 is a view for explaining a state in which the four trellis shown in FIG. 83 are overlaid;

FIG. 85 is a block diagram illustrating a configuration of an addition / comparison / selection circuit in the Iα calculation circuit that performs processing on a code such that two paths arrive from each state on the trellis to a state at the next time; FIG. 14 is a block diagram illustrating a configuration including a selector that selects log likelihood Iα.

FIG. 86 is a block diagram illustrating a schematic configuration of a log-sum operation circuit in the Iα calculation circuit and the Iβ calculation circuit, wherein log-s performing normalization by the first method;
FIG. 3 is a block diagram illustrating a configuration of a um operation circuit.

FIG. 87 is a diagram for describing normalization by the first method, and is a diagram illustrating an example of a dynamic range before and after normalization.

FIG. 88 is a diagram for describing normalization by the second method, and is a diagram illustrating an example of a dynamic range before and after normalization.

FIG. 89 is a block diagram illustrating a schematic configuration of a log-sum operation circuit in the Iα calculation circuit and the Iβ calculation circuit, wherein log-s performs normalization by a third method;
FIG. 3 is a block diagram illustrating a configuration of a um operation circuit.

FIG. 90 is a diagram for describing normalization by the third method, and is a diagram illustrating an example of a dynamic range before and after normalization.

FIG. 91 is a block diagram illustrating a schematic configuration of a log-sum operation circuit, and is a block diagram illustrating a configuration of a log-sum operation circuit that performs a normal log-sum operation.

FIG. 92 is a block diagram illustrating a schematic configuration of a log-sum arithmetic circuit, which calculates values of a plurality of correction terms corresponding to difference values, and selects an appropriate one from among them.
FIG. 9 is a block diagram illustrating a configuration of a log-sum operation circuit that performs a −sum operation.

FIG. 93 is a block diagram illustrating a schematic configuration of a soft output calculation circuit that performs a cumulative addition operation of a log-sum operation without using an enable signal.

FIGS. 94A and 94B are diagrams for explaining normalization for external information in symbol units, where FIG. 94A shows an example of distribution of external information before normalization, and FIG. 94B shows external information having a maximum value; Shows an example of the distribution of the external information after the normalization in which is adjusted to a predetermined value. FIG.
(D) is a diagram illustrating an example of distribution of normalized external information in which the value of external information for one symbol is different from the value of external information for another symbol.

FIG. 95 is a diagram for explaining signal point arrangement by the 8PSK modulation method, and is a diagram showing a state where a boundary line is provided on an I / Q plane.

FIG. 96 is a block diagram illustrating a simplified configuration of a control circuit included in the interleaver.

FIG. 97 is a diagram illustrating timings of writing and reading data when a counter for a write address and a counter for a read address are shared.

FIG. 98 is a diagram illustrating timings of writing and reading data when a counter for a write address and a counter for a read address are separately provided.

FIG. 99 is a diagram for explaining how data is written to and read from the RAM in the interleaver.

FIG. 100 is a view for explaining the manner in which continuous addresses are assigned to RAMs in the interleaver.

FIG. 101 is a diagram for describing how data is written to and read from a RAM in the interleaver, and illustrates how data is written and read when data is not stored in all storage areas of each RAM. FIG.

FIG. 102 is a diagram for explaining how continuous addresses are assigned to RAMs in the interleaver, and for explaining how continuous addresses are assigned to a plurality of physically different RAMs; FIG.

FIG. 103 is a diagram for explaining how to assign an address to a RAM in the interleaver, and is a diagram for explaining how to give a replacement destination address by a combination of a time slot and an input symbol. .

104 is a view for explaining how addresses are assigned to RAMs in the interleaver, and inputs a replacement address as a time slot when data is not stored in all storage areas of each RAM. FIG. It is a figure for explaining a mode given in combination with a symbol.

105 is a diagram for explaining the storage capacity of the RAM in the interleaver, FIG. 105 (A) shows the storage capacity of the RAM in a normal state, and FIG. 105 (B) shows the case where the RAM operates as a partial write RAM; 3 is a diagram showing a pseudo storage capacity of a RAM in FIG.

FIG. 106 is a diagram for explaining how data is written to and read from the RAM in the interleaver.
FIG. 11 is a diagram for describing an example of realizing a delay of an interleave length for six time slots using a bank.

107 is a chart illustrating timings for writing and reading data by the operation shown in FIG. 106.

Fig. 108 is a block diagram illustrating a configuration example of a convolutional encoder.

[Fig. 109] Fig. 109 is a block diagram illustrating a configuration example of an encoding device, and is a block diagram illustrating a manner in which the order between input symbols to an interleaver is changed.

Fig. 110 is a block diagram illustrating a simplified configuration of two adjacent element decoders included in the decoding device, and is a block diagram illustrating a configuration in which the interleaver has a symbol exchange circuit.

Fig. 111 is a block diagram illustrating a simplified configuration of two adjacent element decoders included in the decoding device, and is a block diagram illustrating a configuration in which the soft-output decoding circuit includes a symbol exchange circuit.

FIG. 112 is a block diagram illustrating a configuration of a communication model.

FIG. 113 is a diagram for describing a trellis in a conventional encoding device, and for explaining the contents of probabilities α, β, and γ.

FIG. 114 is a flowchart illustrating a series of steps in performing a soft output decoding by applying a BCJR algorithm in a conventional decoding device.

[FIG. 115] FIG. 115 shows a conventional decoding device, which is Max-Log.
It is a flowchart explaining a series of processes at the time of performing soft output decoding by applying the -BCJR algorithm.

[Explanation of symbols]

Reference Signs List 1 encoding device, 3 decoding device, 50 element decoder, 60,400 control circuit, 70 decoded reception value selection circuit, 80 edge detection circuit, 90 soft output decoding circuit, 100 interleaver, 110 address storage circuit, 120, 411, 421, 422, 42
3,425,426,501,502,503,50
4,520,530,540,603 selector, 1
30 signal lines, 151 code information generation circuit, 152
Internal erasure information generation circuit, 153 termination information generation circuit,
154 received value and prior probability information selection circuit, 155
Receiving data and delay storage circuit, 156 Iγ calculation circuit, 157 Iγ distribution circuit, 158 Iα calculation circuit, 159 Iβ calculation circuit, 160 Iβ storage circuit, 161 soft output calculation circuit, 162 Received value or prior probability information separation circuit, 163 External information calculation circuit,
164 amplitude adjustment and clipping circuit, 165 hard decision circuit, 222 Iγ normalization circuit, 223 branch input / output information calculation circuit, 225 ₁ Iβ0 parallel path processing circuit, 225 ₂ Iβ1 parallel path processing circuit, 2
25 ₃ Iα parallel path processing circuit, 232, 25
3,330 selection control signal generation circuit, 252,37
2,582 lookup table, 240,280
Control signal generation circuit, 241, 242, 283, 28
4 addition comparison selection circuit, 243 Iα + Iγ calculation circuit,
245, 256, 286, 292, 312, 550,
560,580,591 log-sum operation circuit,
247, 258, 288, 294 correction term calculation circuit,
250, 272Iα normalization circuit, 281 Iβ0 addition / comparison / selection circuit, 282 Iβ1 addition / comparison / selection circuit, 291,308 Iβ0 normalization circuit, 310
Iα + Iγ + Iβ calculation circuit, 311 enable signal generation circuit, 313 Iλ calculation circuit, 350 information bit external information calculation circuit, 351 information symbol external information calculation circuit, 352 code external information calculation circuit, 35
7, 554, 564 Normalization circuit, 361 Minimum symbol calculation circuit, 370 I / Q demapping circuit, 40
1 delay address generation circuit, 402 odd-number delay compensation circuit, 403 interleave address conversion circuit,
404 delay address conversion circuit, 405 address selection circuit, 406 input data selection circuit, 407 storage circuit, 408 output data selection circuit, 410,5
65 registers, 421 inverters, 424 R
AM, 510 delay circuit, 531 adder, 59
0 selection circuit, 601 write address generation circuit,
602 read address generation circuit, 610, 61
1,612,613 symbol exchange circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 13/45 H03M 13/45 (72) Inventor Masayuki Hattori 6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo Sony Corporation F term (reference) 5B001 AA10 AA13 AA14 AB02 AB05 AC01 AC04 AC05 AD06 AE02 5J065 AC02 AD10 AD13 AF03 AG05 AG06 AH02 AH06 AH07 AH09 AH13 AH16 AH17 AH21

Claims (30)

[Claims] 1. Probability of passing an arbitrary state is determined based on a received value that is a soft input, and using the probability, a code generated by connecting a plurality of element codes via an interleaver is repeated. A decoding device corresponding to the element code for decoding, the soft output decoding that performs soft output decoding by inputting the received value and the prior probability information and generates a soft output and / or external information at each time. Means, the external information generated by the soft output decoding means is input, and based on the same replacement position information as the interleaver, the order of the external information is replaced and rearranged, or by the interleaver. Interleaving means for permuting and rearranging the order of the external information so as to restore the rearranged information array; and A delay that is the same as the processing time required by the stage, a delay that is at least the same as the processing time that the interleaving means requires, or a plurality of delays that are at least a simultaneous delay with the processing time that the soft output decoding means and the interleaving means require A decoding device comprising: switching means for switching a delay mode. 2. The method according to claim 1, wherein the switching unit is configured to delay at least the processing time required by the soft output decoding unit, at least the processing time required by the interleaving unit, or at least the soft output decoding unit and the soft output decoding unit. 2. The decoding apparatus according to claim 1, wherein a control signal is generated to indicate that one of a processing time required by the interleaving means and a delay at the same time is performed. 3. The decoding device according to claim 2, further comprising a selection unit that selects information output from the soft output decoding unit based on the control signal generated by the switching unit. 4. A delay means for delaying the prior probability information by at least the same time as the processing time required by the soft output decoding means, wherein the selection means outputs the control signal generated by the switching means. On the basis of the information obtained by delaying the prior probability information by the delay means, and information obtained as a result of soft output decoding by the soft output decoding means, 4. The decoding device according to claim 3, wherein 5. The data processing apparatus according to claim 2, wherein the interleaving means performs an address control based on the control signal generated by the switching means to output the input data without rearranging the input data. Decoding device. 6. The decoding device according to claim 1, wherein the decoding device is configured to be integrated on a semiconductor substrate. 7. The decoding according to claim 1, wherein the decoding is for repeatedly decoding codes subjected to parallel concatenation coding, column concatenation coding, parallel concatenation coding modulation, or column concatenation coding modulation. apparatus. 8. The decoding device according to claim 7, wherein said element code is a convolutional code. 9. The soft-output decoding means includes a Log-BCJ
The decoding apparatus according to claim 1, wherein maximum a posteriori probability decoding is performed based on an R algorithm. 10. A probability of passing through an arbitrary state is determined based on a received value that is a soft input, and using the probability,
A decoding method corresponding to the element code for repeatedly decoding a code generated by concatenating a plurality of element codes through a first interleaving step, wherein the received value and the prior probability information are input. A soft output decoding step of performing soft output decoding to generate soft output and / or extrinsic information at each time; and inputting the extrinsic information generated in the soft output decoding step and being the same as the first interleaving step Based on the replacement position information, the order of the external information is replaced and rearranged, or the order of the external information is changed so that the arrangement of the information rearranged in the first interleaving step is restored. A second interleaving step of permuting and rearranging the input data, wherein at least the processing time required for the soft output decoding step and a delay at the same time as at least the second A delay between the processing time required by the interleaving step and a plurality of delay modes for delaying at least the processing time required by the soft output decoding step and the second interleaving step at the same time. Method. 11. A delay at least as long as the processing time required for the soft output decoding step, a delay at least as much as the processing time required for the second interleaving step, or at least the soft output decoding step and the second processing time. 11. The decoding method according to claim 10, further comprising: generating a control signal indicating that one of a processing time required for the interleaving step and a delay between the processing times is performed. 12. The decoding method according to claim 11, further comprising a selection step of selecting information output through the soft output decoding step based on the control signal. 13. A delay step for delaying the prior probability information by at least the same time as the processing time required for the soft output decoding step, wherein the selecting step includes the steps of: 13. The method according to claim 12, wherein one of the information obtained by delaying the prior probability information and the information obtained as a result of soft output decoding in the soft output decoding step is selected. Decryption method. 14. In the second interleaving step,
12. The decoding method according to claim 11, wherein the input data is output without being rearranged by performing address control based on the control signal. 15. A probability of passing through an arbitrary state is determined based on a received value that is a soft input, and using the probability,
A decoding device for repeatedly decoding a code generated by connecting a plurality of element codes via an interleaver, wherein the decoding apparatus includes a plurality of connected element decoders, and each of the element decoders includes: Soft output decoding means for inputting the received value and the prior probability information and performing soft output decoding to generate soft output and / or external information at each time; and outputting the external information generated by the soft output decoding means. Input, and based on the same replacement position information as the interleaver, the external information is replaced and rearranged, or the external information is rearranged by the interleaver so as to restore the original array. Interleaving means for permuting and rearranging the order of information; and input data, at least a delay between the processing time required by the soft output decoding means and a simultaneous delay, at least. A switching means for switching between a plurality of delay modes for delaying at the same time as the processing time required by the interleaving means, or at least a delay at the same time as the processing time required by the soft output decoding means and the interleaving means. Decoding device. 16. The switching means may include a delay at least as long as the processing time required by the soft output decoding means, at least a delay at the same time as the processing time required by the interleaving means, or at least the soft output decoding means and the soft output decoding means. 16. The decoding device according to claim 15, wherein a control signal is generated to indicate that any one of a processing time required by the interleaver and a delay at the same time is performed. 17. The element decoder according to claim 16, further comprising a selection unit that selects information output from the soft output decoding unit based on the control signal generated by the switching unit. The decoding device according to any one of the preceding claims. 18. The element decoder includes delay means for delaying the prior probability information by at least the same processing time as the soft output decoding means, and the selection means generates the prior probability information by the switching means. Based on the control signal, the information obtained by delaying the prior probability information by the delay means, and information obtained as a result of soft output decoding by the soft output decoding means, 18. The decoding device according to claim 17, wherein the decoding device is selected. 19. The apparatus according to claim 15, wherein the interleaving means performs an address control based on the control signal generated by the switching means, and outputs the input data without rearranging the data. Decoding device. 20. The decoding apparatus according to claim 15, wherein the element decoders are connected by a number represented by a product of the number of the element codes and the number of iterations of the iterative decoding. 21. The decoding device according to claim 15, wherein the element decoder is configured to be integrated on a semiconductor substrate. 22. The decoding apparatus according to claim 15, wherein codes subjected to parallel concatenated coding, column concatenated coding, parallel concatenated coding modulation, or column concatenated coding modulation are repeatedly decoded. 23. The decoding apparatus according to claim 22, wherein said element code is a convolutional code. 24. The soft output decoding means, comprising: Log-BC
16. The decoding device according to claim 15, wherein maximum a posteriori probability decoding is performed based on a JR algorithm. 25. A probability of passing through an arbitrary state is determined based on a received value that is a soft input, and using the probability,
A decoding method for repeatedly decoding a code generated by concatenating a plurality of element codes through a first interleaving step, wherein the decoding method includes performing a plurality of element decoding steps consecutively, The element decoding step includes: receiving the received value and the prior probability information, performing soft output decoding, and generating a soft output and / or external information at each time; and a soft output decoding step. The external information generated as described above is input, and the order of the external information is replaced and rearranged based on the same replacement position information as in the first interleaving step, or the external information is arranged in the first interleaving step. A second interleaving step of permuting and rearranging the order of the external information so as to restore the sequence of the permuted information, wherein the element decoding step is performed a plurality of times continuously. When that, the entered data, at least the soft-output decoding step of processing time and the time required delay, at least the second interleaving step of processing time and the time required delay, or,
A decoding method characterized in that a plurality of delay modes for simultaneously delaying at least the processing time required for the soft output decoding step and the second interleaving step are switched. 26. The element decoding step, wherein the delay is at least the same as the processing time required for the soft output decoding step, at least the delay is the same as the processing time required for the second interleaving step, or at least the soft output. 26. The decoding method according to claim 25, further comprising generating a control signal indicating that one of a processing time required for the decoding step and the second interleaving step and a delay for the same time are performed. 27. The element decoding step according to claim 26, further comprising a selection step of selecting information output through the soft output decoding step based on the control signal.
The decoding method described. 28. The element decoding step includes a delay step for delaying the prior probability information by at least the same time as the processing time required for the soft output decoding step. And selecting one of information obtained by delaying the prior probability information in the delay step and information obtained as a result of soft output decoding in the soft output decoding step. 28. The decoding method according to claim 27, wherein 29. In the second interleaving step,
26. The decoding method according to claim 25, wherein the input data is output without being rearranged by performing address control based on the control signal. 30. The decoding method according to claim 25, wherein the element decoding step is performed by a number represented by a product of the number of the element codes and the number of iterations of the iterative decoding.