JP2002076851A - Flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flip-flop circuit that reduces the total capacity of its clock system so as to suppress power consumption. SOLUTION: Inverters 1, 2 supply a clock ck to master and slave side transmission gates 4, 8 without using a clocked inverter for data latching, and an NMOS transistor(TR) 5 and a PMOS TR 6 whose drain voltage/source voltage is inversely connected to that of a conventional CMOS circuit latch data when the transmission gates 4, 8 are open. Thus, the total capacity of the clock system can be reduced so as to suppress the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a flip-flop circuit, and more particularly to a master-slave type flip-flop circuit capable of suppressing power consumption in a clock system.

[0002]

2. Description of the Related Art In recent large-scale integrated circuit systems, high speed and low power consumption have been emphasized. A circuit often used in the system is a flip-flop circuit. In the flip-flop circuit, the data system hardly consumes power if no transition occurs. On the other hand, the clock system always operates unless stopped by the system, so that the power consumption depends on the total capacity of the clock system.

FIG. 3 is a circuit diagram showing a conventionally used flip-flop circuit. The flip-flop circuit includes an inverter 101 that inputs a clock ck and an inverter 1 that inputs an inverted output of the inverter 101.
02, an inverter 103 for inputting data d, a transmission gate 104 for inputting an inverted output of the inverter 103, and a transmission gate 1
Inverter 105 receiving the output of the inverter 104, a clocked inverter 106 receiving the output of the inverter 105 and receiving the output of the inverter 105, a transmission gate 107 receiving the inverted output of the inverter 105, and the transmission gate 107 And an inverter 108 for inputting the output of
A clocked inverter 109 whose input is the output of the inverter 108 and whose output is the input of the inverter 108;
And an inverter 110 which inverts the output of the flip-flop circuit to form the output q of the flip-flop circuit.

The transmission gate 104, the inverter 105, and the clocked inverter 106 form a data holding unit on the master side, and the transmission gate 107, the inverter 108, and the clocked inverter 109 form a data holding unit on the slave side. ing.

In the conventional master / slave type flip-flop circuit configured as described above, the clock ck
Becomes low level, the transmission gate 104 on the master side is opened, and the inverter 105 and the clocked inverter 106 latch the data d. At this time, the transmission gate 107 on the slave side is closed.

Next, when the clock ck goes high, the transmission gate 104 on the master side is closed, and the transmission gate 107 on the slave side is closed.
Is open. As a result, the data latched by inverter 105 and clocked inverter 106 is transferred to inverter 108 and clocked inverter 10.
9 and is output from the output q via the inverter 110.

As described above, in the master-slave type flip-flop circuit, the master latches the input data in the first half of one cycle of the clock, and latches and outputs the input data latched by the master in the second half. .

[0008]

In the case of a standard cell, the clock ck is used in order to prevent the transmission gate on the master side and the transmission gate on the slave side from being opened at the same time and data from being passed through. Is often received in a two-stage buffer. Even if a custom design is performed and the timing is adjusted, reliability cannot be obtained with a single-phase signal, and it is necessary to take a method of supplying a positive / negative phase clock from outside the cell. Therefore, there is a problem that it is difficult to reduce the power of a flip-flop of a static circuit such as a standard cell.

SUMMARY OF THE INVENTION The present invention has been made in view of such a point, and an object of the present invention is to provide a flip-flop circuit capable of reducing the total capacity of a clock system and suppressing power consumption.

[0010]

According to the present invention, in a flip-flop circuit having a latch section for holding data on each of a master side and a slave side, the latch section on the master side captures data by a clock. A first transmission gate to be performed, a first N-type transistor on the power supply side of the substrate, and a first P-type transistor on the ground side of the substrate, and the gate receives data captured by the first transmission gate. A first data holding circuit for holding the data, wherein the latch unit on the slave side is a second transmission gate that performs a complementary operation with the first transmission gate by the clock; N-type transistor, a second P-type transistor is arranged on the ground side of the substrate, and the second And a second data holding circuit receiving and holding the data captured by the lance transmission gate to gate, flip-flop circuit is provided, characterized in that.

According to the above configuration, the first clock is used for the first clock.
Is opened, and high-level data d is input to the gates of the first N-type transistor and the first P-type transistor.
The type transistor is turned on, the node that is the connection between the first N-type transistor and the first P-type transistor goes to a high level, and this level is maintained even when the first transmission gate is closed. Since the potential of the node does not logically have a path for moving charges, it is maintained at a high level as it is. Conversely, when low-level data d is input to the gates of the first N-type transistor and the first P-type transistor, the first P-type transistor is turned on, and the node is set to low level. This level is maintained at the low level state even when the first transmission gate is closed because the node potential has no logical charge injection path. This eliminates the need for a clocked inverter for holding data, so that the total capacity of the clock system can be reduced and power consumption can be reduced.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a flip-flop circuit according to the first embodiment of the present invention.

This flip-flop circuit operates with a clock c
An inverter 1 for inputting k, an inverter 2 for inputting an inverted output of the inverter 1, an inverter 3 for inputting data d, and an inverted output of the inverter 3 as input and clock outputs of the inverters 1 and 2 as input. A transmission gate 4 and an NMOS (N-type metal oxide semiconductor) having the output of the transmission gate 4 as an input
Latch comprising a transistor 5 and a PMOS (P-type metal oxide semiconductor) transistor 6, an inverter 7 receiving an output of the latch, and a clock of the inverters 1 and 2 receiving an inverted output of the inverter 7 as an input. A transmission gate 8 having an output as an input; a latch section comprising an NMOS transistor 9 and a PMOS transistor 10 having an output of the transmission gate 8 as an input; an inverter 11 having an output of the latch section as an input; And an inverter 12 which inverts the output of the flip-flop circuit to form the output q of the flip-flop circuit.

Here, transmission gate 4, transistors 5, 6 and inverter 7 constitute a master side data holding unit, and transmission gate 8, transistors 9, 10 and inverter 11 constitute a slave side data holding unit. are doing.

A feature of this flip-flop circuit is that a normal CMOS (complementary metal oxide semiconductor) inverter circuit does not use a clocked inverter for holding data as a latch unit, and has a drain voltage and The source voltage is constituted by NMOS / PMOS transistors connected in reverse. That is, in a normal CMOS inverter circuit, the PMO
Although the S transistor is connected and the NMOS transistor is connected to the ground terminal side, in the latch section of the flip-flop circuit according to the present invention, the N terminal is connected to the power supply terminal side.
Connect a MOS transistor and connect a PMO
It has a configuration in which S transistors are connected.

Next, the operation of the flip-flop circuit will be described. First, paying attention to the latch section on the master side, when the data d is at the low level and the clock ck is at the low level, the transmission gate 4 is opened, and the node n0 is the inverted of the data d, that is, at the high level. . At this time, the gates of the transistors 5 and 6 are also at a high level, and the transistor 5 is turned on.

After that, when the clock ck becomes high level and the transmission gate 4 is closed, the potential of the node n0 remains unchanged since there is no logical path for moving electric charges.
Are kept in the ON state, and the high level is held as data.

The operation of the data d and the clock ck under the above conditions is the same in the latch section on the slave side. next,
When the data d is at the high level and the clock ck is at the low level, the transmission gate 4 is open, and the node n0 is the inversion of the data d, that is, at the low level. At this time, the gates of the transistors 5 and 6 are also at the low level, and the transistor 6 is turned on.

Thereafter, when the clock ck becomes high level and the transmission gate 4 is closed, the potential of the node n0 remains unchanged because there is no logical charge injection path.
, And the low level is held as data.

The operation of the data d and the clock ck under the above conditions is the same for the slave latch unit. As described above, the flip-flop circuit of the present invention does not use a clocked inverter for holding data,
Accordingly, the total capacity of the clock system can be reduced, power consumption can be suppressed, and power can be reduced irrespective of the speed of the clock signal.

However, in practice, the current driving capability of the transistor increases due to process variations, and accordingly,
The threshold voltage (Vth) of the transistor decreases due to the increase in the substrate leakage current and the temperature rise during operation, and the PMOS / NMOS of the CMOS circuit is simultaneously turned on by a slight rise / fall of the potential, It is easily considered that a through current occurs.

When these facts are applied to the flip-flop circuit shown in FIG. 1, the substrate leakage current is maximized when the transistor is completely turned on. If the node n0 is at a high level, the clock ck is at a high level, and the transmission gate 4 is closed, the transistor 5 is turned on and the base is the ground GND. It leaks through the transistor 5 to the ground GND which is the base. At the same time, charge is injected from the power supply VDD of the substrate via the transistor 6, but since the transistor 6 is in the off state, its ability is low, and charge leakage is dominant.

However, if this state continues, the potential of node n0 will decrease. Then, the ON state of the transistor 5 becomes gradually shallower, and at the same time, the transistor 6 in the state where the threshold value Vth becomes lower due to the above-described factor becomes the shallow ON state. As this state progresses, the ground GND of the substrate is connected via the transistor 5 at the node n0.
Is equal to the charge injected from the power supply VDD of the substrate via the transistor 6, and the node n0
Is stabilized at a potential lower than the high level in the initial state.

Further, even when the node n0 is in the low level state, the node n0 is stabilized at a potential higher than the low level in the initial state in a completely opposite process. These state transitions are the same on the slave side. At this time, the inverters 7 and 11 connected to the nodes n0 and n1, respectively, have intermediate potentials and have a threshold Vt
If the conditions for lowering h are satisfied, the PMOS / NMO
S is turned on at the same time, and a through current is generated. However, if a change in potential exceeding the threshold value Vth of the transistor does not occur, no through current flows, and the flip-flop circuit in FIG. 1 may be effective in power consumption.

Next, a description will be given of a flip-flop in consideration of a problem when there is a change in potential exceeding a threshold value Vth of a transistor. FIG. 2 is a circuit diagram showing a flip-flop circuit according to a second embodiment of the present invention. In FIG. 2, the inverters and the transmission gates are the same as those shown in FIG.

In this flip-flop circuit, the latch section on the master side includes an NMOS transistor 21 and a P-type transistor.
A MOS transistor 22, an NMOS transistor 23, and a PMOS transistor 24;
Compared with the latch unit shown in FIG. 1, a PMOS transistor 22 having a gate connected to the ground GND of the substrate is arranged between the NMOS transistor 21 and the node n01, and between the node n01 and the PMOS transistor 24. An NMOS transistor 23 having a gate connected to the power supply VDD of the substrate is disposed in the power supply. Similarly, the latch section on the slave side also includes an NMOS transistor 25 and a PMOS transistor 25.
Transistor 26 and NMOS transistor 27
And a PMOS transistor 28. Here, it is assumed that the transistors 22, 23, 26, and 27 connected to the nodes n01 and n11 are transistors having sufficiently large on-resistance.

Next, the operation of the flip-flop circuit will be described. First, on the master side, when the data d is at a low level and the clock ck is at a low level, the transmission gate 4 is opened,
The node n01 is the inversion of the data d, that is, goes to the high level. At this time, the gates of the transistors 21 and 24 are also at a high level, and the transistor 21 is turned on. At this time, the potentials of the nodes n00 and n02 are also at the high level.

Thereafter, when the clock ck becomes high level and the transmission gate 4 is closed, the electric charge at the node n00 is transferred through the transistor 21 to
Although it is considered that leakage occurs to the ground GND serving as the substrate, at the same time, charge is injected from the power supply VDD of the substrate via the transistor 22 which is sufficiently turned on, and the node n0
0 is stable in a high level state slightly lower than the power supply VDD of the board. Since the on-resistance of the transistor 22 is sufficiently large, this charge transfer occurs between the ground GND of the base of the transistor 21 related to the node n00 and the power supply VDD of the base of the transistor 22 and has no effect on the node n01.

The node n02 stabilizes at a high level lower than the power supply VDD of the circuit board in the same process as that occurring at the node n0 of the circuit of FIG. 1, but the ON resistance of the transistor 23 is sufficiently large. The transfer of charge occurs between the ground GND of the base of the transistor 23 related to the node n02 and the power supply VDD of the base of the transistor 24, and has no effect on the node n01.

Therefore, the nodes n00 and n02
Has no effect on the node n01.
There is no change in the potential at 1. Therefore, the node n01 is stable in the high level state and holds data. That is, even if the threshold value Vth of the transistor is lowered due to a process variation or a temperature rise during operation, a through current does not flow in the inverter 7. This is exactly the same for the change of the nodes n10, n11 and n12 on the slave side, and is the same even when the data d is at the high level.

[0031]

As described above, the present invention does not use a clocked inverter for holding data as in a conventionally used flip-flop circuit, but uses an ordinary C-type inverter.
The configuration is such that data is held by an NMOS / PMOS whose drain voltage / source voltage is connected in reverse to the MOS circuit. As a result, the total capacity of the clock system can be reduced, and power consumption can be suppressed. At the same time, not only custom designs but also ASICs (Appl
(Communication Specific Integrated Circuit) It is also possible to make a cell as a gate array or a standard cell that can be used for design.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a flip-flop circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a flip-flop circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a flip-flop circuit conventionally used.

[Explanation of symbols]

1,2,3,7,11,12 ... inverter, 4,8 ...
... Transmission gate, 5,9 ... NMOS transistor, 6,10 ... PMOS transistor, 2
1, 23, 25, 27 ... NMOS transistors, 2
2, 24, 26, 28 ... PMOS transistor, c
k: clock, d: data, q: output.

Claims (3)

[Claims] 1. A flip-flop circuit having a latch unit for holding data on each of a master side and a slave side, wherein the latch unit on the master side comprises: a first transmission gate for taking in data by a clock; A first N-type transistor on the power supply side, a first P-type transistor on the ground side of the substrate, and a first data holding circuit for receiving and holding the data received by the first transmission gate at the gate. A latch unit on the slave side, a second transmission gate performing a complementary operation with the first transmission gate by the clock, and a second transmission gate on a power supply side of the substrate.
A second data holding circuit for arranging a second P-type transistor on the ground side of the substrate and receiving and holding the data fetched by the second transmission gate at the gate. Flip-flop circuit. 2. A flip-flop circuit comprising a latch section for holding data on each of a master side and a slave side, wherein the master side latch section includes a first transmission gate for taking in data by a clock, and a base board. A first N-type transistor receiving the data received by the first transmission gate at the gate and a first P-type transistor having the gate connected to the ground of the base are connected in series to the power supply side, and the gate is connected to the ground of the base. Is connected in series to a second N-type transistor connected to the power supply of the substrate and a second P-type transistor receiving at its gate the data received by the first transmission gate, and the data received by the first transmission gate. And a first data holding circuit for holding The slave-side latch unit includes a second transmission gate that performs a complementary operation with the first transmission gate by the clock, and a gate that receives data captured by the second transmission gate on a power supply side of a board. A fourth N-type transistor having a third N-type transistor and a third P-type transistor having a gate connected to the ground of the substrate connected in series, a fourth N-type transistor having a gate connected to the power supply of the substrate on the ground side of the substrate, and A second data holding circuit for connecting in series a fourth P-type transistor that receives data received by the first transmission gate at the gate, and holding the data captured by the second transmission gate; A flip-flop circuit characterized by the following. 3. The first P-type transistor and a second N-type transistor.
3. The flip-flop circuit according to claim 2, wherein the on-resistance of the type transistor, the third P-type transistor, and the fourth N-type transistor is sufficiently large.