JP2002075902A - Treating device for lowering resistance of semiconductor - Google Patents
Treating device for lowering resistance of semiconductorInfo
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- JP2002075902A JP2002075902A JP2000253424A JP2000253424A JP2002075902A JP 2002075902 A JP2002075902 A JP 2002075902A JP 2000253424 A JP2000253424 A JP 2000253424A JP 2000253424 A JP2000253424 A JP 2000253424A JP 2002075902 A JP2002075902 A JP 2002075902A
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- semiconductor
- electron beam
- type semiconductor
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- sample holder
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体の電気抵抗
を低下させる処理装置に関し、特に、照射領域が広範な
幅広の励起電子を生成・放出する電子照射装置を備えた
半導体低抵抗化処理装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processing device for reducing the electric resistance of a semiconductor, and more particularly to a semiconductor low resistance processing device provided with an electron irradiation device for generating and emitting a wide range of excited electrons in a wide irradiation area. About.
【０００２】[0002]
【従来の技術】不純物を添加することによりｐ型化され
たｐ型半導体の電気抵抗を低化させる処理装置として
は、例えば、「応用物理，Vol.65,No.7,1996：ＧａＮ系
発光素子の現状と将来」等に記載されている電子線照射
装置等が、一般に広く知られている。従来より一般に使
用されてきたこれらの電子線照射装置は、試料（半導体
等の電子線照射対象）を真空中に配置して、真空中で電
子線を照射するものであった。2. Description of the Related Art As a processing apparatus for lowering the electric resistance of a p-type semiconductor made into a p-type by adding an impurity, for example, "Applied Physics, Vol. 65, No. 7, 1996: GaN-based light emission" Electron beam irradiation apparatuses and the like described in “Current state and future of element” and the like are generally widely known. Conventionally, these electron beam irradiation apparatuses generally use a sample (an electron beam irradiation target such as a semiconductor) placed in a vacuum and irradiate the electron beam in a vacuum.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
従来技術（従来の電子線照射装置）においては、上記の
文献にも記載されている様に「電子線スポットを試料表
面全面に走査しなければならず、処理時間が長くなって
しまうという生産性の面での問題があった。However, in the above-mentioned prior art (conventional electron beam irradiation apparatus), as described in the above-mentioned document, it is necessary to "scan the entire surface of the sample with an electron beam spot. However, there is a problem in terms of productivity that the processing time becomes longer.
【０００４】また、上記の従来技術においては、半導体
ウエハが真空中に配置されるため、例えばＭｇドープの
ＧａＮより成るｐ型半導体の表面の窒素（Ｎ）が、電子
線照射時に外部へ脱離し、結晶性が低下し易い。そのた
め処理条件設定及び工程管理を十分に行う必要があっ
た。Further, in the above-mentioned prior art, since the semiconductor wafer is placed in a vacuum, nitrogen (N) on the surface of a p-type semiconductor made of, for example, Mg-doped GaN is desorbed to the outside during electron beam irradiation. , Crystallinity is apt to decrease. Therefore, it is necessary to sufficiently set the processing conditions and control the process.
【０００５】本発明は、上記の課題を解決するために成
されたものであり、その目的は、ｐ型半導体の電気抵抗
を効率よく低下させる手段を提供することであり、更に
は、これにより、発光作用や或いは受光作用等を奏する
半導体素子の駆動電圧を効率よく低下させる手段を提供
することである。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a means for efficiently reducing the electric resistance of a p-type semiconductor. Another object of the present invention is to provide a means for efficiently lowering the drive voltage of a semiconductor element having a light emitting function or a light receiving function.
【０００６】[0006]
【課題を解決するための手段】上記の課題を解決するた
めには、以下の手段が有効である。即ち、第１の手段
は、不純物を添加した半導体の電気抵抗を低下させる装
置において、互いに相異なる気圧に設定可能な、励起電
子発生用チャンバと、励起電子を前記半導体に照射する
リアクションチャンバとを備え、半導体を電子取出し窓
に対して所定間隔離して略平行に配置可能な台座又はサ
ンプルホルダを備えることである。In order to solve the above-mentioned problems, the following means are effective. That is, the first means is an apparatus for reducing the electric resistance of a semiconductor to which impurities are added, comprising: a chamber for generating excited electrons, which can be set to different pressures from each other; and a reaction chamber for irradiating the semiconductor with excited electrons. And a pedestal or a sample holder capable of disposing the semiconductor at a predetermined distance from the electron extraction window and disposing the semiconductor substantially in parallel.
【０００７】また、第２の手段は、上記の第１の手段に
おいて、上記の所定間隔をおよそ数ミリメートルから、
数十ミリメートル程度にすることである。[0007] The second means is the first means, wherein the predetermined interval is set to approximately several millimeters.
That is, it is about several tens of millimeters.
【０００８】また、第３の手段は、上記の第１又は第２
の手段において、帯電する半導体の表面上の電子をリー
クする接地線路を設けることである。[0008] The third means may be the first or second means.
Means for providing a ground line for leaking electrons on the surface of the charged semiconductor.
【０００９】また、第４の手段は、上記の第３の手段に
おいて、台座又はサンプルホルダの少なくとも一部分を
導体より構成することである。According to a fourth aspect, in the third aspect, at least a part of the pedestal or the sample holder is formed of a conductor.
【００１０】また、第５の手段は、上記の第１乃至第４
の何れか１つの手段において、台座又はサンプルホルダ
を排気可能なリアクションチャンバ内に配置することで
ある。Further, the fifth means includes the first to fourth means.
In one of the measures, the pedestal or the sample holder is placed in a reaction chamber capable of being evacuated.
【００１１】また、第６の手段は、上記の第１乃至第５
の何れか１つの手段において、台座又はサンプルホルダ
を、直進可能な試料移送ライン上に配置するか、或い
は、直進可能な試料移送ラインの少なくとも一部分とし
て構成することである。Further, the sixth means includes the first to fifth means.
The pedestal or the sample holder may be arranged on a straight-movable sample transfer line, or may be configured as at least a part of the straight-movable sample transfer line.
【００１２】更に、第７の手段は、上記の第１乃至第６
の何れか１つの手段において、台座又はサンプルホルダ
を、回転又は回動可能なターンテーブル上に配置する
か、或いは、回転又は回動可能なターンテーブルの少な
くとも一部分として構成することである。以上の手段に
より、前記の課題を解決することができる。Further, the seventh means includes the first to sixth means.
According to any one of the measures, the pedestal or the sample holder is arranged on a rotatable or rotatable turntable, or is configured as at least a part of the rotatable or rotatable turntable. With the above means, the above-mentioned problem can be solved.
【００１３】[0013]
【作用及び発明の効果】上記の本発明の手段を用いて、
照射領域が広範な幅広の電子をｐ型半導体に面照射すれ
ば、約３分程度と言う従来よりも極めて短時間の間に、
ｐ型半導体を低抵抗化することが可能となる。これは、
電子取出し窓の面積やプラズマチャンバの体積を強く制
約する物理的要件が特に無いために、励起電子の照射領
域を容易に広範にすることができる様になった結果であ
り、これにより、従来の様な長時間にわたって多数回繰
り返すべき走査処理が必要なくなる。Using the above-described means of the present invention,
If the p-type semiconductor is surface-irradiated with a wide range of electrons in a wide range of irradiation, it takes about 3 minutes, which is much shorter than the conventional method.
The resistance of the p-type semiconductor can be reduced. this is,
Since there is no particular physical requirement that strongly restricts the area of the electron extraction window or the volume of the plasma chamber, the irradiation area of the excited electrons can be easily widened. Such a scanning process to be repeated many times over a long time is not required.
【００１４】この時のｐ型半導体と電子取り出し窓との
間隔は、およそ数ミリメートルから、数十ミリメートル
程度が良い。より望ましくは、この間隔は10〜40mm程度
が良い。この間隔が広過ぎると、特に処理雰囲気が大気
圧程度の場合、電子を照射する際のエネルギーロスが大
きくなり、望ましくない。また、この間隔が狭過ぎる
と、電子取り出し窓の個々の穴（窓）の形状が半導体ウ
エハ（ｐ型半導体）に対する照射状態に直接影響し、電
子の照射密度の均一化が図り難くなる。At this time, the distance between the p-type semiconductor and the electron extraction window is preferably about several millimeters to several tens of millimeters. More preferably, this interval is about 10 to 40 mm. If this interval is too wide, especially when the processing atmosphere is at about atmospheric pressure, the energy loss when irradiating electrons increases, which is not desirable. If the interval is too small, the shape of each hole (window) of the electron extraction window directly affects the state of irradiation on the semiconductor wafer (p-type semiconductor), making it difficult to achieve uniform electron irradiation density.
【００１５】また、本発明による装置を用いれば、電子
が非常に安定しているため大気圧中においても従来の電
子線照射の場合よりもエネルギー効率が良い。このた
め、本電子照射工程を実施する前の反応室の排気処理工
程が必ずしも必要ではなくなり、電子照射工程に要する
時間がその分短縮できる。また、処理が大気圧中にて実
施できるため、従来の様に真空中で電子線照射を行う場
合よりも結晶中の窒素（Ｎ）のｐ型半導体表面からの脱
離現象も発生し難くなる。Further, when the apparatus according to the present invention is used, electrons are very stable, so that even at atmospheric pressure, energy efficiency is higher than in conventional electron beam irradiation. For this reason, the evacuation process of the reaction chamber before performing the present electron irradiation step is not necessarily required, and the time required for the electron irradiation step can be shortened accordingly. In addition, since the treatment can be performed at atmospheric pressure, the desorption phenomenon of nitrogen (N) in the crystal from the p-type semiconductor surface is less likely to occur than in the case where electron beam irradiation is performed in a vacuum as in the conventional case. .
【００１６】また、電子照射工程において、上記のｐ型
半導体又は半導体ウエハの電位を接地線路により略一定
に保持すれば、ｐ型半導体の帯電が防止又は緩和できる
ので、これによりｐ型半導体の表面（電子線照射面）の
ダメージを防止又は軽減することが可能となり、ｐ型半
導体の低抵抗化により効果的である。In the electron irradiation step, if the potential of the p-type semiconductor or the semiconductor wafer is kept substantially constant by the ground line, the charging of the p-type semiconductor can be prevented or alleviated. It is possible to prevent or reduce damage to the (electron beam irradiation surface), and it is more effective to lower the resistance of the p-type semiconductor.
【００１７】即ち、例えば、サンプルホルダや或いは台
座の少なくとも一部分を導電性材料より構成し、アース
することにより、ｐ型半導体又は半導体ウエハや、或い
はそれらの表面上に成膜された金属層等の電位を略一定
に保持すことができる。また、特に、この様な金属層を
比較的広域若しくわ全面にわたって成膜し、導電性のサ
ンプルホルダに直接接触させれば、アースがより効果的
となる。これらの手法に従えば、上記のアースによる効
果がより確実に得られる様になる。That is, for example, at least a part of the sample holder or the pedestal is made of a conductive material and grounded, so that a p-type semiconductor or a semiconductor wafer or a metal layer formed on the surface thereof is formed. The potential can be kept substantially constant. In particular, if such a metal layer is formed over a relatively wide area or over the entire surface of the cuff, and is brought into direct contact with the conductive sample holder, the grounding becomes more effective. According to these techniques, the above-mentioned effect by the ground can be obtained more reliably.
【００１８】また、上記の様な金属層は成膜せずに、ｐ
型半導体の表面に直接電子を照射する場合には、ｐ型半
導体又は半導体ウエハの雰囲気中の酸素（Ｏ2 ）濃度は
低い方が良い。より具体的には例えば、酸素(O2)濃度が
１％以下、又は酸素(O2)分圧が１０3Pa以下の気体をｐ
型半導体の雰囲気として用いれば、ｐ型半導体の電子照
射面の酸化を抑制又は軽減することができる。Further, without forming the metal layer as described above,
When the surface of the type semiconductor is directly irradiated with electrons, the oxygen (O 2 ) concentration in the atmosphere of the p-type semiconductor or the semiconductor wafer is preferably low. More specifically, for example, a gas having an oxygen (O 2 ) concentration of 1% or less or an oxygen (O 2 ) partial pressure of 10 3 Pa or less
When used as an atmosphere of a p-type semiconductor, oxidation of the electron-irradiated surface of the p-type semiconductor can be suppressed or reduced.
【００１９】したがって、上記の様に例えば半導体の表
面に直接電子を照射する場合等では、電子照射時の半導
体又は半導体ウエハの処理雰囲気を所望の状態（気体混
合比、分圧、温度等）に制御するために、本発明の装置
のリアクションチャンバは排気可能であることが望まし
く、ガス導入が可能なポートを有することが望ましい。Therefore, for example, in the case where the surface of a semiconductor is directly irradiated with electrons as described above, the processing atmosphere of the semiconductor or semiconductor wafer at the time of electron irradiation is set to a desired state (gas mixture ratio, partial pressure, temperature, etc.). For control, the reaction chamber of the device of the present invention is desirably evacuable and desirably has a port through which gas can be introduced.
【００２０】また、試料（ｐ型半導体又は半導体ウエ
ハ）を直進可能な試料移送ラインに乗せて移動させるこ
とにより、電子の照射密度の均一化を図ることができ
る。更に、この様な試料移送ラインは、照射処理の連続
的な実施を効率よく助けるため、半導体素子等の大量生
産化を図る上で特に有用である。また、この様な試料移
送ラインは、一台の半導体低抵抗化処理装置につき、何
本設けても良い。Further, the electron irradiation density can be made uniform by moving the sample (p-type semiconductor or semiconductor wafer) by placing it on a sample transfer line that can move straight. Further, such a sample transfer line is particularly useful in mass-producing semiconductor devices and the like because it efficiently assists continuous execution of irradiation processing. In addition, any number of such sample transfer lines may be provided for one semiconductor low resistance processing apparatus.
【００２１】また、試料（ｐ型半導体又は半導体ウエ
ハ）を回転又は回動可能なターンテーブルに乗せて移動
させることによっても、同様に、電子の照射密度の均一
化を図ることができる。また、この様なターンテーブル
は、上記の試料移送ライン上に設けても良い。Similarly, the electron irradiation density can be made uniform by moving the sample (p-type semiconductor or semiconductor wafer) on a rotatable or rotatable turntable. Such a turntable may be provided on the above-mentioned sample transfer line.
【００２２】以上の様な装置により低抵抗化された半導
体は、一般の半導体素子、例えば、特に、ＬＥＤや半導
体レーザ等の III族窒化物系化合物半導体素子等に有用
であり、半導体発光素子のみならず、半導体受光素子、
半導体電子デバイス等にも利用することができる。即
ち、この様に十分に低抵抗化されたｐ型半導体を半導体
素子に用いれば、その半導体素子の駆動電圧を従来と比
べて低減させることができる等の効果が得られる。Semiconductors whose resistance has been reduced by the above-described devices are useful for general semiconductor devices, for example, particularly, Group III nitride compound semiconductor devices such as LEDs and semiconductor lasers. Not a semiconductor light receiving element,
It can also be used for semiconductor electronic devices and the like. That is, if a p-type semiconductor having a sufficiently low resistance is used for a semiconductor element, an effect that the driving voltage of the semiconductor element can be reduced as compared with the related art can be obtained.
【００２３】[0023]
【発明の実施の形態】以下、本発明を具体的な実施例に
基づいて説明する。ただし、本発明は以下に示す実施例
に限定されるものではない。図１は、本発明に係わるイ
オンプラズマ型電子照射装置１００の模式的な断面図で
ある。グリッド１０４と電子取出し窓１０７で挟まれた
プラズマチャンバ１０５の内部には、ワイヤ１０６が配
設されている。例えば３００ｖ程度のプラズマ電源とワ
イヤ１０６とを用いてこのプラズマチャンバ１０５内で
発生させたヘリウムイオンガス（Ｈｅ+ ）を、例えば２
００ｋＶ程度の高圧電源により生成させた電界で加速し
て、真空チャンバ１０１内のカソード（冷陰極）１０３
の表面に高速で衝突させることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on specific embodiments. However, the present invention is not limited to the embodiments described below. FIG. 1 is a schematic sectional view of an ion plasma type electron irradiation apparatus 100 according to the present invention. A wire 106 is provided inside the plasma chamber 105 sandwiched between the grid 104 and the electron extraction window 107. For example, a helium ion gas (He + ) generated in the plasma chamber 105 using a plasma power source of about 300
The cathode (cold cathode) 103 in the vacuum chamber 101 is accelerated by an electric field generated by a high voltage power supply of about 00 kV.
At high speed.
【００２４】これにより、カソード１０３の表面から放
出される多数の２次電子を上記の電界でヘリウムイオン
ガスとは逆向きに加速することができ、その結果、本イ
オンプラズマ型電子照射装置１００は、照射領域が広範
な幅広の電子を生成することができる。この様にして生
成された電子は、外気を遮断している電子取出し窓１０
７の外面を形成する薄い金属板１０８を貫通して、外部
に照射される。Thus, a large number of secondary electrons emitted from the surface of the cathode 103 can be accelerated by the above-mentioned electric field in a direction opposite to that of the helium ion gas. As a result, the present ion plasma type electron irradiation apparatus 100 In addition, the irradiation area can generate a wide range of electrons. The electrons generated in this way are supplied to the electron extraction window 10 that blocks the outside air.
7 penetrates the thin metal plate 108 forming the outer surface and is irradiated to the outside.
【００２５】図２に、本発明の電子照射工程におけるｐ
型半導体の模式的な断面図を例示する。イオンプラズマ
型電子照射装置１００の電子取出し窓１０７の直下に、
例えば２０mm程度の間隔を空けて、例えばマグネシウム
（Ｍｇ）を添加した窒化ガリウム（ＧａＮ）等のｐ型半
導体を金属製のサンプルホルダ１０９上に乗せ、金属板
１０８と略平行に配置する。FIG. 2 shows the relationship between p and p in the electron irradiation step of the present invention.
FIG. 2 illustrates a schematic cross-sectional view of a mold semiconductor. Immediately below the electron extraction window 107 of the ion plasma type electron irradiation device 100,
For example, a p-type semiconductor such as gallium nitride (GaN) to which magnesium (Mg) is added is placed on a metal sample holder 109 at intervals of, for example, about 20 mm, and is disposed substantially parallel to the metal plate 108.
【００２６】また、サンプルホルダ１０９を導電性材料
より構成し、アースすることにより、ｐ型半導体や、或
いはその表面上に成膜された金属層の電位を略一定に保
持すことができる。また、特に、この様な金属層を比較
的広域若しくわ全面にわたって成膜し、導電性のサンプ
ルホルダに直接接触させれば、アースがより効果的とな
るため、より確実に上記の作用・効果が得られる様にな
る。Further, by forming the sample holder 109 from a conductive material and grounding it, the potential of the p-type semiconductor or the metal layer formed on the surface thereof can be kept substantially constant. In particular, if such a metal layer is formed over a relatively wide area or over the entire surface of the cuff and is brought into direct contact with the conductive sample holder, the grounding becomes more effective, so that the above-described operation and operation can be performed more reliably. The effect will be obtained.
【００２７】例えば、以上の様に半導体低抵抗化装置１
００を構成した。この様な構成によれば、電子取出し窓
１０７（金属板１０８）の面積やプラズマチャンバ１０
５の体積を強く制約する物理的要件が特に無いために、
照射領域が広範な幅広の電子を容易に生成することがで
きる。また、これにより、従来の様な長時間にわたって
多数回繰り返すべき走査処理が必要なくなる。For example, as described above, the semiconductor resistance reducing device 1
00 was constructed. According to such a configuration, the area of the electron extraction window 107 (metal plate 108) and the plasma chamber 10
Because there is no physical requirement to strongly restrict the volume of 5,
A wide range of electrons can be easily generated in a wide irradiation area. In addition, this eliminates the need for a conventional scanning process that must be repeated many times over a long period of time.
【００２８】例えばこのような装置を用いて、照射領域
が広範な幅広の電子をｐ型半導体に面照射すれば、約３
分程度と言う従来よりも極めて短時間の間に、ｐ型半導
体を低抵抗化することが可能となる。For example, when such a device is used to irradiate the p-type semiconductor with surface-irradiated wide and wide electrons to the p-type semiconductor, about 3
It becomes possible to lower the resistance of the p-type semiconductor in a very short time, which is about a minute.
【００２９】また、これらのｐ型半導体は、特に、 III
族窒化物系化合物で構成すると効果的に上記の作用がえ
られ、また、これらのｐ型半導体に添加するｐ型の不純
物としてはマグネシウム（Ｍｇ）等が、特に有効であ
る。Further, these p-type semiconductors are, in particular, III
The above action can be obtained effectively by using a group nitride compound, and magnesium (Mg) is particularly effective as a p-type impurity added to these p-type semiconductors.
【００３０】（ホール濃度測定用サンプルによる効果の
検証）上記の半導体低抵抗化処理装置１００を用いて低
抵抗化処理を実施したｐ型半導体における低抵抗化の具
体的な効果を、以下に示すホール濃度測定用サンプルを
用いて検証した。図２のサンプル（半導体ウエハ１０）
のサファイア基板１上には、 AlNから成る膜厚約25nmの
バッファ層２と、マグネシウムが添加された窒化ガリウ
ム（ＧａＮ：Ｍｇ）より成るｐ型半導体層５とが積層さ
れている。また、このｐ型半導体層５の表面（電子照射
面）には、コバルト(Co ／Au) より成る金属層７が約１
００Åの厚さに成膜されている。(Verification of Effect by Sample for Measurement of Hole Concentration) The specific effect of the resistance reduction in the p-type semiconductor which has been subjected to the resistance reduction processing using the semiconductor resistance reduction processing apparatus 100 will be described below. It was verified using a sample for measuring hole concentration. Sample of FIG. 2 (semiconductor wafer 10)
On the sapphire substrate 1, a buffer layer 2 of AlN having a thickness of about 25 nm and a p-type semiconductor layer 5 of gallium nitride (GaN: Mg) to which magnesium is added are laminated. On the surface (electron irradiation surface) of the p-type semiconductor layer 5, a metal layer 7 of cobalt (Co / Au)
The film is formed to a thickness of 00 °.
【００３１】このようなサンプル（半導体ウエハ１０）
に対して、大気中にて金属層７越しに、前記のイオンプ
ラズマ型電子照射装置１００による電子照射を実施した
（図２）。ただし、この時の荷電粒子加速機構（高圧電
源：図１）による加速電圧は約１６０〜２００ｋＶ、照
射時間は各サンプルとも約３分間とした。Such a sample (semiconductor wafer 10)
Then, electron irradiation was performed by the above-mentioned ion plasma type electron irradiation apparatus 100 through the metal layer 7 in the air (FIG. 2). However, at this time, the accelerating voltage by the charged particle accelerating mechanism (high-voltage power supply: FIG. 1) was about 160 to 200 kV, and the irradiation time was about 3 minutes for each sample.
【００３２】図３は、ｐ型半導体（ＧａＮ：Ｍｇ）のホ
ール濃度測定用サンプル２０の構成を示した模式的な斜
視図である。上記のサンプル（半導体ウエハ１０）を電
子照射後、王水で処理して表面のCo／Au金属層７を除去
し、本図３に示す様に四隅に膜厚約3000Åのニッケル(N
i)より成る測定用パッド９を蒸着により形成することに
より、本ホール濃度測定用サンプル２０が作成された。FIG. 3 is a schematic perspective view showing the structure of a sample 20 for measuring the hole concentration of a p-type semiconductor (GaN: Mg). After irradiating the sample (semiconductor wafer 10) with electrons, it is treated with aqua regia to remove the Co / Au metal layer 7 on the surface, and as shown in FIG.
The hole concentration measurement sample 20 was prepared by forming the measurement pad 9 consisting of i) by vapor deposition.
【００３３】図４は、４つのホール濃度測定用サンプル
２０に対して、加速電圧をそれぞれ変化させてｐ型半導
体層５のホール濃度を測定した結果を示すグラフであ
る。本測定の結果、略１０17〜１０18／cm3 と言う従来
と比較して同等以上に高いホール濃度が得られることが
検証できた。FIG. 4 is a graph showing the results of measuring the hole concentration of the p-type semiconductor layer 5 with respect to the four hole concentration measurement samples 20 by changing the acceleration voltage. As a result of this measurement, it was verified that a hole concentration of about 10 17 to 10 18 / cm 3, which is higher than or equal to the conventional value, can be obtained.
【００３４】以上の様な方法により低抵抗化されたｐ型
半導体は、一般の半導体素子、ＬＥＤや半導体レーザ等
の発光素子、受光素子、電子デバイス等の III族窒化物
系化合物半導体素子等に有用である。即ち、この様に十
分に低抵抗化されたｐ型半導体を半導体素子に用いれ
ば、その半導体素子の駆動電圧を従来と比べて同等以上
に低減させることができる等の効果が得られる。The p-type semiconductor whose resistance has been reduced by the above method can be used as a general semiconductor device, a light emitting device such as an LED or a semiconductor laser, a light receiving device, a group III nitride compound semiconductor device such as an electronic device, or the like. Useful. That is, if a p-type semiconductor having a sufficiently low resistance is used for a semiconductor element, effects such as a drive voltage of the semiconductor element can be reduced to be equal to or more than that of a conventional semiconductor element can be obtained.
【図１】本発明に係わるイオンプラズマ型電子照射装置
１００の模式的な断面図。FIG. 1 is a schematic sectional view of an ion plasma type electron irradiation apparatus 100 according to the present invention.
【図２】本発明の電子照射工程におけるｐ型半導体（Ｇ
ａＮ：Ｍｇ）の模式的な断面図。FIG. 2 shows a p-type semiconductor (G) in an electron irradiation step of the present invention.
aN: Mg).
【図３】本発明の具体的な実施例に係わるｐ型半導体
（ＧａＮ：Ｍｇ）のホール濃度測定用サンプル２０の構
成を示した模式的な斜視図。FIG. 3 is a schematic perspective view showing a configuration of a hole concentration measurement sample 20 of a p-type semiconductor (GaN: Mg) according to a specific example of the present invention.
【図４】４つのホール濃度測定用サンプル２０に対し
て、加速電圧をそれぞれ変化させてホール濃度を測定し
た結果を示すグラフ。FIG. 4 is a graph showing the results of measuring the hole concentration for four hole concentration measurement samples 20 while changing the acceleration voltage.
１００ … イオンプラズマ型電子照射装置 １０１ … 真空チャンバ １０３ … カソード（冷陰極） １０４ … グリッド １０５ … プラズマチャンバ １０６ … ワイヤ １０７ … 電子取出し窓 １０８ … 金属板 １０９ … サンプルホルダ １０ … 半導体ウエハ（サンプル） ２０ … ホール濃度測定用サンプル １ … サファイア基板 ５ … ｐ型ＧａＮ層 ７ … 金属層 DESCRIPTION OF SYMBOLS 100 ... Ion-plasma type electron irradiation apparatus 101 ... Vacuum chamber 103 ... Cathode (cold cathode) 104 ... Grid 105 ... Plasma chamber 106 ... Wire 107 ... Electron extraction window 108 ... Metal plate 109 ... Sample holder 10 ... Semiconductor wafer (sample) 20 ... sample for measuring hole concentration 1 ... sapphire substrate 5 ... p-type GaN layer 7 ... metal layer
Claims (7)
下させる装置であって、 互いに相異なる気圧に設定可能な、励起電子発生用チャ
ンバと、励起電子を前記半導体に照射するリアクション
チャンバとを有し、 前記半導体を電子取出し窓に対して所定間隔離して略平
行に配置可能な台座又はサンプルホルダを備えているこ
とを特徴とする半導体低抵抗化処理装置。1. An apparatus for lowering the electric resistance of a semiconductor to which impurities are added, comprising: a chamber for generating excited electrons which can be set to different pressures from each other; and a reaction chamber for irradiating the semiconductor with excited electrons. And a pedestal or a sample holder capable of disposing the semiconductor at a predetermined distance from the electron extraction window and being disposed substantially in parallel with the electron extraction window.
ることを特徴とする請求項１に記載の半導体低抵抗化処
理装置。2. The apparatus according to claim 1, wherein the predetermined interval is from about several millimeters to several tens of millimeters.
ークする接地線路を有することを特徴とする請求項１又
は請求項２に記載の半導体低抵抗化処理装置。3. The apparatus according to claim 1, further comprising a ground line for leaking electrons on the surface of the charged semiconductor.
特徴とする請求項３に記載の半導体低抵抗化処理装置。4. The apparatus according to claim 3, wherein at least a part of the pedestal or the sample holder is formed of a conductor.
とを特徴とする請求項１乃至請求項４のいずれか１項に
記載の半導体低抵抗化処理装置。5. The semiconductor low-resistance processing apparatus according to claim 1, wherein the pedestal or the sample holder is disposed in a reaction chamber that can be evacuated. .
は、 直進可能な試料移送ラインの少なくとも一部分として構
成されていることを特徴とする請求項１乃至請求項５の
いずれか１項に記載の半導体低抵抗化処理装置。6. The apparatus according to claim 1, wherein the pedestal or the sample holder is disposed on a straight-movable sample transfer line, or is configured as at least a part of the straight-movable sample transfer line. 6. The semiconductor low-resistance processing apparatus according to claim 1.
か、或いは、 回転又は回動可能なターンテーブルの少なくとも一部分
として構成されていることを特徴とする請求項１乃至請
求項６のいずれか１項に記載の半導体低抵抗化処理装
置。7. The pedestal or the sample holder is arranged on a turntable that can be rotated or rotated, or is configured as at least a part of a turntable that can be rotated or rotated. The semiconductor low-resistance processing apparatus according to claim 1, wherein
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000253424A JP2002075902A (en) | 2000-08-24 | 2000-08-24 | Treating device for lowering resistance of semiconductor |
| PCT/JP2001/007188 WO2002017371A1 (en) | 2000-08-24 | 2001-08-22 | Method for reducing semiconductor resistance, device for reducing semiconductor resistance and semiconductor element |
| US10/362,513 US6943128B2 (en) | 2000-08-24 | 2001-08-22 | Method for reducing semiconductor resistance, device for reducing semiconductor resistance and semiconductor element |
| AU2001280108A AU2001280108A1 (en) | 2000-08-24 | 2001-08-22 | Method for reducing semiconductor resistance, device for reducing semiconductor resistance and semiconductor element |
| TW90120721A TW503461B (en) | 2000-08-24 | 2001-08-23 | Treatment device for lowering resistance of semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000253424A JP2002075902A (en) | 2000-08-24 | 2000-08-24 | Treating device for lowering resistance of semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002075902A true JP2002075902A (en) | 2002-03-15 |
Family
ID=18742523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000253424A Withdrawn JP2002075902A (en) | 2000-08-24 | 2000-08-24 | Treating device for lowering resistance of semiconductor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2002075902A (en) |
| TW (1) | TW503461B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014509039A (en) * | 2010-12-16 | 2014-04-10 | 日立造船株式会社 | Generation of ozone and plasma using electron beam technology. |
-
2000
- 2000-08-24 JP JP2000253424A patent/JP2002075902A/en not_active Withdrawn
-
2001
- 2001-08-23 TW TW90120721A patent/TW503461B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014509039A (en) * | 2010-12-16 | 2014-04-10 | 日立造船株式会社 | Generation of ozone and plasma using electron beam technology. |
Also Published As
| Publication number | Publication date |
|---|---|
| TW503461B (en) | 2002-09-21 |
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