JP2002073721A - Device and method for parallel processiang for layout verification, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the time required for the parallel processing of a design rule check and to effectively utilize a parallel processing device. SOLUTION: This parallel processing device comprises dividing means 102 and 103 for preparing a plurality of split rule files (not shown) by inputting and splitting a rule file 101 for layout verification, uniformizing means 104, 105, and 106 for uniformizing the sizes of the plurality of split rule files, and a verification means 109 for performing the layout verification through a parallel processing, using a plurality of split-rule files 107 with uniformed sizes and an object data 108 for the layout verification.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to layout verification of an integrated circuit, and more particularly to layout verification in which a rule file is divided and parallel processing of design rule checking is performed.

[0002]

2. Description of the Related Art As an example of conventional parallel processing for layout verification, Japanese Patent Application Laid-Open No. Hei 7-21239 (hereinafter referred to as Japanese Unexamined Patent Publication (Kokai) No. 1-21) discloses a technique of a design rule check execution device.

As another example of conventional parallel processing for layout verification, Japanese Patent Laid-Open Publication No. 7-296016
Publication 2) discloses a technique of a parallel processing method of design rule check.

[0004]

However, the above-mentioned prior art has the following problems. In the technique disclosed in Japanese Patent Laid-Open Publication No. H11-107, the division rule file 14 is created only according to the connection between the layers of the rule file 11, so that the size of each division rule file 14 is not uniform, and the processing of each layout verification unit 3 is not performed. There is a difference in time.
Therefore, the layout verification unit 3 that has already completed the processing
Means that the next processing cannot be performed until the processing of the other layout verifying means 3 is completed, so that the processing waits and the parallel processing device cannot be used effectively. Further, the effect of reducing the entire processing time by performing the parallel processing cannot be sufficiently obtained.

[0005] In the technique disclosed in Japanese Patent Laid-Open Publication No. 2000-209, in order to equalize the processing time of each processor in parallel processing, not only the number of tasks but also the processing time of each task and the data transfer time between processors are determined. Assign tasks to each processor. Therefore, processing cannot be performed unless the processing time and data transfer time of each task are known in advance. The processing time and the data transfer time of each task differ depending on the data amount and the content of the processing.
For this reason, in addition to the normal parallel processing of the design rule check, a new process for obtaining the task processing time and the data transfer time in advance is required. This also increases the overall processing time.

In view of the above, an object of the present invention is to reduce the time required for the parallel processing of the design rule check. Another object of the present invention is to make effective use of a parallel processing device.

[0007]

In order to achieve the above object, a layout verification parallel processing apparatus according to a first aspect of the present invention inputs and divides a layout verification rule file into a plurality of division rules. File dividing means, uniformizing means for equalizing the sizes of the plurality of division rule files, and parallel processing using the plurality of division rule files of uniform size and data to be subjected to layout verification. And a verification unit for performing a layout verification in the step (c).

By equalizing the size of a plurality of division rule files obtained by dividing the layout verification rule file, the processing time determined by the size of the division rule file can be equalized for each division rule file. Thereby, the parallel processing device can be effectively used, and the parallel processing time can be reduced.

[0009] The division rule file specifies layer information for specifying a layer to be subjected to layout verification, check information for specifying layout verification check contents, and graphic operation contents from the layer information to the check information. Graphic operation information. Further, the dividing means divides the graphic operation information into a plurality of graphic operation steps for each predetermined processing time, and the plurality of division rule files do not share the same graphic operation step with each other. Rule files can be split.

The dividing means divides the graphic operation information included in the division rule file into a plurality of graphic operation steps for each predetermined processing time, so that the processing time of the division rule file can be easily reduced using the number of graphic operation steps. You can ask. In addition, by dividing a rule file so that a plurality of division rule files do not share the same graphic calculation process, a parallel processing time can be reduced without performing processing redundantly in a plurality of division rule files. .

[0011] The equalizing means may calculate an average value of the number of graphic operation steps included in each of the plurality of division rule files, and may equalize the size according to the calculated average value.

The equalizing means equalizes the size of the division rule file based on the average value of the number of graphic operation steps included in each division rule file, so that the processing time determined by the size of the division rule file can be easily reduced. It can be made uniform and the parallel processing device can be used effectively.

[0013] The equalizing means compares the number of graphic operation steps included in the division rule file with the average value,
The image processing apparatus may further include a re-division unit that divides the plurality of division rule files in which the number of graphic operation steps included in the division rule file is larger than the average value and creates a plurality of sub-division rule files.

By dividing the division rule file in which the number of graphic operation steps is larger than the average value and making the file size uniform, a process for equalizing the file size based on the number of graphic operation steps is performed. It can be easily realized.

[0015] The equalizing means compares the number of the plurality of division rule files and the plurality of re-division rule files with the number of parallel processes of the verification means, and the number of compared files is the number of parallel processes. If the number of files is larger than the number of files compared, a plurality of files are sequentially selected and integrated from the file having the smaller size, and 1
An integration means for creating one integration rule file can be provided.

When the number of division rule files is larger than the number that can be processed in parallel, files having a small number of graphic operation steps are integrated and the file size is made uniform, thereby facilitating processing for uniformity. Can be realized.

The equalizing means compares the number of the plurality of division rule files and the plurality of re-division rule files with the number of parallel processes of the verification means, and the number of files compared is the number of parallel processes. If the number of files is smaller than the above, the file having the largest size among the compared files may be divided to generate a plurality of compulsory division rule files.

When the number of division rule files is smaller than the number that can be processed in parallel, a file having a large number of graphic operation steps is divided and the file size is made uniform, thereby facilitating the processing for uniformity. Can be realized.

The subdivision means extracts the graphic operation steps shared by the plurality of pieces of check information, and, among the extracted graphic operation steps, determines the closest one from the layer information to the plurality of divided The division rule file can be divided so as to be shared by the subdivision rule files.

By reducing the number of graphic operation steps shared by a plurality of divided files, the number of graphic operation steps that are redundantly processed by a plurality of division rule files can be reduced, and the parallel processing time can be reduced. can do.

The forcible division means extracts the graphic operation steps shared by the plurality of check information, and, among the extracted graphic operation steps, extracts the closest one from the check information to the plurality of divided The subdivision rule file can be divided so as to be shared by the compulsory division files.

By reducing the difference between the sizes of the plurality of divided files, the processing time of the plurality of division rule files can be made uniform, and the parallel processing device can be used effectively.

[0023] The information processing apparatus may further include a counting means for counting the results of the parallel processing by the verification means.

By the tabulation means tabulating the results of the parallel processing, it is possible to obtain the same result as when the layout verification processing is performed without dividing the rule file.

In order to achieve the above object, the second aspect of the present invention
The parallel processing method of layout verification according to the aspect of the present invention includes a dividing step of inputting and dividing a layout verification rule file to create a plurality of division rule files, and a uniforming step of equalizing the sizes of the plurality of division rule files. And a verification step of performing layout verification by parallel processing using the plurality of division rule files of uniform size and layout verification target data.

In order to achieve the above object, a third aspect of the present invention is provided.
In the recording medium according to the aspect, a computer having an input / output function is divided by inputting a layout verification rule file and dividing the computer into a plurality of division rule files. Parallel processing for layout verification, comprising: uniformizing means for uniforming; and verification means for performing layout verification by parallel processing using the plurality of division rule files of uniform size and data to be subjected to layout verification. A program for functioning as an apparatus is recorded.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The layout verification of an integrated circuit that performs parallel processing by dividing a rule file will be described.
An integrated circuit is manufactured through a process of forming a pattern of a transistor electrode, a wiring, and the like in a plurality of layers on a surface of a wafer. A mask pattern used to form a pattern of each layer is generated based on layout data of each layer. It is a design rule check (hereinafter, referred to as DRC) in layout verification to check whether the layout data satisfies the integrated circuit design standard (design rule).

The DRC checks whether the shape, position, interval, etc. of the pattern in each layer of the layout data and between the layers satisfies the design standard, based on a rule file created according to the design standard. The DRC processing time is determined by the amount of layout data and the rule file size.

An outline of a parallel processing procedure for layout verification of an integrated circuit in the embodiment of the present invention for optimizing the processing time of the DRC as described above is shown below.

(1) DRC of each layer of layout data
Check items indicating the contents of the DRC, such as checking the shape (width, length, etc.), position, interval, etc. of the figure (pattern) within the layers and between the layers,
A rule file in which graphic operation information indicating the contents of graphic operations such as a logical operation to be performed from a designated layer to a check item, a change in the size of a graphic, and selection of a graphic according to conditions is input. The graphic operation information is described by being divided into a plurality of graphic operation steps indicating the contents of each graphic operation, and the processing time of each graphic operation step is made uniform. As described later, the size of each group obtained by dividing the rule file is adjusted based on the number of graphic operation steps, thereby making the size of each group uniform.
This is because the size of the division rule file created for each group is made uniform and the parallel processing time is made uniform.

(2) A graphic operation tree structure indicating the structure of the rule file is created using the information of the designated layer, the graphic operation process, and the check items.

(3) Basically divide the graphic operation tree structure to form a plurality of parallel processing units (groups) that are the basis of the division rule file. The basic division is performed so that different groups do not share the same graphic operation process.

(4) A predetermined group is subdivided to equalize the number of graphic operation steps in each group. The re-division is performed on a group in which the number of graphic operation steps is larger than the average value of the number of graphic operation steps in each group after the basic division. Further, after the division, the division is performed again so as to reduce the number of graphic operation steps shared by a plurality of groups.

(5) The predetermined groups are integrated, and the number of graphic operation steps in each group is made uniform. When the number of groups is larger than the number that can be processed in parallel, the integration is performed on a group having a small number of graphic operation steps.

(6) A predetermined group is forcibly divided to equalize the number of graphic operation steps in each group. When the number of groups is smaller than the number that can be processed in parallel, the forced division is performed on a group having a large number of graphic operation steps. Also, the forced division is performed so as to reduce the difference in the number of graphic operation steps included in the plurality of groups after the forced division.

(7) Create a division rule file for each formed group. Each of the formed division rule files is subdivided, integrated, and forcibly divided in accordance with the number of graphic operation steps in which the processing time is made uniform, and the size is made uniform.

(8) DRC parallel processing is performed using each of the division rule files and the layout data. Since each split rule file has a uniform size,
The time required for parallel processing is also made uniform.

(9) If necessary, the DR that has been processed in parallel
The result of C is totaled.

A parallel processing device and a parallel processing method for layout verification that realize the above procedures (1) to (9) will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a parallel processing apparatus for layout verification according to an embodiment of the present invention.

The parallel processing apparatus for layout verification shown in FIG. 1 includes a rule file 101, a figure operation tree structure creating means 102, a figure operation tree structure basic division means 103, a group re-division means 104, a group integration means 105
, Group forced division means 106, division rule file 107, layout data 108, DRC means 1
09, a division check result file 110, a check result totaling unit 111, and a check result file 112.
And.

As shown in FIG. 1, a plurality of division rule files 107 are created. Also, the same number of division check result files 110 as the number of division rule files 107 are created. The DRC unit 109 stores a plurality of division rule files 1
07 (a logical number for performing the parallel processing, not a physical number) is provided. Therefore, the division rule file 10
7 is created so that the number of DRC units 109 does not exceed the number that can be processed in parallel.

FIG. 2 is a diagram showing a configuration of an information processing apparatus for realizing a parallel processing apparatus for layout verification according to an embodiment of the present invention, and realizes the parallel processing apparatus for layout verification shown in FIG. It is an example of an information processing device.

The information processing apparatus shown in FIG. 2 includes a data input device 210 having a magnetic disk device and the like, a data processing device 220 operated by program control, a data output device 230 having a magnetic disk device and the like, and various programs. And a storage device 240 for storing data and the like.

The correspondence between the components of the layout verification parallel processing device shown in FIG. 1 and the information processing device shown in FIG. 2 will be described.

The figure operation tree structure creating means 102, the figure operation tree structure basic division means 103, and the group re-division means 1
04, the group integration unit 105, the group compulsory division unit 106, the DRC unit 109, and the check result totaling unit 111 are, for example, the data processing device 2 shown in FIG.
20 is provided.

The rule file 101 and the layout data 108 are externally input using the data input device 210 shown in FIG. 2, and are stored in, for example, the storage device 2 shown in FIG.
40. The division rule file 107, the division check result file 110, and the check result file 112 are generated by the parallel processing of the layout verification in the data processing device 220, and are stored in, for example, the storage device 240 illustrated in FIG.

The rule file 101 and the layout data 108 shown in FIG. 1 are stored in the storage device 24 shown in FIG.
Instead of being stored in 0, it may be stored in an external storage device or the like, and may be input from the outside using the data input device 210 shown in FIG. 2 as necessary. Further, the division rule file 107, the division check result file 110, and the check result file 112 shown in FIG. 1 are not stored in the storage device 240 shown in FIG.
May be stored in an external storage device via the data output device 230 shown in FIG. 2, and may be input from the external storage device using the data input device 210 shown in FIG.

The layout verification parallel processing apparatus shown in FIG. 1 will be described in detail with reference to FIGS.

The rule file 101 is input from the outside using the data input device 210 shown in FIG. The rule file 101 includes a designated layer for designating a layer to be subjected to DRC among the layers of the layout data, a graphic operation step indicating the contents of the graphic operation performed on the specified layer, a check item indicating the contents of the DRC, Is described.

FIG. 3 is a diagram showing a rule file according to an embodiment of the present invention, and shows an example of a part of the contents of the rule file 101 shown in FIG. The rule file 101 shown in FIG. 3 includes a designated layer 300 that designates a layer to be subjected to DRC among the layers of the layout data;
Logical operations such as OR and AND performed on the designated layer 300;
A graphic operation step 310 indicating the contents of graphic operations such as changing the size of a graphic and selecting a graphic according to conditions, and checking the shape (width, length, etc.), position, interval, etc. of a graphic (pattern) in a layer or between layers A check item 320 indicating the content of the DRC.

More specifically, “LAYER IN
"1" designates a layer (layer) called "IN1". “OUT1” in the figure calculation step 310 is an OR of “IN2” and “IN3”.
Perform the operation. “CHECK_1” of the check item 320 is “I
Check "N1" and "IN2".

Each graphic operation step 310 is set in advance so that each processing time is equalized. As a result, as in the technique disclosed in Japanese Unexamined Patent Publication No. 2000-213, the designated layer 300
Calculation process 31 from step to check item 320
The processing time of the rule file 101 can be obtained based on the number of graphic operation steps 310 without obtaining the processing time of 0.

As will be described later, when the rule file 101 is divided into a plurality of divided rule files 107, the rule file 10 is divided based on the number of graphic operation steps.
The size and the number of groups obtained by dividing 1 are adjusted, and a plurality of division rule files 107 having a uniform file size are created. Since the processing time is determined by the file size, the processing time is made uniform by performing the DRC parallel processing using the division rule file 107 whose file size is made uniform.

The graphic operation tree structure creating means 102 inputs the rule file 101 and extracts information on the designated layer 300, the graphic operation step 310 and the check items 320 included in the rule file 101. Then, a graphic operation tree structure representing the processing order, mutual relationship, and the like of the graphic operation process 310 executed from the designated layer 300 to the check item 320 is created.

FIG. 4 is a diagram showing a graphic operation tree structure according to an embodiment of the present invention, which is created from the rule file shown in FIG. The designated layers 401 to 408 shown in FIG. 4 represent the respective layers of the designated layer 300 shown in FIG. The figure calculation steps 411 to 417 represent the respective steps of the figure calculation step 310 shown in FIG. Check items 421 to 425 are check items 3 shown in FIG.
20 items are shown. Designated layers 401 to 408, graphic operation steps 411 to 417, and check items 421 to 421
Arrows connecting 425 indicate mutual relations indicating the order of each processing and the like.

Specifically, the designated layer 401 shown in FIG. 4 represents “LAYER IN1” of the designated layer 300 shown in FIG. 3, the designated layer 402 represents “LAYER IN2”, and so on. The designated layer 408 indicates “LAYER IN8”. The graphic operation step 411 represents “OUT1 = IN2 OR IN3” of the graphic operation step 310, and the designated layer 4 representing “IN2”.
02 and the designated layer 403 representing “IN3” are input to perform an OR operation. The figure calculation step 412 is “OUT2 = IN4 A
ND IN5 ", the designated layer 404 representing" IN4 "and" IN5 "
Is input to the designated layer 405 indicating the AND operation. The figure calculation step 417 represents “RESIZE + 0.5 OUT 6”, and the figure is changed by inputting the figure calculation step 416 representing “OUT6”. Further, the check item 421 corresponds to the check item 320 “CHEC
K_1 (IN1, IN2) "and designated layer 401 representing" IN1 "
And a designated layer 402 representing “IN2” are input to perform the check. Check item 422 is “CHECK_2 (OUT1
)) And a graphic operation step 411 representing “OUT1” is input and checked. The same applies to the following, and the check item 425 indicates "CHECK_5 (OUT5)", and the graphic operation step 415 indicating "OUT5" is input and checked.

Hierarchical level 0 in the graphic operation process shown in FIG.
5 correspond to the order of processing. Designated layers 401-408
Is hierarchical level 0 (lowest hierarchical level), and check items 4
As the number approaches 21 to 425, the numerical value of the hierarchical level sequentially increases (the hierarchical level increases). The order of processing is
The processing is performed in order from the one with the smaller numerical value of the hierarchical level (the one with the lower hierarchical level) to the one with the higher hierarchical level (for example, after performing the processing of the graphic calculation step 412, the processing of the graphic calculation step 414 is performed). In addition, a figure operation step at the same hierarchical level (for example, 414 and 41 at the hierarchical level 2)
In 5), the processing can be performed simultaneously, and the order of the processing does not matter.

The graphic operation tree structure basic dividing means 103 basically divides the graphic operation tree structure created by the graphic operation tree structure creating means 102 into a plurality of groups.

Each of the groups after the basic division is one unit of the parallel processing, and is a basis of the division rule file.
Therefore, the basic division is performed such that each group includes at least one check item. If there is a plurality of check items sharing one graphic operation step, a plurality of check items sharing the graphic operation step should be included in the same group, and different groups should not share the same graphic operation step. I do. Therefore, if the basic division of the graphic operation tree structure cannot be performed so that the graphic operation steps are not shared, the basic division is not performed.

FIG. 5 is a diagram showing the graphic operation tree structure after the basic division according to an embodiment of the present invention, and shows the figure operation tree structure shown in FIG. FIG.
Is divided into three groups 541 to 543. Check item 42
No. 1 does not include a figure calculation step between the designated layers 401 and 402, and thus is set as a group 541 alone. Since the check item 422 does not share the graphic operation step 411 with other check items, the check item 422 is independently set as a group 542. The check items 423, 424, and 425 correspond to the graphic operation step 413.
Are shared, so that the same group 543 is set.

The group re-dividing means 104 divides a group including a large number of graphic operation steps into a plurality of (for example, two) groups among the groups of the graphic operation tree structure which has been basically divided by the graphic operation tree structure basic dividing means 103. Then, the graphic operation tree structure is subdivided. By subdividing,
The size of each group is made uniform by reducing the difference in the number of graphic operation steps included in each group.

In the subdivision, the average value of the number of graphic operation steps included in each group formed by the basic division is calculated, and the group including the graphic operation step more than the average value is selected from the group including the most graphic operation steps. Perform sequentially. Therefore, if the number of graphic operation steps included in each group at the time of the basic division is the same, there is no group including the graphic operation step that is larger than the average value, and thus no re-division is performed.

When performing the subdivision, among the graphic operation steps from the designated layer to each check item in the same group, the graphic operation step having the highest hierarchical level among the graphic operation steps shared by a plurality of check items Is detected. If there are a plurality of sets of check items that share the graphic operation process, a plurality of graphic operation processes are detected, so the check items that share the lowest level of the graphic operation process among the detected graphic operation processes Is a target of subdivision. The graphic operation steps shared by the set of check items to be re-divided are processed redundantly by the re-division.

In the graphic operation step having a lower hierarchical level, the number of graphic operation steps from the designated layer to the graphic operation step is generally smaller than that in the graphic operation step having a higher hierarchical level. For this reason, by dividing a graphic operation process portion having a lower hierarchical level, the number of graphic operation processes shared from a designated layer to a check item is reduced, and processing is performed repeatedly in each group after re-division. The number of graphic operation steps can be reduced.

It is necessary to perform the re-division so that each group includes at least one check item. Therefore, for a group including only one check item at the time of the basic division, the number of graphic operation steps is smaller than the average value. Even if the number is large, the subdivision is not performed.

FIG. 6 is a diagram showing the graphic operation tree structure after the subdivision according to one embodiment of the present invention, and shows the graphic operation tree structure after the basic division shown in FIG. .

As shown in FIG. 6, the group 543 having the largest number of graphic operation steps in FIG. 5 is subdivided to form groups 643 and 644. Group 5 shown in FIG.
Graphic operation steps shared by at least two of the check items 423, 424, and 425 included in 43 are graphic operation steps 412, 413, 414, and 416. Among these graphic operation steps, the one close to each check item (higher hierarchical level) is the graphic operation step 413 in the set of the check items 423, 424 and the check item 425, and the check item 423, the check item 424 Is the figure calculation step 416. Graphic operation steps 413, 4
16, the graphic operation step 413 with the lower hierarchical level
Is divided into a group including the check items 423 and 424 and a group including the check items 425.

As a result, the check items 423, 42
4 and graphic operation steps 412, 413, 414, 41
6, 417 constitute one group 643, and the check item 425 and the graphic operation steps 413, 415 constitute one group 644. By performing the subdivision in this manner, only the graphic operation step 413 is performed in the group 64.
3,644, and the number of graphic operation steps shared by subdivision of the group is minimized.

When the number of groups formed by the basic division or the subdivision is larger than the number that can be processed in parallel by the DRC unit 109, the group integration unit 105
A plurality (for example, two) groups are integrated. The number that can be processed in parallel by the DRC unit 109 can be obtained by searching in advance in the data processing device 220 shown in FIG. By performing the integration, the difference in the number of graphic operation steps included in each group can be reduced, and the difference in the size of each group can be reduced.

The integration is performed sequentially from the group having the smallest number of graphic operation steps in the group. When two groups are integrated, a group including the least number of graphic operation steps and a group including the second least number of graphic operation steps are integrated into the same group. By combining a plurality of groups into one, the number of graphic operation steps in the group is increased and the number of groups is reduced. The integration is repeated until the number of groups falls below the number that can be processed in parallel by the DRC unit 109.

FIG. 7 is a diagram showing the graphic operation tree structure after integration according to an embodiment of the present invention, and shows the graphic operation tree structure after basic division shown in FIG. 5 integrated.
As shown in FIG. 7, the group 541 having the smallest number of graphic operation steps in FIG. 5 and the group 542 having the second smallest number of graphic operation steps are integrated. Thus, the check items 421 and 422 and the graphic operation step 411
One group 741 is formed.

The group forced division means 106 determines whether the number of groups formed by the basic division or the subdivision is DR
If the number is smaller than the number that can be processed in parallel by the C means 109, the group is forcibly divided. The number that can be processed in parallel by the DRC unit 109 can be obtained by searching in advance in the data processing device 220 shown in FIG.
By performing the forced division, the difference in the number of graphic operation steps included in each group can be reduced, and the difference in the size of each group can be reduced.

When the forced division is performed, the division is performed sequentially from the group having the largest number of graphic operation steps in the group. When one group is forcibly divided into two, the check item having the highest hierarchical level is divided in the group having the largest number of graphic operation steps. A check item to be divided and a graphic operation step related to only the check item to be divided among the graphic operation steps up to the check item are divided from the current group. Then, a graphic operation process which is executed redundantly by the divided check item and the other check items is shared by both check items, and a new group is formed by the divided check item and the graphic operation process related thereto. The forced division is repeated until the number of groups reaches a number that can be processed in parallel by the DRC unit 109.

By dividing the check items having the highest hierarchical level of the group to be subjected to the forcible division, the difference in the number of graphic operation steps included in a plurality of (for example, two) groups after the division is reduced. Can be reduced in size of each group.

Since the forced division must be performed so that each group includes at least one check item, a group that includes only one check item at the time of the basic division or re-division is subject to the forced division. Even if it is, the forced division is not performed.

FIG. 8 is a diagram showing the graphic operation tree structure after the forcible division in one embodiment of the present invention, and shows the figure operation tree structure after the basic division shown in FIG. 5 which is forcibly divided. .

As shown in FIG. 8, in the group 543 having the largest number of graphic operation steps in FIG. 5, the check item 424 having the highest hierarchical level is forcibly divided. As a result, one group 843 is composed of the check items 423 and 425 and the graphic operation steps 412 to 416, and the check item 424 and the graphic operation steps 412 to 414 and 41
6, 417 form one group 844. The graphic operation steps 412 to 414 and 416 are divided into groups 843 and
844. By dividing in this way, the difference in size between the group 843 and the group 844 after the forced division can be reduced.

The division rule file 107 contains the basic partitioning means 103 for the graphic operation tree structure, the group re-division means 104,
Group integration means 105 or forced group division means 1
A final group is created for each final group formed in step 06 and stored in the storage device 240.

Each of the division rule files 107 has a designated layer in which a layer necessary for processing the graphic operation process is designated, a check item belonging to the formed group, and a file from the designated layer to the check item. The graphic operation process is described and stored in the storage device 140 shown in FIG.

FIG. 9 is a diagram showing a division rule file according to an embodiment of the present invention. The rule file shown in FIG. 3 is obtained by dividing the rule file shown in FIG. 4 shows a division rule file. The division rule file 941 corresponds to the group 541 shown in FIG. 5, and the division rule file 942 corresponds to the group 542 shown in FIG.
43 corresponds to the group 543 shown in FIG.

The layout data 108 is externally input using the data input device 210 shown in FIG. The layout data 108 describes layout data of an integrated circuit that performs DRC using the division rule file 107.

The DRC unit 109 extracts information from the plurality of division rule files 107 and the layout data 108, and performs DRC parallel processing on the layout data 108 for each group of the division rule file 107.

The division check result file 110 has the DR
It is created for each group in which DRC parallel processing has been performed by the C means 109 and stored in the storage device 240.

The check result summing means 111 sums up the DRC results for each group described in the plurality of divided check result files 110. The DRC tally result obtained by the parallel processing is obtained by using the rule file 101 and the layout data 108 that are not divided.
This is equivalent to the result of executing the DRC in the C means 109.

The check result file 112 describes the DRC total result obtained by the parallel processing in the check result totaling means 111 and is stored in the storage device 240. Although not shown in FIG. 1, the contents of the check result file 112 are stored in the data output device 130 shown in FIG.
Is output to an external display device or the like via the.

FIG. 10 is a flowchart showing a layout verification parallel processing method according to an embodiment of the present invention, showing the operation of the layout verification parallel processing apparatus shown in FIG.

It is assumed that the rule file 101 shown in FIG. 1 is stored in advance in the storage device 240 shown in FIG. The rule file shown in FIG. 3 is an example of the rule file 101 shown in FIG.

The graphic operation tree structure creating means 102 inputs the rule file 101 and extracts information on the designated layer 300, the graphic operation step 310 and the check item 320 included in the rule file 101 (step S1001; hereinafter simply S1001). The same applies to other steps).

The graphic operation tree structure creating means 102 executes S10
01, a graphic operation tree structure is created using the information extracted from the rule file 101 (S1002). The graphic operation tree structure shown in FIG. 4 is an example of the graphic operation tree structure created from the rule file in S1002.

The figure operation tree structure basic division means 103
The graphic operation tree structure created in 1002 is basically divided into a plurality of groups that do not share a graphic operation process with each other (S1003). The graphic operation tree structure after the basic division shown in FIG. 5 is an example of the graphic operation tree structure obtained by basic division in S1003.

The group re-dividing means 104 determines whether or not it is possible to equalize the number of graphic operation steps for each group after the basic division (S1004). The fact that the number of graphic operation steps can be equalized means that the number of graphic operation steps included in each group after the basic division varies.

If it is determined in S1004 that the number of graphic operation steps can be equalized, the flow advances to S1005. S
If it is determined in step 1004 that the number of graphic operation steps cannot be equalized, the process advances to step S1006.

If it is determined in S1004 that the number of graphic operation steps in each group can be equalized, the group re-dividing means 104 re-divides the group of the graphic operation tree structure which is basically divided in S1003 (S1003).
5). The graphic operation tree structure after the subdivision shown in FIG.
5 is an example of a graphic operation tree structure subdivided in 005.

When the processing of S1005 is completed, S100
4 and until the number of graphic operation steps cannot be equalized, that is, until there is no group including graphic operation steps more than the average value of the number of graphic operation steps included in each group after the basic division. repeat.

If it is determined in S1004 that the number of graphic operation steps cannot be equalized, the group re-dividing means 1
04 compares the number of groups formed with the number of groups that can be processed in parallel (the number of parallel processes) (S1006). If it is determined that the number of formed groups is larger than the number of parallel processes, the process proceeds to S1007. If it is determined that the number of groups is smaller than the number of parallel processes, the process proceeds to S1008. If it is determined that the number of groups and the number of parallel processes are the same, S10
Go to 09.

If it is determined in S1006 that the number of groups is larger than the number of parallel processes, the group integration means 105
Integrates a plurality of groups including a small number of graphic operation steps from the formed groups into one group (S1).
007). The graphic operation tree structure after integration shown in FIG.
1007 is an example of a graphic operation tree structure integrated in 1007.
Upon completion of the process in S1007, the process returns to S1006, where the number of groups and the number of parallel processes are compared again.

If it is determined in S1006 that the number of groups is smaller than the number of parallel processes, the group compulsory division means 106 compulsorily divides, among the formed groups, the group including the largest number of graphic operation steps into a plurality of groups. (S1008). The graphic operation tree structure after forcible division shown in FIG. 8 is an example of the graphic operation tree structure forcibly divided in S1008. When the processing of S1008 is completed, S10
Returning to step 06, the number of groups and the number of parallel processes are compared again.

If it is determined in S1006 that the number of groups and the number of parallel processes are the same, the group re-dividing unit 104 creates a division rule file 107 for each formed group (S1009). The division rule file shown in FIG. 9 is an example of the plurality of division rule files 107 created in S1009.

The plurality of DRC units 109 perform DRC parallel processing using the plurality of division rule files 107 and the layout data 108 created in S1009 (S1010). A division check result file 110 is created for each processing of the DRC result and stored in the storage device 240.

The check result totaling means 111 determines in S101
0, the results of the DRCs processed in parallel are imported from the plurality of divided check result files 110 and totaled (S1011), and the totaled results are stored in the check result file 11
2 and the process ends.

FIG. 11 is a flowchart showing another example of the parallel processing method for layout verification in one embodiment of the present invention. The flowchart shown in FIG.
Is substantially the same as the flowchart showing the parallel processing method shown in (1), except that S1011 is not executed. The processing of S1101 to S1110 shown in FIG.
Are the same as S1001 to S1010.

Therefore, when the parallel processing method of layout verification shown in FIG. 11 is executed by the parallel processing apparatus shown in FIG. 1, the processing is terminated by creating the division check result file 110 and the check result totalizing means 111 Does not perform the tallying process. Then, the divided check result file 110 is output as a final check result file to an external display device or the like via the data output device 130 shown in FIG.

In the parallel processing shown in FIG.
After parallel processing of C, without summing up each DRC result, D
Check the results for each RC process. This makes it possible to individually check desired check results among the DRC results processed in parallel.

[0105]

As described above, the present invention has an effect that the time required for DRC parallel processing can be reduced. Further, the present invention has an effect that the parallel processing device can be effectively used.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a parallel processing device for layout verification according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of an information processing apparatus for realizing a parallel processing apparatus for layout verification according to an embodiment of the present invention.

FIG. 3 is a diagram showing a rule file according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating a graphic operation tree structure according to an embodiment of the present invention.

FIG. 5 is a diagram showing a graphic operation tree structure after basic division according to an embodiment of the present invention.

FIG. 6 is a diagram illustrating a graphic operation tree structure after subdivision according to an embodiment of the present invention.

FIG. 7 is a diagram illustrating a graphic operation tree structure after integration according to an embodiment of the present invention.

FIG. 8 is a diagram showing a graphic operation tree structure after forced division according to an embodiment of the present invention.

FIG. 9 is a diagram illustrating a division rule file according to an embodiment of the present invention.

FIG. 10 is a flowchart illustrating a layout verification parallel processing method according to an embodiment of the present invention.

FIG. 11 is a flowchart illustrating another example of a parallel processing method for layout verification according to an embodiment of the present invention.

[Explanation of symbols]

101 Rule File 102 Graphic Operation Tree Structure Creation Unit 103 Graphic Operation Tree Structure Basic Division Unit 104 Group Subdivision Unit 105 Group Integration Unit 106 Group Compulsory Division Unit 107 Division Rule File 108 Layout Data 109 DRC (Design Rule Check) Unit 110 Division Check Result file 111 Check result totaling means 112 Check result file 210 Data input device 220 Data processing device 230 Data output device 240 Storage device 300, 401 to 408 Specified layer 310, 411 to 417 Graphic calculation process 320, 421 to 425 Check items 541 to 541 543,641-644,741,742,8
41-844,941-943 group

Claims (11)

[Claims] 1. A dividing means for inputting and dividing a rule file for layout verification to create a plurality of dividing rule files, a uniforming means for equalizing the sizes of the plurality of dividing rule files, Verification means for performing layout verification by parallel processing using the plurality of divided rule files and layout verification target data. 2. The division rule file includes: layer information for specifying a layer to be subjected to layout verification; check information for specifying the content of a layout verification check; and graphic operation content from the layer information to the check information. Graphic calculation information to be specified, wherein the dividing means divides the graphic calculation information into a plurality of graphic calculation steps at predetermined processing time intervals, and wherein the plurality of division rule files are identical to each other in the same figure calculation processing. 2. The parallel processing apparatus for layout verification according to claim 1, wherein the rule file is divided so as not to share a process. 3. The method according to claim 1, wherein the equalizing means calculates an average value of the number of graphic operation steps included in each of the plurality of division rule files, and equalizes the size according to the calculated average value. The parallel processing device for layout verification according to claim 2. 4. The uniformizing means compares the number of graphic operation steps included in the division rule file with the average value,
The image processing apparatus further includes a re-division unit that divides a file having a number of graphic calculation steps included in the division rule file that is larger than the average value from among the plurality of division rule files and creates a plurality of sub-division rule files. 4. The parallel processing device for layout verification according to claim 3, wherein 5. The equalizing means compares the number of the plurality of division rule files and the plurality of re-division rule files with the number of parallel processes of the verification means, and determines that the number of compared files is the parallel number. If the number of files is larger than the number of processes, a plurality of files are sequentially selected and integrated from the file having the smaller size, and
With integration means to create two integration rule files,
The parallel processing apparatus for layout verification according to claim 4, wherein: 6. The equalizing means compares the number of the plurality of division rule files and the plurality of re-division rule files with the number of parallel processes of the verification means, and determines that the number of compared files is the parallel number. If the number of processes is smaller than the number of processes, the file having the largest size among the compared files is divided to create a plurality of forced division rule files, and a forced division unit is provided. Item 5. A parallel processing device for layout verification according to item 4. 7. The subdivision means extracts the graphic operation steps shared by the plurality of check information, and extracts, from the extracted graphic operation steps, the one closest to the layer information to the plurality of divided information. 7. The parallel processing apparatus for layout verification according to claim 4, wherein the division rule file is divided so as to be shared by the subdivision rule files. 8. The forcible dividing means extracts the graphic operation steps shared by the plurality of check information, and extracts the closest one of the extracted graphic operation steps from the check information to the divided plurality of the check information. The parallel processing apparatus for layout verification according to claim 6, wherein the re-division rule file is divided so as to be shared by the forced division rule file. 9. The parallel processing apparatus for layout verification according to claim 1, further comprising a totalizing means for totalizing a result of the parallel processing by said verifying means. 10. A division step of inputting and dividing a layout verification rule file to create a plurality of division rule files, a uniformizing step of equalizing the sizes of the plurality of division rule files, A verification step of performing layout verification by parallel processing using the plurality of divided rule files and the layout verification target data. 11. A dividing means for dividing a computer having an input / output function by inputting a layout verification rule file and creating a plurality of division rule files; Functioning as a layout verification parallel processing device, comprising: a conversion unit; Computer-readable recording medium on which a program for recording is recorded.