JP2002064972A - Drive control method of dc-dc converter and dc-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive control method of a DC-DC converter and a DC-DC converter which can reduce power loss and increase a power supply capable time. SOLUTION: At least two FET's, an FET 311 with a high switching speed and an FET 312 with a low switching resistance, are used and active terminals (drain terminals and source terminals) of the FET's 311 and 312 are connected in parallel to each other to switch a conductive circuit between an electrically continuity state and an electrically non-continuity state by using the FET's 311 and 312 in parallel. When the conductive circuit is switched from the non- continuity state to the continuity state, a switching control circuit 313 turns on the FET 311 with a high switching speed first and, when the FET 311 is saturated, turns on the 2nd FET 312. In the same way, when the conductive circuit is switched from the continuity state to the non-continuity state, the switching control circuit 313 turns off the FET 312 and then turns off the FET 311 at a voltage close to the saturation voltage of the FET 311.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-efficiency power supply in a portable electronic device, and more particularly, to a DC / DC converter used in a power supply circuit for driving a DC / DC converter with improved efficiency and high-speed response. Control method and DC
/ DC converter.

[0002]

2. Description of the Related Art Heretofore, in notebook personal computers, mobile phones, and other portable electronic devices, the voltage of a battery is reduced by a DC comprising a step-down switching power supply circuit.
The voltage is reduced to a specified voltage by a / DC converter and supplied to an electronic circuit for driving.

As shown in FIG. 2, for example, this type of DC / DC converter has a field effect transistor (FE) that outputs an input voltage Vin from a battery input from an input terminal 21a to an output terminal 21b via an inductor 22.
T), a smoothing capacitor 24 connected between the output terminal 21b and the ground, an inductor 22
And a commutation diode 25 connected in parallel with the series circuit of the smoothing capacitor 24 and with a polarity that maintains the current of the inductor 22, and connected in parallel with the commutation diode 25 and with the same conduction polarity as the commutation diode 25. And a switching control circuit 28. The second switching element 26 is composed of a connected FET, a smoothing capacitor 27 connected between the input terminal 21a and the ground.

The switching control circuit 28 monitors an output voltage Vout from the output terminal 21b, and turns on and off the first and second switching elements 23 and 26 so that the output voltage Vout has a constant value. I do. At this time, control is performed such that the second switching element 26 is turned off when the first switching element 23 is turned on.

According to the DC / DC converter having the above-described structure, when the first switching element 23 is on, the voltage Vin input to the input terminal 21a is smoothed by the inductor 22 and the smoothing capacitor 24, and the output terminal 21b Is output to Also, the first switching element 2
When 3 is off, the second switching element 26 is turned on, the current of the inductor 22 is maintained by the commutation diode 25 and the second switching element 26, and a constant voltage is output to the output terminal 21b.

At this time, the switching control circuit 28 changes the pulse width of the pulse signal for controlling the on / off of the first and second switching elements 23 and 26 in accordance with the change of the output terminal voltage Vout. Feedback control is performed so that the voltage Vout becomes constant.

Further, as shown in FIG. 3, the switching control circuit 28 controls the first and second switching elements 23 and 26 to prevent a cross current in which the first and second switching elements 23 and 26 are simultaneously turned on. After switching from the on state to the off state, a predetermined dead time t _DET is set, and after the dead time t _DET elapses, the second or first switching element 26 or 23 is turned on.

Thus, even when the load supplied to the output terminal 21b (not shown) is a heavy load, the energy stored in the inductor 22 when the first switching element 23 is turned off. Is discharged through the second switching element 26, so that the commutation diode 2
5 does not cause forward voltage loss, and efficient synchronous rectification can be performed.

Further, in the above DC / DC converter, when the input voltage from the battery drops to near the output voltage, the switching element 23 is turned on and the switching element 26 is set to the off state, and the switching operation is performed. By maintaining the stopped conductive state, the output voltage is maintained at a specified voltage, thereby extending the operation time of the battery.

Although the DC / DC converter shown in FIG. 2 is a step-down synchronous rectification type, a step-down chopper type DC / DC converter (see FIG. 4) in which the switching element 26 is removed is also known.

According to the step-down chopper type DC / DC converter, when the switching element 23 is on,
The voltage Vin input to the input terminal 21a is
And the output terminal 21 smoothed by the smoothing capacitor 24.
b.

When the switching element 23 is off, the current in the inductor 22 is maintained by the commutation diode 25, and a constant voltage is output to the output terminal 21b. At this time, the switching control circuit 28 changes the pulse width of a pulse signal for controlling on / off of the switching element 23 according to the change of the output terminal voltage Vout,
Feedback control is performed so that the output terminal voltage Vout becomes constant.

[0013]

However, switching semiconductor devices such as transistors and field effect transistors generally require some time to switch between the off state and the on state. This time is generally called a switching time. If the switching time is long (the switching speed is low), the switching loss increases. For example, when the switching element 23 switches between the off state and the on state, the product of the drain-source voltage Vds and the drain current Id of the switching element 23 causes a power loss between the switching times t1 and t2 as shown in FIG. Becomes

Furthermore, even after the switching element 23 is completely turned on, the drain-source voltage Vds does not drop below the saturation voltage Vsat due to the on-resistance of the element itself, thereby reducing power loss in the element. Has occurred.

In a switching semiconductor device such as a transistor or a field-effect transistor, a switching speed (a switching speed between an off state and an on state) and an on-resistance (saturation voltage) generally have a trade-off relationship. One element cannot achieve both high switching speed and low on-resistance. For this reason, usually, a circuit is configured using switching semiconductor elements in which the switching speed and the on-resistance (saturation voltage) are balanced.

Even if the switching element 23 is maintained in a conductive state, the switching element 23 and the inductor 22 are connected in series between the input terminal 21a and the output terminal 21b. And the output voltage Vout could not be maintained at the specified value.

That is, as shown in FIG. 6, the input voltage Vin from the battery gradually decreases as the driving time of the electronic device elapses, and after the input voltage Vin reaches the voltage Va1, the output voltage V
out gradually decreases. Here, Va1 = Vset + Vdrp, Vset is a set output voltage, and Vdrp is a voltage drop due to a series resistance of the switching element 23 and the inductor 22.

Therefore, when the input voltage Vin reaches the lower limit value Vmin of the allowable driving voltage range of the electronic circuit after reaching the voltage Va1, the driving of the electronic circuit is stopped. Therefore, the increase in the driving time of the electronic circuit by the battery has been the limit.

For these reasons, a battery-driven portable electronic circuit device, particularly a cellular phone or a notebook personal computer, has a limit in reducing the consumption of the battery, and the increase in the driving time by the battery has reached the limit. Also, in a mobile phone, it is necessary to instantaneously switch the power supplied from the DC / DC converter in accordance with the state of the received radio wave. As described above, the switching speed of the switching semiconductor element and the on-resistance have a trade-off relationship. Therefore, there is a problem that when the speed is increased, the driving time by the battery is reduced.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a drive control method and a DC / DC converter for a DC / DC converter capable of reducing power loss and increasing power supply time.

[0021]

According to the present invention, a switching speed (switching time) based on an element area of a switching semiconductor element is devised to achieve the above object.
The relationship between the resistance and the on-resistance (saturation voltage) was used to reduce power loss. Here, the ON resistance includes, for example, an ON resistance of an FET, an equivalent ON resistance based on a saturation voltage of a transistor, and the like.

Generally, in a switching semiconductor element such as a transistor or a field effect transistor, the switching speed is in inverse proportion to the ON resistance (saturation voltage). This is because if the chip area of the switching semiconductor element is large, the on-resistance (saturation voltage) is low, and if the chip area of the switching semiconductor element is large, the capacitance based on the area is large and the input / output signal waveform is dull. There is a relationship that the switching speed becomes slower.

The active terminals of two or more switching semiconductor elements are connected in parallel by utilizing the relationship between the switching speed and the magnitude of the on-resistance (saturation voltage), and these switching semiconductor elements are used in combination. The conduction state and the non-conduction state between the terminals are switched.

When the active terminals of two or more switching semiconductor elements are connected in parallel and used together, for example,
When a field-effect transistor is used as a switching semiconductor element, the drain of each element is connected and the source of each element is connected, and when a transistor is used as a switching semiconductor element, the collector of each element is connected and Used by connecting the emitters of the elements.

Here, the on-resistance (saturation voltage) and the capacitance based on the chip area of the switching semiconductor element are adjusted by controlling the number of switching semiconductor elements to be set to the on state and the switching timing of the on / off state. can do. For example, by setting only one switching semiconductor element to the on state at the beginning of switching from the off state to the on state, it is possible to switch from the off state to the on state at a switching speed based on the capacitance of the single switching semiconductor element. it can. Similarly, when only one switching semiconductor element is set to the on state when switching from the on state to the off state, the switching state is switched from the on state to the off state at a switching speed based on the capacitance of only the switching semiconductor element. be able to. Further, if two or more switching semiconductor elements are set to the on state in the conductive state, these elements are connected in parallel, and the on resistance (saturation voltage) as a whole decreases. Thereby, the on-resistance (saturation voltage) connected in series to the conductive path is lower than when the switching semiconductor element is used alone. Therefore, the power loss due to the ON resistance (saturation voltage) in the ON state of the switching semiconductor element can be reduced.

Further, when a switching semiconductor element having a low on-resistance (saturation voltage) is used together to set the switching semiconductor element to an on state in a conductive state, the switching semiconductor element has a lower inter-terminal saturation voltage than the switching semiconductor element. A low inter-terminal saturation voltage results.

When the switching semiconductor element having a large current-carrying capacity is set to the ON state during the conductive state, current flows through two or more elements including the switching semiconductor element, so that the current-carrying capacity increases.

Further, by setting one of the two or more switching semiconductor elements connected in parallel to the ON state, the conductive path is made conductive during the switching time of the switching semiconductor element. Can be. Thereafter, by setting the other switching semiconductor elements to the ON state, the on-resistance (saturation voltage) connected in series to the conductive path can be reduced as compared with the case where the switching semiconductor element is used alone. .

When the active terminals of two or more switching semiconductor elements connected in parallel are switched from the non-conductive state to the conductive state, one switching semiconductor element is set to the ON state, and then the second and subsequent switching elements are switched. The switching setting of the semiconductor element from the off state to the on state is set such that the terminal voltage of the switching semiconductor element set to the on state immediately before this drops to a predetermined ratio of the terminal voltage when the switching semiconductor element is set to the on state. If this operation is performed, a current will rapidly flow through the conductive path due to the switching speed of the switching semiconductor element which is initially set to the ON state, and the terminal voltage of the switching semiconductor element will decrease.
Thereafter, the switching setting from the off state to the on state of the second and subsequent switching semiconductor elements is performed at the time when the terminal voltage of the switching semiconductor element set to the on state immediately before the switching semiconductor element sets the switching semiconductor element to the on state. This operation is performed when the inter-terminal voltage has decreased to a predetermined ratio, thereby lowering the saturation voltage of these switching semiconductor elements.

When the active terminals of two or more switching semiconductor elements connected in parallel are switched from the conductive state to the non-conductive state, the switching speed from the ON state to the OFF state is higher than that of the other switching semiconductor elements. By finally setting the semiconductor element to the off state, the conductive path is turned off at a high switching speed of the switching semiconductor element.

When the active terminals of two or more switching semiconductor elements connected in parallel are changed from the conductive state to the non-conductive state, all the switching semiconductor elements except one are set to the off state. By setting the last one switching semiconductor element to the off state, the switching semiconductor elements connected in series to the conductive path are reduced to the remaining one switching semiconductor element. As a result, the capacitance due to the chip area of the remaining one switching semiconductor element is set to the minimum value, so that the control signal for making the conductive path non-conductive does not become dull, and the switching of the switching semiconductor element does not occur. At speed, the conductive path is rendered non-conductive.

Further, when switching between the active terminals of the two or more switching semiconductor elements connected in parallel from the conductive state to the non-conductive state to the conductive state, different elements are sequentially set as the switching semiconductor elements which are first set to the ON state. With the use, stress can be prevented from being applied only to a specific switching semiconductor element. That is, a large stress is applied to the switching semiconductor element that is set to the first ON state because power loss at the time of switching becomes large as compared with other elements. However, the stress can be distributed to each switching semiconductor element by sequentially using different elements as the switching semiconductor element to be initially set to the ON state.

When switching between the active terminals of two or more switching semiconductor elements connected in parallel from the non-conductive state to the conductive state, the switching speed from the off state to the on state is higher than that of the other switching semiconductor elements. By setting the ON state sequentially from the semiconductor element, the transition from the OFF state to the ON state is performed in a minimum time.

When the active terminals of the two or more switching semiconductor elements connected in parallel are set from the non-conductive state to the conductive state, the time required for the conductive state is determined by the switching semiconductor element having a high switching speed. Therefore, if all the switching semiconductor elements are set to the ON state at the same time, the switching speed can be improved and the saturation voltage can be reduced.

Also, by setting the threshold levels of two or more switching semiconductor elements connected in parallel to different values, each control signal whose voltage waveform or current waveform changes with the passage of time can be used. On / off control of the switching semiconductor element can be performed. This eliminates the need to generate two or more control signals having different timings. As the waveform of the control signal, for example, a trapezoidal wave, a triangular wave, a step-shaped wave, a sine wave, or the like, in which the rising and falling of the waveform requires a time equal to or more than a predetermined value and continuously or stepwise changes in level. I just need.

Further, by using a field effect transistor as the switching semiconductor element and setting the threshold voltage level of the field effect transistor to a different value,
ON / OFF control of each field effect transistor can be performed by the same voltage waveform. This eliminates the need to generate two or more control voltages with different timings.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a DC / DC converter according to a first embodiment of the present invention, and FIG. 7 is a DC / DC converter.
It is an outline view showing a converter. In the figure, 12 is an inductor, 13 and 14 are capacitors, 15 and 16 are resistors, and 30A is an integrated circuit (hereinafter referred to as IC: DC / D).
DC / D converter
A C converter circuit is configured. A portion excluding the capacitors 13 and 14 in these configurations is mounted on a ceramic substrate 17 as a DC / DC converter element 10A as shown in FIG. On the surface of the ceramic substrate 17, six external terminals 11a to 11f and resistors 15, 16 are provided.
And the IC 30A are mounted, and the inductor 12 is mounted on the back surface of the ceramic substrate 17. Inductor 12
Is formed of a laminated inductor having a rectangular parallelepiped shape mountable on the ceramic substrate 17. Since the capacitors 13 and 14 have a size that is about half of that of the multilayer inductor 12, D
When the C / DC converter element is mounted on the parent circuit board, it is mounted on the parent circuit board and connected. In addition, capacitor 1
DC /
A DC converter element may be configured.

Each of the external terminals 11a to 11f has a height greater than the mounting height of the resistors 15 and 16 and the IC 30A, and the external terminals 11a to 11f face the component mounting surface of the parent circuit board. 11f can be connected to the parent circuit board.

An external terminal 11a to which a voltage Vin from a battery is applied is grounded via a capacitor 13 and is connected to an IC.
It is connected to terminal 30a of 30A. The external terminal 11b connected to the load is grounded via the capacitor 14 and connected to the terminal 30b of the IC 30A via the inductor 12, and outputs the voltage Vout to the load. The external terminal 11b is connected to the resistor 1 connected in series.
5, 16 grounded. These resistors 1
The output voltage Vout is divided by 5 and 16, and a feedback voltage Vfd is generated. This feedback voltage is applied to terminal 3 of IC 30A.
0c so that the IC 30A can input the output voltage Vout as the feedback voltage Vfd.

The IC 30A has two switching circuits 3
1A and 31B, a commutation diode 32, and a switching control circuit 33. Switching circuit 31
A and 31B have the same configuration, and each has a P-channel field-effect transistor (hereinafter referred to as FET) 311,
312 and a switching control circuit 313.

The FET 311 has a shorter on / off switching time, ie, a shorter switching time, than the FET 312, and the FET 312 has a lower on-resistance than the FET 311. These FETs 311,
The active terminals of 312, ie, the drain and source, are connected in an array, and these two FETs 311 and 312 open and close one conductive path.

The FET 311 of the switching circuit 31A,
The source of 312 is connected to the external terminal 11a for input via the terminal 30a, and the drain is connected to the external terminal 11b for output via the terminal 30b and the inductor 12. The FETs 311 and 3 of the switching circuit 31A
The gate of 12 is the control circuit 31 of the switching circuit 31A.
3 is connected.

The FET 311 of the switching circuit 31B
The source of 312 is grounded, and the drain is connected to terminal 30b. Further, the FE of the switching circuit 31B
Gates of T311 and 312 are connected to the control circuit 313 of the switching circuit 31B.

The cathode of the commutation diode 32 is connected to the terminal 30
b, and the anode is grounded.

The control circuit 313 of each of the switching circuits 31A and 31B includes the switching control circuit 3
3 to generate element control signals CS1 and CS2 for switching the respective ON / OFF states of the FETs 311 and 312 based on the ON / OFF control signal CS0 input from
Output to the gates of FETs 311 and 312.

The switching control circuit 33 is, for example, as shown in FIG.
, The error amplifier 331 and the triangular wave generation circuit 33
2. Comparator 333, NPN transistor 33
4. It is composed of a PNP transistor 335.

A feedback voltage Vfd obtained by dividing the output voltage Vout by the resistors 15 and 16 is applied to the error amplifier 331. The resistors 15 and 16 are connected in series, one end of which is grounded, and the other end of which is supplied with a feedback voltage Vfd.
The voltage Vfd obtained by dividing the output voltage Vout is output to the error amplifier 331.
To enter.

The error amplifier 331 receives the voltage Vfd,
An error voltage corresponding to the difference voltage is output so that the voltage Vfd becomes substantially the same as the reference voltage Vref.

The comparator 333 includes the triangular wave generation circuit 3
A comparison is made between the triangular wave voltage outputted from 32 and the above-mentioned error voltage. If the error voltage is larger than the triangular wave voltage, a high-level signal is output. . This output voltage is input to the bases of the transistors 334 and 335, and the transistors 334 and 335 perform a switching operation.
The FETs 311 and 312 of B also perform the switching operation.

Thus, the F of the switching circuit 31A is
When the connection is established between the active terminals (drain and source) of the ETs 311 and 312, the FET 3 of the switching circuit 31B
The active terminals (drain and source) of the switching circuits 11 and 312 are turned off, and the FET 31 of the switching circuit 31B is turned off.
FETs 311 and 312 of the switching circuit 31A when the active terminals (drain and source) of the switching circuits 31 and 312 are conducting.
Twelve active terminals (drain-source) become non-conductive. This operation is repeated, and a continuous substantially constant level DC voltage is output based on these switching operations.

Further, each of the switching circuits 31A, 31
The operation of B will be described in detail.

Here, the switching circuit 31A will be described, but the switching circuit 31B performs the same operation.

Each of the element control signals CS1 and CS2 generated in the control circuit 313 is preferably, for example, a signal as shown in FIG.

That is, at the same time when the on / off control signal CS0 changes from the high level in the off state (period P1) to the low level (period P2 to P4) indicating the on state, one F
The element control signal CS1 for the ET311 also changes from the high level to the low level, and the switching speed is high for the FET.
311 is turned on.

Thus, the potential difference between the terminal 30a and the terminal 30b (the drain-source voltage Vds of the FET 311)
Rapidly decreases in accordance with the switching time of the FET 311 and a current (drain current of the FET 311) Id rapidly flows between the terminals 30a and 30b (period P2).

Thereafter, when the potential difference between the terminals 30a and 30b reaches a saturation voltage based on the ON resistance of the FET 311, the element control signal CS for the other FET 312
2 is switched from high level to low level, and the other F
The ET 312 is set to the ON state. Thereby, the terminal 3
0a, 30b flows through both the FETs 311 and 312, and the on-resistance of one FET 311 is connected in parallel with the on-resistance of the other FET 312.
a, 30b, that is, two FEs connected in parallel.
The drain-source voltage Vds of T311 and 312 decreases in accordance with the switching speed of the other FET 312 (period P3), and settles to the saturation voltage Vsat 'based on the combined on-resistance of these two FETs 311 and 312 (period P3).
4).

Accordingly, the turn-on time ton (switching time of the FET 311) for making the conductive path conductive is shortened, and the power loss at the turn-on time ton is also reduced.

On the other hand, the on / off control signal CS0 changes from a low level in the on state (periods P2 to P4) to a high level (periods P5, P6, and P1) indicating the off state, and at the same time, an element control signal for the other FET 312. CS2 is changed from low level to high level, and the other FET 31
2 is turned off.

As a result, the potential difference between the terminals 30a and 30b (the drain-source voltage Vds of the FETs 311 and 312) increases in accordance with the switching time of the FET 312 (period P5).

Thereafter, when the potential difference between the terminals 30a and 30b reaches a saturation voltage based on the ON resistance of one FET 311, the element control signal CS1 for this FET 311 is switched from low level to high level, and the FET 311
Set to off state.

As a result, the current flowing between the terminals 30a and 30b rapidly decreases in accordance with the switching time of the FET 311, the potential difference between the terminals 30a and 30b rapidly increases (period P6), and the voltage between the terminals 30a and 30b changes. It is made electrically non-conductive (period P1).

Further, when the conductive path is in the conductive state (period P3 to P3)
In 5), since the saturation voltage Vsat 'can be lowered, F
Power loss due to the on-resistance of the ETs 311 and 312 is also reduced as compared with the conventional case.

Therefore, the turn-off time toff (switching time of the FET 11) when the conductive path is turned off.
And the power loss at the turn-off time toff is also reduced.

As described above, according to the DC / DC converter 10A of the present embodiment, the turn-on time ton and the turn-off time toff required for switching can be shortened, so that driving at a high frequency can be easily performed and power loss can be reduced. Can be.

If a low on-resistance FET is further used in place of the other FET 312, the combined on-resistance in the conductive state of the conductive path can be further reduced, and the power loss in the conductive state can be further reduced. be able to.

By appropriately selecting the characteristics of the FETs 311 and 312 to be used, only the switching time can be changed, and the input / output terminals 30a and 3a can be changed.
It is also possible to change only the saturation voltage between 0b.

Further, even if the active terminals (drain, source) of a plurality of FETs are used in parallel instead of the other FET 312, the combined on-resistance and power loss when the conductive path is conductive can be further reduced. It goes without saying that you can do it.

When the two FETs 311 and 312 are turned on first alternately, the stress applied to the FETs when switching from the off state to the on state is reduced.
311 and 312. 3 or more F
When the active terminals of the ET are connected in parallel, the stress applied to the FETs can be dispersed by changing the FETs that are turned on first in order.

In this embodiment, the FETs 311 and 312 having different switching speeds and on-resistances are used. However, these FETs may be almost the same.

Furthermore, when setting from the non-conductive state to the conductive state, the time required for the conductive state depends on the FET 311 having a high switching speed.
The same effect can be obtained even if the ETs 311 and 312 are simultaneously set to the ON state.

In this embodiment, the FET is used as the switching semiconductor element. However, the present invention is not limited to this, and similar effects can be obtained by using a transistor or another semiconductor element.

Next, a detailed example of the switching control circuit of the switching circuits 31A and 31B in the first embodiment will be described.

FIG. 10 is a block diagram showing a switching control circuit according to the first embodiment. In the figure, reference numeral 313A denotes a switching control circuit, which includes a differential amplifier 41, a comparator 42, a reference voltage generation source 43, and gate drive circuits 44 and 45.

The two input terminals of the differential amplifier 41 are connected to the drain and the source of the FETs 311 and 312 connected in parallel, and output a voltage corresponding to the potential difference V1 between the drain and the source. The output voltage of the differential amplifier 41 is input to the non-inverting input terminal of the comparator 42, and the reference voltage Vth output from the reference voltage generation source 43 is applied to the inverting input terminal.

Here, the reference voltage Vth is
Is set to the saturation voltage based on the on-resistance of. Thus, the output signal DS1 of the comparator 42 becomes high level when the potential difference V1 between the drain and the source is equal to or higher than the reference voltage Vth, and becomes low level when the potential difference V1 is lower than the reference voltage Vth.

The output signal DS1 of the comparator 42 and the on / off control signal CS0 are input to each of the gate drive circuits 44 and 45. Based on these signals, the gate circuit 44 generates an element control signal CS1 and the gate drive circuit The circuit 45 generates an element control signal CS2.

According to the above configuration, after the FET 311 is set to the ON state, the potential difference V1 between the drain and the source is set.
When the voltage reaches a saturation voltage based on the ON resistance of the FET 311, the other FET 312 can be set to the ON state. Further, after the other FET 312 is set to the OFF state, the potential difference V1 between the drain and the source is changed to the FET 311.
When the saturation voltage based on the ON resistance of
11 can be set to the off state.

FIG. 11 is a block diagram showing a switching control circuit according to the second embodiment. In the figure, the same components as those in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted. The difference between the second embodiment and the first embodiment is that a two-input OR circuit (hereinafter referred to as an OR circuit) 46 is provided instead of the gate drive circuits 44 and 45.

That is, one input terminal of the OR circuit 46 is connected to the output terminal of the comparator 42, and the other input terminal receives the control signal CS0 and is connected to the gate of the FET 311. The output terminal of the OR circuit 46 is connected to the gate of the FET 312.

As a result, as shown in the timing chart of FIG. 12, the element control signal CS1 for one FET 311 is the same as the on / off control signal CS0, and the element control signal CS2 for the other FET 312 changes from high level to low level. At the same time as the signal DS1, and the rise from the low level to the high level is the same as the signal CS0.

Therefore, the FETs 311 and 3 connected in parallel
It is possible to shorten the turn-on time ton when switching from the non-conductive state to the conductive state between the drain and source of the semiconductor device 12, and reduce the power loss during the turn-on time and the power loss due to the on-resistance during the conductive state. . However, since the two FETs 311 and 312 are simultaneously turned off, the turn-off time toff is the sum of the period P5 and the period P6, and the turn-off time is shortened and the power loss at this time is not significantly improved.

The switching control circuit in which the turn-off time is shortened and the power loss at this time is improved is the third control circuit shown in FIG.
This is the switching control circuit 313C of the embodiment.

In FIG. 13, the same components as those in the above-described second embodiment are denoted by the same reference numerals, and description thereof will be omitted. The switching control circuit 313C is different from the switching control circuit 313B of the second embodiment in that a two-input AND circuit (hereinafter, AND) is used.
Circuit 47). The ON / OFF signal CS0 is input to one input terminal of the AND circuit 47, and the output signal DS1 of the comparator 42 is input to the other input terminal. The output signal of the AND circuit 47 is used as an element control signal CS2 of the FET 312 as an FET.
312 is input to the gate.

With the above configuration, the element control signals CS1 and CS2 shown in the timing chart of FIG. 14 are generated, and the above-described ideal on / off switching can be performed.

Accordingly, the switching control circuit 313 of the third embodiment
DC / D switching circuits 31A and 31B
By providing the C converter 10A, the turn-on time ton and the turn-off time toff can be shortened, and the power loss during the turn-on time and the turn-off time and the power loss due to the on-resistance in the conductive state can be reduced. it can.

Next, a switching circuit according to a fourth embodiment will be described.

FIG. 15 is a configuration diagram showing a switching circuit 31C of the fourth embodiment. This switching circuit 31
C can be used in place of the switching circuits 31A and 31B described above. In the figure, reference numerals 311A and 312A denote N-channel type FETs having a short switching time as in the above-described embodiment. Further, the FET 311
A and 312A have different threshold voltage levels for turning on and turning off, respectively. Here, the threshold voltage level of one FET 311A is V
The threshold voltage level of the other FET 312A is set to Vth2 (> Vth1) higher than Vth1. Reference numeral 313D denotes a switching control circuit, which includes a trapezoidal wave generation circuit 48.

N-channel FETs 311A and 312A
Is turned off when the gate voltage is at a low level, and turned on when the gate voltage is at a high level. Therefore, a signal obtained by inverting the above-mentioned on / off control signal CS0 may be used as the on / off control signal CS0 ′.

The trapezoidal wave generating circuit 48 outputs a trapezoidal wave element control signal CS0 ″ as shown in FIG. 16 based on the ON / OFF control signal CS0 ′. The element control signal CS0 ″
When the on / off control signal CS0 ′ changes from low level to high level, the voltage gradually increases linearly,
When the OFF control signal CS0 ′ changes from the high level to the low level, the voltage gradually decreases linearly. Also, the threshold voltage level V of the FETs 311A and 312A
th1 and Vth2 are set so as to be located between the minimum value and the maximum value of the element control signal CS0 ".

According to the above configuration, as shown in FIG.
When the on / off control signal CS0 'changes from low level to high level and the voltage level of the element control signal CS0 "rises and reaches the first threshold voltage level Vth1, one FET 311A is turned on. Thereafter, when the voltage level of the element control signal CS0 "further increases and reaches the second threshold voltage level Vth2, the other FET 312A
Is turned on. Also, the on / off control signal CS
When 0 ′ changes from the high level to the low level and the voltage level of the element control signal CS0 ″ decreases to reach the second threshold voltage level Vth2, the other FET 312A is turned off. When the voltage level of CS0 "further decreases and reaches the first threshold voltage level Vth1, one FET 311A is turned off.

The above operation can also reduce the power loss at the time of turn-on and turn-off and the power loss attributable to the on-resistance in the conductive state.

The slope of the rise and fall of the trapezoidal wave (element control signal CS0 ″) generated by the trapezoidal wave generation circuit 48 depends on the switching time of each of the FETs 311A and 312A, the saturation voltage and the threshold voltage level Vth1, It is preferable to set the optimum value in consideration of Vth2.

Next, a switching circuit according to a fifth embodiment will be described.

FIG. 17 is a block diagram showing a switching circuit 31D according to the fifth embodiment. This switching circuit 31
C can be used in place of the switching circuits 31A and 31B described above. In the figure, reference numerals 311 and 312 denote the same FET as described above, which has a short switching time and a high on-resistance. Reference numeral 51 denotes an FET which has a shorter switching time at the time of turn-on than the FETs 311 and 312 and a longer switching time at the time of turn-off than the FETs 11 and 12. Reference numeral 52 denotes an FET, whose switching time at the time of turn-off is shorter than that of the FETs 311 and 312, and whose switching time at the time of turn-on is longer than that of the FETs 311 and 312. Here, there is a trade-off relationship between the switching speed of the FET and the on-resistance as described above. The FETs 311, 312, 51, and 52 are connected in parallel with each other, and their sources and drains are connected with each other.

Reference numeral 313E denotes a switching control circuit,
3, comparators 55a and 55b, reference voltage source 54
a, 54b, OR circuits 56a to 56c, and AND circuit 5
7.

The two input terminals of the differential amplifier 53 are connected to the drain and source of the FET 311, 312, 51, 52 connected in parallel, and the potential difference V between the drain and source is set.
Outputs 1.

The output voltage of the differential amplifier 53 is input to the non-inverting input terminal of the comparator 55a, and the first reference voltage Vth-a output from the reference voltage generating source 54a is applied to the inverting input terminal. . Here, the first reference voltage V
th-a is set to a saturation voltage based on the ON resistance of the FET 51. Thereby, the output signal DSa of the comparator 55a becomes high level when the potential difference V1 between the input and output terminals is equal to or higher than the first reference voltage Vth-a, and when the potential difference V1 is lower than the first reference voltage Vth-a. It goes low.

The output voltage of the differential amplifier 53 is input to the non-inverting input terminal of the comparator 55b, and the second reference voltage Vth-b output from the reference voltage generating source 54b is applied to the inverting input terminal. . Here, the second reference voltage V
th-b is set to a saturation voltage based on the ON resistance of the FET 52. As a result, the output signal DSb of the comparator 55b becomes high when the potential difference V1 between the input and output terminals is equal to or higher than the second reference voltage Vth-b, and when the potential difference V1 is lower than the second reference voltage Vth-b. It goes low.

The OR circuit 56a receives the output signal DSa of the comparator 55a and the on / off control signal CS0,
A signal obtained by performing an OR operation on these signals is output to the gate of the FET 311 as an element control signal CSb of the FET 311.

The OR circuit 56b receives the output signal DSa of the comparator 55a and the on / off control signal CS0,
A signal obtained by performing an OR operation on these signals is output to the gate of the FET 312 as an element control signal CSc of the FET 312.

The OR circuit 56c receives the output signal DSa of the comparator 55a and the on / off control signal CS0,
The logical sum of these signals is output.

The AND circuit 57 receives the output signal of the OR circuit 56c and the output signal DSb of the comparator 55b,
The signal obtained by ANDing them is used as the element control signal C of the FET 52.
The signal is output to the gate of the FET 52 as Sd.

The on / off control signal CS0 is FE
The element control signal CSa for T51 is input to the gate of the FET 51.

Next, the operation of the switching circuit 31D having the above configuration will be described with reference to the timing chart shown in FIG.

Here, the FETs 311, 312, 5
The description will be made on the assumption that the conductive path is switched between the conductive state and the non-conductive state by switching the ON / OFF states of the FETs 1 and 52, and a predetermined current flows through the conductive path when the FET is in the ON state.

The on / off control signal CS0 changes from the high level (period P1) in the off state to the low level (periods P2 to P4) indicating the on state, and the element control signal CSa for the FET 51 also changes from the high level to the low level. In other words, the FET 51 is set to the ON state.

Thus, the FET 31 connected in parallel
The potential difference between the drain and the source (the drain-source voltage Vds of the FET 51) is equal to that of the FET 1, 312, 51, and 52.
51 rapidly decreases in accordance with the switching time of the transistor 51, and a current (drain current of the FET 51) I
d quickly flows out (period P2).

Thereafter, the potential difference between the drain and the source becomes F
When the saturation voltage based on the ON resistance of the ET51 is reached, the FET
Element control signals CSb, C for 311, 312, 52
Sc and CSd change from high level to low level, and F
The ETs 311, 312 and 52 are set to the ON state. As a result, the current flowing between the drain and the source becomes four F
ET51, 311, 312, 52, both FETs
On-resistances 51, 311, 312, and 52 are connected in parallel. The potential difference between the drain and the source (voltage V1)
Decrease in accordance with the switching speed of the FETs 311, 312, and 52 (period P3), and these four FETs 51,
The saturation voltage Vsat 'based on the combined on-resistance of 311, 312, and 52 is settled (period P4).

Therefore, the turn-on time ton (the switching time of the FET 51) for making the conductive path conductive is shortened, and the power loss during the turn-on time ton is reduced.

On the other hand, the on / off control signal CS0 changes from a low level in the on state (periods P2 to P4) to a high level (periods P5 to P7) indicating the off state, and F
Element control signal CS for ET51, 311 and 312
a, CSb, and CSc change from the low level to the high level, and the FETs 51, 311 and 312 are set to the off state. Thereby, the potential difference between the drain and the source (voltage V
1) rises according to the switching time of the FETs 51, 311 and 312 (period P5).

Thereafter, when the potential difference (voltage V1) between the drain and the source reaches a saturation voltage based on the ON resistance of the FET 52, the element control signal CSd for the FET 52 changes from a low level to a high level, and the FET 52 is turned off. Is set. As a result, the current flowing between the drain and the source rapidly decreases in accordance with the switching time of the FET 52, the potential difference V1 (Vds) between the drain and the source rapidly increases (period P6), and the electrical connection between the drain and the source occurs. The non-conductive state is established (period P7).

Accordingly, the turn-off time toff (switching time of the FET 52) when the conductive path is made non-conductive.
And the power loss at the turn-off time toff is also reduced.

When the conductive path is in the conductive state (period P3 to P3)
In 5), since the saturation voltage Vsat 'can be made lower than in the conventional case, the power loss due to the combined ON resistance of the FETs 51, 311, 312, and 52 can be reduced as compared with the conventional case.

As described above, according to the switching circuit 31D of the present embodiment, the turn-on time ton and the turn-off time toff for switching can be shortened and the power loss can be reduced.

If a low on-resistance FET is used in place of the other FETs 311 and 312, the combined on-resistance in the conductive state of the conductive path can be further reduced, and the power loss in the conductive state can be further reduced. be able to.

Further, even if the active terminals of a plurality of FETs are used in parallel instead of the other FETs 311 and 312, the combined on-resistance and power loss when the conductive path is conductive can be further reduced. No.

Further, if a plurality of FETs equivalent to the FET 51 having a short turn-on switching time are connected in parallel and the first one is turned on alternately, the stress applied to the FET when switching from the off state to the on state is reduced. Can be dispersed. When the active terminals of three or more FETs are connected in parallel, the stress applied to the FETs can be dispersed by changing the FETs that are turned on first in order.

In this embodiment, the FET is used as the switching semiconductor element. However, the present invention is not limited to this. A similar effect can be obtained by using a transistor or another semiconductor element.

Next, a switching circuit according to a sixth embodiment will be described.

FIG. 19 is a configuration diagram showing a switching circuit 31E of the sixth embodiment. In the figure, the third
The same components as those in the embodiment (FIG. 13) are denoted by the same reference numerals, and description thereof will be omitted. The difference between the sixth embodiment and the third embodiment is that the FETs 58 and 59 having lower on-resistances than the FETs 311 and 312 are connected in parallel to the FET 312, and the gates of the FETs 312, 58 and 59 are connected to the elements. That is, the control signal CS2 is input to perform on / off control.

As described above, the FET having the low on-resistance during the conduction state except for the turn-on period and the turn-off period.
By setting 58 and 59 to the ON state, power loss due to ON resistance in the conductive state can be significantly reduced.

Next, D in the second embodiment of the present invention will be described.
The C / DC converter will be described.

FIG. 20 is a diagram showing DC / DC in the second embodiment.
FIG. 3 is a circuit diagram illustrating a DC converter. In the figure, the same components as those in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted. Further, the DC / DC converter element 10B in the second embodiment enables the set value of the output voltage Vout to be changed by an external control signal, and when the output voltage (set voltage) is high, the PWM (pulse) at a low frequency is used. Switching control by width modulation) is performed, and when the output voltage (set voltage) is low, switching control by PFM (pulse frequency modulation) is performed to maintain the output voltage at a set value. PWM and PFM are switched at about a half of the maximum value of the output voltage (set voltage). Thus, the output set value can be easily changed from the outside, and the conversion efficiency can be improved according to the output set value.

In the present embodiment, as shown in FIG. 21, resistors 336a and 336b, an error amplifier 337, switch circuits 338a to 338c interlocking with each other, and a set value control circuit are different from the switching control circuit of the first embodiment. V that can change the oscillation frequency by the circuit 339 and voltage
A switching control circuit 33B including a triangular wave generating circuit 332B having a built-in CO is provided.

The set value control circuit 339 inputs a digital 2-bit output control signal from the outside and switches the switch circuits 338a to 338c having three circuits and four contacts to switch the set value of the output voltage in four stages. When the first output set value is the highest, the feedback voltage Vfd is determined by the resistors 336a and 336b.
Is input to the error amplifier 331, and the VCO of the triangular wave generation circuit 332B supplies a constant voltage V11
Is applied to generate a triangular wave voltage having a frequency based on the voltage V11. When the second output set value is the next highest, the feedback voltage Vfd is input to the error amplifier 331, the constant voltage V11 is applied to the VCO of the triangular wave generation circuit 332B, and a triangular wave voltage having a frequency based on the voltage V11 is generated. You.
When the output setting value is the third highest value smaller than 1/2 of the maximum output voltage value, the constant voltage V12 is input to the error amplifier 331, and the output voltage of the error amplifier 337 is input to the VCO of the triangular wave generation circuit 332B. . At this time, the error amplifier 3
37 inputs the reference voltage Vref1 and the feedback voltage Vfd and outputs an error voltage between them. At the lowest output set value, the constant voltage V12 is input to the error amplifier 331, and the output voltage of the error amplifier 337 is input to the VCO of the triangular wave generation circuit 332B. At this time, the error amplifier 337 outputs the reference voltage Vref2 (different from Vref1) and the feedback voltage Vfd.
To output these error voltages.

The above configuration is an example, and the output control signal may be 1 bit or 3 bits or more, the output control signal may be input as an analog signal,
You may make it input by a bit serial signal. Further, as a method of changing the set value, the reference voltage of the error amplifier 331 may be switched. Further, as a method of varying the oscillation frequency of the triangular wave generation circuit 332B, a resistor or a capacitor that determines a time constant of the oscillation circuit may be switched. The output set value may be switched using only one of PWM and PFM.

In the first embodiment or the second embodiment, as shown in FIG.
It is also possible to configure a DC / DC converter circuit with a DC / DC converter element 10C using an IC 30C that performs switching control with only one FET connected in parallel to the two. Further, as shown in FIG. 23, a DC / DC converter circuit can be configured by a DC / DC converter element 10D using an IC 30D that performs switching control by removing an FET connected in parallel with the commutation diode 32. These DC / DC converters can improve the efficiency and the like as in the first and second embodiments.

Next, a third embodiment of the present invention will be described.

In the third embodiment, the DC / DC converter circuit described above is applied to a portable telephone, and the DC / DC converter circuit and other electronic circuits are formed on the same circuit board. FIG. 24 is an external perspective view showing the mobile phone 60, FIG. 25 is a perspective view of a main part of the electronic circuit board 62, and FIG.
6 is a sectional side view of a main part. As shown in the figure, the portable telephone 60 includes a small casing 61 suitable for carrying, and an electronic circuit board 62 and a battery (not shown) are housed in the casing 61. The circuit board 61 includes the DC / DC power amplifier PA and other circuit elements as described above.
A DC converter element 10A is mounted, and a DC / DC converter element 10A and capacitors 13 and 14
/ DC converter circuit is configured. This DC / D
A battery (not shown) is connected to the C converter circuit, and the battery voltage is reduced to supply a predetermined voltage to each electronic circuit and the high-frequency power amplifier PA. In addition, a bypass capacitor BC is connected to a supply line from the output of the DC / DC converter circuit to the high-frequency power amplifier PA, thereby removing noise.

According to the above-mentioned portable telephone, the conversion efficiency of the DC / DC converter circuit is improved as compared with the related art, and the drivable time by the battery can be increased.

It is needless to say that a similar effect can be obtained by forming a DC / DC converter circuit using any of the DC / DC converter elements 10A to 10J of the above-described embodiments.

As shown in FIG. 27, the DC /
The DC / DC converter circuit may be formed by directly mounting the IC 30A (to 30J), the inductor 12, and the resistors 15, 16 on the circuit board 61 without using the DC converter elements 10A to 10J. In this case, FIGS. 28 and 29
By mounting the inductor 12 upright on the circuit board 62 as shown in (1), the component mounting space on the circuit board 62 can be effectively utilized.

In this embodiment, the portable telephone is constructed. However, the present invention is not limited to this, and other portable electronic circuit devices, such as a hand-held personal computer and a portable CD player, may be used. Similar effects can be obtained by using a converter.

The above embodiments and examples are merely specific examples of the present invention, and the present invention is not limited to these embodiments and examples. Those skilled in the art will be able to fully understand the present invention without describing all combinations of these embodiments and examples as separate embodiments.

[0136]

As described above, according to the drive control method of the DC / DC converter according to the first to twenty-fourth aspects of the present invention, the active terminals of two or more switching semiconductor elements are connected in parallel. When used in combination, the on-resistance (saturation voltage) connected in series to the conductive path is lower than when the switching semiconductor element is used alone, and the power due to the on-resistance (saturation voltage) in the on-state of the switching semiconductor element Loss is reduced. Furthermore, the switching time can be shortened, and the power loss that occurs during the switching time is reduced. Thus, when a battery is connected to the input terminal and used, the time during which power can be supplied to the load can be extended, and the operating time of the electronic circuit to be driven can be extended.

According to the DC / DC converters of the twenty-fifth to fifty-ninth aspects, the active terminals of two or more switching semiconductor elements are connected in parallel and used together, so that the switching semiconductor elements can be used alone. The on-resistance (saturation voltage) connected in series between the input and output can be reduced as compared with the case where the switching semiconductor device is used, and the power loss due to the on-resistance (saturation voltage) in the on state of the switching semiconductor element can be reduced. . Further, the switching time is shortened, and the power loss that occurs during the switching time is reduced. Thus, when a battery is connected to the input terminal and used, the time during which power can be supplied to the load can be extended, and the operating time of the electronic circuit to be driven can be extended.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a DC / DC converter according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional DC / DC converter.

FIG. 3 is a timing chart illustrating a switching operation in a conventional DC-DC converter circuit.

FIG. 4 is a circuit diagram showing another conventional DC / DC converter.

FIG. 5 is a timing chart illustrating a switching operation in a conventional DC-DC converter circuit.

FIG. 6 is a diagram illustrating a change in output voltage due to battery operation in a conventional example.

FIG. 7 is an external view showing a DC / DC converter according to the first embodiment of the present invention.

FIG. 8 is a circuit diagram showing a switching control circuit according to the first embodiment of the present invention.

FIG. 9 is a timing chart illustrating a switching operation according to the first embodiment of the present invention.

FIG. 10 is a circuit diagram showing a switching control circuit according to a first example of the first embodiment of the present invention;

FIG. 11 is a circuit diagram showing a switching control circuit according to a second example of the first embodiment of the present invention;

FIG. 12 is a timing chart showing the switching operation of the switching control circuit according to the second example of the first embodiment of the present invention;

FIG. 13 is a circuit diagram showing a switching control circuit according to a third example of the first embodiment of the present invention;

FIG. 14 is a timing chart illustrating the switching operation of the switching control circuit according to the third example of the first embodiment of the present invention;

FIG. 15 is a circuit diagram showing a switching circuit according to a fourth example of the first embodiment of the present invention.

FIG. 16 is a timing chart showing the switching operation of the switching circuit according to the fourth example of the first embodiment of the present invention;

FIG. 17 is a circuit diagram showing a switching circuit of a fifth example according to the first embodiment of the present invention.

FIG. 18 is a timing chart showing the switching operation of the switching circuit according to Example 5 of the first embodiment of the present invention.

FIG. 19 is a circuit diagram showing a switching circuit according to Example 6 of the first embodiment of the present invention.

FIG. 20 shows DC / DC according to the second embodiment of the present invention.
Circuit diagram showing converter

FIG. 21 is a circuit diagram showing a switching control circuit according to a second embodiment of the present invention.

FIG. 22 illustrates another DC / DC according to the second embodiment of the present invention.
Circuit diagram showing a configuration example of a DC converter

FIG. 23 shows another DC / DC according to the second embodiment of the present invention.
Circuit diagram showing a configuration example of a DC converter

FIG. 24 is an external perspective view showing a mobile phone according to a third embodiment of the present invention.

FIG. 25 is a perspective view showing a main part of an electronic circuit board according to a third embodiment of the present invention.

FIG. 26 is a side sectional view showing a main part according to a third embodiment of the present invention.

FIG. 27 is a perspective view showing another configuration example of the DC / DC converter on the electronic circuit board according to the third embodiment of the present invention.

FIG. 28 is a perspective view showing another configuration example of the DC / DC converter on the electronic circuit board according to the third embodiment of the present invention.

FIG. 29 is a side sectional view showing a main part of another configuration example of the DC / DC converter on the electronic circuit board according to the third embodiment of the present invention;

[Explanation of symbols]

10A to 10D DC / DC converter elements, 11a to
11f: external terminal, 12: inductor, 13, 14: capacitor, 15, 16: resistor, 17: ceramic substrate, 30A to 30D: IC (electronic parts for DC / DC converter) 31A to 31E: switching circuit, 32 ... Commutation diode, 33, 33B to 33D: switching control circuit,
34, 35 ... FET, 36 ... FET (current control element),
37 ... Drive circuit, 311, 312, 311A, 312A
... FET (switching semiconductor element), 313, 313
A to 313E: switching control circuit, 331: error amplifier, 3
32, 332B ... triangular wave generating circuit, 333 ... comparator, 334 ... NPN transistor, 335 ... PNP transistor, 336a, 336b ... resistor, 337 ...
Error amplifiers, 338a to 338c: switch circuit, 33
9: set value control circuit, 371: N-channel type FET,
372: resistor, 373: capacitor, 374: diode, 41: differential amplifier, 42: comparator, 43 ...
Reference voltage generation sources, 44, 45 ... gate drive circuit, 46 ...
OR circuit, 47: AND circuit, 48: trapezoidal wave generation circuit,
51, 52, 58, 59: FET (switching semiconductor element), 53: differential amplifier, 54a, 54b: reference voltage generation source, 55a, 55b: comparator, 56a to 56
c: OR circuit, 57: AND circuit, 60: portable telephone, 61: casing, 62: circuit board.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takaya Nakajima 6-16-20 Ueno, Taito-ku, Tokyo Inside Taiyo Denki Co., Ltd. (72) Inventor Yasuo Hosaka 6-16-20 Ueno, Taito-ku, Tokyo Taiyo F Term (in reference) 5H730 AA10 AA14 AS00 AS01 AS05 AS19 BB13 BB57 DD04 DD13 EE13 EE59 FD01 FF02 FF16 FG05 FG07 FG22 FG25 FV05 ZZ05 ZZ11 ZZ12 ZZ17

Claims (59)

[Claims] A first switching semiconductor device and an inductor connected in series between an input terminal and an output terminal, wherein the first switching semiconductor device performs a switching operation to determine a voltage applied to the input terminal. A drive control method for a DC / DC converter for converting the voltage to a voltage of a value, outputting the voltage to the output terminal via the inductance, monitoring the output voltage, and maintaining the output voltage at a set value. An active terminal connected to the active terminal of the first switching semiconductor element in parallel with one or more second switching semiconductor elements, and conducting the switching operation by using the first and second switching semiconductor elements together; A drive control method for a DC / DC converter, characterized by switching between a state and a non-conductive state. 2. A first switching semiconductor device, comprising: a third switching semiconductor device having one active terminal connected to the active terminal on the inductance side of the first switching semiconductor device and the other active terminal grounded. 2. The DC switching device according to claim 1, wherein each of the switching semiconductor devices is switched so that the active terminals of the third switching semiconductor device and the active terminals of the third switching semiconductor device alternately become conductive.
/ DC converter drive control method. 3. The semiconductor device according to claim 1, wherein at least one of said first switching semiconductor element and one or more second switching semiconductor elements is provided.
The switching semiconductor element according to claim 1, wherein a switching semiconductor element having a higher switching speed than other switching semiconductor elements is used as the switching semiconductor elements.
Drive control method for C / DC converter. 4. At least one of the first switching semiconductor element and one or more second switching semiconductor elements.
4. The drive control method for a DC / DC converter according to claim 1, wherein a switching semiconductor element having a lower terminal saturation voltage than other switching semiconductor elements is used as the switching semiconductor elements. . 5. The switching semiconductor device according to claim 3, wherein an active terminal of the switching semiconductor device having a larger conduction capacity than the switching semiconductor device is connected in parallel to the switching semiconductor device having a higher switching speed. A drive control method for a DC / DC converter. 6. When turning on the active terminals of the first and second switching semiconductor elements connected in parallel, the first and second switching semiconductor elements are turned off more than other switching semiconductor elements. 4. The drive control method for a DC / DC converter according to claim 3, wherein one switching semiconductor element having a high switching speed from a state to an ON state is set to an ON state first. 7. When connecting between the active terminals of the first and second switching semiconductor elements connected in parallel, one of the first and second switching semiconductor elements is turned on.
After setting the two switching semiconductor elements to the ON state,
2. The drive control method for a DC / DC converter according to claim 1, wherein when the voltage between terminals of the switching semiconductor element is substantially saturated, another switching semiconductor element is set to an ON state. 8. When the active terminals of the first and second switching semiconductor elements connected in parallel are brought into a conductive state, one of the first and second switching semiconductor elements is turned on.
After setting the two switching semiconductor elements to the ON state,
The switching setting of the second and subsequent switching semiconductor elements from the off state to the on state is performed by changing the voltage between the terminals of the switching semiconductor element that has just been set to the on state between the terminals when the switching semiconductor element is set to the on state. The method according to claim 1, wherein the method is performed when the voltage decreases to a predetermined ratio. 9. When the active terminals of the first and second switching semiconductor elements connected in parallel are brought into a non-conductive state based on the control signal, the first and second switching semiconductor elements are connected in the first and second switching semiconductor elements. 4. The drive control method for a DC / DC converter according to claim 3, wherein a switching semiconductor element having a higher switching speed from an ON state to an OFF state than another switching semiconductor element is finally set to an OFF state. 10. When the active terminals of the first and second switching semiconductor elements connected in parallel are brought into a non-conductive state based on the control signal, the first and second switching semiconductor elements are connected to each other. After setting all the other switching semiconductor elements except one to the off state,
2. The drive control method for a DC / DC converter according to claim 1, wherein two switching semiconductor elements are set to an off state. 11. When the active terminals of the first and second switching semiconductor elements connected in parallel are brought into a conductive state based on the control signal, a terminal is provided in the first and second switching semiconductor elements. When a switching semiconductor element whose inter-saturation voltage shows a lower value than other elements is set to an ON state for the second and subsequent times, and when the active terminals of the first and second switching semiconductor elements are turned off, The DC switching device according to claim 4, wherein the switching semiconductor device having a lower terminal saturation voltage than another device is set to an OFF state before the last one switching semiconductor device.
/ DC converter drive control method. 12. When switching between the non-conductive state and the conductive state between the active terminals of the first and second switching semiconductor elements connected in parallel based on the control signal,
2. The DC / DC converter according to claim 1, further comprising: means for sequentially using different elements as the switching semiconductor element that is first set to the ON state among the first and second switching semiconductor elements. Drive control method. 13. When the active terminals of the first and second switching semiconductor elements connected in parallel are brought into a conductive state based on the control signal, another one of the first and second switching semiconductor elements is used. 2. The drive control method for a DC / DC converter according to claim 1, wherein the switching semiconductor elements having a higher switching speed from an off state to an on state than the switching semiconductor elements are set to an on state in order. 14. An on-state and an off-state are switched by comparing a control current or control voltage level with a threshold level, and different threshold levels are respectively set according to the switching order of the off-state and the on-state. And a control signal whose level changes stepwise or continuously with the passage of time, and the first and second switching semiconductor elements are used as the first and second switching semiconductor elements. 2. The drive control method for a DC / DC converter according to claim 1, wherein each of the first and second switching semiconductor elements is individually switched between an on state and an off state using a difference in threshold level. . 15. The method according to claim 14, wherein a field effect transistor is used as each of the first and second switching semiconductor elements, and a control signal whose voltage level changes with time is used. A drive control method for a DC / DC converter. 16. One or more fourth switching semiconductor elements having an active element connected in parallel to an active terminal of the third switching semiconductor element, and these third and fourth switching semiconductor elements are used in combination. 3. The drive control method for a DC / DC converter according to claim 2, wherein the switching operation switches between a conduction state and a non-conduction state. 17. The semiconductor device according to claim 17, wherein
17. The DC / DC converter according to claim 16, wherein a switching semiconductor element having a higher switching speed than another switching semiconductor element is used as at least one of the four or more fourth switching semiconductor elements. Drive control method. 18. The semiconductor device according to claim 18, wherein
17. A switching semiconductor element having a lower terminal saturation voltage than other switching semiconductor elements as at least one switching semiconductor element among the four or more fourth switching semiconductor elements.
Or a drive control method for a DC / DC converter according to claim 17. 19. The semiconductor device according to claim 19, wherein the third switching semiconductor element and
The plurality of fourth switching semiconductor elements, wherein an active terminal of a switching semiconductor element having a larger conduction capacity than the switching semiconductor element having a higher switching speed is connected in parallel to the switching semiconductor element having a higher switching speed and used together. Item 18. A drive control method for a DC / DC converter according to item 17. 20. When making the active terminals of the third and fourth switching semiconductor elements connected in parallel conductive, the third and fourth switching semiconductor elements are turned off more than the other switching semiconductor elements. 18. The drive control method for a DC / DC converter according to claim 17, wherein one switching semiconductor element having a high switching speed from a state to an ON state is set to an ON state first. 21. When a conduction state is established between the active terminals of the third and fourth switching semiconductor elements connected in parallel, one of the third and fourth switching semiconductor elements is turned on. 21. The method according to claim 16, wherein when the voltage between the terminals of the switching semiconductor element is substantially saturated after the setting, the other switching semiconductor element is set to the ON state.
4. The drive control method for a DC / DC converter according to claim 1. 22. When a conduction state is established between the active terminals of the third and fourth switching semiconductor elements connected in parallel, one of the third and fourth switching semiconductor elements is turned on. After the setting, the switching setting of the second and subsequent switching semiconductor elements from the off state to the on state is set, and the terminal voltage of the switching semiconductor element set to the on state immediately before this sets the switching semiconductor element to the on state. 21. The drive control method for a DC / DC converter according to claim 16 or 20, wherein the method is performed when the voltage between terminals at the time when the voltage falls to a predetermined ratio. 23. An output variable control signal input from outside,
2. The DC / DC according to claim 1, wherein a set value of the output voltage is changed based on the output variable control signal.
Converter drive control method. 24. When the set value based on the output variable control signal is equal to or greater than a predetermined threshold, the output voltage value is maintained at the set value by performing on / off control of the switching semiconductor element using pulse width modulation. When the set value based on the output variable control signal is smaller than a predetermined threshold, the output voltage value is maintained at the set value by performing on / off control of the switching semiconductor element using pulse frequency modulation. 24. D according to claim 23, characterized in that:
Drive control method for C / DC converter. 25. A semiconductor device comprising: a first switching semiconductor element and an inductor connected in series between an input terminal and an output terminal; and a control circuit for performing a switching operation of the first switching semiconductor element. A DC / DC converter that down-converts a voltage to a predetermined value, outputs the voltage to the output terminal via the inductor, monitors the output voltage value, and maintains the output voltage value at a set value; At least one second switching semiconductor element having an active terminal connected in parallel to an active terminal of the switching semiconductor element is provided, and the control circuit switches on / off states of the first and second switching semiconductor elements. A DC / DC converter comprising switching control means for controlling. 26. A third switching semiconductor device, wherein one active terminal is connected to the active terminal on the inductance side of the first switching semiconductor device and the other active terminal is connected to a ground terminal. The circuit includes switching control means for switching each switching semiconductor element so as to alternately conduct between active terminals of the first switching semiconductor element and active terminals of the third switching semiconductor element. The DC / D according to claim 25, wherein
C converter. 27. The first switching semiconductor device and the first switching semiconductor device
26. The switching semiconductor device according to claim 25, wherein at least one switching semiconductor device among the two or more second switching semiconductor devices is a switching semiconductor device having a value whose switching speed is faster than other switching semiconductor devices.
4. The DC / DC converter according to 1. 28. The first switching semiconductor device and the first switching semiconductor device
26. The switching semiconductor device according to claim 25, wherein at least one switching semiconductor device among the two or more second switching semiconductor devices is a switching semiconductor device having a lower terminal saturation voltage than other switching semiconductor devices. A DC / DC converter as described. 29. The first switching semiconductor device and the first switching semiconductor device
26. The DC / DC converter according to claim 25, wherein at least one switching semiconductor element among the two or more second switching semiconductor elements is a switching semiconductor element having a larger conduction capacity than other switching semiconductor elements.
DC converter. 30. The switching control means, when the input and output are brought into a conductive state based on the control signal, another switching among the first switching semiconductor element and one or more second switching semiconductor elements. 26. The DC / DC converter according to claim 25, further comprising: means for first setting a switching semiconductor element having an on-state switching speed higher than that of the switching semiconductor element to an on-state.
DC converter. 31. The switching control means according to claim 27, wherein said switching control means sets a conduction state between said active terminals of said first and second switching semiconductor elements connected in parallel based on said control signal.
After one of the first and second switching semiconductor elements is set to the ON state, the other switching semiconductor element is set to the ON state when the voltage between the terminals of the switching semiconductor element is substantially saturated. 26. The method of claim 25, further comprising the step of:
C / DC converter. 32. The switching control means, when the conduction between the active terminals of the first and second switching semiconductor elements connected in parallel based on the control signal,
After setting one of the first and second switching semiconductor elements to the ON state, the switching setting of the second and subsequent switching semiconductor elements from the OFF state to the ON state is performed immediately before the ON state. 26. The apparatus according to claim 25, further comprising means for performing when the voltage between the terminals of the switching semiconductor element set in the step (c) decreases to a predetermined ratio of the voltage between the terminals when the switching semiconductor element is set to the ON state. DC / DC converter. 33. The switching control means, wherein when the active terminals of the first and second switching semiconductor elements connected in parallel are turned off based on the control signal, the first and second switching semiconductor elements are turned off. 28. The semiconductor device according to claim 27, further comprising: a switching semiconductor element having a higher switching speed from an on-state to an off-state than other switching semiconductor elements among the switching semiconductor elements. DC / DC converter. 34. The switching control means, when the non-conductive state is established between the active terminals of the first and second switching semiconductor elements connected in parallel based on the control signal, the first and second switching semiconductor elements. Means for setting the last one switching semiconductor element to an off state after setting all the other switching semiconductor elements except one of the switching semiconductor elements to an off state. 26. The DC / DC converter according to 25. 35. The switching control means according to claim 27, wherein said switching control means sets a conduction state between said active terminals of said first and second switching semiconductor elements connected in parallel based on said control signal.
Means for setting a switching semiconductor element having a lower inter-terminal saturation voltage than the other switching elements in the first and second switching semiconductor elements to a second and subsequent ON states; and the first and second switching semiconductor elements. A switching semiconductor element whose terminal saturation voltage shows a lower value than other elements when the active terminals of the semiconductor element are brought into a non-conductive state is set to an off state before the last one switching semiconductor element. 29. The DC / DC converter according to claim 28, further comprising: 36. The switching control means, when switching from the non-conductive state to the conductive state between the active terminals of the first and second switching semiconductor elements connected in parallel based on the control signal, performs the first control. 26. The DC / DC according to claim 25, further comprising: means for sequentially using different elements as the switching semiconductor element that is first turned on among the second switching semiconductor elements.
converter. 37. The switching control means, when the conduction between the active terminals of the first and second switching semiconductor elements connected in parallel based on the control signal,
The semiconductor device further comprises means for setting the switching semiconductor element, which has a higher switching speed from the OFF state to the ON state than the other switching semiconductor elements among the first and second switching semiconductor elements, to the ON state in order. A DC / DC converter according to claim 25. 38. Each of the first and second switching semiconductor elements connected in parallel switches between an on state and an off state by comparing a control current or control voltage level with a threshold level, and switches between the off state and the on state. Different threshold levels are set in accordance with the switching order of the states, and the switching control means includes a first threshold having a plurality of threshold levels.
And outputting, to the first and second switching semiconductor elements, the control current or control voltage having a waveform capable of individually switching the on / off state of the second switching semiconductor element by using the difference in the threshold level. 26. The DC / DC converter according to claim 25, wherein: 39. Each of the first and second switching semiconductor elements connected in parallel is a field effect transistor, and the switching control means has a first threshold having a plurality of thresholds at a gate terminal of the field effect transistor. And switching the conductive state and the non-conductive state between the input and output by inputting a control voltage having a waveform capable of individually switching the ON state and the OFF state to the second switching semiconductor element by utilizing the difference in the threshold value. 39. The DC / DC converter according to claim 38. 40. One or more fourth switching semiconductor elements having an active element connected in parallel to an active terminal of the third switching semiconductor element, and the control circuit is configured to control the third and fourth switching semiconductor elements. 27. The DC / DC converter according to claim 26, further comprising means for switching between a conducting state and a non-conducting state of the switching operation by using an element. 41. The third switching semiconductor device and the third switching semiconductor device
41. The switching semiconductor device according to claim 40, wherein at least one of the four or more fourth switching semiconductor devices is a switching semiconductor device exhibiting a value whose switching speed is faster than the other switching semiconductor devices.
4. The DC / DC converter according to 1. 42. The third switching semiconductor device and the third switching semiconductor device
41. The switching semiconductor device according to claim 40, wherein at least one of the four or more fourth switching semiconductor devices is a switching semiconductor device having a lower terminal saturation voltage than other switching semiconductor devices. A DC / DC converter as described. 43. The third switching semiconductor element and the third switching semiconductor element
41. The DC / DC converter according to claim 40, wherein at least one switching semiconductor element of the four or more fourth switching semiconductor elements is a switching semiconductor element having a larger conduction capacity than the other switching semiconductor elements.
DC converter. 44. The switching control means, when making the input and output conductive based on the control signal, switches between the third switching semiconductor element and one or more fourth switching semiconductor elements. 41. The DC / DC converter according to claim 40, further comprising means for first setting a switching semiconductor element having an on-state switching speed higher than that of the switching semiconductor element to an on-state.
DC converter. 45. The switching control unit according to claim 37, wherein the switching control unit sets a conduction state between the active terminals of the third and fourth switching semiconductor elements connected in parallel based on the control signal.
After one of the third and fourth switching semiconductor elements is set to the ON state, the other switching semiconductor element is set to the ON state when the voltage between the terminals of the switching semiconductor element is substantially saturated. 41. The method of claim 40, further comprising the step of:
C / DC converter. 46. The switching control means according to claim 27, wherein said switching control means is configured to establish a conduction state between said active terminals of said third and fourth switching semiconductor elements connected in parallel based on said control signal.
After setting one of the third and fourth switching semiconductor elements to the ON state, the switching setting of the second and subsequent switching semiconductor elements from the OFF state to the ON state is performed immediately before the ON state. 41. The apparatus according to claim 40, further comprising means for performing the operation when the voltage between the terminals of the switching semiconductor element set in the step (c) is reduced to a predetermined ratio of the terminal voltage when the switching semiconductor element is set to the ON state. DC / DC converter. 47. The switching control means, wherein the third and fourth switching semiconductor elements are connected to each other in a non-conductive state based on the control signal between the active terminals of the third and fourth switching semiconductor elements. 43. The switching device according to claim 41, further comprising: a switching semiconductor element having a higher switching speed from an on state to an off state than other switching semiconductor elements among the switching semiconductor elements, and finally setting the switching semiconductor element to an off state. A DC / DC converter as described. 48. The switching control means, when the non-conductive state is established between the active terminals of the third and fourth switching semiconductor elements connected in parallel based on the control signal, the third and fourth switching semiconductor elements. Means for setting the last one switching semiconductor element to an off state after setting all the other switching semiconductor elements except one of the switching semiconductor elements to an off state. 40. The DC / DC converter according to 40. 49. The switching control means, when the conduction between the active terminals of the third and fourth switching semiconductor elements connected in parallel based on the control signal,
Means for setting the second and subsequent switching semiconductor elements having a lower inter-terminal saturation voltage than the other switching elements in the third and fourth switching semiconductor elements to the ON state, and the third and fourth switching elements A switching semiconductor element whose terminal saturation voltage shows a lower value than other elements when the active terminals of the semiconductor element are brought into a non-conductive state is set to an off state before the last one switching semiconductor element. 43. The DC / DC converter according to claim 42, further comprising: 50. The switching control means, when switching from the non-conductive state to the conductive state based on the control signal, between the active terminals of the third and fourth switching semiconductor elements connected in parallel, 41. The DC / DC according to claim 40, further comprising: means for sequentially using different elements as the switching semiconductor element that is set to the on state first among the fourth switching semiconductor elements.
converter. 51. The switching control means, when the conduction between the active terminals of the third and fourth switching semiconductor elements connected in parallel based on the control signal,
The semiconductor device further comprises means for setting the switching semiconductor element, which has a higher switching speed from the off state to the on state than the other switching semiconductor elements in the third and fourth switching semiconductor elements, to the on state in order. The DC / DC converter according to claim 40. 52. Each of the third and fourth switching semiconductor elements connected in parallel switches between an on state and an off state by comparing a control current or control voltage level with a threshold level, and switches between the off state and the on state. Different threshold levels are set in accordance with the switching order of the states, and the switching control means includes a third threshold level having a plurality of threshold levels.
And outputting, to the first and second switching semiconductor elements, the control current or the control voltage having a waveform capable of individually switching an on state and an off state using the difference in the threshold level. 41. The DC / DC converter according to claim 40, wherein: 53. Each of the third and fourth switching semiconductor elements connected in parallel is a field effect transistor, and the switching control means has a third terminal having a plurality of thresholds at a gate terminal of the field effect transistor. And switching a conductive state and a non-conductive state between the input and output by inputting a control voltage having a waveform capable of individually switching an ON state and an OFF state using the difference between the threshold values and the fourth switching semiconductor element. 53. The DC / DC converter according to claim 52. 54. The DC / DC converter according to claim 25, wherein the inductor is a multilayer inductor. 55. The control circuit according to claim 25, wherein the control circuit comprises a semiconductor integrated circuit housed in a package.
4. The DC / DC converter according to 1. 56. A wiring board, wherein the inductor is mounted on one surface of the wiring board, and the control circuit and other circuits and external connection terminals are formed on the other surface. 26. The DC / DC converter according to 25. 57. The DC according to claim 56, wherein the external connection terminal has a height dimension larger than electronic components constituting the control circuit and other circuits.
/ DC converter. 58. An output variable control signal input from outside,
26. The DC / DC converter according to claim 25, further comprising: a set value changing unit that changes a set value of the output voltage based on the output variable control signal. 59. The switching control means, wherein when the set value based on the output variable control signal is equal to or greater than a predetermined threshold, performs on / off control of the switching semiconductor element using pulse width modulation, and controls the output variable control. 59. The device according to claim 58, further comprising means for performing on / off control of the switching semiconductor element using pulse frequency modulation when a set value based on the signal is smaller than a predetermined threshold value.
C / DC converter.