JP2002064103A - Method of manufacturing semiconductor element and semiconductor element obtained thereby - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor element by which the concentration of an n-type carrier can be increased easily and, in addition, the conductivity of the carrier can be changed and the characteristics of a semiconductor element can be improved according to the kind of the element, and to provide a semiconductor element obtained by the manufacturing method. SOLUTION: A buffer layer 11, n-type contact layer 12, n-type clad layer 13, n-type optical waveguide layer 14, active layer 15, p-type optical waveguide layer 16, p-type clad layer 17, and p-type contact layer 18 are successively laminated upon a substrate 10, and the layers 13, 14, 15, 16, 17, and 18 above the n-type contact layer 12 are patterned in a stripe-like shape. Then RIE is performed on the surface of the n-type contact layer 12 and p-type contact layer 18 by using a chlorine gas. Near the surface of the contact layer 12, the n-type carrier increases and an n+ region 12a is formed. Near the surface of the contact layer 18, similarly, the n-type carrier increases and the conductivity of the layer 18 changes to i- or n-type, resulting in the formation of a current constricting region 18a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical device such as a semiconductor laser and a phototransistor, and an FET.
(Field Effect Transistor)
The present invention relates to a method for manufacturing a semiconductor device typified by a semiconductor electronic device such as a semiconductor device and a semiconductor device obtained by the method, and more particularly to a method for manufacturing a semiconductor device using a nitride compound semiconductor.

[0002]

2. Description of the Related Art In so-called semiconductor devices such as semiconductor lasers and FETs, plasma CVD (Chemical Vapor
It is common to modify the surface of the semiconductor layer using techniques such as Deposition (chemical vapor deposition), ion implantation, and diffusion to partially add new properties or improve properties. . Such a method itself can be applied regardless of the material of the semiconductor.
For example, it can be handled in substantially the same manner as a III-V semiconductor such as a GaAs or InP semiconductor, or a II-VI semiconductor such as a ZnSe or CdTe semiconductor.

However, the material properties of nitride-based compound semiconductors are often unique. That is, p-type conductivity is not easily obtained, and wet etching cannot be easily performed due to extremely high chemical resistance. Note that a typical II
GaN, which is a Group I nitride-based compound semiconductor, is still difficult to manufacture as a high-quality bulk substrate.
A sapphire substrate is used for forming a system semiconductor element.

However, since the sapphire substrate has a high resistance, conventional GaN-based semiconductor elements cannot form electrodes on the lower surface of the substrate, and both the p-side electrode and the n-side electrode are formed on the upper surface side of the substrate. Have been. Therefore, etching is usually performed so that the p-type contact layer provided with the p-side electrode is exposed on the element surface. The etching at this time is not wet etching but dry etching for the above-mentioned reason. Specifically, RIE (Reactive I
Sputter etching such as on-etching (reactive ion etching) is common. In this method, reactive species contained in the etching gas are dissociated into active radicals and ions, and the etching proceeds due to these chemical reactions and collision with the substrate.

[0005]

A semiconductor device using such a nitride compound can be designed as an optical device in a wide wavelength range from ultraviolet to infrared, and as an electronic device, this material can be used. Because of its large band gap, high saturation drift speed, and large electrostatic breakdown electric field, it excels in high-temperature operation, high-speed switching, high-power operation, etc., and is expected to be used in various applications. However, a semiconductor device using a nitride compound such as a semiconductor laser is required to have further improved characteristics, and a new method for that is required.

The present invention has been made in view of such a problem, and an object of the present invention is to increase the concentration of n-type carriers and change the conductivity type by a simple method. It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of improving characteristics according to the requirement, and a semiconductor device obtained by the method.

[0007]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming at least one surface of one or more semiconductor layers made of a nitride-based compound semiconductor after forming a layer. Exposing the portion to a gas atmosphere containing chlorine to increase the conduction electrons at the portion.

In the semiconductor device according to the present invention, chlorine is introduced into at least a part of the vicinity of the surface of a specific layer among one or two or more semiconductor layers made of a nitride-based compound semiconductor. The conduction electrons are increasing.

In the method for manufacturing a semiconductor device according to the present invention,
By exposing the surface of a specific layer to a gas atmosphere containing chlorine, dry etching proceeds, and chlorine is introduced near the surface to increase conduction electrons (n-type carriers).

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.
1 shows a configuration of a gain-guided GaN-based semiconductor laser according to the embodiment. This GaN-based semiconductor laser includes, for example, a buffer layer 11 made of, for example, GaN, an n-type contact layer 12 made of, for example, n-type GaN, for example, n-type AlGaN doped with Si as an impurity, on a substrate 10 made of c-plane sapphire. N-type cladding layer 13
For example, an n-type optical waveguide layer 14 made of n-type GaN, for example, G
an active layer 15 having a multiple quantum well structure composed of a _1-x In _x N (well layer) and Ga _1-y In _y N (barrier layer);
For example, a p-type optical waveguide layer 16 made of p-type GaN doped with magnesium (Mg) as a p-type impurity, a p-type clad layer 17 made of p-type AlGaN doped with Mg as an impurity, and Mg added as an impurity, for example It has a configuration in which p-type contact layers 18 made of p-type GaN are stacked. On the p-type contact layer 18, a p-side electrode 20 is provided. A portion of the n-type contact layer 12 and a portion above the n-type contact layer 12 have a stripe shape extending at a constant width in a direction perpendicular to the paper surface.
N ⁺ region 12a is formed on the surface of
A side electrode 21 is provided. The n-side electrode 21 and the p-side electrode 20 are parallel to the stripe structure.

On the surface of the p-type contact layer 18, current confinement regions 18a are provided on both sides in the width direction, and a silicon nitride (SiN _x ) layer 19 is formed on the current confinement region 18a.
Are formed. As described later, the current confinement region 18a is a region of the p-type contact layer 18 made of p-type GaN in which chlorine (Cl) is introduced and the resistance is remarkably increased, or shows n-type conductivity.

Next, a method of manufacturing the semiconductor laser will be described with reference to FIGS.

First, as shown in FIG. 2, a substrate 10 made of, for example, c-plane sapphire is prepared, and, for example, MOCVD (Metal Organic Chemical Vapor
Deposition 550 by metal organic chemical vapor deposition)
The buffer layer 11 made of GaN is formed at a low temperature of about
m. Thereafter, epitaxial growth is performed on the buffer layer 11 sequentially by using, for example, the MOCVD method. For example, an n-type contact layer 12 made of n-type GaN to which silicon (Si) is added as an n-type impurity is formed in 3.
N having a thickness of 0 μm and adding Si as an impurity
N-type clad layer 13 of 0.5 μm
, And an n-type optical waveguide layer 14 of n-type GaN is formed to a thickness of 0.1 μm. Subsequently, for example, Ga _{1- x} In _x N (well layer) and Ga _1-y In _y N
Active layer 1 having multiple quantum well structure composed of (barrier layer)
5 is formed to a thickness of 40 nm. Next, for example, p-type GaN doped with magnesium (Mg) as a p-type impurity
The p-type optical waveguide layer 16 is formed to a thickness of 0.1 μm, the p-type cladding layer 17 made of p-type AlGaN to which Mg is added as an impurity is formed to a thickness of 0.5 μm. P composed of added p-type GaN
The mold contact layer 18 is formed to a thickness of 0.5 μm. The active layer 15 is about 800 ° C., and the other layers are 100 ° C.
It is grown at a temperature of about 0 ° C.

At this time, for example, trimethylaluminum gas ((CH
_{3) 3} Al), as a source gas of gallium (raw material as the gas trimethylgallium gas _{Ga) ((CH 3) 3} Ga) or triethyl gallium gas _{((C 2 H 5) 3} Ga), indium (In) Trimethyl indium gas ((CH ₃ ) ₃ In), ammonia (NH ₃ ) as a source gas for nitrogen (N), monosilane gas (SiH ₄ ) as a source gas for silicon, and bis = methylcyclo as a source gas for magnesium Pentadienyl magnesium gas (MeCp ₂ Mg) or bis cyclopentadienyl magnesium gas (Cp ₂ Mg) is used.

Next, as shown in FIG. 3, a stripe-shaped resist pattern 22 is formed on the upper surface of the p-type contact layer 18 by lithography. Further, anisotropic etching is performed using the resist pattern 22 as a mask until the n-type contact layer 12 is exposed, for example, by RIE, thereby forming an upper layer of the n-type contact layer 12, ie, the n-type cladding layer 13, the n-type photoconductive layer. Wave layer 14, active layer 1
5. The p-type optical waveguide layer 16, the p-type cladding layer 17, and the p-type contact layer 18 are patterned in a stripe shape.

Next, as shown in FIG.
The resist pattern 22 is removed except for the portion where is located. Next, chlorine is introduced selectively into the p-type contact layer 18 to increase the n-type carrier concentration using the remaining resist pattern 22 as a mask. Therefore, in this embodiment, RIE using chlorine (Cl ₂ ) as an etching gas is used. That is, etching is performed again.

[0018] In this case, the radical active group Cl ^* and chlorine ions Cl ^- but etching proceeds by the chemical reactions and the like, at the same time, high Cl atoms of these reactive enters in the depth direction from the surface to be etched. At this time, the present inventors have found that the conductivity type tends to change to n in a region where Cl atoms are present.
That is, the p-type becomes i-type and further inverted to n-type, and the n-type becomes n ⁺ . This is because electrons or charges are supplied by Cl atoms entering the vicinity of the surface, and as a result, the n-type carrier concentration increases in the region where Cl atoms exist. Therefore, the etching is performed here for the purpose of controlling the n-type carrier concentration without the purpose of processing the element. Incidentally, RIE using a chlorine-based gas is well known as an etching method, but until now only the etching effect has been studied, and chlorine residues may affect the characteristics of the etched semiconductor layer. Rather, it was expected to be sufficiently removed.

As a method for introducing an impurity into the surface of the semiconductor layer, ion implantation or diffusion is generally used.
In these diffusions, in particular, the impurity diffuses from the surface to the inside and spreads also in the layer surface direction, so that it is difficult to control such that the impurity oozes out of the target region or the impurity concentration is generated from the surface toward the boundary of the impurity region. . On the other hand, RIE is anisotropic etching, and etching can be performed only in a target direction, so that impurities can be introduced only into a target region with good controllability. In particular, in the case where impurities are introduced only near the surface of the semiconductor layer, it is difficult to control by the above-described diffusion method or the like. However, according to RIE, chlorine atoms as impurities are introduced at a high concentration only in a limited region. There is an advantage that can be.

Here, the n-type contact layer 12 and the p-type
RIE using Cl ₂ gas is performed on the surface of the mold contact layer 18. The reaction conditions at this time are appropriately selected in consideration of the etching depth together with the amount and depth of introduction of chlorine, the gas flow rate is within a range of, for example, 2 to 30 cc / min, and the reaction time is, for example, 1 to 5 minutes. Each is set within the range. As a result, in the vicinity of the surface of the n-type contact layer 12, n-type carriers increase at an appropriate depth of, for example, about 0.1 to 0.2 μm to become n ⁺ , and the n ⁺ region 12
a is formed. Similarly, near the surface of the p-type contact layer 18, the n-type carriers increase at an appropriate depth. As a result, the conduction type of this portion changes to i-type or n-type, and the current confinement region 18a is formed.

Next, as shown in FIG.
The iN _x layer 19 is formed, for example, by CVD (Chemical Vapor Depos).
ition; chemical vapor deposition) method, vacuum evaporation method, sputtering method and the like. Then, resist pattern 2
2 is removed by etching.

Next, as shown in FIG. 1, a resist pattern (not shown) having a predetermined shape is formed on the substrate surface by, for example, lithography. Using this resist pattern as a mask, for example, a Ti film, A
Thereafter, the resist pattern is removed together with the Ti film and the Al film thereon (lift-off). Thereby, the n-side electrode 21 is located at a predetermined position on the n ⁺ region 12a.
Is formed. Similarly, a p-side electrode 20 made of a Ni film and an Au film is formed at a predetermined position on the p-type contact layer 18.

Finally, the substrate 10 has a predetermined width perpendicular to the length direction of the stripe (resonator length direction) and is formed by cleavage or dry etching to form opposing resonator end faces, thereby forming a gain waveguide type. Is completed. Note that a coating for controlling the reflectance may be applied to the cleavage plane as needed.

In the GaN-based semiconductor laser manufactured as described above, when a predetermined voltage is applied between the p-side electrode 20 and the n-side electrode 21, a current is injected into the active layer 15. As a result, in the active layer 15, light emission due to electron-hole recombination occurs, and light is extracted to the outside via a not-shown reflecting mirror. Here, since the current confinement regions 18 a provided on both sides of the p-side electrode 20 are i-type or n-type, the electric resistance is increased with respect to the p-type contact layer 18. Accordingly, the current is constricted in this portion, and carrier confinement is achieved only in a part of the active layer 15. Therefore, the horizontal and lateral modes can be controlled, and the semiconductor laser stably oscillates in a single mode.

In the present embodiment, in the GaN-based semiconductor laser, the current confinement region 18a is selectively formed by introducing chlorine into the vicinity of the surface of both ends of the p-type contact layer 18, so that the accuracy is high. A current confinement structure is formed,
The threshold current and operating current of the laser can be reduced, and the transverse mode can be controlled.

Further, in the present embodiment, chlorine is selectively introduced near the surface of n-type contact layer 12 to form n ⁺ region 12a having an increased number of n-type conduction carriers. The contact property between the contact layer 21 and the n-type contact layer 12 is improved, and the contact resistance and the parasitic capacitance are reduced.

Further, in this embodiment, the step of selectively introducing chlorine near the surfaces of the p-type contact layer 18 and the n-type contact layer 12 is performed by RIE using chlorine as an etching gas. Current confinement region 18a
Alternatively, the n ⁺ region 12a can be manufactured with high accuracy by a simple and controllable process. Further, an existing apparatus for RIE may be used as the apparatus, and a simple manufacturing method can be provided.

[Second Embodiment] FIG. 6 shows a second embodiment of the present invention.
1 shows a configuration of a GaN-based heterojunction phototransistor according to the embodiment. This phototransistor has a buffer layer 31 made of, for example, AlN, for example, n ⁺ on a substrate 30 made of, for example, c-plane sapphire.
A first n ⁺ -type layer 32 of n-type AlGaN, for example, an n-type layer 33 of n-type AlGaN, for example, a p-type layer 34 of p-type GaN, and a second n ⁺ -type layer 35 of n ⁺ -type GaN. It has a laminated structure. First n ⁺ -type layer 32
Are formed in a stripe shape extending in a direction perpendicular to the paper surface.

A high-concentration n ⁺ -type layer 32 a is provided in the surface region of the first n ⁺ -type layer 32, and a high-concentration n ⁺ -type layer 35 a is provided in the surface region of the second n ⁺ -type layer 35. . On the second n ⁺ -type layer 35 and the electrode 36 is provided, electrodes 37 and 38 on both sides of the stripe first respective n ⁺
It is provided on the mold layer 32. These electrodes 36, 3
7, 38 have a shape parallel to the stripe structure.

Next, a method of manufacturing the phototransistor will be described with reference to FIGS.

As shown in FIG. 7, a buffer layer 11 made of AlN is formed on a substrate 30 made of, for example, c-plane sapphire at a low temperature of about 550.degree.
Grow. The buffer layer 11 as nuclei, for example, also at a temperature of about 1000 ° C. by MOCVD, the following, for example, a first n consisting of n ⁺ -type AlGaN
⁺ -Type layer 32, n-type layer 33 of n-type AlGaN, p-type layer 34 of p-type GaN, second layer of n ⁺ -type GaN
The n ⁺ -type layer 35, are sequentially epitaxially grown.

Next, as shown in FIG. 8, a resist pattern 39 having a stripe shape is formed on the upper surface of the second n ⁺ -type layer 35 by lithography, and the resist pattern 39 is used as a mask to form a resist pattern by, for example, RIE. 1 n ⁺
The anisotropic etching is performed until the mold layer 32 is exposed. Thereby, the upper layer portion of the first n ⁺ -type layer 32, that is, the n-type layer 33, the p-type layer 34, and the second n ⁺ -type layer 35 are patterned in a stripe shape.

Next, as shown in FIG. 6, the resist pattern 39 is removed, and RIE using an etching gas of chlorine (Cl ₂ ) is performed as in the first embodiment. Thus, a high-concentration n ⁺ -type layer 32a is formed near the surface of the first n ⁺ -type layer 32, and a high-concentration n ⁺ -type layer 35a is formed near the surface of the second n ⁺ -type layer 35. Subsequently, the electrodes 36, 37, 38 are formed by, for example, a vacuum evaporation method or a sputtering method.

When the phototransistor thus manufactured is irradiated with light from the substrate 30 side as indicated by an arrow in FIG. 6, the carriers excited by the light in the n-type layer 33 and the p-type layer 34. Is generated. Carriers are pairs of holes and conduction electrons, and the internal electric field at the pn junction separates holes into the p-type layer 34 and electrons into the n-type layer 33 to generate electromotive force. By connecting the electrode 36 and the electrodes 37 to 38 to an external load, an amplified current is obtained. Here, the high-concentration n ⁺ -type layers 32a, 32
Since the contact holes 5a are provided, the contact characteristics are good, and the current is efficiently extracted from the electrodes 36 to 38.

In the phototransistor according to the present embodiment, both ends of the first n ⁺ -type layer 32 and the second n ^{+
Since the} high-concentration n ⁺ -type layers 32a and 35a are selectively formed by introducing chlorine near the surface of each ⁺ -type layer 35, the electrodes 36, 37 and 38 and the n ⁺ -type layers 32 and 35 Is improved, and contact resistance and parasitic capacitance are reduced. By the way, the dark current in the phototransistor lowers the sensitivity of the device, and the occurrence thereof is greatly influenced by the crystal defect density, surface leakage current, and the like. Therefore, such dark current density can be reduced with the improvement of the contact property.

Also in this embodiment, as in the first embodiment, chlorine is introduced into both ends of the first n ⁺ -type layer 32 and near the surface of each of the second n ⁺ -type layers 35. This step is performed by RIE using chlorine as an etching gas, so that the high-concentration n ⁺ -type layers 32a and 35a can be manufactured accurately by a simple and controllable process. Further, an existing apparatus for RIE may be used as the apparatus, and a simple manufacturing method can be provided.

[Third Embodiment] FIG. 9 shows a third embodiment of the present invention.
GaN-based Schottky field effect transistor (MESFET; Metal-Semiconduc
tor Field Effect Transistor).
In this MESFET, a buffer layer 4 made of, for example, GaN is formed on a substrate 40 made of, for example, c-plane sapphire.
1, for example, a semi-insulating layer 42 of i-type GaN, for example, n
N-type layers 43 of n-type GaN are sequentially stacked,
An n ⁺ -type layer 43a is provided in the vicinity of the surface of 3. n
^{On the +} type layer 43a, the source electrode 44, the gate electrode 4
5 and a drain electrode 46 are provided.

Next, a method of manufacturing the MESFET will be described with reference to FIG.

A substrate 40 made of, for example, c-plane sapphire
A buffer layer 41 made of GaN is grown at a low temperature of about 550 ° C. by MOCVD, for example. Next, using the buffer layer 41 as a nucleus, for example,
OCVD method at a temperature of about 1000 ° C.
Forming a semi-insulating layer 42 with a thickness of 3 μm using the type GaN,
Subsequently, an n-type layer 43 is formed with a thickness of 250 nm using n-type GaN.

Next, RIE using chlorine (Cl ₂ ) as an etching gas is performed in the same manner as in the first embodiment. The etching conditions at this time are selected such that the surface of the n-type layer 43 is etched at a depth of, for example, 0.1 μm. Thereby, the n ⁺ -type layer 43a is provided near the surface of the n-type layer 43.
Is formed. Subsequently, a source electrode 44, a gate electrode 45, and a drain electrode 46 are formed by, for example, a vacuum evaporation method or a sputtering method.

In the MESFET fabricated in this manner, an n ⁺ -type layer 43 a having high shape accuracy is obtained, and the n ⁺ -type layer 43 is interposed between the n ⁺ -type layer 43 and each of the electrodes 44 to 46. The contact property between them is improved. Further, with the improvement of the contact properties, the main characteristics of the MESFET, such as the transconductance, the current cutoff frequency, and the maximum oscillation frequency, are improved. Further, since the step of forming the n ⁺ -type layer 43 is performed by RIE using chlorine as an etching gas, the n ⁺ -type layer 43 can be manufactured accurately by a simple and controllable process.

Fourth Embodiment FIG. 10 shows a GaN-based junction FET (JFE) according to a fourth embodiment of the present invention.
T). In this JFET, for example, Ga is placed on a substrate 50 made of, for example, c-plane sapphire.
A p-type layer 52 made of, for example, p-type GaN is formed via a buffer layer 51 made of N. In the center of the surface of the p-type layer 52, an n-type layer 5 made of, for example, GaN
2a, and a gate electrode 54 is provided on the n-type layer 52a. A source electrode 53 and a drain electrode 55 are provided on the p-type layer 52 exposed on both sides of the n-type layer 52a.

Next, a method of manufacturing this JFET will be described with reference to FIG.

First, a buffer layer 51 made of GaN is grown on a substrate 50 made of, for example, c-plane sapphire at a low temperature of about 550 ° C. by MOCVD, for example. Next, on this buffer layer 51, for example,
A p-type layer 52 made of p-type GaN is formed at a temperature of about 1000 ° C. by a VD method.

Next, a resist pattern (not shown) having an opening corresponding to the position where the n-type layer 52a is to be formed is formed by lithography. Subsequently, similarly to the first embodiment, RI using an etching gas of chlorine (Cl ₂ ) is used.
Perform E. The p-type layer 52 is etched using the resist pattern as a mask, and the conductivity type near the surface changes from p-type to n-type. Thus, an n-type layer 52a is formed near the surface of the p-type layer 52. After removing the resist pattern, a source electrode 53, a gate electrode 54 and a drain electrode 55 are formed by, for example, a vacuum evaporation method or a sputtering method.

In the JFET manufactured as described above,
An n-type layer 52a having a highly accurate shape is obtained. Also,
Since the n-type layer 52a and the gate electrode 54 have excellent contact properties, the JFET
The main characteristics such as mutual conductance, current cutoff frequency, and maximum oscillation frequency are improved. Furthermore, since the step of forming the n-type layer 52a is performed by RIE using chlorine as an etching gas, the n-type layer 52a can be manufactured accurately by a simple and controllable process.

[Fifth Embodiment] FIG. 11 shows a nipi structure according to a fifth embodiment of the present invention. Such a nipi structure can be applied as an electronic element or a light receiving element or a light emitting element. This n
The ipi structure has a substrate 6 made of, for example, c-plane sapphire.
0, a p-type layer 62 made of p-type GaN is formed via a buffer layer 61 made of GaN.
Has a structure in which an n-type layer 62a is provided near the surface and an i-type layer 62b is provided in a boundary region between the p-type layer 62 and the n-type layer 62a. That is, when viewed from above, the n-type layer 62
The a, i-type layer 62b, the p-type layer 62, and the i-type layer 62b are arranged in stripes in this order.

This nipi structure can be manufactured as follows. That is, 550 ° C. is deposited on the c-plane sapphire substrate 60 by MOCVD, for example.
The buffer layer 61 made of GaN is grown at a low temperature. Next, on this buffer layer 61, for example, the p-type G
A p-type layer 62 made of aN is formed.

Next, a resist pattern (not shown) having an opening corresponding to a region where the n-type layer 62a is to be formed is formed by lithography. Subsequently, similarly to the first embodiment, the etching gas is changed to chlorine (Cl ₂ ).
RIE is performed. The p-type layer 62 is etched using the resist pattern as a mask, and the conductivity type near the surface changes from p-type to n-type. At this time, the vicinity of the boundary between the p-type region and the n-type region becomes the high-resistance i-type. Thereby, the n-type layer 62a and the i-type layer 6 are located near the surface of the p-type layer 62.
2b is formed. After that, by removing the resist pattern and forming an arbitrary electrode, it can be processed as an electronic element, a light receiving element, a light emitting element, or the like.

Also in the present embodiment, the step of forming the n-type layer 62a and the i-type layer 62b is performed by RIE using chlorine as an etching gas. Can be made.

Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and can be variously modified. For example, although a sapphire substrate is used in the above embodiment, any substrate may be used, and a GaN substrate, a SiC substrate, a ZnO substrate, a spinel substrate, or the like can be used as necessary. When a conductive material such as a GaN substrate or a SiC substrate is used, an electrode can be formed on the substrate.

In the above embodiment, the case where the present invention is applied to a GaN-based optical element and an electronic element has been described. However, the present invention relates to a nitride semiconductor mixed crystal containing aluminum (Al), indium (In), or the like. It is also possible to apply to an element constituted by another compound semiconductor. However, when applied to a GaN-based semiconductor, it is extremely effective as compared with other systems. That is,
In the present invention, the RIE technique using chlorine gas is used as a specific method for introducing chlorine. However, originally, this etching has high reactivity especially in a GaN-based semiconductor. Also, unlike other semiconductors, GaN-based semiconductors are difficult to perform wet etching, and RIE is used exclusively for etching, so that the same apparatus can be used to simplify the process,
This is because operational convenience can be achieved.

It is needless to say that the present invention can be applied to optical elements and electronic elements other than the optical elements and electronic elements specifically exemplified in the above embodiment. Further, when chlorine is introduced into the p-type semiconductor, the conduction type does not need to change from p-type to complete i-type or n-type, and is introduced to such an extent that the intended electrical characteristics can be obtained within the intended region. do it.

[0054]

As described above, according to the method for manufacturing a semiconductor device of the present invention, at least a part of the surface of a specific layer of a semiconductor layer made of a nitride-based compound semiconductor is formed after the layer is formed. By exposing it to a gas atmosphere containing chlorine, the number of conduction electrons at that site is increased, so that a region with a high concentration of n-type carriers compared to the base semiconductor layer can be easily and easily controlled. It can be manufactured with high accuracy. In addition, since an existing apparatus for RIE can be used as the apparatus, a simple manufacturing method can be used.
It is also possible to simplify the process.

Further, according to the semiconductor device of the present invention, since the semiconductor device is manufactured by applying the manufacturing method of the present invention, it is possible to improve device characteristics and solve problems related to the periphery of the electrode such as contact resistance and parasitic capacitance. Will be able to

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor laser according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor laser shown in FIG.

FIG. 3 is a cross-sectional view for explaining a step following the step shown in FIG. 2;

FIG. 4 is a cross-sectional view for explaining a step following the step shown in FIG. 3;

FIG. 5 is a cross-sectional view for explaining a step following the step shown in FIG. 4;

FIG. 6 is a cross-sectional view illustrating a configuration of a phototransistor according to a second embodiment of the present invention.

7 is a cross-sectional view for explaining a manufacturing process of the phototransistor shown in FIG.

FIG. 8 is a cross-sectional view for explaining a step following the step shown in FIG. 7;

FIG. 9 shows a MESFET according to a third embodiment of the present invention.
It is sectional drawing showing the structure of.

FIG. 10 is a sectional view illustrating a configuration of a JFET according to a fourth embodiment of the present invention.

11A and 11B are diagrams illustrating a nipi structure according to a fifth embodiment of the present invention, wherein FIG. 11A is a plan view and FIG. 11B is a cross-sectional view.

[Explanation of symbols]

10 ... substrate, 11 ... buffer layer, 12 ... n-type contact layer, 12a ... n ⁺ region, 13 ... n-type cladding layer, 14 ...
n-type optical waveguide layer, 15 ... active layer, 16 ... p-type optical waveguide layer, 1
7 ... p-type cladding layer, 18 ... p-type contact layer, 18a
... current confinement region, 19 ... SiN _x layer, 20 ... p-side electrode,
21 ... n-side electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/146 H01L 21/265 F 31/10 21/302 N H01S 5/042 610 F 5/343 27 / 14 A 31/10 A F term (reference) 4M118 AA10 AB10 BA06 CA05 CA09 CB01 EA01 GA02 5F004 AA16 DB19 FA03 5F045 AA04 AB09 AB14 AB33 AC01 AC08 AC19 AD09 AD12 AD14 AF09 DA52 DA53 DA55 DA62 HA11 HA13 5F049 MA11 MB01 MB07 NA08 NA08 QA09 SS01 5F073 AA07 AA45 AA74 CA07 CB05 CB07 DA05 DA25 DA35

Claims (13)

[Claims] 1. A method of manufacturing a semiconductor device having one or two or more semiconductor layers made of a nitride-based compound semiconductor, wherein at least one of the surfaces of a specific one of the semiconductor layers is formed after the layer is formed. Exposing the part to a gas atmosphere containing chlorine to increase conduction electrons at the part. 2. The method according to claim 1, wherein the specific layer is p-type, and at least a part of the surface is exposed to a gas atmosphere containing chlorine to make the surface n-type or i-type. A method for manufacturing a semiconductor device. 3. The semiconductor layer according to claim 1, wherein said semiconductor layer is n-type.
At least partly n ⁺Gas atmosphere containing chlorine
The method according to claim 1, further comprising a step of exposing to ambient air.
Manufacturing method of the above-mentioned semiconductor element. 4. The method according to claim 1, wherein the step of exposing in a gas atmosphere containing chlorine is dry etching using an etching gas containing chlorine. 5. The gas containing chlorine (Cl) is C
l _2, BCl _3, The method according to claim 1, characterized in that any one of SiCl _4. 6. The method according to claim 1, wherein the flow rate of the gas containing chlorine is in a range of 2 cc / min to 30 cc / min, and the specific layer is exposed to the gas in a range of 1 min to 5 min. A method for manufacturing a semiconductor device according to claim 1. 7. A semiconductor device having one or two or more semiconductor layers made of a nitride-based compound semiconductor, wherein chlorine is introduced into at least a part of the vicinity of the surface of a specific layer of the semiconductor layers. A semiconductor element characterized in that the conduction electrons in this portion are increased by the application. 8. The semiconductor device according to claim 7, wherein the specific layer is p-type, and has an n-type region formed by introducing chlorine in at least a part near the surface. 9. The semiconductor device according to claim 7, wherein the specific layer is n-type, and has an n ⁺ -type region formed by introducing chlorine into at least a part near the surface. 10. The semiconductor device according to claim 7, which constitutes a semiconductor optical device. 11. The method according to claim 10, wherein the specific layer is a p-type contact layer, and an n-type region formed by introducing chlorine into at least a part of the vicinity of the surface is a current confinement region. Semiconductor element. 12. The method according to claim 1, wherein the specific layer is an n-type contact layer, and has an n ⁺ -type region formed by introducing chlorine into at least a part near the surface thereof.
The semiconductor element according to 0. 13. The semiconductor device according to claim 7, which constitutes a semiconductor electronic device.