JP2002059614A - Ink jet printer, and driving waveform generator and generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ink jet printer and a driving waveform generator and a generating method of an ink head in which high accuracy printing can be ensured even if a noise pulse enters a reset signal or a floor signal. SOLUTION: A driving waveform generating circuit 46 generates a waveform for driving a plurality of drive elements in an ink head 50 and performs logical operation of a flag referring to an operation mode signal, a reset signal and a floor signal such that the reset signal and the floor signal do not become active when a noise is mixed thus preventing disturbance and deterioration of image quality and damage of the head.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for generating a drive waveform used for driving an ink head in an ink jet printer.

[0002]

2. Description of the Related Art In recent years, an ink jet printer which discharges several colors of ink from an ink head and prints an image processed by a computer or the like in multiple colors and multiple gradations has been widely used as an output device of a computer. In order to realize multi-tone printing, the weight of ink droplets ejected from nozzles of an ink head is controlled, and the size of ink dots formed on a print medium is controlled.

Conventionally, it has been common practice to binarize whether or not to form an ink dot, and express the halftone of a printed image by determining the number of pixels in a given area where the ink dot is to be formed. Was. However, recently, by forming a plurality of dots of different sizes in one pixel using dark and light inks, it is possible to express a halftone of a print image with more gradations.

For example, in an ink jet printer using a piezo element, in order to form ink dots having different sizes, it is necessary to control the meniscus (the surface shape of the ink at the nozzle opening) at the nozzle opening of the ink head and to control the ink. It is important to control the timing of drop ejection. Therefore, in order to form a desired ink dot, a drive waveform for operating the piezo element of the ink head is changed according to the size of the ink dot to be formed.

The driving waveform for operating the piezo element has a different resistance value by using a method in which the absolute value of the driving voltage at an arbitrary time is previously stored in a memory or by utilizing the fact that the piezo element forms a capacitor. It has been controlled by switching the resistance between the piezo elements. However, in the former case, a large amount of memory is required to store the driving waveform, and in the latter case, a complicated timing pulse signal is required.

In order to solve these problems, a method of obtaining a drive waveform in a programmable manner by determining the amount of change in the drive voltage of the drive waveform at an arbitrary time and sequentially adding the values by an adder is proposed. Proposed.

FIG. 10 is a block diagram showing the internal configuration of a conventional drive waveform generator for generating a drive waveform. FIG. 11 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation device shown in FIG. The drive waveform generator 1 shown in FIG. 10 includes a memory 2, an accumulator 4, and a digital / analog converter 6.

[0008] The memory 2 stores drive waveform data indicating the waveform of the drive signal COM. As shown in the figure, the driving waveform data {V1,
ΔV2 and ΔV3 are the clock signals CL
It is sequentially accumulated in synchronization with K. Here, the drive waveform data is data representing a change amount of the drive voltage per one cycle t of the clock signal CLK.

The upper 10 bits of the 18-bit accumulation result are converted by the digital / analog converter 6 into digital / analog signals.
The motion signal COM is generated by the analog conversion. When the reset signal RESET is input to the accumulator 4, the 18-bit accumulation result is cleared to 0 and the output voltage is set to, for example, 1.4V.
Further, when the floor signal FLOOR is input to the accumulator 4, the lower 8 bits of the 18-bit accumulation result are cleared to 0, and the output voltage is set to, for example, 2.5V.

[0010]

However, in the above-described driving waveform generating apparatus, the reset signal R is output during the printing operation.
When a noise pulse enters the ESET or floor signal FLOOR, the following problem occurs. That is, when a noise pulse is included in the reset signal RESET, the waveform is inverted when the amount of change in the drive voltage is negative, and the piezo element malfunctions due to a sharp change in the drive voltage, and may be destroyed in some cases. Was.

Further, when a noise pulse is input to the floor signal FLOOR, depending on the timing of clearing 0, a carry may not occur where a carry is required, and a normal drive waveform may not be obtained. ,
In addition, a borrow occurs, the waveform is inverted, and the piezo element malfunctions due to a sharp change in the drive voltage, and in some cases, it may be destroyed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned various problems, and has as its object to provide an ink jet printer capable of performing high-precision printing even if a noise pulse is included in a reset signal or a floor signal. It is another object of the present invention to provide an ink head drive waveform generation device and a drive waveform generation method.

[0013]

In order to achieve the above object, an ink jet printer according to the present invention includes an ink head having a plurality of nozzles and a plurality of driving elements for driving these nozzles to discharge ink droplets. Generating a drive waveform for driving the plurality of drive elements, and so that a reset signal and a floor signal are not activated when noise enters, a flag referring to an operation mode signal, the reset signal and the floor signal, And a drive waveform generating circuit that performs the logical operation of (1).

In addition, a drive waveform for driving a plurality of drive elements is generated, and the drive waveform and the reset signal and the floor signal are combined so that the reset signal and the floor signal do not become active when noise enters. A drive waveform generating circuit for performing a logical operation is provided.
In addition, a driving waveform for driving a plurality of driving elements is generated, and a clock signal for generating the driving waveform is input so that a reset signal and a floor signal do not become active when noise enters. And a drive waveform generating circuit for performing a logical operation of the counter signal, the reset signal, and the floor signal.

Thus, even if noise enters during the printing operation, the driving waveform is not affected by the noise, so that the image quality can be prevented from being disturbed, degraded, and the head damaged, and the accumulated error of the lower bits of the driving signal can be prevented. Since the clear abnormal operation is eliminated, it is possible to obtain a theoretical driving waveform.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a perspective view showing a main part of an ink jet printer according to an embodiment of the present invention. As shown in FIG. 1, in an ink jet printer 100, a carriage 101 is connected to a carriage motor 103 via a timing belt 102 of a carriage mechanism 12, and is guided by a guide member 104 to reciprocate in a sheet width direction of a recording sheet 105. It is configured as follows. The inkjet printer 100 is also provided with a paper feed mechanism 11 using a paper feed motor 106.

Recording paper 105 on carriage 101
An ink jet type ink head 50 is attached to a surface facing the above, ie, a lower surface in the example shown in FIG. The ink head 50 receives the supply of ink from the ink cartridge 107 mounted on the upper portion of the carriage 101, and moves the recording paper 1 in accordance with the movement of the carriage 101.
05 to form dots by ejecting ink droplets on recording paper 1
05, images and characters are printed.

A capping device 108 is provided in a non-printing area of the ink jet printer 100. The capping device 108 seals the nozzle opening of the ink head 50 during the pause of printing. Therefore, the ink does not increase in viscosity or form an ink film due to the solvent being scattered from the ink during the printing pause, so that there is no possibility that the nozzles will be clogged during the printing pause. Also, the capping device 108
Receives ink droplets from the ink head 50 due to a flushing operation performed during a printing operation. A cleaning device 109 is provided near the capping device 108. This cleaning device 10
Reference numeral 9 denotes a structure in which the surface of the ink head 50 is wiped with a blade or the like to wipe off ink droplets and paper powder attached thereto.

FIG. 2 is a sectional view showing one of a plurality of nozzles formed in the ink head 50. As shown in FIG. FIG.
As shown in FIG.
No. 0, a nozzle opening 111 is formed, and a flow path forming plate 112 is formed.
Are provided with through holes for partitioning the pressure generation chamber 113, and the pressure generation chamber 11
There are formed through holes or grooves defining two ink supply ports 114 communicating with both sides of the ink supply port 3, and through holes defining two common ink chambers 115 communicating with the respective ink supply ports 114. The vibration plate 116 is made of an elastically deformable thin plate, and is a piezoelectric vibrator 11 such as a piezo element.
7 <fixed to the tip of the pressure generating element>. Further, the vibration plate 116 is fixed integrally with the nozzle plate 110 in a liquid-tight manner with the flow path forming plate 112 interposed therebetween, and forms a flow path unit 118.

The base 119 has a housing chamber 120 for vibratingly accommodating the piezoelectric vibrator 117, and an opening 121 for supporting the flow path unit 118, and exposing the tip of the piezoelectric vibrator 117 from the opening 121. The piezoelectric vibrator 11
7 is fixed by a fixed substrate 122. In addition, base 119
The ink head 50 is assembled by fixing the flow path unit 118 to the opening 121 with the island portion 116a of the vibration plate 116 in contact with the piezoelectric vibrator 117.

With this configuration, when a pulse is applied to the piezoelectric vibrator 117 from a drive signal to be described later, the piezoelectric vibrator 117 contracts and the pressure generating chamber 113 expands. Flows into the pressure generating chamber 113 via the ink supply port 114. When the piezoelectric vibrator 117 expands and the pressure generating chamber 113 contracts after a lapse of a predetermined time, ink in the pressure generating chamber 113 is compressed and ink droplets are ejected from the nozzle opening 111. Then, the piezoelectric vibrator 117 contracts again and the pressure generating chamber 113
Expands, new ink of the common ink 115 flows into the pressure generating chamber 113 via the ink supply port 114.

FIG. 3 shows an ink jet printer 100.
3 is a functional block diagram of FIG. As shown in FIG. 3, the ink jet printer 100 includes a control circuit 40 that controls the ink head 50, the paper feed mechanism 11, and the carriage mechanism 12 according to a command from a computer 95.

In the computer 95, an application program operates under a predetermined operating system. The operating system incorporates a video driver and a printer driver, and displays an image on a display and performs various image processing.

The control circuit 40 includes an interface 41 for receiving a print signal and the like from the computer 95, a RAM 42 for storing various data, a ROM 43 for storing various data processing routines and the like, an oscillation circuit 44,
A control unit 45 including a CPU and the like;
And the paper feed motor 106 of the paper feed mechanism 12, the carriage motor 103 of the carriage mechanism 12, and the ink head 50.
47 for sending print signals and drive signals to the
And

The RAM 42 is used as a receiving buffer 42A, an intermediate buffer 42B or an output buffer 42C. The print signal from the computer 90 is stored in the reception buffer 42A via the interface 41.
This data is converted into an intermediate code and stored in an intermediate buffer 4.
2B. Then, necessary processing is performed by the control unit 45 with reference to font data, graphic functions, and the like in the ROM 43, dot pattern data is developed, and stored in the output buffer 42C. The dot pattern data is sent to the ink head 5 via the interface 47.
Sent to 0.

FIG. 4 is a block diagram showing the electrical configuration of the ink head 50. The ink head 50 includes a plurality of shift registers 51A to 51N corresponding to the number of nozzles.
, A plurality of latch circuits 52A to 52N, a plurality of level shifters 53A to 53N, and a plurality of switch circuits 54A to 54N.
54N, and a plurality of piezo elements 55A to 55N. The print signal SI is input to the shift registers 51A to 51N in synchronization with the clock signal CLK from the oscillation circuit 44. Then, the signals are latched by the latch circuits 52A to 52N in synchronization with the latch signal LAT. The latched print signal SI is amplified by the level shifters 53A to 53N to a voltage that can drive the switch circuits 54A to 54N,
The signals are supplied to the switch circuits 54A to 54N. A drive waveform generation circuit 46 is provided on the input side of the switch circuits 54A to 54N.
The drive signal COM is input to the piezo elements 55A to 55N on the output side.

The switch circuits 54A to 54N include, for example,
When the print signal SI is “1”, the drive signal COM is supplied to the piezo elements 55A to 55N to be operated, and when the print signal SI is “0”, it is shut off and not operated. Piezo elements 55A to 55N
As is well known, the crystal structure is distorted by the application of voltage,
It is an element that performs electro-mechanical energy conversion at a very high speed. Although not shown, the drive signal COM is supplied to the piezo element 55A.
To 55N, the piezo element 55
A to 55N are deformed, and the wall of the ink chamber 115 is also deformed.
This controls the ejection of ink droplets from the nozzle openings 111. Printing is performed by the ejected ink droplets adhering to the recording paper 105.

FIG. 5 is a first block diagram showing the internal configuration of the drive waveform generation circuit 46. The drive waveform generation circuit 46A includes a memory 60 for storing drive waveform data supplied from the control unit 45, a first latch 62 for temporarily holding drive waveform data read from the memory 60, and a first latch 62. , And an output of a second latch 66 described later, an adder 64, a second latch 66, and a digital / analog converter 70 for converting the output of the second latch 66 into an analog signal. The adder 64 and the second latch 66 constitute an accumulator 68 for accumulating the driving waveform data. Further, the converted analog signal is supplied to a piezo element 5.
Voltage amplifying unit 7 for amplifying voltage to operate 5A-55N
2 and a current amplifying unit 74 for supplying a current corresponding to the amplified voltage signal.

Further, based on the operation mode setting from the control unit 45 and the drive waveform data from the memory 60, a first flag 76 which outputs 0 only at the time of starting the non-printing minute vibration and at the time of starting the starting, And a second flag 78 that outputs 0 only at the time of end-down activation, an OR gate 80 that performs an OR operation by receiving a signal from the first flag 76 and a reset signal RESET, and a signal from the second flag 78 and a floor signal FLOOR. An OR gate 82 for performing an OR operation by input is provided.

The memory 60 has a first clock signal CL
K1, a data signal representing drive waveform data, address signals A0 to A3, and an enable signal are supplied. The first latch 62 also has a second clock signal CLK2
And a signal from the OR gate 80 are supplied. The second latch 66 is supplied with the third clock signal CLK3 and signals from the OR gates 80 and 82.

The first flag 76 and the second flag 78 are set to 1 at a timing other than when the reset signal RESET and the floor signal FLOOR are input by the control from the memory 60 or the outside. The power-on reset signal RESET is output from the power supply PSC signal (P /
Scut) becomes inactive, the first signal is output in synchronization with the reset signal RESET output timing.
The outputs of the flag 76 and the second flag 78 are output as 0 for a certain period of time.

FIG. 6 is a timing chart showing the timing of writing drive waveform data in the memory 60.
Prior to generation of the drive waveform COM, the data signal indicating the drive waveform data and the address of the data signal are the first signal.
Is supplied from the control unit 45 to the memory 60 in synchronization with the clock signal CLK1. The data signal is one bit, but as shown in FIG. 6, the first clock signal CLK1
The drive waveform data is transferred one bit at a time by serial transfer using as a synchronization signal. That is, when the drive waveform data is transferred from the control unit 45 to the memory 60, first,
A data signal for a plurality of bits is supplied in synchronization with the first clock signal CLK1.

Thereafter, address signals A0 to A3 indicating a write address for storing the data and an enable signal are supplied. The memory 60 stores the address signals A0 to A3 at the timing when the enable signal is supplied.
Is read, and the received drive waveform data is written to the address. Since the address signals A0 to A3 are 4 bits, a maximum of 16 types of drive waveform data can be stored in the memory 60.

FIG. 7 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation circuit 46. When the read address B is output as the address signals A0 to A3 after the writing of the drive waveform data into the memory 60 is completed, the first drive waveform data # V1 is output from the memory 60. Thereafter, when a pulse of the second clock signal CLK2 is generated, the driving waveform data # V1 is held in the first latch 62. In this state, when the next pulse of the third clock signal CLK3 is generated, the second latch 66
And the 16-bit output of the first latch 62 are added by the adder 64, and the addition result is held in the second latch 66. That is, as shown in FIG. 7, once the drive waveform data corresponding to the address signal is selected, every time the third clock signal CLK3 is received, the output of the second latch 66 is set to the drive signal. The values of the waveform data are accumulated.

In the example shown in FIG. 7, a voltage per cycle t of the third clock signal CLK3 is stored in the address B as △.
Drive waveform data indicating that the voltage is increased by V1 is stored. Therefore, when the address B becomes valid by the second clock signal CLK2, the voltage increases by ΔV1. In addition, the address A stores ΔV2, 0 as the drive waveform data, that is, a value indicating that the voltage is held. Therefore, the second clock signal CL
When the address A becomes valid by K2, the waveform of the drive signal is maintained in a flat state with no increase or decrease. Further, the drive waveform data indicating that the voltage per one cycle t of the third clock signal CLK3 is reduced by ΔV3 is stored in the address C. Therefore, after the address C is made valid by the second clock signal CLK2, the voltage ΔV3
The voltage will gradually decrease. The increase or decrease is determined by the sign of the data stored at each address.

Thus, the 1 added by the adder 64
Of the 8-bit addition result, the upper 10 bits of the voltage level data D are input to the digital / analog converter 70. The entire 18-bit addition result is added to the adder 64.
Will be re-entered. As a result, the voltage level data D output from the second latch 66 changes stepwise as shown in FIG. This voltage level data D is converted by the digital / analog converter 70 to form the drive waveform shown in FIG.

Then, the first latch 62 and the second latch 6
Since 6 is cleared to 0 by application of a low pulse, when the original reset signal RESET and floor signal FLOOR become active (low), the outputs of the first flag 76 and the second flag 78 are set to 0. , The output of the OR gate 80 and the output of the OR gate 82 can be set to zero. On the other hand, when noise enters, the first flag 76
By setting the output of the second flag 78 to 1, the outputs of the OR gate 80 and the OR gate 82 remain at 1 even if 0 is input to the reset signal RESET and the floor signal FLOOR, and are not cleared to 0. . Thereby, it is possible to prevent the influence of the noise pulse. The first flag 76 and the second flag 78
May be provided in the memory 60. Also, the first flag 7
The sixth flag 78 and the second flag 78 can be handled not only by hardware processing but also by software processing.

FIG. 8 is a second block diagram showing the internal configuration of the drive waveform generation circuit 46 in correspondence with FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted. The drive waveform generation circuit 46B includes a first flag 76, a second flag 78, an OR gate 80, and an OR gate 82 in FIG.
In place of the above, an OR gate 84 that inputs the digital 10-bit output of the second latch 66 and the reset signal RESET to perform an OR operation, and an OR gate 85 that inputs the digital 10-bit output of the second latch 66 and the floor signal FLOOR to perform an OR operation And

According to such a configuration, at least one of the upper 10 bits of the digital signal from the second latch is 1 at normal times, and therefore the reset signal RESE
No matter how the T or floor signal FLOOR changes, the outputs of OR gates 84 and 85 will be one, ie, hig
h, and the reset signal RESET or the floor signal FLOOR has no effect. On the other hand, in the case of the original reset signal RESET or floor signal FLOOR, the outputs of the OR gates 84 and 85 are changed by the reset signal RESET or floor signal FLOOR. This allows
It is possible not to be affected by the noise pulse.

FIG. 9 is a third block diagram showing the internal configuration of the drive waveform generation circuit 46 in correspondence with FIG.
The same components as those described above are denoted by the same reference numerals and description thereof is omitted. The drive waveform generation circuit 46C includes a first flag 76 and a second flag 78, an OR gate 80, and an OR gate 82 in FIG.
, A counter 86 that inputs a third clock signal CLK3 and a reset signal RESET,
, An OR gate 90 that inputs the output of the NAND gate 88 and the reset signal RESET, performs an OR operation, and a counter 8 that inputs the third clock signal CLK3 and the floor signal FLOOR.
7, a NAND gate 89 for performing a NAND operation on an output from the counter 87, an output of the NAND gate 89 and a floor signal F
An OR gate 91 for inputting LOOR and performing an OR operation is provided.

According to such a configuration, the third clock signal CLK3 is watched, and when the drive waveform is not output, the third clock signal CLK3 is not output. High is output for a time twice as long as the high time. And NAND gate 8
Even if the noise reset signal RESET or the floor signal FLOOR is input when the output Z1 of 8, 89 is high, the output Z2 of the OR gates 90, 91 remains high and is not cleared to 0 since it does not become low. Therefore, it is possible to prevent the influence of the noise pulse. The numbers of QA to QN of the counters 86 and 87 are changed according to the shape of the drive waveform.

As described above, the present invention has been described with respect to various embodiments. However, the present invention is not limited to the above embodiments, and other embodiments may be included within the scope of the invention described in the claims. It goes without saying that also applies.

[0044]

As described above, according to the ink jet printer, the ink head driving waveform generating apparatus and the driving waveform generating method according to the present invention, even if noise is present during the printing operation, the driving waveform is not affected by the noise. Since it is not received, it is possible to prevent the image quality from being disturbed, deteriorated and the head from being damaged.
In addition, since the abnormal operation of clearing the accumulated error of the lower bits of the drive signal is eliminated, a theoretical drive waveform can be obtained, and high-precision printing can be performed.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a main part of an ink jet printer according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one of a plurality of nozzles included in an ink head of the ink jet printer shown in FIG.

FIG. 3 is a functional block diagram of the ink jet printer shown in FIG.

FIG. 4 is a block diagram showing an electrical configuration of an ink head of the ink jet printer shown in FIG.

FIG. 5 is a first block diagram illustrating an internal configuration of a drive waveform generation circuit of the inkjet printer illustrated in FIG. 1;

FIG. 6 is a timing chart showing a timing of writing drive waveform data in a memory of the drive waveform generation circuit shown in FIG.

FIG. 7 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation circuit shown in FIG.

8 is a second block diagram showing an internal configuration of a drive waveform generation circuit of the ink jet printer shown in FIG.

FIG. 9 is a third block diagram illustrating an internal configuration of a drive waveform generating circuit of the ink jet printer illustrated in FIG. 1;

FIG. 10 is a block diagram showing an internal configuration of a conventional drive waveform generator for generating a drive waveform.

11 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation device shown in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 paper feed mechanism 12 carriage mechanism 40 control circuit 41 interface 42 RAM 42A reception buffer 42B middle buffer 42C output buffer 43 R0M 44 oscillation circuit 45 control unit 46 drive waveform generation circuit 47 interface 50 ink head 51A to 51N shift registers 52A to 52N Latch circuit 53A-53N Level shifter 54A-54N Switch circuit 55A-55N Piezo element 60 Memory 62 First latch 64 Adder 66 Second latch 68 Accumulator 70 D / A converter 72 Voltage amplifier 74 Current amplifier 76 First Flag 78 Second flag 80, 82 OR gate 84, 85 OR gate 86, 87 Counter 88, 89 NAND gate 90, 91 OR gate 95 Computer 100 Inkjet printer 1 Reference Signs List 1 carriage 102 timing belt 103 carriage motor 104 guide member 105 recording paper 106 paper feed motor 107 ink cartridge 108 capping device 109 cleaning device 110 nozzle plate 111 nozzle opening 112 flow path forming plate 113 pressure generating chamber 114 ink supply port 115 ink chamber 116 Vibration plate 117 Piezoelectric vibrator 118 Flow path unit 119 Base 120 Housing chamber 121 Opening 122 Fixed substrate

Claims (9)

[Claims] 1. An ink jet printer for printing an image on a recording medium based on a print signal of the image, comprising: a plurality of nozzles; and a plurality of driving elements for driving the nozzles to discharge ink droplets. An ink head comprising: a driving signal for driving the plurality of driving elements; a flag referring to an operation mode signal; and the reset signal, so that a reset signal and a floor signal are not activated when noise is input. And a drive waveform generating circuit for performing a logical operation on the floor signal. 2. An ink jet printer for printing an image on a recording medium based on a print signal of the image, comprising: a plurality of nozzles; and a plurality of driving elements for driving the nozzles to discharge ink droplets. And a drive waveform for driving the plurality of drive elements, and the drive waveform, the reset signal, and the floor signal so that a reset signal and a floor signal do not become active when noise enters. And a drive waveform generating circuit for performing a logical operation of the following. 3. An ink jet printer for printing an image on a recording medium based on a print signal of the image, comprising: a plurality of nozzles; and a plurality of driving elements for driving the nozzles to discharge ink droplets. And a clock signal for generating the drive waveform such that a reset signal and a floor signal do not become active when noise is input, while generating a drive waveform for driving the plurality of drive elements. An ink jet printer comprising: a driving waveform generating circuit that performs a logical operation of a counter signal obtained by inputting the counter signal, the reset signal, and the floor signal. 4. A driving waveform generating apparatus for generating a driving waveform for driving a driving element, comprising: a flag that refers to an operation mode signal so that a reset signal and a floor signal are not activated when noise is input. And a logical operation of the reset signal and the floor signal. 5. A drive waveform generator for generating a drive waveform for driving a drive element, wherein the drive waveform and the reset signal are set so that a reset signal and a floor signal do not become active when noise enters. And a logical operation with the floor signal. 6. A drive waveform generating apparatus for generating a drive waveform for driving a drive element, wherein the drive waveform is generated so that a reset signal and a floor signal do not become active when noise enters. A logical operation of a counter signal obtained by inputting said clock signal, said reset signal and said floor signal. 7. A driving waveform generating method for generating a driving waveform for driving a driving element, comprising: inputting a flag referring to an operation mode signal; inputting a reset signal and a floor signal; Performing a logical operation of the flag, the reset signal, and the floor signal to prevent the reset signal and the floor signal from being activated when noise is input. 8. A driving waveform generating method for generating a driving waveform for driving a driving element, comprising: inputting a flag referring to an operation mode signal; inputting a reset signal and a floor signal; Performing a logical operation of a drive waveform, the reset signal, and the floor signal to prevent the reset signal and the floor signal from being activated when noise occurs. . 9. A driving waveform generating method for generating a driving waveform for driving a driving element, comprising: inputting a flag referring to an operation mode signal; inputting a reset signal and a floor signal; By performing a logical operation on the counter signal obtained by inputting a clock signal for generating a drive waveform, the reset signal, and the floor signal, when noise enters, the reset signal and the floor signal become active. A driving waveform generating method.