JP2002056675A - Clock generating circuit, and synchronous semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generating circuit which can generate two normal internal clock signals even when deviation occurs in a logic threshold value of a clock buffer in a clock generating circuit provided with two clock buffers. SOLUTION: This circuit is provided with a clock activating circuit 50 which activates internal clock signals ICLK12 and ICLK22 when both of an internal clock signal ICLK11 outputted from the clock buffer 1 and an internal clock signal ICLK21 outputted from the clock buffer 2 are activated between clock buffers 1, 2 and a pulse width control circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock generation circuit and a synchronous semiconductor memory device using the same, and more particularly to an improvement of a clock generation circuit having two types of clock buffers.

[0002]

2. Description of the Related Art A synchronous semiconductor memory device such as a synchronous dynamic random access memory (SDRAM) is provided with a clock generation circuit for generating an internal clock signal in response to an external clock signal. FIG.
FIG. 1 is a circuit diagram showing an example of a conventional clock generation circuit. As shown in FIG. 6, the clock generation circuit includes two clock buffers 1 and 2 and a pulse width control circuit 3.

A clock buffer 1 is enabled in response to an external clock enable signal ECKE, receives an external clock signal ECLK, and receives an internal clock signal ICLK.
11 is output. Clock buffer 2 is always operable regardless of external clock enable signal ECKE, and receives internal clock signal ECLK and outputs internal clock signal ICLK21.

The pulse width control circuit 3 includes a delay circuit 31 and
An inverter circuit 32 and AND circuits 33 and 34 are included. As a result, pulse width control circuit 3 converts internal clock signals ICLK11 and ICLK21 into one-shot pulses to determine their pulse widths, thereby generating internal clock signals ICLK1 and ICLK2.

Internal clock signal ICLK1 is applied to a buffer 4 for control signals (for example, row address strobe signal / RAS, column address strobe signal / CAS, write enable signal / WE), and internal clock signal ICLK2 is applied to clock enable (CKE). ) Is supplied to the buffer 5.

The SDRAM generally has an operation mode in which the internal clock signal is stopped to reduce power consumption. At this time, there is no problem if the internal control signal ICLK1 for controlling the operation of the command decoder (not shown) and the like is stopped, but only the internal clock signal ICLK2 must be operated to sample the external clock enable signal ECKE. Must. Therefore, two types of clock buffers 1 and 2 are provided as shown in FIG. The clock buffer 1 is enabled in response to an external clock enable signal ECKE, and generates an internal clock signal ICLK1 (ICLK11) for controlling a command decoder and the like. On the other hand, the clock buffer 2 is always operable and generates an internal clock signal ICLK2 (ICLK21) for controlling the CKE buffer 5.

When there are two types of clock buffers 1 and 2 as described above, the logical thresholds may be shifted due to process variations. However, even in this case, the transition time (rise time t) of the input external clock signal ECLK is
This is not a problem when r / fall time tf) is short.

FIG. 7 is a timing chart showing an operation when the transition time of the external clock signal ECLK is short, that is, when the waveform of the external clock signal ECLK is not distorted. Even when the logical threshold values of the two types of clock buffers 1 and 2 are extremely shifted, the internal clock signal ICLK1
1, the rising deviation of ICLK21 does not exceed the transition time of external clock signal ECLK. That is, even if the transition time is 1-2 nanoseconds, the internal clock signal ICL
The shift between K11 and ICLK21 is 1 to 2 nanoseconds at the maximum, and the internal clock signals ICLK1 and ICLK2 are generated normally.

[0009]

SUMMARY OF THE INVENTION External clock signal EC
Since the transition time of the LK is determined by the product specifications, the above-described problem does not occur in an actual product. However, among current shipping tests, there is a long-term voltage / temperature acceleration test called “burn-in”. Because these are time consuming, many chips are tested simultaneously. In this case, since a large number of chips are connected to the tester, the waveform of the external clock signal ECLK may become considerably long. This is out of product specification, but the product must work properly for testing.

FIG. 8 is a timing chart showing an operation when the transition time of the external clock signal ECLK is short. When the logical threshold value TH2 of the clock buffer 2 is lower than the logical threshold value TH1 of the clock buffer 1, the internal clock signal ICLK21 becomes H (logical high) level before the internal clock signal ICLK11. The pulse width control signal / DICLK21 for determining the pulse width of the internal clock signals ICLK1 and ICLK2 is equal to the internal clock signal ICL.
Since K21 is activated with a delay, the falling of the pulse width control signal / DICKL21 causes the internal clock signal I
If the internal clock signal ICLK2 is generated faster than the rising edge of CLK11, the internal clock signal ICLK1 is generated.
Does not occur. Therefore, buffer 4 outputs control signal / RA
S, / CAS, / WE, etc. cannot be fetched, and the command decoder does not operate normally. Further, the rising edge of the internal clock signal ICLK11 is higher than the pulse width control signal /
Even if it is faster than the falling edge of DICLK21, if the pulse width control signal / DICLK21 falls immediately after the rising edge of the internal clock signal ICLK11, the pulse width of the internal clocking signal ICLK1 becomes extremely short. May not work properly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can stably generate two types of internal clock signals even when the logical thresholds of the two types of clock buffers deviate. It is an object of the present invention to provide a possible clock generation circuit and a synchronous semiconductor memory device using the same.

[0012]

A clock generation circuit according to the present invention includes a first clock buffer, a second clock buffer, an activating means, and a pulse width control circuit. The first clock buffer is enabled in response to a clock enable signal and receives an external clock signal. The second clock buffer receives an external clock signal. The activating means activates the first and second internal clock signals when both the signal output from the first clock buffer and the signal output from the second clock buffer are activated. The pulse width control circuit inactivates the first and second internal clock signals and determines a pulse width of the first and second internal clock signals.

Preferably, the activating means comprises a first A
An ND circuit and a second AND circuit are included. First AND
The circuit receives a signal output from the first clock buffer and a signal output from the second clock buffer. The second AND circuit receives a signal output from the first clock buffer and a signal output from the second clock buffer.

[0014] More preferably, the pulse width control circuit includes a delay circuit, a first gate circuit, and a second gate circuit. The delay circuit delays a signal output from the second AND circuit. The second gate circuit transmits a first internal clock signal in response to a signal output from the delay circuit. The second gate circuit transmits a second internal clock signal in response to a signal output from the delay circuit.

In the above clock generation circuit, even if a difference occurs between the logical threshold value of the first clock buffer and the logical threshold value of the second clock buffer, the first
The first and second internal clock signals are activated when both the signal output from the second clock buffer and the signal output from the second clock buffer are activated. And normal first and second internal clock signals are generated.

Alternatively, the clock generation circuit further includes a first latch circuit and a second latch circuit. The first latch circuit latches a signal output from the first clock buffer and provides the latched signal to the activating means. The second latch circuit latches a signal output from the second clock buffer and supplies the latched signal to the activating means.

[0017] More preferably, the pulse width control circuit includes a delay circuit and a one-shot pulse. The delay circuit delays the second internal clock signal output from the second AND circuit. The one-shot pulse circuit generates a reset signal for the first and second latch circuits in response to a signal output from the delay circuit.

In the clock generation circuit, signals to be output from the first and second clock buffers are latched, and the first and second latch circuits are responsive to a reset signal obtained by delaying the second internal clock signal. Is reset, the pulse widths of the first and second internal clock signals are maintained at a predetermined length even when the pulse width of the external clock signal is short.

A synchronous semiconductor memory device according to the present invention comprises:
It includes a memory cell array, read / write means, a clock generation circuit, a clock enable buffer, and a control signal buffer. The read / write means reads and writes data from and to the memory cell array. The clock generation circuit generates first and second internal clock signals in response to an external clock signal. The clock enable buffer receives the external clock enable signal and outputs the internal clock enable signal in synchronization with the second internal clock signal. The control signal buffer receives the external control signal for controlling the reading / writing means and outputs the internal control signal in synchronization with the first internal clock signal. The clock generation circuit includes a first clock buffer, a second clock buffer, an activation unit, and a pulse width control circuit. First
Are enabled in response to an external clock enable signal and receive the external clock signal.
The second clock buffer receives an external clock signal. The activating means activates the first and second internal clock signals when both the signal output from the first clock buffer and the signal output from the second clock buffer are activated. The pulse width control circuit deactivates the first and second internal clock signals to generate the first and second internal clock signals.
Of the internal clock signal is determined.

In the above-mentioned synchronous semiconductor memory device, even if a difference occurs between the logical threshold value of the first clock buffer and the logical threshold value of the second clock buffer, the output from the first clock buffer is reduced. The first and second internal clock signals are activated when both the signal to be output and the signal output from the second clock buffer are activated. First
And a second internal clock signal is generated.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

[First Embodiment] FIG. 1 is a block diagram showing an entire configuration of an SDRAM according to a first embodiment of the present invention. Referring to FIG. 1, SDRAM 10 includes a memory cell array 12 composed of a large number of memory cells arranged in a matrix, a row decoder 14 for selecting a row of memory cell array 12, and a column decoder for selecting a column of memory cell array 12. 16 and a data input / output circuit 18 for inputting / outputting data of a memory cell selected by the row decoder 14 and the column decoder 16.

The SDRAM 10 further responds to an external clock signal ECLK in response to an internal clock signal ICLK1.
And a clock generation circuit 20 for generating ICLK2,
A clock enable (CKE) buffer 22 receiving an external clock enable signal ECKE and outputting an internal clock enable signal ICKE, and a row address strobe (RA) receiving a row address strobe signal / RAS.
S) Buffer 24 and column address strobe signal /
A column address strobe (CAS) buffer 26 receiving CAS, a write enable (WE) buffer 28 receiving write enable signal / WE,
A command decoder 40 that decodes a command consisting of RAS, / CAS, and / WE to generate an internal control signal (a row activation signal, a column activation signal, a precharge signal, etc.) for controlling data reading and writing; Receiving the address signal AD of the row decoder 14 and the column decoder 1
6 and a data input / output buffer 44 for inputting / outputting n-bit data DQ between the data input / output circuit 18 and the data input / output circuit 18.

The clock signal ICLK1 includes an address buffer 42, a data input / output buffer 44, a control signal buffer for receiving an external control signal and outputting an internal control signal, such as a RAS buffer 24, a CAS buffer 26, and a WE buffer 28. And various internal circuits of SDRAM 10. Internal clock signal ICLK2 is applied to CKE buffer 22. Therefore, RAS buffer 24 takes in row address strobe signal / RAS in synchronization with internal clock signal ICLK1. CAS buffer 26 takes in column address strobe signal / CAS in synchronization with internal clock signal ICLK1. WE buffer 28 takes in write enable signal / WE in synchronization with internal clock signal ICLK1. Address buffer 42 takes in address signal AD in synchronization with internal clock signal ICLK1. Data input / output buffer 44 takes in externally applied data DQ in synchronization with internal clock signal ICLK1.

On the other hand, the internal clock enable signal ICK
E is the RAS buffer 24, CAS buffer 26, WE
A control signal buffer such as buffer 28 is provided.
These control signal buffers 24, 26, 28 are enabled in response to an internal clock enable signal ICKE.

FIG. 2 is a circuit diagram showing a specific configuration of clock generation circuit 20 in FIG. Referring to FIG. 2, clock generation circuit 20 includes an external clock signal ECLK.
Clock buffer 1 receiving the external clock signal ECLK and outputting an internal clock signal ICLK21, and internal clock signals ICLK11 and ICL.
When both K21 are activated, the internal clock signal ICL
An internal clock activation circuit 50 for activating K12 and ICLK22, and an internal clock signal ICLK12 (IC
LK1) and ICLK22 (ICLK2) to determine the pulse width of internal clock signals ICLK1 and ICLK2.

External clock enable signal ECKE is applied only to clock buffer 1. Clock buffer 1 is formed of, for example, a two-input AND circuit, to which external clock signal ECLK and external clock enable signal ECKE are input. Therefore, clock buffer 1 is made operable in response to external clock enable signal ECKE, while clock buffer 2 is always operable.

Clock activation circuit 50 receives internal clock signals ICLK11 and ICLK21 and outputs internal clock signal ICLK12, and AND circuit 52 receives internal clock signals ICLK11 and ICLK21 and outputs internal clock signal ICLK22. And Therefore, AND circuit 51 outputs a signal indicating that both internal clock signals ICLK11 and ICLK21 are at H level.
When the internal clock signal ICLK12 becomes H level
Activate to the level. Similarly, AND circuit 52 has both internal clock signals ICLK11 and ICLK21 at H level.
When the internal clock signal ICLK22 becomes H level
Activate to the level.

The pulse width control circuit 3 includes a delay circuit 31 for delaying the internal clock signal ICLK22 and a delay circuit 3
Inverter circuit 32 for inverting the signal delayed by 1
And internal clock signal ICL in response to pulse width control signal / DICLK22 output from inverter circuit 32.
A gate circuit 33 transmitting K12 as internal clock signal ICLK1 and a gate circuit 34 transmitting internal clock signal ICLK22 as internal clock signal ICLK2 in response to pulse width control signal / DICLK22 are included. Each of the gate circuits 33 and 34 comprises an AND circuit.

Next, the operation of the clock generation circuit configured as described above will be described with reference to the timing chart of FIG. Here, the logic threshold value TH1 of the clock buffer 1 is larger than that of the clock buffer 2 due to process variation.
The description will be made on the assumption that the threshold value is higher than the logical threshold value TH2.

As shown in FIG. 3, external clock signal CLK
If the rise time is long and its waveform is rounded,
The level of the external clock signal CLK first exceeds the logical threshold value TH2 of the clock buffer 2, and then exceeds the logical threshold value TH1 of the clock buffer 1. Therefore, clock buffer 2 raises internal clock signal ICLK21 to H level when the level of external clock signal ECLK exceeds logical threshold value TH2. Subsequently, the clock buffer 1 outputs the internal clock signal ICL when the level of the external clock signal ECLK exceeds the logical threshold value TH1.
K11 is raised to H level. As a result, the internal clock signal ICLK11 rises to the internal clock signal ICL.
It is slower than the rise of K21.

However, this clock generation circuit 20
Is provided with a clock activation circuit 50,
ND circuit 51 has internal clock signals ICLK11 and ICLK11.
When both CLK21 are at H level, internal clock signal ICLK12 is raised to H level. AND circuit 5
2 also has the internal clock signal ICLK11 and ICL
When both K21 are at H level, internal clock signal ICLK22 is raised to H level. The pulse width control circuit 3 controls the internal clock signal I activated to the H level.
CLK12 and ICLK22 are inactivated to L level after a predetermined time elapses, and the pulse widths of internal clock signals ICLK1 and ICLK2 are determined. That is, while the pulse width control signal / DICLK22 is at the H level, the internal clock signal ICLK12 is output as the internal control signal ICLK1 through the gate circuit 33, and the internal clock signal ICCLK is output.
LK22 passes the internal clock signal I through a gate circuit 34.
Output as CLK2. Internal clock signal ICLK
22 is delayed by delay circuit 31, and after a lapse of a predetermined time from the rise of internal clock signal ICLK22, pulse width determination signal / DICLK22 falls to L level. Therefore, gate circuits 33 and 34 are disconnected, and internal clock signals ICLK1 and ICLK2 attain L level.

As described above, according to the first embodiment of the present invention, internal clock signals ICLK11 and ICLK21
Are activated, the internal clock signal ICLK12
Activating circuit 5 for activating clock and ICLK 22
Since 0 is provided, two normal internal clock signals ICLK1 and ICLK2 can be generated even if the logical threshold values of the clock buffers 1 and 2 are shifted due to process variations. Therefore, even when a test such as burn-in is performed on SDRAM 10 provided with clock generation circuit 20, command decoder 40 and other internal circuits operate normally. As a result, an accurate test can be performed.

[Second Embodiment] FIG. 4 is a circuit diagram showing a configuration of a clock generation circuit 20 according to a second embodiment of the present invention. Unlike the first embodiment shown in FIG. 2, clock generating circuit 20 according to the second embodiment shown in FIG. 4 latches internal clock signal ICLK11 and outputs the latched internal clock signal ICLK13 to clock activating circuit 5.
0 and an internal clock signal ICL
K21 is latched and the latched internal clock signal I is latched.
And a latch circuit 62 that supplies CLK23 to the clock activation circuit 50. In place of pulse width control circuit 3 shown in FIG. 2, internal clock signals ICLK13 and ICLK23 are inactivated to generate internal clock signal ICLK.
1 and a pulse width control circuit 64 for determining the pulse width of ICLK2. The pulse width control circuit 64 includes a delay circuit 65 for delaying the internal clock signal ICLK2, and a latch circuit 60 in response to a signal output from the delay circuit 65.
And a one-shot pulse circuit 66 for generating a reset signal RST.

Next, the operation of the clock generation circuit 20 configured as described above will be described with reference to the timing chart of FIG. Here, operations different from those of the first embodiment will be mainly described.

Internal clock signal ICLK21 is latched by latch circuit 62, whereby internal clock signal ICLK23 rises to H level. Internal clock signal ICLK11 is latched by latch circuit 60, whereby internal clock signal ICLK13 rises to H level. Since internal clock signal ICLK11 rises later than internal clock signal ICLK21, internal clock signal ICLK13 also rises later than internal clock signal ICLK23.

Internal clock signal ICLK13 and IC
When both LK23 are activated to H level, clock activation circuit 50 activates internal clock signals ICLK1 and ICLK2 to H level.

The internal clock signal ICLK2 is supplied to the delay circuit 6
5 and the one-shot pulse circuit 66 responds to the delayed signal to reset signal RS
T is generated. The reset signal RST is output from the latch circuit 60
And 62, whereby latch circuits 60 and 62 are reset. Therefore, the reset signal R
When ST is activated to H level, internal clock signal I
CLK13 and ICLK23 are inactivated to L level, whereby internal clock signals ICLK1 and ICCLK are deactivated.
LK2 is also inactivated to L level.

In the first embodiment, when the pulse width of the external clock signal ECLK (H level period) is reduced, the pulse widths of the internal clock signals ICLK1 and ICLK2 (H level Period) becomes short. On the other hand, in the second embodiment, since latch circuits 60 and 62 are provided and internal clock signal ICLK2 is delayed to reset latch circuits 60 and 62, the pulse width of external clock signal ECLK is reduced. Internal clock signal I
Even if the pulse width of CLK11 becomes short, the pulse widths of internal clock signals ICLK1 and ICLK2 are held for a certain period.

It should be understood that the embodiments disclosed herein are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0041]

As described above, according to the present invention, when both signals output from the two clock buffers are activated, the two internal clock signals are activated. Accordingly, two normal internal clock signals can be generated even when the logical threshold values of the two clock buffers are shifted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an SDRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a clock generation circuit in FIG.

FIG. 3 is a timing chart showing an operation of the clock generation circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a clock generation circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation of the clock generation circuit shown in FIG.

FIG. 6 is a circuit diagram showing a configuration of a conventional clock generation circuit.

FIG. 7 is a timing chart showing an operation of the clock generation circuit shown in FIG. 6 when the external clock signal is not distorted.

8 is a timing chart showing an operation of the clock generation circuit shown in FIG. 6 when an external clock signal is distorted.

[Description of Signs] 1, 2 clock buffer, 3, 64 pulse width control circuit, 10 SDRAM, 12 memory cell array, 14
Row decoder, 16 column decoder, 18 data input / output circuit, 20 clock generation circuit, 22 clock enable buffer, 24 row address strobe buffer, 26 column address strobe buffer, 28
Write enable buffer, 31,65 delay circuit,
32 inverter circuits, 33, 34 AND circuits, 51,
52 gate circuit 60, 62 latch circuit, 66 one-shot pulse circuit.

Claims (6)

[Claims] A first clock buffer operable in response to a clock enable signal and receiving an external clock signal; a second clock buffer receiving the external clock signal; and an output from the first clock buffer. Activation means for activating the first and second internal clock signals when both the signal to be activated and the signal output from the second clock buffer are activated; and A pulse width control circuit for inactivating a clock signal to determine a pulse width of the first and second internal clock signals. 2. The circuit according to claim 1, wherein the activating means includes: a first AND circuit receiving a signal output from the first clock buffer and a signal output from the second clock buffer; 2. The clock generation circuit according to claim 1, further comprising a second AND circuit receiving a signal output from the second clock buffer and a signal output from the second clock buffer. 3. The pulse width control circuit includes: a delay circuit for delaying a signal output from the second AND circuit; and a first internal clock signal in response to a signal output from the delay circuit. 3. The clock generation circuit according to claim 2, further comprising: a first gate circuit for transmitting, and a second gate circuit for transmitting the second internal clock signal in response to a signal output from the delay circuit. 4. A first latch circuit for latching a signal output from the first clock buffer and supplying the latched signal to the activating means, and a signal output from the second clock buffer. 3. The clock generation circuit according to claim 2, further comprising: a second latch circuit that latches and supplies the latched signal to the activation unit. 5. A pulse width control circuit comprising: a delay circuit for delaying the second internal clock signal output from the second AND circuit; and a delay circuit in response to a signal output from the delay circuit. 5. The clock generation circuit according to claim 4, further comprising: a one-shot pulse circuit for generating a reset signal for the two latch circuits. 6. A memory cell array, read / write means for reading / writing data from / to said memory cell array, and a clock generator for generating first and second internal clock signals in response to an external clock signal A circuit, a clock enable buffer synchronized with the second internal clock signal, receiving an external clock enable signal and outputting an internal clock enable signal, and synchronizing with the first internal clock signal, A control signal buffer for receiving an external control signal for controlling and outputting an internal control signal, wherein the clock generation circuit is enabled in response to an external clock enable signal, and receives a first external clock signal. A clock buffer; a second clock buffer receiving the external clock signal; Activating means for activating the first and second internal clock signals when both the signal output from the clock buffer and the signal output from the second clock buffer are activated; A pulse width control circuit for inactivating two internal clock signals to determine pulse widths of the first and second internal clock signals.