JP2002055878A - Data storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a data storage device capable of remarkably enhancing high speed read and write of data. SOLUTION: The data storage device is constituted by providing a data storage means consisting of plural semiconductor memories, memory units in which the respective semiconductor memories of the data storage means are embedded by being sectionalized into clusters by every plural pieces and on which the respective clusters are freely attachably/detachably mounted as one body, a sorting means to sort and provide the data to be given from the outside to the clusters in the respective memory unit and a write control means to be provided in the respective memory units and to simultaneously write the respective pieces of the data sorted by the sorting means by sorting them into the respective semiconductor memories in the memory unit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and is suitably applied to, for example, a server system for AV (Audio Video) data.

[0002]

2. Description of the Related Art Conventionally, for example, in a broadcasting station, a high image quality is required as a video material, and in particular, a large number of accesses are concentrated on a video material used in a news program in the same time zone. Hard disk drive (HDD: Ha: high rate and large storage capacity)
rd Disc Drive).

However, in this server system, since the hard disk drive has a mechanical mechanism such as a motor,
If an accuracy error occurs at the time of driving, the reliability of data recording / reproduction decreases by that much, but there is a practically insufficient problem such as relatively high power consumption. Has proposed and realized a server system using a flash memory composed of a nonvolatile memory as a data storage medium.

[0004]

The flash memory is a non-volatile memory capable of electrically erasing and rewriting data all at once. When data is written, data that has already been written is erased. Since there is a characteristic that new data cannot be written until after the batch erasing, the writing time becomes longer than the reading time by the time required for the batch erasing of data at the time of writing. There was a problem.

Therefore, in a server system using a flash memory as a data storage medium, there has been a problem that the number of input ports tends to be smaller than the number of output ports as a whole.

For example, in the case of a NAND flash memory, the write speed is 2.5 [Mbyte / sec], whereas the read speed is 20 [Mbyte / sec]. 4 [mse
c], the server system using the NAND flash memory has five output ports and one input port.

Therefore, even when such a flash memory is used as a data storage medium, the problem of the slow writing speed relative to the reading speed peculiar to the flash memory can be solved and practically used for real-time recording / reproducing processing. It would be highly desirable to be able to build a server system that can respond sufficiently.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a data storage device capable of remarkably improving high-speed data reading and writing.

[0009]

According to the present invention, there is provided a data storage unit comprising a plurality of semiconductor memories, and each semiconductor memory of the data storage unit is built in a plurality of clusters. A memory unit that can be removably loaded integrally with each of the clusters, a distribution unit that distributes externally provided data to clusters in each memory unit, and a distribution unit that is provided in each memory unit and is distributed by the distribution unit. Write control means for distributing the obtained data to the respective semiconductor memories in the memory unit and writing the data all at once is provided.

As a result, in this data storage device, a user simply inserts or removes a memory unit selected from a plurality of memory units constituting the data storage means as necessary, and exchanges data with another recording / reproducing device. It can be exchanged, thus avoiding the trouble of performing the electrical data capturing operation according to the user's operation.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Configuration of Server System According to the Present Embodiment In FIG. 1, reference numeral 1 denotes a server system according to the present embodiment as a whole.
Area network), and is connected to a higher-level controller 3 provided externally. Based on various commands given from the higher-level controller 3, a plurality of recording processing blocks 4A to 4C and reproduction processing blocks 5A to 5C and The erase block 6 is controlled individually, and the memory block 8 is controlled via the bus cross switch 7.

Each of the recording processing blocks 4A to 4C has a CPU
After performing predetermined data processing such as compression encoding and format conversion on the video / audio data S1A to S1C supplied from outside based on the recording command C1 given from Video and audio data S2
A to S2C are sent to the memory block 8 via the bus cross switch block 7.

Each of the reproduction processing blocks 5A to 5C has a C
Based on the reproduction command C2 given from the PU2, predetermined data such as decoding or format conversion is performed on the compressed video / audio data S2D to S2F supplied from the memory block 8 via the bus cross switch block 7 as necessary. After the processing, the obtained video and audio data S1D to S1F in the original signal form are output to the outside.

Further, the erasure processing block 6 is configured to execute the operation of each memory unit 8A constituting the memory block 8 based on an erasure command C3 given from the CPU 2 as necessary.
_{1 ~8A N} compressed are recorded for each audiovisual data S
It is adapted to erase only the recording capacity of which is specified in the memory unit 8A ₁ ~8A _N units 2A～S2C.

The server system 1 is a multi-access server that provides a plurality of inputs and outputs (three inputs and three outputs). The server system 1 transmits compressed video and audio data S2A to S2C obtained through each of the recording processing blocks 4A to 4C to a bus cross. through the switch block 7 is adapted to accumulate one by one to a plurality of memory units 8A ₁ ~8A _N in the memory block 8.

[0017] In the memory block 8, all the plurality of memory units 8A ₁ ~8A _N have the same shape and the same structure, are detachably attached respectively corresponding memory block 8 body.

[0018] The server system 1, after reading the designated compressed video and audio data S2D~S2F from each memory unit 8A ₁ ~8A _N to the compressed video and audio data S2D~S2F are accumulated, the corresponding reproduction process The original video / audio data S1D- through blocks 5A-5C
The data is output to the outside as S1F.

Further, in the server system 1, the compressed video and audio data S2A to S2A to
The read / write processing by the memory block 8 in S2F is executed by the CPU so that the compressed video / audio data S2A to S2F to be read / written does not collide with the bus cross switch 7.
2 is performed.

In practice, the CPU 2 sends a switching command C4 based on a control command from the host controller 3 to the bus cross switch block 7 at a predetermined timing to selectively switch the connection state in the bus cross switch block 7. As shown in FIG. 2, the plurality of recording processing blocks 4A to 4C and the plurality of reproduction processing blocks 5A to 5A
For 5C each time (for example, 100 [msec],
Hereinafter, this predetermined time is referred to as an allocated time. T ₁ is cyclically (that is, one cycle TC (= 6T) every 600 [msec].
₁ ) and is connected to the memory block 8.

Then, the CPU 2 determines the assigned time T
₁Supplied via the bus cross switch block 7
A compressed video and audio data S2A to S2C
8 in each memory unit 8A₁ ~ 8A_N Write in order to
Or its allotted time T₁ Compressed video and audio specified in
The voice data S2D to S2F are stored in the corresponding memory block 8
Memory unit 8A₁ ~ 8A_N Read from
Have been.

As described above, in the server system 1, C
Under the control of the PU 2, the writing operation and the reading operation can be performed in a time division manner in the memory block 8, and the data transfer from each of the recording processing blocks 4 A to 4 C to the memory block 8 and the memory block 8 Thus, the writing operation and the reading operation can be performed in parallel without competing with the data transfer to each of the reproduction processing blocks 5A to 5C.

(2) Configuration of Memory Block As shown in FIG. 3, the memory block 8 is composed of a plurality of substrates 9A _{1 to} 9A _X (X is a natural number) electrically interconnected. each substrate 9A ₁ ~9A _X, 4 pieces of those unitized flash memory 10A~10D as access unit of one of the read and write operations (hereinafter, referred to as clusters) plurality 10X is a matrix (10X ₁ ~ 10X _N ).

The actual multiple clusters 10X ₁ ~10X _N constituting the memory block 8 is provided corresponding to Figure 4 in the configuration memory unit 8A in _{1 ~8A N} as shown, the respective memory unit 8A ₁ ~8A _N corresponding substrate 9A ₁ ~9A in array pattern as described above
It is placed on _X.

Each of these memory units 8A _{1 to} 8A _N
Is adapted to be removably attached respectively to the corresponding substrate 9A ₁ ~9A _X, electrically connected to the bus cross switch block 7 through the substrate 9A ₁ ~9A _X during mounting (Fig. 1) It has been made to be.

[0026] In accordance memory unit 8A ₁ ~8A _N, the memory controller 11, host controller 3
Based on the control command (FIG. 1), the CPU 2 reads and writes (R / W: Read / Write) both at the logical "H" level.
A signal S5 and a chip select (CS) signal S6 are received, and an erasing signal S7 for collectively erasing data in each of the flash memories 10A to 10D in cluster units as needed.

[0027] In this case, the period in which falls to logic "L" level of the chip select signal S6, the memory unit 8A ₁ corresponds to the assigned time T ₁ described above for ～8A _N, the assigned time T ₁ The compressed video / audio data S2A to S2C and the address data D1 are supplied from the external bus cross switch block 7 to the data bus 13 and the address bus 14 via the bus switch 12, respectively.

[0028] Inside the memory unit 8A ₁ ~8A _N,
Plural (four) flash memories 10A to 10D and D
A RAM (Dynamic Random Access Memory) 15 are connected to each other via a data bus 13 and address bus 14, each end (i.e. input stage of the memory unit 8A ₁ ~8A _N) of the data bus 13 and address bus 14 A bus switch 12 is provided.

The memory controller 11 transmits both the data bus 13 and the address bus 14 to the external bus cross switch block 7 while transmitting the switching signal S8 at the logic "H" level to the bus switch 12 under the control of the CPU 2. While the connection state is set, the switching signal S8 falls to a logic "L" level at a predetermined timing, whereby both the data bus 13 and the address bus 14 are switched from the bus cross switch block 7 to the disconnected state.

When writing data, the memory controller 11
The control signal S9 is sent to the DRAM 15 in synchronization with the timing at which the read / write signal S5 (FIG. 5A) and the chip select signal S6 (FIG. 5B) both fall to the logic "L" level. The compressed video and audio data S2A to S2C supplied via the data bus 13 (FIG. 5) while sequentially designating addresses based on the address data D1 (FIG. 5C) supplied via the address bus 14.
(D)) is written into the DRAM 15.

[0031] Then the memory controller 11 is, when the allotted time T ₁ is finished in the memory unit 8A ₁ ~8A _N, write signal is in the falling state of the logic "L" in accordance with the control of the CPU 2 S5 (FIG. 5 (A)), the switching signal S8 (FIG. 5 (E)) supplied to the bus switch 12 is lowered to a logic "L" in synchronization with the rising timing, and the control signal S9 is sent to the DRAM 15 to transmit data. While the bus 13 and the address bus 14 are both disconnected from the bus cross switch block 7, the DRAM
15 to read the compressed video and audio data S2A to S2C.

At this time, the memory controller 11 sends control signals S10A to S10D to the plurality of flash memories 10A to 10D, respectively,
4 through the same address data D2 (FIG. 5).
(F)), the compressed video / audio data S2A to S2C read from the DRAM 15 (FIG. 5).
(G)) is striped (separated) in byte units via the data bus 13, and the obtained plurality of data (hereinafter, referred to as compressed separated data) S ₂ X _{1 to} S ₂ X ₄ (FIG. 4) are respectively stored in the flash memory. Writing is performed all at once while sequentially assigning addresses to 10A to 10D.

Eventually, the memory units 8A _{1 to} 8A _N
When the writing of the compressed separation data S2X ₁ ~S2X ₄ to each flash memory 10A~10D is completed, the bus switch 12 switching signal S8 is supplied to a (FIG. 5 (E)) by raising a logic "H" , The data bus 13 and the address bus 14 are both switched to the original connection state with the bus cross switch block 7.

On the other hand, at the time of data reading, the memory controller 11 keeps the read / write signal S5 (FIG. 6A) at the logic "H" level while keeping the chip select signal S5 high.
6 (FIG. 6B) falls to the logical "L" level, and the plurality of flash memories 10A-1A-1
By transmitting the control signals S10A to S10D to the respective flash memories 10A to 10D while sequentially designating the addresses based on the address data D2 (FIG. 6C) supplied via the address bus 14,
From the compressed video / audio data S2A via the data bus 14
To S2C (FIG. 6D).

As a result, each of the memory units 8A _{1 to} 8A
_N writes the supplied compressed video and audio data S2A to S2C into the DRAM 15 once,
From a predetermined timing (that is, the flash memory 10
A-10D is written at the same time) and the compressed video / audio data S2A-S2C is read out and written simultaneously to each flash memory 10A-10D in cluster units, so that the writing speed of the DRAM 15 is reduced to the flash memory 10A. ~10D much a fast frequency than the writing speed of the can as compared to the case of writing directly to the flash memory 10A~10D improve the writing speed of the entire memory unit 8A ₁ ~8A _N.

Generally, flash memories 10A to 10D
Has several tens of times the memory capacity of the DRAM 15 and
When data is transferred from the flash memory 15 to the flash memories 10A to 10D, as shown in FIG.
The memory space of 0A to 10D is divided into blocks corresponding to the total memory capacity of the DRAM 15, and data transfer is performed by sequentially applying all data read from the DRAM 15 to each block.

Further, each of the memory units 8A _{1 to} 8A _N
Is the compressed video / audio data S read from the DRAM 15
2A to S2C are respectively compressed and separated data S2X _{1 to} S2
X ₄ divided into four flash memories 10
Flash memory 10 for writing to A-10D all at once
There is an advantage that a recording / reproducing circuit having a transfer rate about four times the effective transfer rate per one of A to D and a memory capacity about four times as large as that of the flash memories 10A to 10D can be constructed.

In this memory block 8, for example, video / audio data S1A having a data transfer rate of 50 [Mbps].
When recording S1C for one hour, a total of 180 [Gbi
storage capacity t] is required, when using a flash memory 10A~10D having a storage capacity of for example 64 [Mbite] was above the 720 flash memory 10A~10D plurality of substrate 9A on _{1 ~9A X} It must be allocated and arranged in cluster units (ie, 180 clusters).

As a result, the writing speed of the flash memories 10A to 10D having a storage capacity of 64 [Mbite] becomes 2.5 [Mbit].
byte / sec] and the reading speed is 20 [Mbyte / sec],
Cluster 10X of each memory unit 8A in _{1 ~8A N 1}
～10X _N, since and reading speed at writing speed of 80 [Mbyte / sec] is 640 [Mbyte / sec], the data transfer rate for the video and audio data of 50 [Mbyte / sec], the writing speed The reading speed can be increased up to 12 times speed while the speed is 1 times speed.

Actually, in the server system 1, the CPU
Reference numeral 2 denotes a memory (not shown) in which a file system including a directory (file management information) and a table (file distribution index) is stored.
In writing, according to the file management in the file system based on the above command, a free cluster (cluster in which no data is written) 10X _E (E is 1) out of a plurality of clusters 10X _{1 to} 10X _N in the memory block 8 at the time of writing.
≤ E ≤ N (a natural number that satisfies N), or at the time of reading, the cluster 10X _R (R
Is a natural number that satisfies 1 ≦ R ≦ N).

The directory in such a file system
The file name and data attributes (read-only
) Is written in the table, and each cluster 10
X₁ -10X_N What class is the continuation of the file for
Data is written.

More specifically, the directory contains the beginning cluster number of the file, and the table sequentially contains the subsequent cluster number at the corresponding number in the predetermined table area. At this time, the last cluster of the file and the free cluster 10X _{In the case of E} , predetermined setting numbers are respectively entered.

Thus, at the time of writing and reading, the CPU 2
After first searching the files in response in the file system on the first cluster directory, by sequentially searching files subsequent cluster based on the contents of the table one after another, a plurality of clusters 10X ₁ ~10X in the memory block 8 each is configured so as to be able to find the cluster 10X _R as a free cluster 10X _E or read from among the _N.

In response to a file deletion request given by the CPU 2, the upper controller 3 sequentially designates clusters from among a plurality of clusters 10X _{1 to} 10X _N in the memory block 8, and the designated cluster is by sending an erase command to CPU2 so that empty cluster 10X _E, CPU2 is in accordance with the erase command,
A plurality of clusters 10X _{1 to} 10X in the memory block 8
Erase the data of the cluster specified from _N.

At this time, the timing at which the CPU 2 erases the data from the cluster designated in the memory block 8 may be, for example, at the end of one day's work or when the memory capacity of an empty cluster has become equal to or less than a predetermined amount. The data may be sequentially deleted from the less frequent cluster each time, or even when a cluster in which the error correction code is broken is detected.

(3) Management of Memory Block In addition to this configuration, the server system 1
U2 is a memory based on a command from the host controller 3.
Block 8 is assigned to each memory unit 8A₁ ~ 8A_N Dressed every
It is made to manage the presence / absence and file data
I have.

Actually, the CPU 2 operates in each memory unit 8A.
For each _{1 ~8A N,} respectively units Neimu, recording I
D, by allocating the recording capacity and unit entry consisting destination ID or the like in the case strides over other memory units 8A ₁ ~8A _N (Unit Entry) information, based on the respective unit entry information, the corresponding memory Unit 8A
It is adapted to manage _{1 ~8A N.}

Among the unit entry information, the record ID describes information such as a serial number assigned to the video camera, a photographer, a photographing place and a date, and the other memory units 8A ₁ to 8A ₁ . the destination ID when strides over 8A _N, indicating that a memory unit connected after if not fit in the memory units are present are described. In this case, the file continues between the memory units connected to each other by describing the unit name of the preceding memory unit in the link destination ID of the unit entry information corresponding to the subsequent memory unit as the link destination. Is described.

[0049] Further CPU2, if each memory unit 8A ₁ ~8A _N in the memory block 8 is loaded, is adapted to construct a file image FI shown in FIG. 8 (A). This file image FI is stored in each memory unit 8 loaded in the memory block 8.
It has A ₁ ~8A respectively corresponding folder tree (tree) in _N shape connecting structure are adapted to hierarchically assigning a file representing a further data contents in the respective folder as subordinate folders.

Here, the memory unit is stored in the memory block 8.
To 8A₁ ~ 8A_Four , 8A₆ , 8A₇ , 8A₉ , 8A₁₂,
8A_FifteenIs loaded by the user beforehand.
Is a memory unit 8A_Five Is loaded in the memory block 8
Then, the CPU 2 executes the memory unit 8A_Five From
After reading the unit entry information,
8A_Five Folder "Camera Sozai" (memory
Unit 8A_Five File data stored in
File image described above)
It is inserted into the tree structure of the FI (FIG. 8B).

At this time, the CPU 2
After the memory unit 8A ₅ has notified loaded in,
According to the file management in the file system based on a command of the host controller 3, a cluster 10X corresponding to the memory unit 8A ₅ loaded in the memory block 8
To detect the recording capacity.

[0052] The CPU2, by reading the link destination ID of the read unit entry information from the memory unit 8A ₅ loaded, the data exceeding the recording capacity of the recording time of the memory unit 8A _5, is linked subsequent memory units 8A _X (X is a natural number satisfying 1 ≦ X ≦ N) are made so as to record the transfer.

On the other hand, when the memory unit 8A arbitrarily designated by the user is pulled out from the memory block 8, the CPU 2 deletes the unit entry information read from the memory unit 8A, and deletes the unit entry information. 3 is notified as an error that the memory unit 8A has been removed. At this time, CPU2
Deletes the folder corresponding to the extracted memory unit 8A from the tree structure of the file image FI described above.

(4) Write Command Processing Procedure In this server system 1, when receiving a write command from the host controller 3, the CPU 2 enters a write command processing procedure RT1 shown in FIG. 9 from step SP0. while searching for sequential file from the directory and tables in the file system, the routine proceeds to step SP2, free clusters 10X _E from a plurality of clusters 10X ₁ ~10X _N in the memory block 8
It is determined whether or not exists.

[0055] If an affirmative result is obtained in step SP2, this means that there is a free cluster 10X _E to cluster 10X ₁ ~10X _N there are retrieved file, CPU 2 at this time, step SP
Proceed to 3, by switching the bus cross switch block 7, after connecting the free clusters 10X _E in the recording processing block 4A~4C the input side and the memory block 8, to start the write operation in step SP4. At this time, the compressed video and audio data S2A to S2C are stored in the file system.
Is written to a file existing in the cluster 10X in which is written.

Eventually, the CPU 2 advances to step SP5 to determine whether or not the writing has been completed.
This means that the compressed video and audio data S2A~S2C is written to free clusters 10X _E, CPU 2 at this time, ends this write instruction processing procedure RT1 proceeds directly to step SP6.

On the other hand, if a negative result is obtained in step SP5, the CPU 2 proceeds to step SP7 to determine whether there is any remaining memory capacity of each of the flash memories 10A to 10D constituting the cluster, and obtains a positive result. Then, the process returns to step SP5 again, and the same processing as described above is repeated until the remaining memory capacity is exhausted or the writing is completed.

If an affirmative result is obtained in step SP7, this means that there is no remaining memory capacity in each of the flash memories 10A to 10D constituting the clusters 10X _{1 to} 10X _N. returning to step SP2, and repeats the same procedure as described above from the search of the free clusters 10X _E based on the file system.

On the other hand, a negative decision is made in step SP2.
If the result is obtained, this means that the searched file exists
Cluster 10X₁ -10X_N Free cluster 10
X_E Does not exist, and at this time, the CPU 2
Proceeds to step SP8, and indicates that writing is disabled
And the process proceeds to step SP9.
Delete the file (cluster data
Data deletion), and then proceed directly to step SP6.
Then, the write instruction processing procedure RT1 ends.

In response to the file deletion request given by the CPU 2, the upper controller 3 sequentially designates clusters from the plurality of clusters 10X _{1 to} 10X _N in the memory block 8, and the designated cluster is by sending an erase command to CPU2 so that empty cluster 10X _E, CPU2 is in accordance with the erase command,
A plurality of clusters 10X _{1 to} 10X in the memory block 8
Erase the data of the cluster specified from _N.

(5) Read command processing procedure In this server system, when receiving a read command from the host controller 3, the CPU 2 enters a read command processing procedure RT2 shown in FIG. 10 from step SP10, and in step SP11, the file system While searching for a file from the directory and the table, the process proceeds to step SP12 to determine whether or not a file to be read exists.

If an affirmative result is obtained in step SP12, this means that the searched file is a file to be read, and at this time the CPU
In step SP13, the file system determines the relationship between the file and the cluster, such as which cluster the retrieved file corresponds to (or both clusters when a cluster is straddling the file). Search based on.

Subsequently, at step SP14, the CPU
2 detects whether there is a reproduction request simultaneously to cluster 10X _R number of output ports to be read subject (i.e. reproduction processing block 5A~5C the output side) from a plurality of clusters 10X ₁ ~10X _N , The cluster 10
Compressed video and audio data S2C~S2F read from X _R
Is determined to be transferable to all the reproduction processing blocks 5A to 5C for which a reproduction request has been made.

If a positive result is obtained in step SP14, the CPU 2 proceeds to step SP15,
By switching the bus cross switch block 7, after connecting the cluster 10X _R as a read target output side of the reproduction processing block 5A~5C and memory block 8, to start the read operation proceeds to step SP16.

[0065] Eventually CPU2, the process proceeds to step SP17, it is determined whether read end, a positive result is obtained, this is read out compressed video and audio data S2D~S2F from the cluster 10X _R to be read subject At this time, the CPU 2 proceeds to step S
Proceeding to P18, the read instruction processing procedure RT2 is completed.

On the other hand, if a negative result is obtained in step SP17, the CPU 2 returns to step SP13 again, and repeats the same processing procedure from the search of the relationship between the searched file and the cluster 10 based on the file system.

On the other hand, if a negative result is obtained in step SP12, this means that the searched file is not a file to be read. At this time, the CPU 2 proceeds to step SP19, and determines that the file cannot be read. After notifying the host controller 3 of the fact, the process directly proceeds to step SP18 to end the read command processing procedure RT2.

(6) Memory Unit Management Processing Procedure In the server system 1, the CPU 2 actually sends the memory units 8 A _{1 to} 8 A _N from the host controller 3.
When receiving the management command, enter the memory unit management processing procedure RT3 shown in FIG. 11 from step SP20, in step SP21, whether there is a change in state of each memory unit 8A ₁ ~8A _N in the memory block 8 While judging, wait until a positive result is obtained.

If a positive result is obtained in step SP21, the CPU 2 proceeds to step SP22, and determines whether or not the change in the memory block 8 is caused by the loading of the memory unit 8A. If a positive result is obtained, the process proceeds to step SP23.

In this step SP23, the CPU 2
Notifies the upper controller 3 that a new memory unit 8A is loaded in the memory block 8, and
After acquiring the unit entry information from the loaded memory unit 8A, the process proceeds to step SP24 to detect the use state of the cluster 10A accompanying the addition of the memory unit 8A and manage the recording capacity in cluster units. Thereafter, the process proceeds to step SP25.

[0071] On the other hand, if a negative result is obtained in step SP22, that one of the memory units 8A of the memory unit 8A ₁ ~8A _N This is which is previously loaded into the memory block 8 is pulled out by the user At this time, the CPU 2 executes step SP2
6, the memory unit 8A is stored in the memory block 8.
Is notified to the upper-level controller 3 as an error, and the process proceeds to step SP27.

At this step SP27, the CPU 2
After deleting unit entry information corresponding to the extracted memory unit 8A, the process proceeds to step SP28, and the cluster 1 associated with the removal of the memory unit 8A is deleted.
After detecting the use state of 0A and managing the recording capacity in cluster units, the process proceeds to step SP25.

Thus, the CPU 2 executes this step SP2
In 5, it is determined whether or not the current processing is to be terminated in response to a termination command from the upper controller 3 or the user's action, and if an affirmative result is obtained, the process directly proceeds to step SP 29 and proceeds to step SP 29. The unit management processing procedure RT3 ends.

On the other hand, if a negative result is obtained in step SP25, the CPU 2 returns to step SP21 again, and returns to steps SP21 to SP2 described above.
5 or steps SP21-SP22-SP26-SP2
The processing of 8-SP25 is repeated.

(7) Operation and Effect of the Present Embodiment In the above configuration, in the server system 1, the memory block 8 is divided into a plurality (four) of flash memories 10.
Cluster 10X (10X
_{1 to 10} X _N ) built-in memory unit 8A (8A
_{1 to} 8A _N ) are connected to each other in such a manner that they can be removably loaded.

[0076] In the state according to all the memory blocks 8 memory units 8A ₁ ~8A _N is not loaded, the memory unit 8A selected by the user in the free site is loaded, the CPU 2, the memory unit 8A Is detected, and the recording capacity in cluster units is recognized.

At the time of data recording, the CPU 2 transfers the compressed video / audio data S2A to S2F exceeding the recording capacity of the loaded memory unit 8A to another linked memory unit 8A to perform a write operation. Let

[0078] On the other hand, when the memory unit 8A selected by the user among the plurality of memory units 8A ₁ ~8A _N loaded in the memory block 8 is withdrawn,
The CPU 2 detects the use state of the cluster 10X corresponding to the memory unit group 8A other than the memory unit 8A.

When the memory unit 8A is extracted during data recording, the CPU 2 causes the compressed video / audio data S2A to S2F to be written to another memory unit 8A which is a link destination of the extracted memory unit 8A. On the other hand, when the memory unit 8A is pulled out at the time of data reproduction, the CPU 2 notifies the host controller 3 of an error, and skips the data stored in the memory unit 8A and links the other memory unit 8A as a link destination. Reads the data stored in.

As described above, in the server system 1, even when data is exchanged with another recording / reproducing device (for example, a video camera or the like), the memory unit 8A is directly physically
Only need to be exchanged, thus avoiding the complexity of performing the electrical data capturing operation according to the user's operation.

According to the above configuration, this server system
1, a plurality (four) of flash memories 10A to 10A to 10
Cluster 10X (10X₁ -10
X_N ) Built-in memory unit 8A (8A₁ ~ 8A_N
 ) Can be connected in a detachable manner.
To build the memory block 8
This allows other recording / reproducing devices (for example, video cameras)
Etc.) when exchanging data.
Just attach / detach memory unit 8A selected by user
As a result, electrical data acquisition according to the user's operation
Work can be avoided, and
A service that can significantly improve the speed of reading and writing data
The system 1 can be realized.

(8) Other Embodiments In the above-described embodiment, four flash memories 10A to 10D as shown in FIG. it has dealt with the case of applying the memory block 8 the divided cluster 10X (10X ₁ ~10X _N) memory units 8A incorporated (8A ₁ ~8A _N) formed by connecting a plurality, the invention is limited thereto The point is that if a plurality of (three or less or any number of five or more) semiconductor memories are partitioned so as to be read and written in parallel as a cluster, the data storage means may be any other. Various configurations can be widely applied.

In this case, the case where the flash memories 10A to 10D are applied as the semiconductor memory has been described. However, the present invention is not limited to this, and the point is that any semiconductor memory capable of collectively erasing data can be used. In addition to the flash memory, the present invention can be widely applied to various semiconductor memories such as an electrically erasable and writable programmable ROM.

[0084] Furthermore, in the above-described embodiment, and divided into the flash memory of the memory block (data storing means) 8 cluster 10X (semiconductor memory) 10A to 10D are each plurality (10X ₁ ~10X _N) Internal are, each such cluster 10X (10X ₁ ~10X _N) can be loaded detachably integrally a memory unit 8A (8
A _{1 to} 8A _N ), a memory unit 8A (8) for constructing a memory block 8 in the server system 1 shown in FIG.
It has dealt with the case of applying the A ₁ ~8A _N), the present invention is not limited thereto, detachably loaded if each cluster integrally, can be widely applied to other various memory units .

[0085] In the above embodiment, the cluster 10X in audiovisual data S1A～S1C (i.e. compressed video and audio data S2A～S2C) each memory unit 8A externally applied (8A ₁ ~8A _N) (10
X _{1 to} 10 X _N )
Although the case where the CPU 2 and the bus cross switch block 7 in the server system 1 shown in FIG. 1 are applied has been described, the present invention is not limited to this, and if data can be distributed to each cluster, other various distribution means Can be widely applied to.

In this case, the CPU 2 and the bus cross switch block 7 in the server system 1 as distribution means
FIG. 1 shows the supplied compressed video and audio data S2A to S2S.
2C is a case has been described to give after splitting it into one memory unit 8A ₁ ~8A _N in order, and striping (separation) of the compressed video and audio data S2A~S2C to be fed to a predetermined unit, obtained a plurality of compressed separation data each memory unit (not shown) 8A was _{1 ~8A N}
And may be written in parallel. As a result, the writing speed can be remarkably increased as compared with the case of the present embodiment, because the writing is performed in parallel.

Further, in the above-described embodiment, each
Raster 10X (10X₁ -10X_N ) Provided by the bus
Compression distributed via cross switch block 7
The video and audio data S2A to S2C are stored in the cluster 10X.
(10X₁ -10X_N ))
The write control means for distributing to 0D and writing all at once is
CPU 2 in server system 1 shown in FIG.
Each memory unit 8A₁ ~ 8A_N Memory control in
Described the case where it is configured from the controller 11
However, the present invention is not limited to this, and the point is that each file is
Rush memory (semiconductor memory) 10A to 10D all at once
If data can be written to
It can be widely applied to control means.

Further, in the above embodiment, the memo
Reunit 8A (8A₁ ~ 8A_N ) Is a memory block
(Data storage means) When loaded into the memory unit 8,
Knit 8A (8A₁ ~ 8A_N )
Based on the client entry information (management information).
Star 10X (10X₁ -10X_N ) Detect the storage capacity
After that, if the storage capacity is exceeded, another memory
8A (8A₁ ~ 8A_N ) For data transfer
Although the description has been made of the case in which
The main point is that the memory unit loaded by the user is
Record data even when the recording capacity of
If it is possible, not only the other memory units 8A but also D
Transfer to various recording means such as RAM 15 for recording
You may do it.

Further, in the above-described embodiment, a cluster including flash memories (semiconductor memories) 10A to 10D in which designated compressed video / audio data S2D to S2F are written out of memory blocks (data storage means) 8. 10X for (10X ₁ ~10X _N), the read from the cluster 10X each flash memory (semiconductor memory) of (10X ₁ ~10X _N) in 10A~10D simultaneously compressed separation data S2X ₁ ~S2X _N, compressed video and audio data Read control means for restoring to S2D to S2F,
It has dealt with the case of constituting a memory controller 11 of each memory unit 8A in ₁ ～8A _N shown in CPU2 and 4 in the server system 1 shown in FIG. 1, the present invention is not limited to this, short If data can be simultaneously read from each of the flash memories (semiconductor memories) 10A to 10D in cluster units, it can be widely applied to various other read control means.

Further, in the above embodiment, the compressed video and audio data S2A to S2F and each flash memory 1
At the time of writing, the compressed video / audio data S
Free cluster 10X in which 2A to S2F are not written
While searching for _E per cluster, at the time of reading, it has dealt with the case of searching the cluster 10X _R to be read subject specified compressed video and audio data S2A~S2F is written for each cluster, the invention is not limited thereto. in short, by the file management based on the file system, in units of clusters, research free cluster 10X _E during writing, and is possible to search the cluster 10X _R to be read subject at the time of reading If possible, various other file management methods may be used.

Further, in the above-described embodiment, a plurality of recording processing blocks 4A to 4A as a plurality of input / output means are provided.
C and a plurality of reproduction processing blocks 5A-5C, respectively by allocating a predetermined allocation time T ₁ cyclically, for each said allocated time T _1, the memory unit 8A (8A ₁ ~
8A _N ), when the write operation and the read operation are performed in a time-division manner, the compressed video / audio data S2A to S2F are input / output through the corresponding recording processing blocks 4A to 4C and the corresponding reproduction processing blocks 5A to 5C. However, the present invention is not limited to this, and the point is that the compressed video transferred via the plurality of recording processing blocks 4A to 4C and the plurality of reproduction processing blocks 5A to 5C at the time of writing and reading is important. while preventing voice data S2A~S2F is from clashing the bus cross switch block 7, the writing operation and the reading operation if it is possible to parallel performed on the memory unit 8A (8A ₁ ~8A _N), this Data control may be performed based on various other time management methods.

Further, in the above-described embodiment, the case where the present invention is applied to the server system 1 configured as shown in FIG. 1 has been described. However, the present invention is not limited to this, and The present invention can be widely applied to various systems other than reading and writing video / audio data S2A to S2F or various other data from / to a plurality of semiconductor memories.

[0093]

As described above, according to the present invention, the data storage means comprising a plurality of semiconductor memories and each semiconductor memory of the data storage means are divided into a plurality of clusters and built therein. A memory unit that can be removably loaded as a unit, distribution means for distributing data given from the outside to clusters in each memory unit, and data provided in each memory unit and distributed by the distribution means. By providing the writing control means for distributing and writing to all the semiconductor memories in the memory unit at the same time, by simply attaching and detaching a memory unit selected by a user as needed among a plurality of memory units, Data can be exchanged with other recording / reproducing devices, and as a result, electrical data acquisition according to user operations is performed. Can avoid the complexity of performing only work, thus the data storage device can be realized capable of significantly enhancing high speed in reading and writing data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a server system according to the present embodiment.

FIG. 2 is a schematic diagram for explaining a read / write control process by a CPU shown in FIG. 1;

FIG. 3 is a schematic diagram illustrating an internal configuration of a memory block illustrated in FIG. 1;

FIG. 4 is a block diagram showing an internal configuration of a memory unit according to the present embodiment.

FIG. 5 is a timing chart for explaining an operation timing at the time of data writing;

FIG. 6 is a timing chart for explaining an operation timing when reading data;

FIG. 7 is a schematic diagram illustrating a state of data transfer from a DRAM to a flash memory;

FIG. 8 is a schematic plan view for explaining a file image of each memory unit.

FIG. 9 is a flowchart for explaining a write instruction processing procedure;

FIG. 10 is a flowchart for explaining a read command processing procedure;

FIG. 11 is a flowchart for explaining a memory unit management processing procedure;

[Explanation of symbols]

1 server system, 2 CPU, 3 upper controller, 4A-4C recording processing block, 5A-5
C: Reproduction processing block, 6: Erasure processing block, 7
...... bus cross switch block, 8 ...... memory blocks, 8A ₁ ~8A _N ...... memory unit, 9A ₁ ~9A
_X ...... board, 10X ₁ ~10X _N ...... cluster, 10A
_E: Empty cluster, 10A _R: Cluster to be read, 10A to 10D: Flash memory, 11:
Memory controller, 12 Bus switch, 13
Data bus, 14 ... Address bus, 15 ... DRA
M, FI ...... file image, S1A~S1F ...... video and audio data, S2A~S2F ...... compressed video and audio data, S2X ₁ ~S2X _N ...... compression separation data.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B060 AA12 AA20 AC11 CA14 MM01 5B065 BA05 CA07 CA40 CC03 CC08 CH13 EK01 5C052 AA17 AB02 CC11 DD04 GA09 GB01 GC05 GD09 GE00 GE06 GF01 GF04

Claims (4)

[Claims] 1. A data storage means comprising a plurality of semiconductor memories, wherein each of said semiconductor memories of said data storage means is divided into a plurality of clusters and built therein, and said clusters are removably mountable as one unit. A memory unit, distribution means for distributing data provided from outside to clusters in each of the memory units, and providing each of the data provided in each of the memory units and distributed by the distribution means in the memory unit. And a write control means for distributing the data to each of the semiconductor memories and writing the data all at once. 2. When the memory unit is loaded, the write control means detects a storage capacity of a corresponding cluster based on management information stored in the memory unit, and then determines the storage capacity. 2. The data storage device according to claim 1, wherein when the number exceeds the limit, the other memory unit is designated as a data transfer target. 3. The write control means for distributing, from the data storage means, the memory unit including the semiconductor memory in which the designated data is written, from each of the semiconductor memories in the memory unit. 2. The data storage device according to claim 1, further comprising: read control means for simultaneously reading out the written data and restoring the data distributed by the distribution means. 4. The data storage device according to claim 3, wherein said read control means recognizes that the memory unit has been removed as an error when the memory unit is removed.