JP2002050198A - Non-volatile semiconductor memory and its testing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a testing time for short-circuiting of a decoder and a bit line in testing a flash EEPROM. SOLUTION: This memory is provided with a memory cell array 6 in which memory cells which can electrically rewrite data are arranged in a matrix in the directions of row and column, a row decoder 5, and a column decoder 1, dummy cells 8(B, i), 8(D, i), 8(F, i), 8(H, i) of (i) rows in which memory cells are arranged in only even numbered columns (or odd numbered columns) of the memory cell columns, after erasing all bits, dummy cell rows are read out successively, and short-circuiting between bit lines is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting an electrically rewritable nonvolatile semiconductor memory, and more particularly to a method for inspecting an electrically rewritable nonvolatile semiconductor memory.
EP-ROM, EEP-ROM, and flash EE
The present invention relates to an inspection method for a P-ROM or the like.

[0002]

2. Description of the Related Art In recent years, the demand for flash EEP-ROMs has rapidly increased, and the number of flash EEP-ROMs has been increasing. inside that,
In the inspection process, it is desired to perform more complete screening in a short time.

The following (conventional example 1) is a conventional inspection method.
(Conventional Example 2) will be described. (Conventional Example 1) FIG. 9 shows a general 64-bit nonvolatile semiconductor memory.

A0, A1 and A2 are input to the column decoder 1 and select the memory cells 3 in the column direction according to the address. A3, A4, and A5 are input to the row decoder 2,
The row direction of the memory cell 3 is selected according to the address.
The memory cells 3 are 64-bit flash EEPROM cells arranged in a matrix. The source control circuit 4 controls the source potential of the memory cell 3.

FIG. 10 shows general memory cell data used at the time of detecting a bit line short, and is referred to as a detection pattern 1. Each square represents one bit of the memory cell 3, and "0" and "1" written therein indicate data of the memory cell. Here, the memory cell data in the erased state is “1”, and the memory cell data in the written state is “1”.
0 ". A, B, C, D, E, F, G, and H indicate bit line numbers, and a, b, c, d, e, f, g, and h indicate word line numbers. The memory cell in column a row is replaced with cell (A,
a).

FIG. 11 shows general memory cell data used when detecting a short circuit between memory cells.
This is referred to as detection pattern 2. FIG. 12 is an explanatory diagram of the simultaneous writing pattern 2.

[0007] First, the memory cell is entirely erased (all memory cell data "1"), and the pattern shown in FIG. 11 is written. FIG. 12 shows a pattern to be written when the bit lines C and D are short-circuited in the decoder or on the bit lines.

Since the cell (C, a) is not written, the cell (D, a) is written because the bit line C is short-circuited with the adjacent bit line D, although the data should be "1". At the same time, the data becomes "0". Similarly, cell (C, c), cell (C,
e), cell (C, g), cell (D, b), cell (D,
d), cell (D, f), and cell (D, h) also have data "
0 ".

In this manner, a short circuit of a decoder or a bit line can be detected. However, Flash E
Since the writing and erasing characteristics of EP-ROM are very slow,
An increase in the number of rewrites in the inspection greatly affects the inspection time.

(Conventional Example 2) A second conventional method for inspecting a nonvolatile semiconductor memory will be described with reference to the drawings.

FIGS. 13 to 15 show write data of a memory cell expressed in the same expression as in FIG. First, all the memory cells are erased and data is set to "1" (FIG. 1).
3). Next, the cell (A, a) is read with an expected value “1”,
If PASS is performed, writing is performed (FIG. 14). Further, the cell (B, a) is similarly read and written with the expected value “1”.

At this time, if the bit line A and the bit line B are short-circuited in the column decoder, and the cell (A, a) is selected and written, the cell (B, a) is simultaneously written. ) Is also selected, so that writing is also performed on the cell (B, a) (FIG. 15).

Therefore, when reading is performed with the expected value "1", FAIL is performed. Thereafter, similarly, cells (C,
a), cell (D, a), cell (E, a), cell (F,
By performing the same operation on a), cell (G, a), and cell (H, a), all short circuits in the column decoder can be detected.

However, a flash EEPROM-ROM
Since the writing and erasing characteristics are very slow, an increase in the number of rewrites in the inspection greatly affects the inspection time.

[0015]

In such a nonvolatile semiconductor memory, a short circuit of a decoder and a bit line can be detected, but there is a problem that a test time is increased.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of performing a short-circuit detection of a decoder and a bit line of a nonvolatile semiconductor memory in a short time, and an inspection method thereof. And

[0017]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory including a memory cell array in which electrically rewritable memory cells are arranged in rows and columns in a matrix. , A row decoder that receives an X address signal and selects a row of the memory cell array, and a column decoder that receives a Y address signal and selects a column of the memory cell array, wherein the memory cell array includes a memory cell. A dummy cell row in which memory cells are arranged only in even columns or odd columns is arranged.

According to a second aspect of the present invention, there is provided the nonvolatile semiconductor memory according to the first aspect, wherein the dummy cell row is arranged farthest from a column decoder.
The nonvolatile semiconductor memory according to a third aspect of the present invention is the nonvolatile semiconductor memory according to the second aspect, further comprising a word line boosting circuit for boosting a power supply voltage VDD to the dummy cell row and applying a voltage higher than a threshold voltage of the memory cell. It is characterized by having done.

According to a fourth aspect of the present invention, there is provided a nonvolatile semiconductor memory, comprising a memory cell array in which electrically rewritable memory cells are arranged in a matrix in the row and column directions, and an X address signal. A row decoder for selecting a row of the memory cell array, and a column decoder for receiving a Y address signal and selecting a column of the memory cell array. The memory cell array has a data latch for each bit line. A latch circuit is provided.

According to a fifth aspect of the present invention, there is provided a method for testing a nonvolatile semiconductor memory, comprising: a memory cell column of a memory cell array in which electrically rewritable memory cells are arranged in a matrix in a row and column direction; A dummy cell in which memory cells are arranged only in even or odd columns is formed in advance, and after erasing all bits, the dummy cell rows are sequentially read to detect a short circuit between bit lines.

According to a sixth aspect of the present invention, in the inspection method of the nonvolatile semiconductor memory according to the fifth aspect, the dummy cell rows are arranged in advance at a position farthest from the column decoder, and after all bits are erased, the dummy cell rows are sequentially arranged. It is characterized by reading and detecting disconnection of a bit line.

According to a seventh aspect of the present invention, in the inspection method of the nonvolatile semiconductor memory according to the fifth aspect, the power supply voltage VDD is boosted to the dummy cell row in a diffusion completed state and is higher than the threshold voltage of the memory cell. The method is characterized in that a voltage is applied from a word line booster circuit to which a voltage is applied and the voltage is sequentially read to detect a short circuit between bit lines.

According to an eighth aspect of the present invention, there is provided a method for testing a nonvolatile semiconductor memory, comprising: a memory cell array in which electrically rewritable memory cells are arranged in a matrix in the row and column directions; In testing a nonvolatile semiconductor memory in which an X address and a Y address are selected by a row decoder and a column decoder, a latch circuit for data latch is previously formed on each bit line of the memory cell array, and the data of the latch circuit is Are set to the first value, the first value is sequentially read out, the second value is written, and short-circuit detection in the decoder is performed.

[0024]

(Embodiment 1) FIGS. 1 to 4 show (Embodiment 1) of the present invention.

FIG. 1 shows a 64-bit nonvolatile semiconductor memory represented by the same expression as FIG. FIG. 2 to FIG.
This is the write data of the memory cell represented by the same expression as 0.

The nonvolatile semiconductor memory shown in FIG. 1 includes a column decoder 1, a row decoder 5, a memory cell 6, and a source control circuit 4. The memory cell 6 is a cell (A, a)
To a cell (H, h) of 64 bits (flash type EEP-ROM cell) and dummy cells 8 (B, i), 8 (D, i), 8 for bit line short check.
(F, i) and 8 (H, i). In this dummy cell, an N-channel transistor is formed at each address in advance at the same time as the 64-bit memory cell, and is arranged.

The row decoder 5 has A3, A4, A5,
DMX that specifies the selection of the dummy cell in the i-th row is input, the row direction of the memory cell is selected according to the address, and the memory cell in the i-th row is selected only when DMX is input.

The operation of this circuit will be described with reference to FIGS. First, all the memory cells are erased and the data is set to "1".
(FIG. 2). Next, the column i and row i are read with the expected value “1”. However, there is no memory cell in column A and row i. In the flash EEP-ROM, data is rewritten by manipulating Vt of a memory cell, and data is set to "1" when a selected cell flows, and "0" when no current flows. Therefore, when there is no memory cell and no current flows, data "0" is recognized. That is, the expected value of the data to be read is as shown in FIG.
become.

However, if the bit line C and the bit line D are short-circuited in the decoder or on the bit line, the data read out from the cell is as shown in FIG. 4, and the short-circuit of the bit line can be detected. As a result, a short circuit between bit lines can be detected without increasing the number of rewrites, and an increase in inspection time can be slightly suppressed as compared with the conventional inspection method.

In the above (Embodiment 1), the dummy cells are arranged only in the even columns B, D, F and H of the memory cell columns, but are arranged only in the odd columns A, C, E and G. The same can be applied.

The power supply voltage VDD is applied to the dummy cell row.
In the case where a word line boosting circuit for boosting the threshold voltage and applying a voltage higher than the threshold voltage of the memory cell is mounted, the same effect as described above can be obtained without a rewriting operation. Immediately after the end of manufacturing, Vt (threshold voltage) is distributed around about 3 volts in the memory cell. Vt is changed to about 5 volts in the writing state and to about 2 volts in the erasing state. Therefore, since accurate reading cannot be performed when Vt is about 3 volts, in the above embodiment, reading is performed after erasing once. On the other hand, by increasing the gate voltage at the time of reading, the same effect as that of Vt being relatively lowered can be obtained, and reading can be realized without performing the erasing operation.

(Embodiment 2) FIGS. 5 to 8 show (Embodiment 2) of the present invention. FIG. 5 is a 64-bit non-volatile semiconductor memory represented by the same expression as FIG.
Is write data of a memory cell expressed in the same expression as in FIG.

The nonvolatile semiconductor memory shown in FIG. 5 includes a column decoder 1, a row decoder 5, a memory cell 3, a source control circuit 4, and a plurality of latch circuits 7A to 7H. Here, in the latch circuits 7A to 7H, the latch circuit 7A is arranged at an address (A, i), and the latch circuits 7B to 7H are arranged at addresses (B, i) to (H, i). The latch circuits 7A to 7H are formed and arranged at the same time as the memory cells 3.

The memory cell 3 is a 64-bit memory cell (flash type E) of cells (A, a) to (H, h).
EP-ROM cell). A3, A4, A5 and DMX designating selection of the dummy cell in the i-th row are input to the row decoder 5, and the row direction of the memory cell is selected according to the address. Only the i row provided with the latch circuits 7A to 7H is selected.

The latch circuits 7A to 7H latch bit line data when a dummy cell row i is input in a write operation, and latch data when a dummy cell row i is input in a read operation. Is output to the bit line.

The operation of this circuit will be described with reference to FIGS. Rows i in FIGS. 6 to 8 are data latched by the latch circuits 7A to 7H. At the time of inspection, the data of the latch circuit is first set to "1" (FIG. 6). Next, the cell (A, i) is read with the expected value “1”, and is written if PASS is performed (FIG. 7). Further, similarly, the cells (B,
i) also executes reading and writing with the expected value “1”. At this time, if there is a short circuit in the column decoder and the bit lines A and B are short circuited, the cell (A,
When cell i is selected and written, cell (B, i) is selected at the same time, so cell (B, i) is also written (FIG. 8). Therefore, FAIL is performed when reading is performed with the expected value “1”. Hereafter, similarly,
The same operation is performed for the cell (C, i), the cell (D, i), the cell (E, i), the cell (F, i), the cell (G, i), and the cell (H, i). , All short circuits in the column decoder can be detected. Also, since a latch circuit is used for writing, high-speed rewriting can be realized. This allows
A short circuit between bit lines can be detected at high speed, and an increase in inspection time can be slightly suppressed as compared with the conventional inspection method.

[0037]

As described above, in the nonvolatile semiconductor memory device of the present invention, dummy cells in which memory cells are arranged only in even columns (or odd columns) of a memory cell array of a memory cell array are arranged, and all bits are erased. Thereafter, the dummy cell rows are sequentially read to detect a short circuit between the bit lines, so that a bit line short circuit and a decoder short circuit can be realized in a shorter inspection time as compared with the related art.

Further, a latch circuit for data latch is formed in advance on each bit line of the memory cell array, and after all the data of the latch circuit are set to the first value, the first value is sequentially read out. , The second value is written, and short-circuit detection in the decoder is performed.

[Brief description of the drawings]

FIG. 1 shows a flash EE according to a first embodiment of the present invention.
PROM circuit diagram

FIG. 2 is an explanatory diagram of a write pattern 1 according to the first embodiment.

FIG. 3 is an explanatory diagram of a write pattern 2 according to the first embodiment.

FIG. 4 is an explanatory diagram of a write pattern 3 in the first embodiment.

FIG. 5 is a diagram illustrating a flash EE according to a second embodiment of the present invention.
PROM circuit diagram

FIG. 6 is an explanatory diagram of a write pattern 1 according to the second embodiment.

FIG. 7 is an explanatory diagram of a write pattern 2 in the second embodiment.

FIG. 8 is an explanatory diagram of a write pattern 3 in the second embodiment.

FIG. 9 is a circuit diagram of a general flash EEPROM.

FIG. 10 is an explanatory diagram of a bit line short detection pattern 1 of a general flash EEPROM.

FIG. 11 is an explanatory diagram of a bit line short detection pattern 2 of a general flash EEPROM.

FIG. 12 is an explanatory diagram of a bit line short detection pattern 3 of a general flash EEPROM.

FIG. 13 is an explanatory diagram of a decoder short detection pattern 1 of a general flash EEPROM.

FIG. 14 is an explanatory diagram of a decoder short detection pattern 2 of a general flash EEPROM.

FIG. 15 is an explanatory diagram of a decoder short detection pattern 3 of a general flash EEPROM.

[Explanation of symbols]

1 column decoder 3 memory cell 4 source control circuit 5 row decoder 6 memory cell 7A to 7H latch circuit 8 (B, i), 8 (D, i), 8 (F, i), 8 (H,
i) Dummy cells A, B, C, D, E, F, G, H Bit line numbers a, b, c, d, e, f, g, h Word line numbers i Dummy cell row

Claims (8)

[Claims] 1. A memory cell array in which electrically rewritable memory cells are arranged in a matrix in a row and column direction, and a row decoder which receives an X address signal and selects a row of the memory cell array. And a column decoder that receives a Y address signal and selects a column of the memory cell array. The memory cell array includes a dummy cell row in which memory cells are arranged only in even or odd columns of memory cell columns. Non-volatile semiconductor memory arranged. 2. The nonvolatile semiconductor memory according to claim 1, wherein said dummy cell row is arranged farthest from a column decoder. 3. The nonvolatile semiconductor memory according to claim 2, further comprising a word line boosting circuit for boosting a power supply voltage VDD and applying a voltage higher than a threshold voltage of the memory cell to said dummy cell row. 4. A memory cell array in which electrically rewritable memory cells are arranged in a matrix in a row and column direction, and a row decoder which receives an X address signal and selects a row of the memory cell array. And a column decoder which receives a Y address signal and selects a column of the memory cell array, wherein the memory cell array has a latch circuit for data latch arranged on each bit line. 5. A dummy cell having memory cells arranged only in even or odd columns of a memory cell column of a memory cell array in which electrically rewritable data memory cells are arranged in a matrix in the row and column directions. A method for inspecting a nonvolatile semiconductor memory, which is formed in advance and sequentially reads out the dummy cell rows and detects a short circuit between bit lines after erasing all bits. 6. The inspection of a nonvolatile semiconductor memory according to claim 5, wherein said dummy cell row is previously arranged at a position farthest from a column decoder, and after all bits are erased, said dummy cell row is sequentially read to detect a bit line disconnection. Method. 7. A voltage is applied from a word line booster circuit which boosts a power supply voltage VDD to the dummy cell row and applies a voltage higher than a threshold voltage of a memory cell in a diffusion completed state to sequentially read out the bit lines. 6. The inspection method for a nonvolatile semiconductor memory according to claim 5, wherein a short circuit is detected. 8. A nonvolatile memory for selecting an X address and a Y address by a row decoder and a column decoder for a memory cell array in which electrically rewritable memory cells are arranged in a matrix in the row and column directions. When testing a non-volatile semiconductor memory, a latch circuit for data latch is formed in advance on each bit line of the memory cell array, and after all the data of the latch circuit are set to a first value, the first A method for inspecting a nonvolatile semiconductor memory, in which the value of (i) is read, the second value is written, and a short circuit in the decoder is detected.