JP2002050045A - Recorder and recording method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that the recording operation performing by appropriately generating a light pulse against the fluctuation of the linear velocity of an optical disk is difficult for a consumer use optical disk device from a standpoint of the device performance and also the cost although it is allowed by using a high frequency clock, and also keeping the time accuracy of a specified value or lower is difficult for the light pulse when plural fixed delay lines are used. SOLUTION: The duty of a 2nd clock is maintained to 50% by a 1st loop consisting of a 1st error signal adding means 22, a buffer 24 and a 1st error signal extracting means 25. The duty control pulse is stably generated by a 2nd loop consisting of a 2nd error signal adding means 23, a digital signal processing means 21 and a 2nd error signal extracting means 26. By the digital signal processing means 21, two pulses PP and MP are generated from the 2nd and 4th clocks and recording data. By subtracting these pulses PP and MP by an operational amplifier 27, the light pulse is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a recording apparatus and a recording method, and more particularly to a recording apparatus and a recording method for recording a digital information signal on a rewritable optical disk by generating a strategy.

[0002]

2. Description of the Related Art Conventionally, in the field of rewritable optical disks such as DVD-RW, further increase in information recording density has been promoted. The mark edge recording employed in the field of the rewritable optical disk can increase the recording density as compared with the mark position recording, but causes more data errors due to the mark shape distortion than the mark position recording. As a technique for suppressing the shape distortion of a mark, there is a write strategy technique. This technique divides a recording waveform by a laser beam into a plurality of short pulses and irradiates the optical disc with a writing laser beam, and suppresses heat accumulation at the rear end of the recording mark to eliminate distortion of the recording mark. It was made.

For example, a write strategy technique used for a DVD-RW uses a plurality of laser pulses having three types of power levels. The three types of power levels are a peak power (write power), a medium power (erase power), and a bias power (read power) in order from the highest level. When the optical disk is irradiated with the laser light having the above peak power, the recording film of the optical disk is melted. Thereafter, when the optical disk is rapidly cooled, the optical disk becomes an amorphous state (amorphous state), and the light reflectance decreases. This is used as a recording mark. For example, a peak power requires an optical output of about 11 mW.

When the optical disk is irradiated with a medium power laser beam, the recording film of the optical disk is brought into a crystalline state. The portion of the optical disk that was in an amorphous state before the irradiation with the laser beam becomes crystalline, and the portion of the optical disk that was originally in a crystalline state remains in a crystalline state. This allows
Record marks can be deleted. The optical output of the semiconductor laser required for erasing a recording mark is, for example, about 5 mW. The laser beam of the bias power is used for reading an information signal recorded on the optical disc.

As an example, FIG. 11 shows a basic specification of a write strategy in a DVD-RW. FIG. 3A shows the recording data after NRZI (Non Return to Zero Inverted) conversion, and FIG. 3B shows the write pulse input to the laser light source. This write pulse is generated as shown in FIG.
The top pulse I of the width Ttop synchronized with the rise of the recording data (information signal) after the NRZI conversion, the multi-pulse II of the period "1" of the following recording data, and the width of the period "0" of the recording data Tcl cooling pulse III
Consists of The multi-pulse II is a pulse train in which a peak power level having a width Tmp and a bias power level having a width (T-Tmp) are alternately repeated. The multi-pulse is used to suppress heat accumulation during recording. It is. Here, T is a bit period of one bit of the recording data.

Here, the falling edge of the top pulse I is set to be a position delayed by 2T from the rising edge of the recording data after NRZI conversion, and the multipulse II starts from the position delayed by 2T, NR
It is set to end at the multi-value falling edge position of the recording data after ZI conversion. Also, the cooling pulse III is
It is set to start from the falling edge of the recording data after NRZI conversion. The above widths Ttop, Tmp,
Various values can be set for Tcl. However, even if the linear velocity fluctuates due to uneven rotation of the disk, that is, even if the bit period T fluctuates, it is displayed at a constant ratio to T. Since it is desirable to set the position to the position T, it is basically expressed as a ratio to T, and Ttop = 0.50
T, Tmp = 0.40T, and Tcl = 0.60T are recommended values.

[0007]

However, the widths Ttop and Tm are set with respect to the bit period T of the recording data.
It is possible to control p and Tcl to a position represented by a fixed ratio by using a clock of a higher frequency synchronized with T, but such a control is required in a consumer optical disk device which requires strict price reduction. It is difficult to use a very high clock in terms of device performance and cost. Therefore, in practice, the above-described write pulse is generated using a plurality of fixed delay lines or using an output from a tap close to a target position from another-stage delay block cut in fine steps.

However, since the measurement is directly affected by temperature characteristics and variations, even if calibration is performed to measure the number of steps corresponding to the length of T, a time accuracy of the order of several nanoseconds or 1 nsec or less is obtained. Is difficult to keep.

Further, multi-speed recording (2X, 10X, 20X, etc.) having the merit of high speed is expected in the future, but it is desirable that the write pulse also follows the change in the linear velocity. However, using the multi-stage delay block described above,
Although there is a method of switching the delay amount according to the speed, it is still difficult to maintain time accuracy of the order of several nanoseconds or 1 nsec or less.

In the future, CAV recording and ZCAV recording, which have the advantage that the spindle motor can be downsized by keeping the rotation speed of the disk constant, are expected in the field of optical disks. Therefore, it is desirable that the write pulse also follows. Again, using the multi-stage delay block described above,
Although it is conceivable to switch the delay amount according to the disk radial position, it is also difficult to maintain the time accuracy on the order of several nanoseconds or 1 nsec or less.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a recording apparatus and a recording method capable of recording an information signal by generating a write pulse adaptively following a variation in disk rotation or a change in linear velocity without using a high-frequency clock.

[0012]

In order to achieve the above object, a recording apparatus according to the present invention uses a strategy generation circuit to support a write strategy based on a first clock synchronized with recording data and recording data. In a recording apparatus for generating a write pulse and driving a writing light source to record recording data on an optical recording medium based on a laser beam emitted from the writing light source, the strategy generation circuit includes a first clock. Error signal adding means for adding an error signal to the second clock to generate a second clock; clock generating means for shaping the waveform of the second clock by a comparator operation to generate a third clock; The frequency component is extracted as an error signal and supplied to the error signal adding means, and the error signal extraction for maintaining the duty of the second clock at 50% is performed. It is obtained by a structure having a unit.

According to the present invention, the duty of the internal clock of the strategy generating circuit can be maintained at 50% by the loop including the error signal adding means, the clock generating means, and the error signal extracting means.

In order to achieve the above object, the recording apparatus of the present invention generates a write pulse corresponding to a write strategy by a strategy generation circuit based on a first clock synchronized with recording data and the recording data. In a recording apparatus that generates and drives a light source for writing and records recording data on an optical recording medium based on a laser beam emitted from the light source for writing, a strategy generation circuit includes:
An error signal adding means for adding an error signal to the clock of the second clock to generate a second clock, a timing of rising or falling of a clock corresponding to the first clock, receiving the second clock and the recording data as inputs. And a duty control pulse in which the relationship between the falling and rising timings of the clock corresponding to the second clock is maintained at a fixed rate with respect to the period of the first clock. The configuration includes a pulse generation unit that generates a write pulse corresponding to the pulse, and an error signal extraction unit that extracts a low-frequency component of the duty control pulse as an error signal and supplies the error signal to the error signal addition unit.

According to the present invention, the duty of the internal clock of the strategy generating circuit can be maintained at an arbitrary value by the loop including the error signal adding means, the pulse generating means, and the error signal extracting means.

In order to achieve the above object, according to the present invention, the above-mentioned pulse generation means sets the rising or falling edge of a clock corresponding to the first clock to a trailing edge or a leading edge, and First means for generating an m-pulse having the leading or trailing edge of the falling or rising edge of the clock corresponding to the clock, and when the duty ratio of the m-pulse is m: n (where m + n = 1) , When the natural number p times the difference between m and n becomes the natural number q, the logical value “1” of the m pulses is forcibly changed to the logical value “0” or “1” at a rate of q times in the p period of the second clock. And a second means for generating the duty control pulse indicated by "".

According to the present invention, in order to achieve the above object, in place of the above error signal adding means, a variable delay means for variably controlling a delay time with respect to a first clock according to the level of an error signal. May be provided.

In order to achieve the above object, the method of the present invention generates a write pulse corresponding to a write strategy based on recording data synchronized with a first clock and the first clock. In a recording method for recording recording data on an optical recording medium based on a laser beam driven by a pulse, a first step of adding a first error signal to a first clock to generate a second clock Generating a third clock by shaping the waveform of the second clock by a comparator operation, and adding a second error signal to the first clock or the second clock to generate a fourth clock. Step 2, the rising or falling timing of the clock corresponding to the second clock, and the falling or rising edge of the clock corresponding to the fourth clock. A third step of generating a duty control pulse in which the relationship with the rising timing is maintained at a constant rate with respect to the cycle of the first or second clock; A fourth step of extracting a low frequency component of the duty control pulse as a second error signal; a sixth step of generating a write pulse corresponding to the recording data and the duty control pulse; And a step of:

According to the present invention, a write pulse can be generated without using a clock having a repetition frequency higher than the repetition frequency of the first to fourth clocks.

[0020]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the recording apparatus according to the present invention. In the figure, an information signal extracted by source encoding such as compression encoding by a source encoder 11 is temporarily stored in a recording track buffer 12, and then is temporarily stored in a channel encoder 13.
In this case, the data is subjected to NRZI conversion for code modulation such as EFM plus and mark edge recording in synchronization with a clock from the clock generation circuit 14 to become recording data.

The recording data extracted from the channel encoder 13 is generated by the strategy generation circuit 15 in synchronization with a clock from the clock generation circuit 14 to generate a write pulse corresponding to the recording data. The above clock is locked to pre-pit information on the disk as necessary by using a phase locked loop (PLL) circuit. This write pulse is applied to the laser drive circuit 1
The laser light is supplied to the optical pickup 17 as a laser drive signal by 6 and drives a laser light source in the optical pickup 17 to emit a laser light whose light intensity is modulated according to recording data. The recording is performed by irradiating a rewritable optical disk such as an RW. At this time, in order to optimally control the laser power of the laser light,
An APC (Auto Power Control) circuit 18 processes the laser drive signal and feeds it back to the laser drive circuit 16 as necessary.

Although the above-described block configuration itself is conventionally known, the present invention is characterized by the configuration of the strategy generation circuit 15. In other words, the present invention is a recording apparatus having the strategy generation circuit 15 having a novel configuration.

FIG. 2 is a circuit diagram of a strategy generating circuit according to a first embodiment, which is a main part of the recording apparatus according to the present invention. The NRZI-converted recording data extracted from the channel encoder 13 in FIG. 1 is input to the digital signal processing unit 21 in FIG. On the other hand, the clock output from the clock generation circuit 14 of FIG.
The signal LK1 is supplied to the first error signal adding means 22 and the second error signal adding means 23 in FIG.

The digital signal processing means 21 receives two clocks (second clock CLK2 and fourth clock CLK4), which will be described later, as inputs, and outputs two pulses corresponding to the recording data after the NRZI conversion. P
P and MP, and a third clock CLK3
And a duty control pulse is generated and output. The above-mentioned pulses PP and MP are output from the operational amplifier 27 and the resistors R1 to R1.
The signal is converted into a target write pulse by being subtracted in an analog manner by a subtractor composed of R4.

It is an object of the present invention to provide the pulse PP and M
The purpose is to generate P as an appropriately-timed pulse. For that purpose, it is only necessary that a plurality of clocks existing at appropriate timing and duty (ratio) can be generated inside the digital signal processing means 21. Here, DVD
-To realize RW basic strategy, 2
Two clocks (second clock CLK2) in one loop
And a fourth clock CLK4) is generated and input to the digital signal processing means 21.

First, generation of the first clock, that is, the second clock CLK2 will be described. The second clock CLK2 is output from the first error signal adding means 22. The first error signal adding means 22 is provided, for example, in FIG.
After the high frequency component of the first clock CLK1 is removed by an integrating circuit unit including resistors R11 and R12 and a capacitor C1, a first error signal extraction of FIG. 2 described later is performed. The first error signal ERR1 extracted by the means 25 is supplied to the mixing resistor R shown in FIG.
13 and the added signal is supplied to the second clock C
Output as LK2.

This second clock CLK2 is supplied to the digital signal processing means 21 shown in FIG. 2 and passes through an internal buffer 24 which sets a threshold level near the center level of the second clock CLK2 to a third clock of a square wave. After being set to CLK3, it is output to the outside of the digital signal processing means 21 and supplied to the first error signal extraction means 25.

The first error signal extracting means 25 has, for example, a configuration as shown in FIG. 5, and is constituted by an integrating circuit comprising a resistor R13 and a capacitor C3.
, Is temporarily held by the buffer and polarity inversion circuit 31, and is inverted, so that the third clock CLK
3 as a first error signal ERR.
Output as 1. This first error signal ERR1 is
The signal is supplied to the above-described first error signal adding means 22 in FIG. 2 and is added to the first clock CLK1 to form a second clock CLK2.

Here, the second clock CLK2 supplied to the digital signal processing means 21 is used as an internal clock whose waveform is shaped at a certain threshold level by the comparator operation of the input section. Sometimes, even if the first clock CLK1 is an accurate rectangular wave with a duty of 50%, the duty of the internal clock is not always 50%. However, there should be a condition that the duty of the internal clock becomes 50% by slightly smoothing the second clock CLK2 (making the second clock CLK2 close to a sine wave) and controlling it to an appropriate DC level. Further, at that time, the duty of the output third clock CLK3 should also be 50%. Therefore, the output of the third clock CLK3 is integrated and the polarity of the first clock CLK1 is inverted as the first error signal ERR1. , A negative feedback operation is performed, and the duty of the internal clock can be stably maintained at 50% regardless of the clock cycle.

Next, generation of another clock (fourth clock CLK4) will be described. The fourth clock CLK4 is output from the second error signal adding means 23. The second error signal adding means 23 has, for example, a circuit configuration as shown in FIG.
After removing high-frequency components from LK1 by an integrating circuit unit including resistors R21 and R22 and a capacitor C2, a second error signal ERR2 extracted by a second error signal extracting unit 26 shown in FIG. Mixing resistor R23
Via the fourth clock CLK
Output as 4.

The fourth clock CLK4 is supplied to the digital signal processing means 21 and, as described later, is output as a duty control pulse by calculation. The duty control pulse is supplied to the second error signal extraction means 26, and the low-frequency component is output as the second error signal ERR2 by the integration operation. That is, the second error signal extraction means 26 is configured as shown in FIG. 6, for example, and integrates the duty control pulse by an integration circuit including a resistor R41 and a capacitor C4, and then integrates the buffer 32
And temporarily outputs the low-frequency component of the duty control pulse as the second error signal ERR2. This second
The error signal ERR2 is supplied to the above-described second error signal adding means 23 in FIG.
Is added to obtain a fourth clock CLK4.

Here, the fourth clock CLK4 supplied to the digital signal processing means 21 is used as an internal clock whose waveform is shaped at a certain threshold level by the comparator operation of the input section. Sometimes, for example, even if the first clock CLK1 is an accurate rectangular wave with a duty of 60%, the duty of the internal clock is not always 60%.

However, there is a condition that the duty of the internal clock becomes 60% by slightly smoothing the fourth clock CLK4 (making it close to a sine wave) and controlling it to an appropriate DC level. is there. Although a method of generating the duty control pulse will be described later, a negative feedback operation is performed by adding the integration of the duty control pulse to the second clock as the second error signal ERR2, and the internal clock is stable regardless of the clock cycle. And the second clock C
The edge can be kept at a fixed ratio position with respect to LK2. As a result, a pulse having an arbitrary duty, which will be described later, is obtained, and a stable write pulse can be produced.

Next, the generation of the duty control pulse by the digital signal processing means 21 will be described with reference to the timing chart of FIG. Here, in order to create a basic strategy for DVD-RW, the duty ratio is set to 0.
A method of generating a duty control pulse for obtaining a pulse of 6T: 0.4T will be described.

FIG. 7A shows the digital signal processing means 21.
The internal clock corresponding to the second clock obtained by shaping the waveform at a certain threshold level by the comparator operation of the input unit of the digital signal processing means The duty is accurately controlled to 50% by the loop. FIG. 7B shows a fourth clock CLK4 input to the digital signal processing means 21 which is obtained by shaping the waveform at a certain threshold level by the comparator operation of the input section of the digital signal processing means 21. Is an internal clock corresponding to this clock.

The digital signal processing means 21 generates a pulse having a waveform shown in FIG. 7C by a logical operation operation using the internal clocks corresponding to the second clock and the fourth clock as inputs. Where mpulse
7A to 7C show waveforms which rise at the falling edge of the internal clock in FIG. 7B and fall at the rising edge of the internal clock in FIG. 7A. If you are in the correct position, the duty of the pulse will be
As shown in FIG. 7C, when the L level period is 0.6T,
The level period should be 0.4T.

Next, the digital signal processing means 21 performs a modulo 6 counting operation on the internal clock corresponding to the second clock shown in FIG. Value and the count value is “0”
The H level of the pulse of the polarity inversion of mpulse during the period is forced to the L level. Thus, mpulse
The duty control pulse shown in FIG. 7 (E) is that the H level for the period of 0.6T is forcibly changed to the L level at a rate of 1 cycle out of 6 cycles of the pulse whose polarity is inverted.

The duty control pulse is taken out from the digital signal processing means 21 and integrated as described above by the second error signal extraction means 26 in FIG. 2 to output a low frequency component as a second error signal ERR2. However, when the H level of the duty control pulse is set to +1 and the L level is set to −1, the DC component for each cycle T is calculated as shown in FIG. 7F. It turns out that it becomes. That is, the pulse is
As shown in (C), the L level period is 0.6T (or 0.4T), and the H level period is 0.4T (or 0.6T).
(That is, 0.6T: 0.4T), the second error signal ERR2 is zero.

If the DC component of the fourth clock CLK4 is shifted, the waveform of the clock shown in FIG. 7B changes, and as a result, the duty ratio of the pulse becomes 0.6.
Even if T deviates from 0.4T, the DC component of the duty control pulse changes in the direction opposite to the direction in which the pulse duty shifts, so that a negative feedback loop results. Stabilizes as shown.

Note that the duty ratio of the pulse is set to 0.
If 7T: 0.3T is desired, an internal clock corresponding to the second clock is subjected to a modulo 5 count operation, and
The H level of mpulse may be forced to L level at a rate of two out of five times. In short, if the duty of mpulse is to be mT: nT (m> n, where m + n = 1), (m− When a natural number p times n) becomes a natural number q,
The H level of mpulse may be forced to the L level at a rate of q times during the period of pT. Considering the polarity etc., m
<N states can also be created.

Next, the operation of generating the pulses PP and MP for generating the write pulse by the digital signal processing means 21 will be described with reference to the timing chart of FIG. FIG. 8A shows the second clock CLK2 input to the digital signal processing means 21 which is obtained by shaping the waveform at a certain threshold level by the comparator operation of the input section of the digital signal processing means 21. The duty is accurately controlled to 50% by the above-described loop. FIG.
(B) is the NRZI-converted recording data input from the channel encoder 13 of FIG. 1 to the digital signal processing means 21.

The digital signal processing means 21 delays the input record data by a latch operation as necessary in synchronization with an internal clock (FIG. 8A) corresponding to the second clock, and forms a logic circuit. A top pulse gate pulse having a width T that rises at the point of delaying 1T from the rising edge of the input recording data (FIG. 8C), rises at the falling edge of the top pulse gate pulse, and rises at the falling edge of the recording data. A falling multi-pulse gate pulse (FIG. 8D) and a cooling pulse gate pulse having a width T rising at the falling edge of the multi-pulse gate pulse (FIG. 8E) are generated.

The digital signal processing means 21
Using the pulse generated in the method described with reference to FIG. 7 and having the appropriate duty ratio shown in FIG. 8F and the above three types of gate pulses, the first pulse shown in FIG. , And a second pulse MP shown in FIG.

That is, the high-level period of the top pulse gate pulse shown in FIG. 8C rises in synchronization with the fall of the internal clock in FIG. A pulse composed of a pulse having a width of 0.5T that falls in synchronization with the fall of the gate pulse and mpulse output as it is during the H level period of the multi-pulse gate pulse shown in FIG. Generate as PP. Also, during the H-level period of the multi-pulse gate pulse shown in FIG. 8D, a pulse whose polarity has been inverted from the pulse shown in FIG. 8F and the cooling pulse gate pulse H shown in FIG. During the level period, a pulse composed of a gate output and the internal clock of FIG. 7A is generated as a second pulse MP.

The above-mentioned first pulse PP is taken out of the digital signal processing means 21 and supplied to the non-inverting input terminal of the operational amplifier 27 through a resistor voltage dividing circuit composed of resistors R1 and R2 shown in FIG. The second pulse MP is extracted from the digital signal processing means and supplied to the inverting input terminal 27 of the operational amplifier 27 through the resistor R3 shown in FIG. The operational amplifier 27 having the feedback resistor R4 operates as a subtractor and performs an analog subtraction operation of (PP-MP) to generate a pulse shown in FIG.
This is output as a write pulse.

As described above, according to the present embodiment, the repetition frequency of the clocks CLK1 to CLK4 to be used is a low frequency of, for example, about 27 MHz, and 50 MHz.
A write pulse can be generated without using a high-frequency clock of not less than Hz. In the write pulse shown in FIG. 8I generated according to the present embodiment, when the linear velocity of the optical disk fluctuates during recording, the first clock CLK1 fluctuates following the fluctuation, and the second clock CLK1 fluctuates accordingly. Since the clocks CLK2 and CLK4 operate so that the error signals ERR1 and ERR2 are minimized by the negative feedback operation of the two loops, the two pulses PP and MP generated by the digital signal processing means 21 fluctuate, Even if the absolute length of T changes due to a change in linear velocity, a write pulse that follows that length can be generated.

Next, another embodiment of the present invention will be described. FIG. 9 is a circuit diagram of a strategy generating circuit according to a second embodiment, which is a main part of the recording apparatus according to the present invention. In the figure, the same components as those in FIG.
The description is omitted. The second embodiment shown in FIG.
It is characterized in that a variable delay means 35 is provided instead of the second error signal adding means 23 in FIG.

The variable delay means 35 is a block capable of varying the delay time in accordance with the voltage. For example, as shown in FIG. 10, the variable error means 35 supplies the second error signal to the anode of the varicap 37 to reduce the capacitance value. By changing the resistance,
By changing the integration time constant of the integration circuit composed of the resistor 6 and the varicap 37, the rising slope of the first clock CLK1 input to one end of the resistor 36 is varied and output as the fourth clock CLK4. The fourth clock CLK4 of this analog waveform is supplied to the digital signal processing means 21 of the subsequent stage.
Of the fourth clock CLK4 is shaped into a square wave, and its rising edge is delayed in accordance with the capacitance value of the varicap 37.

The present invention is not limited to the above embodiment, and the second error signal adding means 23 and the variable delay means 35 are provided with the second clock CLK2 instead of the first clock CLK1. May be input, and when generating the duty control pulse, the second
The first clock CLK1 can be used together with the fourth clock CLK4 instead of the clock CLK2.

[0050]

As described above, according to the present invention,
Since the duty control pulse can be stably obtained without using a clock having a repetition frequency equal to or higher than the repetition frequency of the first to fourth clocks, a write pulse can be stably generated based on the duty control pulse. . Further, according to the present invention, since the first clock is generated in phase synchronization with pre-pit reproduction information recorded in advance on the optical recording medium, recording is performed by a change in linear velocity due to uneven rotation of the optical recording medium. Even if the absolute recording length of the data bit period T fluctuates, the above-described write pulse can be generated following this fluctuation, and an appropriate bit pattern can be recorded without being affected by the fluctuation of the linear velocity. .

As described above, according to the present invention, at the multiple speed recording having the advantage of high-speed recording, recording can be performed without using a high frequency clock, and CAV recording having the advantage of downsizing the spindle motor. ZCA
In V recording, etc., even if the linear velocity changes according to the radial position of a disk-shaped optical recording medium, a write pulse adaptively following the linear velocity change is generated without using a high-frequency clock. Thus, a good information signal can always be recorded.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a circuit diagram of a first embodiment of a strategy generation circuit which is a main part of the device of the present invention.

FIG. 3 is a circuit diagram of an example of a first error signal adding unit in FIG. 2;

FIG. 4 is a circuit diagram of an example of a second error signal adding means in FIG. 2;

FIG. 5 is a circuit diagram of an example of a first error signal extracting unit in FIG. 2;

FIG. 6 is a circuit diagram of an example of a second error signal extracting unit in FIG. 2;

FIG. 7 is a timing chart for explaining a method of generating a duty control pulse by the digital signal processing means in FIG. 2;

8 is a timing chart for explaining pulses PP and MP by the digital signal processing means in FIG. 2 and a method for generating a write pulse in FIG. 2;

FIG. 9 is a circuit diagram of a strategy generation circuit according to a second embodiment, which is a main part of the device of the present invention.

FIG. 10 is a circuit diagram of an example of a variable delay unit in FIG. 9;

FIG. 11 is a diagram showing a relationship between recording data transfer and pulses of an optical disc of the DVD-RW standard.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Source encoder 12 Recording track buffer 13 Channel encoder 14 Clock generation circuit 15 Strategy generation circuit 16 Laser drive circuit 17 Optical pickup 21 Digital signal processing means 22 First error signal addition means 23 Second error signal addition means 25 First Error signal extracting means 26 Second error signal extracting means 27 Operational amplifier 35 Variable delay means

Claims (6)

[Claims] 1. A write pulse corresponding to a write strategy is generated by a strategy generation circuit based on a first clock synchronized with recording data and the recording data, and a writing light source is driven. A recording apparatus for recording the recording data on an optical recording medium based on a laser beam emitted from the optical disc, wherein the strategy generation circuit generates an error signal to the first clock to generate a second clock An error signal adding means, a clock generating means for shaping the waveform of the second clock by a comparator operation to generate a third clock, and extracting a low-frequency component of the third clock as the error signal to generate the error signal. The signal is supplied to the signal adding means,
And an error signal extracting means for maintaining the duty of the clock at 50%. 2. A write pulse corresponding to a write strategy is generated by a strategy generating circuit based on a first clock synchronized with recording data and the recording data, and a writing light source is driven. A recording apparatus for recording the recording data on an optical recording medium based on a laser beam emitted from the optical disc, wherein the strategy generation circuit generates an error signal to the first clock to generate a second clock An error signal adding unit, receiving the second clock and the recording data as inputs, and detecting a rising or falling timing of a clock corresponding to the first clock and a rising or falling timing of a clock corresponding to the second clock. The relationship with the falling or rising timing is held at a fixed rate with respect to the cycle of the first clock. A pulse generating means for generating a duty control pulse and generating the write pulse in accordance with the recording data and the duty control pulse; and extracting the low frequency component of the duty control pulse as the error signal and generating the error signal. A recording apparatus, comprising: an error signal extracting unit that supplies the error signal to the adding unit. 3. The pulse generator according to claim 1, wherein a rising edge or a falling edge of the clock corresponding to the first clock is set as a trailing edge or a leading edge, and the falling edge or the rising edge of the clock corresponding to the second clock is set. A first means for generating an m-pulse having an edge as a leading edge or a trailing edge;
In the case of 1), when the natural number p times the difference between m and n becomes a natural number q, the logical value “1” of the m pulse is forcibly logically applied q times in the p period of the second clock. 3. The recording apparatus according to claim 2, further comprising: a second unit configured to generate the duty control pulse having a value of “0” or “1”. 4. A variable delay means for variably controlling a delay time of said first clock in accordance with a level of said error signal, in place of said error signal adding means. The recording device according to any one of claims 3 to 3. 5. The recording apparatus according to claim 1, wherein the first clock is generated in phase synchronization with a reproduction signal of pre-pit information previously recorded on the optical recording medium. 6. A write pulse corresponding to a write strategy is generated based on recording data synchronized with a first clock and the first clock, and a light pulse is generated based on a laser beam driven by the write pulse. In a recording method for recording the recording data on a recording medium, a second error signal is added to the first clock to generate a second error signal.
A second step of generating a third clock by generating a third clock by shaping the waveform of the second clock by a comparator operation, and generating a third error signal in the first clock or the second clock. Adding a second clock to generate a fourth clock, a rising or falling timing of a clock corresponding to the second clock, and a falling or rising timing of a clock corresponding to the fourth clock. A third step of generating a duty control pulse in which the relationship with the timing is maintained at a constant rate with respect to the cycle of the first or second clock; A fourth step of extracting a low-frequency component of the duty control pulse as the second error signal. And a sixth step of generating the write pulse corresponding to the recording data and the duty control pulse.