JP2002043426A - Verifying method of design parameter of semiconductor and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily verify a parameter for LPE to a transistor grasping a shape when the circuit simulation of a semiconductor is carried out. SOLUTION: TCAD is carried out in a step 51 to prepare a database 52. A net list produced in a step 44 by using the database 52 is verified in a step 53. For instance, TCAD sets a parameter for TCAD so that an electric characteristic is obtained for the transistor 10. By the verification in a step 53, for instance, if drain current obtained from the transistor of the net list produced in a step 44 is matched to the result of the database 52 in a prescribed range, it is advanced to a step 45, and the circuit simulation is carried out. But if they are not matched, a parameter 46 for LPE is renewed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for designing and manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, with the rapid progress of miniaturization technology, high integration has been dramatically advanced. Along with the expansion of the market, it is required to develop a low-cost, low-power-consumption, high-frequency semiconductor device in a short period of time and connect it to mass production.

In order to cope with such a situation, the design of a semiconductor device and the development of a transistor that is a part of the semiconductor device are performed in a manner that is almost simultaneous. It is necessary to estimate in a short time how much performance a semiconductor device designed at the stage when the development of a transistor has progressed to some extent, or whether the semiconductor device meets predetermined specifications.

As one of the measures to meet such a demand, there is an evaluation of a signal delay time by a circuit simulation. Evaluation by simulation can quickly respond to changes in design, transistors, and specifications.

In a circuit simulation of a semiconductor device, the semiconductor device is divided into a wiring and an element such as a transistor, and the capacitance and resistance parasitic to the wiring are taken into consideration as parameters. The calculation is performed in consideration of the characteristics.

If a transistor is taken as an example of an element, an analytic expression for expressing transistor characteristics called a transistor model is adopted. Then, parameters appearing in the analytical formula (hereinafter, “transistor parameters”) are set so that the transistor characteristics obtained from the analytical formula match the measured transistor characteristics. A circuit simulation is performed using the transistor parameters set as described above.

The shape of the transistor employed in the above matching is a simple shape such as a rectangular active region. However, in a semiconductor device to be designed, a transistor having a more complicated shape is also used. Different shapes may have different transistor characteristics. Therefore, even if a circuit simulation of a semiconductor device to be designed is performed by using the transistor parameters set in the matching using the transistor model, the result does not always estimate an actual value.

In order to avoid such a problem, design parameter extraction software (hereinafter referred to as “LPE”: Layout Param)
eter Extraction) is used. L
The PE finds out the transistor from the semiconductor device design layout and grasps its shape. Then, based on the shape, the transistor is recognized by being decomposed into a reference transistor and an additional resistor and an additional capacitor, or is decomposed into a plurality of reference transistors and recognized. Then, a circuit simulation is performed using the transistor parameters of the reference transistor.

[0009]

However, even when the LPE is used, the above-mentioned additional resistance and additional capacitance are determined by associating any additional resistance and additional capacitance with any shape, or how to disassemble it. Must be determined in advance by the user. This is a parameter in the LPE (hereinafter referred to as “LPE
Parameter)).

FIG. 11 is a flowchart showing a procedure for performing a circuit simulation using the LPE. In this flowchart, each step may be regarded as a block, and may be understood as a block diagram. A layout design is performed in step 41, and a transistor net is generated in step 42 based on the obtained layout. The transistor net has a connection relationship between the transistors. Then, in step 43, the LPE parameter 4
6, additional resistances and additional capacitances are set to be added to the reference transistor to form transistors of various patterns on the layout.

Next, at step 44, the additional resistance and the additional capacitance are integrated with the wiring resistance and the wiring capacitance to generate a net list. At this time, the transistor parameters 47 for the reference transistor are also read, and a transistor model is adopted. Then, a circuit simulation is performed in step 45 based on the generated netlist.

Whether the actual values of the characteristics of various transistors can be estimated by setting the additional resistance and the additional capacitance by using the LPE parameters is determined by producing transistors for verification and obtaining the characteristics. No. This adds to the cost of the design and requires additional time for verification.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a technique for easily verifying LPE parameters for a transistor whose shape has been grasped when performing a circuit simulation of a semiconductor device. It is intended to be.

[0014]

Means for Solving the Problems Claim 1 of the present invention
The present invention relates to a method for verifying design parameters of a semiconductor device, which comprises: (a) grasping the shape of a transistor from a design layout of a semiconductor device and using the design parameters;
(B) generating a netlist using the result of the step (a) and the transistor model, and (c) determining electrical characteristics of the transistor. (D) obtaining the design based on the characteristics of the transistor based on the netlist and the characteristics obtained in step (c), using a process simulation, a device simulation, and a wiring simulation. Verifying the validity of the parameters.

According to a second aspect of the present invention,
2. The method for verifying design parameters of a semiconductor device according to claim 1, wherein the electrical characteristics obtained in the step (c) for a plurality of transistors having different sizes constitute a database.

According to a third aspect of the present invention, there is provided:
3. The method for verifying design parameters of a semiconductor device according to claim 1, wherein said step (c) is performed by (c-
1) simulating the electrical characteristics for at least one size transistor;
-2) obtaining the electrical characteristics of a plurality of transistors of different sizes based on the result of the step (c-1).

According to a fourth aspect of the present invention,
4. The method for verifying design parameters of a semiconductor device according to claim 3, wherein in said step (c-1), a plurality of said electrical characteristics are obtained for a plurality of transistors having discretely different sizes. In 2), a response surface method is adopted.

According to a fifth aspect of the present invention,
4. The method of verifying design parameters of a semiconductor device according to claim 3, wherein in the step (c-1), the electrical characteristics of a transistor having a predetermined size are simulated, and in the step (c-2), the simulation is performed. Based on the predetermined size and the electric characteristics obtained in the step (c-1), the electric characteristics of transistors of other sizes can be obtained by an analytical solution.

According to a sixth aspect of the present invention, there is provided:
4. The method of verifying design parameters of a semiconductor device according to claim 3, wherein in the step (c-1), the electrical characteristics of a transistor having a predetermined size are simulated, and in the step (c-2), the simulation is performed. Based on the predetermined size and the electrical characteristics obtained in the step (c-1), the electrical characteristics of transistors of other sizes can be obtained by a numerical solution.

According to a seventh aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising the method for verifying design parameters of a semiconductor device according to any one of the first to sixth aspects.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a flowchart illustrating a procedure of a circuit simulation according to the first embodiment of the present invention. In this flowchart, each step may be regarded as a block, and may be understood as a block diagram. In the same manner as in the prior art, a layout design is performed in step 41, and a transistor net is generated in step 42.

FIG. 2 shows a reference MOS transistor 1 corresponding to a transistor parameter 47 already prepared.
FIG. 9 is a plan view illustrating an example of a layout of No. 0. FIG. 3 is a plan view showing an example of the MOS transistor 20 existing in the transistor net. Transistor 10,
The shape of 20 is different and to compensate for this difference,
In step 43, additional resistance and additional capacitance are set, and division based on the transistor 10 is performed.

Referring to FIG. 2, transistor 10 is formed in a rectangular active region, and has a rectangular gate electrode 10G at the center thereof, and rectangular source 10S and drain 10D on both sides in plan view. Is arranged. In the transistor 10, the gate width W, the gate length L, and the length of the source 10S in the gate length direction (hereinafter, “source length”)
B ₀ is fixed. Drain 10D, source 1
OSS is provided with contacts 11 to 14 and contacts 15 to 18, respectively.

Referring to FIG. 3, transistor 20 is formed in an active region having a shape different from that of transistor 10, and has a gate electrode 20G at the center thereof and a source 20S and a drain 20S on both sides in plan view. 20D are arranged. The gate electrode 20G has the same shape as the gate electrode 10G, that is, a rectangle having a gate width W and a gate length L, and the drain 20D has the same shape as the drain 10D. The shape and arrangement of the contacts 21 to 24 provided in the drain 20D are the same as those of the contact 11 in the drain 10D.
Same as １４14.

However, unlike the source 10S, the source 20S is not rectangular but has an L-shape, and a single contact 28 is provided. The contact 28 is arranged at a position corresponding to the contact 18 in the same shape as the contact 18, and has a rectangle S having a width W _p and a source length B _{0 in} the vicinity thereof.
1 is present in source 20S. The lower end of the rectangle S1 in the figure coincides with the lower end of the source 10S, and the right end (that is, the end farthest from the gate electrode 20G) in the figure of the rectangle S1 is the source 1
It coincides with a part of the right end of 0S. Length B on source 20S
(<B ₀ ) and a rectangle S2 having a width (W−W _p )
1 and S2 are adjacent to each other to form a source 20S. The upper end of the rectangle S2 in the figure coincides with a part of the upper end of the source 10S, and the left end of the rectangle S2 in the figure (that is, the end adjacent to the gate electrode 20G in plan view) coincides with a part of the left end of the source 10S. I do. The lower end of the rectangle S2 coincides with a part of the upper end of the rectangle S1.

Assuming that the process conditions employed in the manufacture of the transistors 10 and 20 such as ion implantation conditions and diffusion conditions are the same, an additional resistance and an additional capacitance are set which reflect the difference between the two characteristics. .

FIG. 4 is a circuit diagram illustrating an equivalent circuit of the transistor 20 determined in step 43. Additional capacity is omitted for simplicity. Transistor 20
Is basically divided into parallel connections of transistors Q1 and Q2. However, an additional resistor R is interposed between the source of the transistor Q1 and the source of the transistor Q2. For example, the additional resistance R is set as a diffusion resistance in the rectangle S1 having no contact. For example, the transistors Q1 and Q2 are obtained by multiplying the current driving capability of the transistor 10 by (W−W _p ) / W and W _p / W, respectively. Is set.

After the additional resistance and the additional capacitance are obtained in step 43, a transistor list 47 is read and a transistor model is used to generate a netlist 44 in the same manner as in the prior art.

However, L is set to obtain an equivalent circuit.
Whether the parameters for PE are appropriate must be separately verified as described above. In the present invention, a computer-aided design technology (hereinafter, “TCAD”: Technology-Computer-Aided) is used without actually manufacturing a transistor.
Verification is performed using a simulation of the operation of the transistor obtained by using Design). Here, TCAD does not include circuit simulation. For example, it includes a process simulation, a device simulation, and a wiring simulation.

In FIG. 1, TCAD is executed in step 51 to create a database 52. Using this database 52, the netlist generated in step 44 is verified in step 53.

In the TCAD, for example, parameters for the TCAD are set so that the electrical characteristics of the transistor 10 that match the actual measurement result within an allowable range are calculated. In other words, even if the gate width W and the source length B ₀ are varied within a certain range, it is possible to calculate appropriate electric characteristics. If the TCAD is involved in the transistor development, this setting may have already been performed in the normal calibration, and in that case, there is no need to perform it again.

After that, a simulation of electric characteristics is performed based on the shape of the transistor 20. Here, the rectangle S1
Are fixed, ie, W _p and B ₀ are fixed, the characteristics of the transistor 20 depend on the gate width W and the source length B in the rectangle S2. The electrical characteristics obtained by the simulation constitute a database 52.

FIG. 5 shows the parameters for TCAD set for the transistor 10, the source length B and the gate width W.
4 shows the value of the drain current J _dr obtained by the TCAD simulation. Here, the results of a simulation performed for a case where nine discrete plural values of W and B are used are shown. In the figure, plots indicated by black circles, black squares, and black triangles each have B = 0.5.
Cases of μm, 0.31 μm, and 0.15 μm are shown, respectively, and W _p is calculated as 2/3 μm. However, for each value of the gate width W, the value is normalized by the current value when B = B ₀ . The source potential Vs applied to the contact 28 is equal to the substrate potential of the transistor and is 0 V, and the gate voltage Vg and the drain voltage Vd with respect to the source potential are uniformly applied at 2.5 V to the gate electrode 20G and the drain 20D, respectively. It is calculated as being.

It can be seen that the longer the gate width W and the shorter the source length B, the larger the diffusion resistance in the rectangle S1 and the smaller the drain current. In this manner, for example, electrical characteristics such as a drain current are obtained as the database 52 by simulation corresponding to various values of the source length B and the gate width W.

As a result of the verification in step 53, for example, the drain current obtained from the transistor in the netlist generated in step 44 (ie, the transistor represented by the equivalent circuit shown in FIG. If they match within the predetermined range, the process proceeds to step 45, where the circuit simulation is executed. However, if they do not match, the LPE parameters 46 will be updated.

There are various methods for updating the LPE parameters 46. For example, when the drain current of the transistor in the netlist is smaller than that obtained from the database 52, the LPE parameter 46 is updated so that the magnitude of the resistor R becomes smaller. However, whatever update method is employed, according to the present invention, L
This does not impair the effect that the verification of the PE parameters 46 can be performed quickly.

As a modification of the present embodiment, in order to enrich the database 52, a response surface method (RSM: Response Surface M
ethod). FIG. 6 is a flowchart showing the procedure of the circuit simulation in such a case. After step 51, a calculation employing RSM is further performed at step 54. In the above example, the calculation using RSM

[0038]

(Equation 1)

Is required. The curve obtained from this equation is also shown in FIG. Curves L1, L2 and L3 are B
= 0.5 μm, 0.31 μm, and 0.15 μm. Since the calculation by the response surface method can be performed at a very high speed, the database 52 can be stored in the database 52 at a high speed for substantially continuous values of W and B as compared with the case where the TCAD simulation is performed for all the desired W and B. Can be generated.

FIG. 7 is a plan view showing an example of the layout of the MOS transistor 70. The transistor 70 is formed in a rectangular active region similarly to the transistor 10, has a rectangular gate electrode 70G at the center thereof, and has a rectangular source 70S and a drain 70D on both sides in plan view. . In the drain 70D, contacts 71 to 74 corresponding to the contacts 11 to 14, respectively, are provided. However, unlike transistor 10, contact 78 at source 70S
Is provided only one. L for such a shape
Naturally, the present invention can be applied also when PE is used.

Embodiment 2 In the first embodiment, in order to enrich the database 52, the TCAD simulation is performed several times, and RSM is adopted based on the result. In this embodiment, the number of TCAD simulations is reduced by adopting a more analytical method,
Thus, the calculation time is reduced.

FIG. 8 is a flowchart showing the procedure of the circuit simulation according to the present embodiment.
After that, a calculation employing an analytical method described below is performed in step 55.

FIG. 9 is a plan view for explaining an analytical method in this embodiment, and shows how to set the x coordinate for the configuration of the transistor 20.

The x-axis is set parallel to the direction of the gate width,
The origin, that is, the position where the coordinate x = 0, is set at the boundary between the rectangles S1 and S2. Then, in this method, the transistor 20 is approximated as a parallel connection of minute transistors having a gate width of the minute width Δx with respect to the coordinate x. The gate voltage Vg and the drain voltage Vd are uniformly set to 2.5 V with respect to the gate electrode 20G and the drain 20D, respectively, based on the source potential Vs (0) applied to the contact 28 (the parentheses indicate the x coordinate). And the potential Vb is uniformly applied to the substrate of the transistor.

[0045] In the transistor to a rectangular S2 source, that is, in a transistor-existing x = x ₀ (> ₀₎ between x = W-W _p, the source potential because contact does not exist depending on the x-coordinate I do. Considering that the drain current flows, the source 20S at x = x ₀
Potential Vs (x ₀ ) and the source 20S at x = x ₀ + Δx
And a potential difference exists between the potential Vs (x ₀ + Δx)

[0046]

(Equation 2)

Is calculated. Here, j _d (x) is a drain current flowing when a unit width transistor is assumed at the coordinate x, and Vd−Vb, Vg−Vb, Vs
(X) is a function of -Vb. Further, the resistivity of the source 20S is defined as ρ.

Equation (1) can be rewritten as a calculus equation for x,

[0049]

(Equation 3)

Is obtained. Differentiating both sides of equation (2) gives

[0051]

(Equation 4)

The following differential equation is obtained.

The drain current j _d (x) is generally Vs
Since it is difficult to analytically solve for the term including the second-order or higher order of (x) -Vb, an approximation is introduced. Assuming that Vs (0) -Vb is small, Vs (x) -Vb is also considered to be small. I mean

[0054]

(Equation 5)

Suppose that Where α and β are V
These parameters are dependent on d, Vg, Vb, and Vs (0). The boundary condition of the differential equation (3) is a boundary condition of Vs (x) -Vb at x = 0.

[0056]

(Equation 6)

[0057] and is the boundary conditions of the electric field at x = W-W _p

[0058]

(Equation 7)

Are set. When Equation (3) is solved using Equations (5) and (6) indicating the boundary conditions and the approximate equation (4), the drain current flowing through the transistor 20 as a whole becomes

[0060]

(Equation 8)

Is obtained. However, the source potential is uniformly Vs (0) by the contact 28 in the rectangle S1.
And it is, the current flowing through the transistor in the rectangular S1 is set to a (β-αVsb) W _p. The current flowing through the entire transistor 10 is (β
−αVsb) W, and using this to normalize the value of the drain current j _d ,

[0062]

(Equation 9)

Is obtained. In equation (8), (ρα /
B) If a value of ^1/2 is set, the dependence of the normalized drain current _{Jdr on} the gate width W is determined.

In step 51, a TCAD simulation is performed once, and based on the result, (ρα /
B) Estimate ^1/2 , and in step 55, standardize the drain current J by an analytical method using equation (8).
_The dependence of _{dr on} the gate width W is obtained.

For example, B = 0.5 μm, W = 10 μm, W
_From the TCAD simulation in the case of _p = ２ μm, (ρα / B) ^1/2 = 0.067 (unit: μm ⁻¹ ) is calculated. Since this value is for B = 0.5 μm, in order to correspond to various drain lengths B, (ρα / B) ^1/2 = 0.067 (0.5
/ B) ^1/2 (unit is μm ⁻¹ ). If you show this concretely

[0066]

(Equation 10)

Is obtained. By using equation (9), the drain current J _dr normalized for arbitrary W and B is
It can be calculated quickly without using RSM.

FIG. 10 is a graph showing the value of the normalized drain current J _dr obtained from the equation (9).
4, L5 and L6 are B = 0.5 μm and 0.31 μm, respectively.
m, 0.15 μm. Also shown are nine results of the simulation by TCAD described in the first embodiment. The result obtained by using the expression (9) and the result of the simulation by TCAD are in good agreement, and the same effect as in the first embodiment can be obtained by performing the verification in step 53 using the present embodiment. I understand.

Embodiment 3 In the second embodiment,
Approximate expression (4) was assumed with the intention of solving the differential equation (3) analytically. However, a specific form of j _d (x) may be obtained by employing a transistor model. Generally, even in that case, j _d (x) is Vs (x) −Vb
Or higher order terms.

Therefore, instead of solving the differential equation (3) analytically, it may be numerically solved. Even if a specific form of j _d (x) is obtained by employing the transistor model, the transistor parameter 47 is unknown. The transistor parameters 47 are generally set for a model of a transistor having a simple structure such as the transistor 10.

Therefore, in step 51, the electrical characteristics of the transistor 10 formed under the same process conditions as those for forming the transistor 20 are obtained by TCAD simulation. Then, a transistor parameter 47 is extracted from the result. That is, in FIG.
The transistor parameter 47 is generated by 1 and will be used further in step 55.

As described above, in step 55, j
The specific form of _d (x) can be determined, and then the differential equation (3) may be solved by a numerical solution for the variable x. This numerical solution can also be performed quickly as compared with the TCAD simulation.

Modification. The semiconductor device can be designed by adopting the LPE parameters 46 verified by the above embodiment and performing the circuit simulation in step 45. It is natural that the semiconductor device can be manufactured based on the design, and the period required for this is short.

[0074]

According to the method for verifying design parameters of a semiconductor device according to claim 1 or 2 of the present invention, verification of design parameters can be verified without actually manufacturing a transistor.

According to the method for verifying design parameters of a semiconductor device according to claim 3 or 4 of the present invention,
The simulation of the electrical characteristics in the step (c) of the transistor whose shape has been grasped in the step (a) can be quickly performed.

According to the method for verifying design parameters of a semiconductor device according to claim 5 or 6 of the present invention,
Electrical characteristics can be obtained more quickly.

According to the method of manufacturing a semiconductor device according to the seventh aspect of the present invention, since the design can be performed quickly, the period required for manufacturing the semiconductor device is also shortened.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a procedure according to the first embodiment of the present invention.

FIG. 2 is a plan view illustrating an example of a layout of a reference transistor.

FIG. 3 is a plan view illustrating an example of a transistor existing in a transistor net.

FIG. 4 is a circuit diagram illustrating an equivalent circuit of a transistor;

FIG. 5 is a graph showing a result of the first embodiment of the present invention.

FIG. 6 is a flowchart showing a procedure of a modification of the first embodiment of the present invention.

FIG. 7 is a plan view showing another example of the layout of the transistor.

FIG. 8 is a flowchart showing a procedure according to the second embodiment of the present invention.

FIG. 9 is a plan view illustrating an analytical method according to the second embodiment of the present invention.

FIG. 10 is a graph showing a result of the second embodiment of the present invention.

FIG. 11 is a flowchart showing a procedure of a conventional technique.

[Explanation of symbols]

46 LPE parameters, 47 transistor parameters, 52 database.

Claims (7)

[Claims] (A) grasping the shape of a transistor from a design layout of a semiconductor device, decomposing the transistor based on a reference transistor using design parameters, and recognizing the transistor; (b) performing the step (a) (C) generating a netlist by using the result of (1) and the transistor model; (c) obtaining electrical characteristics of the transistor by using a process simulation, a device simulation, and a wiring simulation; A method for verifying design parameters of a semiconductor device, comprising: verifying the validity of the design parameters based on the characteristics of the transistor based on a list and the characteristics obtained in the step (c). 2. The method according to claim 1, wherein the electrical characteristics obtained in the step (c) for a plurality of transistors having different sizes constitute a database.
A method for verifying design parameters of a semiconductor device according to claim 1. 3. The step (c) comprises: (c-1) simulating the electrical characteristics of at least one type of transistor; and (c-2) based on a result of the step (c-1). 3. The method for verifying design parameters of a semiconductor device according to claim 1, further comprising obtaining the electrical characteristics of a plurality of transistors having different sizes. 4. In the step (c-1), a plurality of the electric characteristics of a plurality of transistors having discretely different sizes are obtained, and the response surface method is adopted in the step (c-2). Item 3. The method for verifying design parameters of a semiconductor device according to Item 3. 5. In the step (c-1), the electrical characteristics of a transistor having a predetermined size are simulated. In the step (c-2), the predetermined size and the transistor in the step (c-1) are simulated. 4. The method according to claim 3, wherein the electrical characteristics of transistors of other sizes are obtained by an analytical solution based on the obtained electrical characteristics. 6. In the step (c-1), the electrical characteristics of a transistor having a predetermined size are simulated, and in the step (c-2), the predetermined size and the transistor in the step (c-1) are simulated. 4. The method according to claim 3, wherein the electrical characteristics of transistors of other sizes are obtained by a numerical solution based on the obtained electrical characteristics. 7. A method of manufacturing a semiconductor device, comprising the method of verifying design parameters of a semiconductor device according to claim 1.