JP2002043321A - Semiconductor device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can realize a high switching speed and excellent high frequency characteristics even if a high density integrated structure is employed by reducing the resistances of the semiconductor layers and the contact resistance between the semiconductor layers and the metal electrodes, and to provide the manufacturing method of the semiconductor device. SOLUTION: In this semiconductor device, a surface of a 1st electrode 25E connected to a 1st region of a bipolar transistor 2 with the 1st region 20, a 2nd region 17B and a 3rd region 21 and the surface of the 2nd region 17B are silicidized, insulating side walls 32 are formed on the side parts of the 1st electrode 25E, and both the silicide layers 31 formed respectively on the 1st electrode 25E and the 2nd region 17B are brought into contact with the side walls 32. The manufacturing method of the semiconductor device includes a process in which the 2nd insulating film 32 is subjected to anisotropic etching to expose the surface of the 1st electrode 25E and the surface of the 2nd region 17B, and side walls are formed on the 1st electrode 25E; and a process in which, after a high melting point metal layer is formed over the whole surfaces, the surface of the 1st electrode 25E and the surface of the 2nd region 17E are silicidized by annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art BiCMOS in which a bipolar transistor and a CMOS transistor are both formed on the same substrate.
As a semiconductor device, a high-performance semiconductor device can be realized by utilizing the advantages of high-accuracy analog processing capability and high-speed operation of a bipolar transistor and the advantages of high integration and low power consumption of CMOS.

[0003] As the above BiCMOS semiconductor device,
For example, a configuration shown in a schematic configuration diagram (cross-sectional view) in FIG. 12 is known. This BiCMOS semiconductor device has an NPN transistor 52 having a structure in which a resistor 51 made of polycrystalline silicon 75 and an emitter electrode 75E made of polycrystalline silicon 75 are formed on a silicon substrate 61, and a CMOS transistor (NMOS transistor) having an LDD structure. 53
And a PMOS transistor 54).

The manufacture of the BiCMOS semiconductor device shown in FIG. 12 is performed, for example, as described below.

First, an NPN transistor formation region (52) on the surface of a P-type (100) silicon
After forming an N ⁺ buried layer 62 in the S transistor formation region (54), an N-type epitaxial layer 63 is formed on the P-type silicon substrate 61 to a thickness of 0.7 to 2.0 μm.

Further, a field oxide film 72 having a thickness of 600 to 1500 nm is formed and the surface is planarized.
An N ⁺ sinker 63S is formed in the collector lead portion of the N transistor 52.

Thereafter, boron is ion-implanted into the P-type silicon substrate 61 and the N-type epitaxial layer 63, thereby forming the P ⁺ channel stop region 64 and the NMOS.
A P-type semiconductor well region 65 in the transistor formation region (53) is formed. Further, an N-type semiconductor well region 66 is formed in the N-type epitaxial layer 63 in the PMOS transistor formation region (54) (see FIG. 13A).

Next, after a gate oxide film 73 having a thickness of 15 to 50 nm is formed on the surface, a 100 nm thick N ⁺
Polycrystalline silicon film 76 and 100 nm thick WSi film 7
7 are sequentially formed. Thereafter, the polycrystalline silicon film 76 and the WSi film 77 are patterned by dry etching to form the polycrystalline silicon film 76 and the WSi film 77.
The gate electrodes G of the MOS transistors 53 and 54 are formed.

Next, ion implantation is performed using the gate electrode G as a mask, so that N ^{− is} formed in the P-type semiconductor well region 65 in the NMOS transistor formation region (53).
Is formed, and a P ⁻ LDD region 69L is formed in the N-type semiconductor well region 66 in the PMOS transistor formation region (54). Further, a P ⁺ base region 6 is formed in the NPN bipolar transistor formation region (52).
7 (see FIG. 13B).

Thereafter, an SiO ₂ film 74 for an LDD sidewall spacer is formed on the entire surface covering the surface to a thickness of 150 to 250 nm by a CVD method. Next, an opening 74H is formed in the emitter portion of the NPN bipolar transistor formation region (52) of the SiO ₂ film 74 by reactive ion etching to expose the semiconductor portion.
Thereafter, a polycrystalline silicon film 75 for forming the emitter region 70 and the resistor 51 is formed on the entire surface.

The NPN bipolar transistor 5
As (arsenic) is applied to the polycrystalline silicon film 75 of the emitter portion of No. 2 with an energy of 30 to 70 keV and a dose of 1 × 10
Ion implantation is performed at ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . In order to obtain a desired resistance value, As is applied to the polycrystalline silicon film 75 of the polycrystalline silicon resistance portion 51 at a dose of 1 × 10 ¹³ to 1 ×.
Ion implantation is performed at 10 ¹⁴ cm ⁻² (see FIG. 14C).

Next, the NPN bipolar transistor 52
The dry etching of the polycrystalline silicon film 75 is performed using the resist pattern that leaves the emitter portion and the polycrystalline silicon resistance portion 51. Thereby, the polycrystalline silicon resistor 5 is formed.
One polycrystalline silicon film 75 (75R) and the polycrystalline silicon film 75 (75E) of the emitter electrode of the NPN bipolar transistor 52 remain. Subsequently, by etching the SiO ₂ film 74, an LDD sidewall spacer 74 (78) is formed on the side wall of the gate electrode G (see FIG. 14D).

Next, using the gate electrode G as a mask, As
The source / drain region 68 of the NMOS transistor 53 is formed by ion implantation of (arsenic), and As is ion-implanted into the collector extraction portion of the NPN bipolar transistor 52 to form the collector extraction region 7.
Form one. Further, the gate electrode G and the emitter electrode 75
By ion implantation of BF ₂ using E as a mask,
The self-aligned source /
Drain region 69, NPN bipolar transistor 52
To form a graft base region 67B. Then, 10
Annealing is performed at 00 ° C. to 1100 ° C. for 5 to 30 seconds to anneal the source / drain regions 68 and 69 and at the same time, the As in the emitter electrode 75E made of the polycrystalline silicon film of the NPN bipolar transistor 52 is removed from the base region 67. To form an N ⁺ emitter region 70 (see FIG. 15E).

Thereafter, an interlayer insulating film 79 is formed under the first layer of aluminum wiring (not shown) by a usual method, and after flattening the surface, contact holes and metal electrodes 80B, 8B are formed.
0E, 80C, 80S, and 80D (see FIG. 15).
F). Thus, the BiCMOS semiconductor device including the NMOS transistor 54, the PMOS transistor 53, the NPN bipolar transistor 52, and the polycrystalline silicon resistor 51 shown in FIG. 12 is formed.

[0015]

In the BiCMOS semiconductor device having the conventional structure, the base resistance is increased because the graft base region 67B of the NPN transistor 52 is formed of P ⁺ silicon. . When the base resistance is large, fmax (maximum oscillation frequency) is reduced and noise is increased. Also,
With the miniaturization of transistors, the emitter resistance increases,
Decreases high frequency characteristics.

In the MOS transistors 53 and 54 as well, the diffusion resistance of the source / drain regions 68 and 69 and the contact resistance with the metal electrodes 80S and 80D increase with the miniaturization of the elements, and lower the switching speed.

In order to solve the above-mentioned problem, the present invention reduces the resistance of the semiconductor layer and the contact resistance between the semiconductor layer and the metal electrode, so that a high switching speed and a good switching performance can be obtained even if high integration is achieved. Provided are a semiconductor device capable of achieving high-frequency characteristics and a method for manufacturing the same.

[0018]

According to the present invention, there is provided a semiconductor device comprising:
A surface of a first electrode connected to a first region of a bipolar transistor having a first region, a second region, and a third region, and a second electrode connected to a surface of the second region and / or a second region Is silicided, an insulating sidewall is formed on a side of the first electrode, and a silicide formed on the first electrode and a silicide formed on the second region and / or the second electrode are formed. Are both in contact with the side walls.

According to the structure of the semiconductor device of the present invention described above, since the surface of the first electrode and the surface of the second region and / or the surface of the second electrode are silicided, they can The contact resistance and the resistance of these electrodes and regions can be reduced. In addition, since the silicide formed on the first electrode and the silicide formed on the second region and / or the second electrode are both in contact with the insulating sidewall, these silicides can be brought close to each other. However, a short circuit can be prevented by the insulating sidewall.

According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device in which a bipolar transistor having a first region, a second region and a third region is formed on a semiconductor substrate, the second region is formed on the semiconductor substrate. Or second
Forming a second electrode connected to the region and the second region; forming a first insulating film on the entire surface; and then forming an opening in the first insulating film that defines the first region. Forming a first electrode made of polycrystalline silicon connected to the first region after forming a polycrystalline silicon film on the entire surface, and forming a second insulating film on the entire surface; Anisotropic etching is performed on the second insulating film to expose the surface of the first electrode and the surface of the second region and / or the surface of the second electrode connected to the second region. Forming a sidewall on the side wall of the electrode, and forming a refractory metal on the entire surface, and then performing annealing to connect the surface of the first electrode to the second region and / or the second region connected to the second region. Silicidizing the surface of the electrode.

According to the above-described method of the present invention, after the high melting point metal is formed on the entire surface, annealing is performed to silicide the surface of the first electrode and the second region and / or the surface of the second electrode. By doing so, a semiconductor device in which the contact resistance and the resistance of the first electrode and the second region and / or the second electrode are reduced can be manufactured.

According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device having a bipolar transistor having a first region, a second region and a third region and a resistor on the same semiconductor substrate, Forming an insulating element isolation layer on the semiconductor substrate outside the formation region; forming a second region on the semiconductor substrate within the formation region of the bipolar transistor; or forming the second region and a second electrode connected thereto Forming a first insulating film over the entire surface, and then forming an opening in the first insulating film that defines a first region of the bipolar transistor;
After forming a polycrystalline silicon film on the entire surface, patterning is performed to form a first electrode made of polycrystalline silicon connected to the first region of the bipolar transistor, and a resistor made of the polycrystalline silicon film on the element isolation layer. Forming a second insulating film over the entire surface, covering the second insulating film on the resistor with a mask, and performing anisotropic etching on the second insulating film to form a first insulating film. Exposing the surface of the electrode and the surface of the second region and / or the surface of the second electrode connected to the second region, and forming a sidewall on the side wall of the first electrode; After the formation, annealing is performed to silicify the surface of the first electrode and the second region and / or the surface of the second electrode connected to the second region, and the step of removing the mask is performed. Have

According to the above-described method of the present invention, after a high-melting-point metal is formed on the entire surface, annealing is performed so that the surface of the first electrode of the bipolar transistor and the surface of the second region and / or the surface of the second electrode are separated. And a step of silicidation of the first electrode, a semiconductor device with reduced contact resistance and resistance between the first electrode and the second region and / or the second electrode can be manufactured. Further, by covering the second insulating film on the resistor with a mask before forming the refractory metal on the entire surface, the polycrystalline silicon film of the resistor can be prevented from being silicided.

According to the method of manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device having a bipolar transistor and a MOS transistor having a first region, a second region and a third region on the same semiconductor substrate, Forming a second region on a semiconductor substrate in a formation region of the second region, or forming a second region and a second electrode connected to the second region, and via an insulating film on the semiconductor substrate in a formation region of a MOS transistor. Forming a gate electrode of the MOS transistor; forming a first insulating film on the entire surface; forming an opening defining the first region of the bipolar transistor on the first insulating film; After forming the film, the polysilicon film is patterned to form a polysilicon film connected to the first region of the bipolar transistor. Forming a first electrode, the first
Forming a sidewall on the gate electrode by performing anisotropic etching on the insulating film, forming a source / drain region of the MOS transistor by performing ion implantation using the gate electrode and the sidewall as a mask; Forming a second insulating film on the MOS transistor, covering the second insulating film on the MOS transistor with a mask, and performing anisotropic etching on the second insulating film to form a first electrode in the bipolar transistor. Exposing the surface of the first electrode and the second region and / or the surface of the second electrode, forming a sidewall on the side wall of the first electrode, and forming a refractory metal on the entire surface, followed by annealing. Silicidizing the surface of the first electrode and the surface of the second region and / or the surface of the second electrode connected to the second region, and removing the mask. It is intended.

According to the above-described method of the present invention, after the refractory metal is formed on the entire surface, annealing is performed to silicide the surface of the first electrode and the second region and / or the surface of the second electrode. By doing so, it is possible to manufacture a semiconductor device in which the contact resistance and the resistance of the first electrode and the second region and / or the second electrode of the bipolar transistor are reduced. Further, by covering the second insulating film over the MOS transistor with a mask before forming the refractory metal on the entire surface, the gate electrode and the source / drain regions of the MOS transistor can be prevented from being silicided.

The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a bipolar transistor, a MOS transistor and a resistor having a first region, a second region and a third region on the same semiconductor substrate. Forming an insulating element isolation layer on the semiconductor substrate outside the bipolar transistor formation region and the MOS transistor formation region; and forming a second region on the semiconductor substrate inside the bipolar transistor formation region, or Forming a region and a second electrode connected to the region; and forming an M layer on the semiconductor substrate in a region where the MOS transistor is formed via an insulating film.
A step of forming a gate electrode of the OS transistor; a step of forming a first insulating film on the entire surface; and a step of forming an opening for defining a first region of the bipolar transistor in the first insulating film; Forming a silicon film and then patterning to form a first electrode made of polysilicon connected to the first region of the bipolar transistor and forming a resistor made of the polysilicon film on the element isolation layer Forming a sidewall on the gate electrode by performing anisotropic etching on the first insulating film;
Forming a source / drain region of a MOS transistor by performing ion implantation using the gate electrode and the sidewall as a mask, forming a second insulating film over the entire surface, and forming a second insulating film on the resistor and the MOS transistor; A step of covering the film with a mask and performing anisotropic etching on the second insulating film to form a bipolar transistor on the surface of the first electrode and the second electrode connected to the second region and / or the second region. A step of exposing the surface and forming a sidewall on the side wall of the first electrode, and after forming a high melting point metal on the entire surface, annealing is performed to make the surface of the first electrode and the second region and / or The method includes a step of silicidizing the surface of the second electrode connected to the second region and a step of removing the mask.

According to the above-described method of the present invention, after the refractory metal is formed on the entire surface, annealing is performed to silicide the surface of the first electrode and the second region and / or the surface of the second electrode. By doing so, it is possible to manufacture a semiconductor device in which the contact resistance and the resistance of the first electrode and the second region and / or the second electrode of the bipolar transistor are reduced. Further, by covering the second insulating film on the resistor and the MOS transistor with a mask before forming the high melting point metal on the entire surface, the polycrystalline silicon film of the resistor, the gate electrode and the source / drain region of the MOS transistor are silicide. Can be prevented.

[0028]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar transistor having a first region, a second region and a third region, the surface of a first electrode connected to the first region and the surface of the second region and / or The surface of the second electrode connected to the second region is silicided, an insulating sidewall is formed on the side of the first electrode, and the silicide formed on the first electrode and the second region and And / or a silicide formed on the second electrode is in contact with the sidewall.

The present invention also relates to the above semiconductor device,
The bipolar transistor and the resistor are provided on the same semiconductor substrate, and the same insulating film as the insulating sidewall is formed to cover the resistor.

According to the present invention, in the above semiconductor device,
The bipolar transistor and the MOS transistor are formed on the same semiconductor substrate, and the same insulating film as the insulating sidewall is formed to cover the gate electrode and the source / drain region of the MOS transistor.

According to the present invention, in the above semiconductor device,
The bipolar transistor and the MOS transistor are formed on the same semiconductor substrate, and the first of the bipolar transistors is formed.
And the same silicide film as the silicide film formed in the second region is formed on the surface of the gate electrode and the surface of the source / drain region of the MOS transistor.

The present invention also relates to the above semiconductor device,
The bipolar transistor, the MOS transistor, and the resistor are provided on the same semiconductor, and the same insulating film as the insulating sidewall is formed to cover the gate electrode, the source / drain region, and the resistor of the MOS transistor.

According to the present invention, in the above semiconductor device,
A bipolar transistor, a MOS transistor and a resistor are provided on the same semiconductor, and the first of the bipolar transistors
And the same silicide film as the silicide film formed in the second region is formed on the surface of the gate electrode and the surface of the source / drain region of the MOS transistor, and covers the resistance and is the same insulating film as the insulating sidewall. Is formed.

The present invention relates to a method of manufacturing a semiconductor device in which a bipolar transistor having a first region, a second region, and a third region is formed on a semiconductor substrate.
Forming a second region, or forming a second electrode connected to the second region and the second region, forming a first insulating film on the entire surface, and then forming the first region on the first insulating film. Forming an opening that defines the following conditions; and, after forming a polycrystalline silicon film on the entire surface, patterning the polycrystalline silicon film to form a first electrode made of polycrystalline silicon connected to the first region. Forming a second insulating film on the entire surface; and performing anisotropic etching on the second insulating film to form a second insulating film connected to the surface of the first electrode and the second region and / or the second region.
Exposing the surface of the first electrode and forming a sidewall on the side wall of the first electrode; forming a high melting point metal on the entire surface; and then annealing the first electrode and the second region. And / or silicidizing the surface of the second electrode connected to the second region.

According to the present invention, the first region,
A method of manufacturing a semiconductor device having a bipolar transistor having a second region and a third region and a resistor,
Forming an insulating element isolation layer on the semiconductor substrate outside the region where the bipolar transistor is formed; and forming a second region on the semiconductor substrate inside the region where the bipolar transistor is formed, or connecting to the second region and the second region. Forming a second electrode, forming a first insulating film on the entire surface, forming an opening defining an emitter in the first insulating film, and forming a polycrystalline silicon film on the entire surface. Patterning the polycrystalline silicon film to form a first polycrystalline silicon connected to the first region of the bipolar transistor.
Forming a resistor made of a polycrystalline silicon film on the element isolation layer, forming a second insulating film on the entire surface, and covering the second insulating film on the resistor with a mask. Performing anisotropic etching on the second insulating film to expose the surface of the first electrode and the second region and / or the surface of the second electrode connected to the second region;
Forming a side wall on the side wall of the first electrode;
Forming a refractory metal on the entire surface and then annealing to silicide the surface of the first electrode and the second region and / or the surface of the second electrode connected to the second region;
And a step of removing the mask.

According to the present invention, a first region, a first region,
A method of manufacturing a semiconductor device comprising a bipolar transistor and a MOS transistor having a second region and a third region, wherein the second region is formed on a semiconductor substrate in a region where the bipolar transistor is formed, or Forming a second electrode connected to the second region;
Forming a gate electrode of a MOS transistor on a semiconductor substrate in an area where an OS transistor is to be formed via an insulating film, forming a first insulating film on the entire surface, and then forming a first region of the bipolar transistor on the first insulating film; After forming a polycrystalline silicon film on the entire surface,
Patterning the polycrystalline silicon film to form a first electrode made of polycrystalline silicon connected to the first region of the bipolar transistor; and performing anisotropic etching on the first insulating film to form a gate electrode. Forming a sidewall, and performing ion implantation using the gate electrode and the sidewall as a mask to form a source /
Forming a drain region, forming a second insulating film over the entire surface, covering the second insulating film over the MOS transistor with a mask, and performing anisotropic etching on the second insulating film. Exposing the surface of the first electrode and the surface of the second region and / or the surface of the second electrode connected to the second region in the bipolar transistor, and forming a sidewall on the side wall of the first electrode After forming the refractory metal on the entire surface, annealing is performed to connect the surface of the first electrode and the second region and / or the second region connected to the second region.
And a step of removing the mask.

Further, according to the present invention, in the method of manufacturing a semiconductor device, after the step of forming a second insulating film over the entire surface,
The surface of the emitter electrode and the surface of the base region are silicided without covering the second insulating film on the OS transistor with a mask, and the surface of the gate electrode and the surface of the source / drain region of the MOS transistor are also changed. To silicide.

According to the present invention, a first region,
A method of manufacturing a semiconductor device comprising a bipolar transistor having a second region and a third region, a MOS transistor, and a resistor, wherein the semiconductor substrate outside the region where the bipolar transistor is formed and the region where the MOS transistor is formed is insulated. Forming an isolation layer, forming a second region on a semiconductor substrate in a formation region of a bipolar transistor, or forming a second region and a second electrode connected to the second region; Forming a gate electrode of a MOS transistor on a semiconductor substrate in a formation region via an insulating film; forming a first insulating film on the entire surface; and defining a first region of the bipolar transistor on the first insulating film. Forming an opening, forming a polycrystalline silicon film over the entire surface, and patterning the polycrystalline silicon film to form a bipolar film. Forming a first electrode made of polycrystalline silicon connected to the first region of the transistor, forming a resistor made of a polycrystalline silicon film on the element isolation layer, and forming an anisotropic film on the first insulating film; Forming a sidewall on the gate electrode by etching; performing ion implantation using the gate electrode and the sidewall as a mask to form source / drain regions of the MOS transistor; Forming, covering the second insulating film on the resistor and the MOS transistor with a mask, and performing anisotropic etching on the second insulating film to form a second transistor on the surface of the first electrode in the bipolar transistor. Exposing the surface of the second electrode connected to the second region and / or the second region, and forming a sidewall on the side wall of the first electrode; Forming a refractory metal on the entire surface and then annealing to silicify the surface of the first electrode and the second region and / or the surface of the second electrode connected to the second region; And a step of removing the semiconductor device.

Further, according to the present invention, in the method for manufacturing a semiconductor device, the step of covering the second insulating film with a mask may include:
The second insulating film on the resistor is covered with a mask, but the second insulating film on the MOS transistor is not covered with the mask.

FIG. 1 is a schematic configuration diagram (cross-sectional view) of a semiconductor device according to an embodiment of the present invention. This semiconductor device is an embodiment of the aforementioned BiCMOS semiconductor device,
As in the BiCMOS semiconductor device shown in FIG. 12, a polycrystalline silicon resistor 1 and an NPN bipolar transistor 2
, The NMOS transistor 3 and the PMOS transistor 4 are formed on the same silicon substrate 11.

The polycrystalline silicon resistor 1 is composed of a polycrystalline silicon film 25 (25R) formed on the insulating film 24, and its entire surface is covered with a thin oxide film 32. This polycrystalline silicon resistor 1 is connected to a silicon substrate 11
And an N-type epitaxial layer 13 on the thick element isolation layer 22 formed on the surface of the semiconductor substrate. The semiconductor substrate (11, 1) under the element isolation layer 22 in the portion where the polycrystalline silicon resistor 1 is formed
In 3), a P ⁺ channel stop region 14 is formed.

The NPN bipolar transistor 2 has a structure in which an N ⁺ buried layer 12 is formed on a semiconductor substrate composed of a silicon substrate 11 and an N-type epitaxial layer 13 thereon. In the N-type epitaxial layer 13, a P ⁺ base region 17 and a graft base region 17B are formed, and further, an N ⁺ emitter region 20 is formed. In the collector drawer, N ⁺
13S and a collector lead-out region 21 are formed. An emitter electrode 25 (25E) made of a polycrystalline silicon film is connected to the emitter region 20. Then, the graft base region 17B, the emitter electrode 25
(25E) Metal electrodes 30B, 30E, and 30C made of, for example, Al are connected to the collector lead-out region 21, respectively. With such a configuration, the NPN bipolar transistor 2 is a so-called washed-emitter bipolar transistor.

The NMOS transistor 3 is composed of the semiconductor substrate 1
P-type semiconductor well regions 15 are formed in the insides 1 and 13. Then, N ⁺ source / drain regions 18 are formed in the P-type semiconductor well region 15. N (the channel side) inside these source / drain regions 18
A low-concentration LDD region 18L of the mold is formed. A gate electrode G having a laminated structure of a polycrystalline silicon film 26 and a WSi film 27 is formed on the channel via a gate oxide film 23. On the side wall of the gate electrode G, a side wall 28 made of an insulating film is formed. Electrodes 30S and 30D made of, for example, Al are connected to the source / drain regions 18, respectively.

The PMOS transistor 4 is a semiconductor substrate 1
An N ⁺ buried layer 12 is formed inside 1 and 13, and an N-type semiconductor well region 16 is formed on the surface. Then, P ⁺ source / drain regions 19 are formed in the N-type semiconductor well region 16. Inside the source / drain region 19 (on the channel side), a P-type low-concentration LDD region 19L is formed. A polycrystalline silicon film 26 is formed on the channel through a gate oxide film 23.
And a WSi film 27 are formed to form a gate electrode G having a laminated structure. On the side wall of the gate electrode G, a side wall 28 made of an insulating film is formed. In the source / drain regions 19, the electrodes 3 made of, for example, Al
0S and 30D are connected.

In the present embodiment, particularly in NPN bipolar transistor 2, metal electrode 30 made of Al
B, 30E, and 30C, ie, the graft base region 17B, the emitter electrode 25 (25E) made of a polycrystalline silicon film, and the vicinity of the interface of the collector lead-out region 21 are silicided to form a silicide film 31 such as TiSi _2.
Are formed.

As a material of the silicide film 31, a compound of silicon and a metal having a high melting point, for example, a metal selected from Ti, W, Co, Ni, Pt, and Mo is used.

As described above, the metal electrodes 30B, 30E, 30
Since the silicide film 31 is formed near the interface of the connection with C, these metal electrodes 30B, 30E, 3
The contact resistance with 0C can be reduced. Further, the graft base region 17B, the emitter electrode 25E,
The resistance of the collector lead-out region 21 itself is also reduced.

In this embodiment, in particular, a thin oxide film 32 formed so as to cover polycrystalline silicon resistor 1 is formed of NP
The emitter electrode 25 (25) of the N bipolar transistor 2
E) is also formed on the side wall to form a side wall. Further, in the NMOS transistor 3 and the PMOS transistor 4, the thin oxide film 32 forms the gate electrode G and the side wall 2 of the side wall of the gate electrode G.
8 and the source / drain regions 18 and 19.

Since the thin oxide film 32 is formed, the surface of the polycrystalline silicon film 25 (25R) of the polycrystalline silicon resistor 1 is protected from silicidation, as described later, so that a predetermined resistance is obtained. Value can be secured.

The thin oxide film 32 is formed as a side wall on the side wall of the emitter electrode 25 (25E) of the NPN bipolar transistor 2. Thus, the silicide film 31 on the surface of the emitter electrode 25 (25E) and the silicide film 31 on the surface of the graft base region 17B are brought into contact with the sidewall 32 to form a sufficiently wide silicide film 31 to reduce the contact resistance. And the silicide films 31 can be separated so as not to be short-circuited. If these silicide films 31 are short-circuited, there arises a problem that the NPN bipolar transistor 2 does not operate properly.

Next, a method of manufacturing the semiconductor device shown in FIG. 1 of the present embodiment will be described with reference to FIGS. First, the NP on the surface of the P-type (100) silicon substrate 11
S using Sb 2 O 3 at 1200 ° C. in the N transistor formation region (2) and the PMOS transistor formation region (4).
b N ⁺ buried layer 12 is formed by vapor phase diffusion. Thereafter, an N-type epitaxial layer 13 of 1 to 5 Ωcm is formed on the P-type silicon substrate 11 to a thickness of 0.7 to 2.0 μm.

After the entire surface is thermally oxidized by 50 nm, Si ₃ N ₄ is formed to a thickness of 100 nm by the CVD method. After forming a pattern for opening the active region and forming Si ₃ N ₄ and SiO ₂ , the silicon substrate 11 is
Etch 50 nm. After that, 1000-1050
At a temperature of 3 ° C. for 3 to 8 hours.
First, a recessed field oxide film 22 having a thickness of 600 to 1500 nm is formed.

Subsequently, the Si ₃ N ₄ film is removed and the surface is flattened. Thereafter, P (phosphorus) is applied to the collector lead-out portion of the NPN bipolar transistor 2 with an energy of 70 ke.
V, and the ion implanted at a dose 5 × 10 ¹⁵ cm ^-2, by diffusing heat treated further at 1000 ° C. 30 minutes to form a N ⁺ sinker 13S. Thereafter, boron is supplied at an energy of 200 to 720 keV and a dose of 1 × 10
Ion implantation is performed at ¹³ to 1 × 10 ¹⁴ cm ⁻² to form a P ⁺ channel stop region 14 and a P-type semiconductor well region 15 of an NMOS transistor formation region (3). Also,
An N-type semiconductor well region 16 is formed in the N-type epitaxial layer 13 in the PMOS transistor formation region (4) (see FIG. 3A).

Next, thermal oxidation at 850 to 950 ° C.
A gate oxide film 23 having a thickness of 15 to 50 nm is formed on the surface. Thereafter, a 100 nm-thick N ⁺ polycrystalline silicon film 26 doped with phosphorus by CVD over the entire surface and a
A WSi film 27 having a thickness of 00 nm is sequentially formed. Then, using a resist pattern, Cl ₂ / CH ₂ F ₂ / SF ₆
The polycrystalline silicon film 26 and the WSi film 27 are patterned by dry etching using a gas system.
The gate electrodes G of the MOS transistors 3 and 4 formed by laminating the polycrystalline silicon film 26 and the WSi film 27 are formed.

Next, by performing ion implantation using the gate electrode G as a mask, an N ⁻ LDD region 18L is formed in the P-type semiconductor well region 15 in the NMOS transistor formation region (3), and the PMOS transistor formation region is formed. (4) P ⁻ LD in the N-type semiconductor well region 16
A D region 19L is formed. Further, a P ⁺ base region 17 is formed in the NPN bipolar transistor formation region (2) (see FIG. 2B). Note that the base region 17 is P ⁻
May be formed simultaneously with the LDD region 19L.

Thereafter, an SiO ₂ film 24 for LDD side wall spacers is formed to a thickness of 150 to 250 nm by CVD over the entire surface covering the surface. Next, an opening 24H is formed in the emitter portion of the NPN bipolar transistor formation region (2) of the SiO ₂ film 24 by reactive ion etching to expose the semiconductor portion. Thereafter, a polycrystalline silicon film 25 for forming the emitter region 20 and the resistor 1 is formed on the entire surface to a thickness of 100 to 150 nm.

Then, the NPN bipolar transistor 2
As (arsenic) to the polycrystalline silicon film 25 of the emitter portion
Energy 30-70 keV, dose 1 × 10 ¹⁵ ~
Ion implantation is performed at 1 × 10 ¹⁶ cm ⁻² . In order to obtain a desired resistance value, As is applied to the polycrystalline silicon film 25 of the polycrystalline silicon resistance portion 1 at a dose of 1 × 10 ¹³ to 1 × 10 ^14.
Ion implantation is performed at cm ⁻² (see FIG. 3C).

Next, dry etching of the polycrystalline silicon film 25 is performed using a resist pattern that leaves the emitter portion of the NPN bipolar transistor 2 and the polycrystalline silicon resistance portion 1. Thereby, the polysilicon film 25 (25R) of the polysilicon resistor 1 and the polysilicon film 25 (2R) of the emitter electrode of the NPN bipolar transistor 2 are formed.
5E) remains.

Subsequently, by etching the SiO ₂ films 24 and 23, LDD sidewall spacers 24 (28) are formed on the side walls of the gate electrode G (FIG. 3D).
reference).

Next, using the gate electrode G as a mask, As
By implanting (arsenic) ions, the source / drain regions 18 of the NMOS transistor 3 are formed, and energy of 25 to 40 keV and a dose of 2 × 1 are applied to the collector lead-out portion of the NPN bipolar transistor 2.
As is ion-implanted at 0 ^{15 to} 7 × 10 ¹⁵ cm ⁻² to form a collector extraction region 21. Also, the gate electrode G,
Using the emitter electrode 25E as a mask, the energy 25 to
The source / drain regions 19 of the PMOS transistor 4 are self-aligned by ion-implanting BF ₂ at 40 keV and at a dose of 2 × 10 ^{15 to} 7 × 10 ¹⁵ cm ⁻² .
The graft base region 17B of the NPN bipolar transistor 2 is formed. Subsequently, 1000C to 1100C,
Anneal for 5 to 30 seconds to form source / drain region 1
At the same time as the annealing of 8, 19 and others, As in the emitter electrode 25E made of a polycrystalline silicon film of the NPN bipolar transistor 2 is diffused into the base region 17 and N ⁺
(FIG. 4E).

Next, an SiO ₂ film 3 is formed on the entire surface by CVD.
2 is formed to a thickness of 50 to 150 nm. Next, MO
A resist pattern 33 covering S transistor portions 3 and 4 and polycrystalline silicon resistor portion 1 and opening NPN bipolar transistor portion 2 is formed (see FIG. 4F).

Next, by reactive ion etching, N
The SiO ₂ film 32 of the PN bipolar transistor section 2 is removed. At this time, Si is formed on the side wall of the emitter electrode 25E.
The O ₂ film 32 remains as a sidewall.

Subsequently, a refractory metal such as titanium is formed on the entire surface by sputtering or the like,
Anneal for about 1 minute, and refractory metal is
5E, the silicide film 31 is formed by reacting with the silicon in the graft base region 17B to form silicide. After that, the unreacted high melting point metal formed on the insulating film is removed by wet etching (see FIG. 5G).

At this time, since the MOS transistor portions 3 and 4 are covered with the SiO ₂ film 32, they are not silicided. Therefore, the compatibility of characteristics with the conventional MOS transistor can be ensured, and the design environment and the like can be shared. The polycrystalline silicon resistor 1 is made of SiO ₂
Since the film 32 is covered with the film 32, high resistance can be realized without being silicided. Furthermore, since the SiO ₂ film 32 is formed in a sidewall shape on the side wall of the emitter electrode 25E of the NPN bipolar transistor 2, a silicide bridge is formed between the emitter electrode and the graft base silicide film 31 during the silicidation process. The short circuit between the emitter and the base caused by the short circuit can be prevented.

Thereafter, an interlayer insulating film 29 is formed under the first layer of aluminum wiring (not shown) by a usual method, and after the surface is flattened, contact holes and metal electrodes 30B, 3B are formed.
0E, 30C, 30S, 30D (see FIG. 5H
reference). Thus, the BiC composed of the NMOS transistor 4, the PMOS transistor 3, the NPN bipolar transistor 2, and the polysilicon resistor 1 shown in FIG.
A MOS semiconductor device is formed.

According to the present embodiment described above, in NPN bipolar transistor 2, silicide film 31 is formed on the surface of emitter electrode 25E, the surface of graft base region 17B, and the surface of collector extraction region 21. Therefore, these electrodes 25E and the regions 17B and 21
Contact resistance between the metal electrodes 30E, 30B, and 30C connected to the first and second electrodes can be reduced. Further, the resistances of the emitter electrode 25E, the graft base region 17B, and the collector extraction region 21 themselves are also reduced.

As a result, the switching speed can be increased by reducing the contact resistance. Further, since the emitter resistance and the base resistance are reduced, noise is reduced, the lowering of the maximum oscillation frequency is prevented, and good high-frequency characteristics are enabled.

Since the surface of the polycrystalline silicon resistor 1 is covered with the thin oxide film 32, the polycrystalline silicon resistor 1
Since the polycrystalline silicon film 25R is not silicided, a desired high resistance value can be obtained without a decrease in resistance value due to silicidation.

The thin oxide film 32 is formed on the gate electrodes G of the MOS transistors 3 and 4 and the source / drain regions 1.
8 and 19 also cover the MOS transistors 3 and 4
Can be formed similarly to conventional designs. That is,
The MOS transistors 3 and 4 ensure the same characteristics as the conventional one, and the NPN bipolar transistor 2 can increase the speed.

Further, a thin oxide film 32 covering the surface of the polycrystalline silicon resistor 1 forms an NPN bipolar transistor 2
Is formed as a side wall on the side wall of the emitter electrode 25E, and the silicide film 31 on the surface of the emitter electrode 25E and the silicide film 31 on the surface of the graft base region 17B are brought into contact with the side wall 32 to provide a sufficiently wide area. A silicide film 31 is formed to reduce the contact resistance, and these silicide films 3 are formed.
1 can be separated from one another so as not to short circuit. This prevents the emitter-base short circuit,
NPN bipolar transistor 2 can be operated well. In addition, even if the element is miniaturized, a short circuit between the emitter and the base can be prevented by the sidewall 32, so that high integration of the semiconductor device can be achieved.

Further, since oxide film 32 covering polycrystalline silicon resistor 1 and sidewall 32 formed on the side wall of emitter electrode 25E are formed of the same oxide film 32, they are formed in a series of steps. be able to. Therefore, the steps to be increased as compared with the conventional manufacturing steps shown in FIGS. 13 to 15 include a step of covering the entire surface with the oxide film 32 and a step of covering the oxide film 32 with the resist mask 33 and performing anisotropic etching. This is a step of forming a side wall made of the oxide film 32 on the side wall of the emitter electrode 25E, and an increase in the number of steps is small. Since these steps can be performed by being incorporated in a series of manufacturing steps, the time required for the steps does not increase much.

That is, according to the present embodiment, a high-performance semiconductor device can be manufactured without increasing the number of steps and without significantly increasing the manufacturing cost.

Next, another embodiment of the present invention will be described. In this embodiment, in addition to the emitter lead-out portion and the graft base region of the NPN transistor silicided in the previous embodiment, the source / drain region and the gate electrode of the MOS transistor are silicided. This is an effective technique when compatibility with a conventional MOS transistor is not required.

FIG. 6 is a schematic configuration diagram (cross-sectional view) of the semiconductor device of the present embodiment. This semiconductor device is similar to the semiconductor device of the previous embodiment shown in FIG.
It constitutes a semiconductor device.

In the present embodiment, in particular, the gate electrodes G of the MOS transistors 3 and 4 are formed by a laminated structure of the polycrystalline silicon film 26 and the silicide film 31, and the source / drain regions 18 and 19 is silicided to form a silicide film 31.

Thus, also in the MOS transistors 3 and 4, the gate electrode G and the source / drain regions 18,
19 can be reduced in contact resistance with the metal electrode connected thereto. Also, the source / drain regions 18,
19 can also reduce the diffusion resistance.

However, the source / drain regions 18 and 19
Since the characteristics of the MOS transistors 3 and 4 may change from the case where the silicide film 31 is not formed due to the silicide film 31 formed on the gate electrode G, the change in the characteristics of the MOS transistors 3 and 4 is taken into consideration at the time of design. There is a need to.

Further, in FIG. 1, the SiO ₂ film 32 is
The entirety including the gate electrodes G and the sidewalls 28 of the S transistors 3 and 4 was covered. On the other hand, in the present embodiment, the SiO ₂ film 32 remains only on the side walls of the gate electrodes G of the MOS transistors 3 and 4, and forms a side wall insulating film together with the side wall 28 formed from the oxide film 24. ing.

The other structure is the same as that of the semiconductor device of the previous embodiment shown in FIG. 1, and the same reference numerals are given and the repeated explanation is omitted.

Next, a method of manufacturing the semiconductor device shown in FIG. 6 of the present embodiment will be described with reference to FIGS.

First, as shown in FIG. 7A, assume the state of FIG. 2A of the previous embodiment.

Next, thermal oxidation at 850-950 ° C.
A gate oxide film 23 having a thickness of 15 to 50 nm is formed on the surface. Thereafter, a 200 nm thick N ⁺ polycrystalline silicon film 26 doped with phosphorus is formed on the entire surface by CVD. Then, using a resist pattern, Cl ₂ / CH
By dry etching with ₂ F ₂ / SF ₆ gas system,
The polycrystalline silicon film 26 is patterned to form the gate electrodes G of the MOS transistors 3 and 4.

Next, the gate electrode 26 (G) is
By performing ion implantation as a mask, NMOS
In the P-type semiconductor well region 15 in the transistor formation region (3)
N ^-Forming the LDD region 18L of the PMOS transistor
P in the N-type semiconductor well region 16 in the star formation region (4)
^-LDD region 19L is formed. Also, NPN Bipo
In the transistor region (2), P⁺Base area of
17 (see FIG. 7B). The base area 1
7 is P^-May be formed simultaneously with the LDD region 19L.

Thereafter, an SiO ₂ film 24 for LDD sidewall spacers is formed on the entire surface covering the surface to a thickness of 150 to 250 nm by the CVD method. Next, an opening 24H is formed in the emitter portion of the NPN bipolar transistor formation region (2) of the SiO ₂ film 24 by reactive ion etching to expose the semiconductor portion. Thereafter, a polycrystalline silicon film 25 for forming the emitter region 20 and the resistor 1 is formed on the entire surface to a thickness of 100 to 150 nm.

Then, the NPN bipolar transistor 2
As (arsenic) to the polycrystalline silicon film 25 of the emitter portion
Energy 30-70 keV, dose 1 × 10 ¹⁵ ~
Ion implantation is performed at 1 × 10 ¹⁶ cm ⁻² . In order to obtain a desired resistance value, As is applied to the polycrystalline silicon film 25 of the polycrystalline silicon resistance portion 1 at a dose of 1 × 10 ¹³ to 1 × 10 ^14.
Ion implantation is performed at cm ⁻² (see FIG. 8C).

Next, dry etching of the polycrystalline silicon film 25 is performed using a resist pattern that leaves the emitter portion of the NPN bipolar transistor 2 and the polycrystalline silicon resistance portion 1. Thus, the emitter electrode 2 composed of the polycrystalline silicon film 25 (25R) of the polycrystalline silicon resistor 1 and the polycrystalline silicon film of the NPN bipolar transistor 2
5 (25E) remains.

Subsequently, by etching the SiO ₂ films 24 and 23, LDs are formed on the side walls of the gate electrode 26 (G).
The D sidewall spacer 24 (28) is formed (see FIG. 8D).

Next, As (arsenic) is ion-implanted using the gate electrode 26 (G) as a mask, thereby forming the NMOS.
A source / drain region 18 of the transistor 3 is formed, and a collector lead portion of the NPN bipolar transistor 2 has an energy of 25 to 40 keV and a dose of 2
As is ion-implanted at 10 ^{15 to} 7 10 ¹⁵ cm ^-2 to form a collector extraction region 21. Using the gate electrode 26 (G) and the emitter electrode 25 E as a mask, energy is 25 to 40 keV, and dose is 2 × 10 ^{15 to} 7 × 1.
0 By the ¹⁵ cm ^-2 in BF ₂ is ion-implanted to form source / drain regions 19, NPN bipolar transistor 2 graft base region 17B of the PMOS transistor 4 in a self-aligned manner. Then, 1000 ° C ~
Anneal at 1100 ° C. for 5 to 30 seconds to anneal the source / drain regions 18 and 19,
As in the emitter electrode 25E made of polycrystalline silicon of the N bipolar transistor 2 is diffused into the base region 17 to form the N ⁺ emitter region 20 (FIG. 9E).
reference).

Next, an SiO ₂ film 3 is formed on the entire surface by CVD.
2 is formed to a thickness of 50 to 150 nm. Subsequently, a resist pattern 34 covering the polycrystalline silicon resistance portion 1 and opening the NPN bipolar transistor portion 2 and the MOS transistor portions 3 and 4 is formed (see FIG. 9F).

Next, by reactive ion etching, N
The SiO ₂ film 32 of the PN bipolar transistor section 2 and the MOS transistor sections 3 and 4 is removed. At this time, the SiO ₂ film 32 remains on the side wall of the emitter electrode 25E in a sidewall shape. Further, the SiO ₂ film 32 remains in a sidewall shape outside the sidewall 28 on the sidewall of the gate electrodes 26 (G) of the MOS transistors 3 and 4, and the thickness of the sidewall increases.

Subsequently, a high-melting point metal such as titanium is formed on the entire surface by sputtering or the like.
Anneal for about 1 minute, and refractory metal is
5E, the silicon in the graft base region 17B, the polycrystalline silicon film 26 of the gate electrode G of the MOS transistor, and the silicon in the source / drain regions 18 and 19 react with each other to form silicide, thereby forming silicide films 31 respectively. After that, the unreacted high melting point metal formed on the insulating film is removed by wet etching (see FIG. 10G).

At this time, the polycrystalline silicon resistor 1 is made of SiO
_Since it is covered with the _two films 32, it is not silicided and high resistance can be realized. Further, the polycrystalline silicon film 25E at the emitter lead-out portion of the NPN bipolar transistor 2
Since the SiO ₂ film 32 is formed in a side wall shape on the side wall of the emitter, a silicide bridge is formed between the emitter lead-out portion and the graft base silicide film 31 during the silicidation process to cause a short-circuit.
The short circuit of the base can be prevented.

In a MOS transistor, the diffusion resistance of the source / drain regions is reduced by silicidation.
The contact resistance with the metal can be reduced, and high speed can be realized.

Thereafter, an interlayer insulating film 29 under the first layer aluminum wiring (not shown) is formed by a usual method, and after the surface is flattened, contact holes and metal electrodes 30B, 3B are formed.
0E, 30C, 30S, and 30D (see FIG. 10).
H). In this manner, the Bi composed of the NMOS transistor 4, the PMOS transistor 3, the NPN bipolar transistor 2, and the polysilicon resistor 1 shown in FIG.
A CMOS semiconductor device is formed.

According to the present embodiment described above, similarly to the previous embodiment, in NPN bipolar transistor 2, emitter electrode 25E, graft base region 17B,
Collector extraction region 21 and connected metal electrode 30
E, 30B, 30C to reduce the contact resistance between,
The switching speed can be increased. Emitter resistance and base resistance are reduced, noise is reduced, and good high-frequency characteristics are enabled. Also, a polycrystalline silicon resistor 1
Is covered with the thin oxide film 32, a desired high resistance value can be obtained.

Since this thin oxide film 32 is formed as a sidewall on the side wall of emitter electrode 25E of NPN bipolar transistor 2, short circuit between the emitter and the base is prevented, and NPN bipolar transistor 2 operates properly. Can be done.

According to the present embodiment, since the silicide film 31 is also formed on the surfaces of the gate electrodes G of the MOS transistors 3 and 4 and the surfaces of the source / drain regions 18 and 19, the MOS transistors 3 and 4 Contact resistance with a metal electrode (not shown) connected to the gate electrode G,
The contact resistance between the metal electrodes 30S and 30D connected to the source / drain regions 18 and 19 and the diffusion resistance of the source / drain regions 18 and 19 can be reduced. That is, in the MOS transistors 3 and 4 as well, the speed can be increased similarly to the NPN bipolar transistor 2.

According to the present embodiment, the insulating films 28, 3 are formed on the side walls of the gate electrodes G of the MOS transistors 3, 4.
Since the sidewall made of 2 is formed, it is possible to prevent short-circuit between the silicide film 31 formed on the gate electrode G and the silicide film 31 formed on the source / drain regions 18 and 19. This allows MO
The short circuit between the gate and the source / drain of the S transistors 3 and 4 can be prevented.

Therefore, even if the element is miniaturized, the emitter-emitter of the NPN bipolar transistor 2 is formed by the sidewall.
Since short-circuiting of the base and short-circuiting of the gate-source / drain of the MOS transistors 3 and 4 can be prevented, high integration of the semiconductor device can be achieved.

Further, in this embodiment, FIG.
15 are increased in comparison with the conventional manufacturing process shown in FIG. 15, a process of covering the entire surface with an oxide film 32, and a process of covering the oxide film 32 with a resist mask 34 and performing anisotropic etching to form an emitter electrode 25 </ b> E and Oxide film 32 on the side wall of gate electrode G
This is a step of forming a sidewall made of, and an increase in the number of steps is small. Since these steps can be performed by being incorporated in a series of manufacturing steps, the time required for the steps does not increase much.

That is, according to this embodiment, a high-performance semiconductor device can be manufactured without increasing the number of steps and without increasing the manufacturing cost.

Next, still another embodiment of the present invention will be described. In the above embodiments, the emitter electrode 25E of the bipolar transistor and the graft base region 17
B, a silicide film 31 was formed in the collector lead-out region 21. On the other hand, in the present embodiment, a bipolar transistor is provided with a base lead portion connected to the base region, and a silicide film is formed on the electrode of the base lead portion and the base region.

FIG. 11A is a schematic configuration diagram (cross-sectional view) of a main part of a semiconductor device according to still another embodiment of the present invention. FIG. 11A shows a polycrystalline silicon resistor 1 and an NPN bipolar transistor 2. In this semiconductor device, in particular, the NPN bipolar transistor 2 is configured by a heterojunction bipolar transistor (HBT).

That is, the semiconductor substrate 4 made of N-type silicon
1, an insulating film 42 is formed, and a P ⁺ semiconductor layer 43 made of SiGe is formed including the opening of the insulating film 42. The main part of the P ⁺ semiconductor layer 43 that is in contact with the semiconductor substrate 41 is a single crystal layer 43S, and the insulating film 42
Above and in the vicinity thereof are polycrystalline layers 43P. Near the central surface of the single crystal layer 43S, an N-type emitter region 4 is formed.
5 are formed.

The emitter of the bipolar transistor 2 includes a polycrystalline silicon film 46 and a silicide film 4 on the surface thereof.
7, an emitter electrode is formed, and sidewalls made of an insulating film 48 are formed on both side walls of the emitter electrode. The semiconductor layer 4 outside the side wall 48
3, a silicide film 47 is also formed.

On the other hand, in the polycrystalline silicon resistor 1, the polycrystalline silicon film 49 is covered with the above-mentioned insulating film 48 constituting the side wall. The polycrystalline silicon film 49 is the polycrystalline silicon film 4 of the emitter electrode of the bipolar transistor 2.
6 can be formed simultaneously.

With such a configuration, since the silicide film 47 is formed, the polycrystalline layer 4 serving as an electrode of the base lead portion, that is, an electrode connected to the base region is formed.
The contact resistance between 3P and the metal electrode connected to polycrystalline layer 43P can be reduced. Similarly to the above-described embodiments, the insulating film 48 prevents the polycrystalline silicon film 49 of the polycrystalline silicon resistor 1 from being silicided, and the side wall 48 forms the silicide film 47 of the emitter electrode of the bipolar transistor 2 and the base. A short circuit between the single crystal layer 43S corresponding to the region and the silicide film 47 can be prevented.

The structure of the semiconductor device shown in FIG.
By forming the MOS transistors 3 and 4 shown in FIGS. 1 and 6 on the same semiconductor substrate 41, the BiCMO
An S semiconductor device can be configured.

In FIG. 11A, the silicide film 47 is formed on the single crystal layer 43S corresponding to the base region and the polycrystal layer 43P corresponding to the electrode of the base lead portion, but only in the polycrystal layer 43P. A configuration in which the silicide film 47 is formed is also possible. A cross-sectional view of one embodiment in this case is illustrated in FIG. 11B. In the structure shown in FIG. 11B, the side wall 4 of the emitter lead-out portion is opened from the opening of the insulating film 42.
8, the silicide film is formed only on the polycrystalline layer 43P of the semiconductor layer 43. Also in the case shown in FIG. 11B, the effect of reducing the contact resistance and the effect of preventing a short circuit between the emitter and the base can be realized.

In the above embodiments, the present invention is applied to the NPN bipolar transistor 2.
The present invention can be similarly applied to a P bipolar transistor. Also in that case, the contact resistance can be reduced by siliciding the polycrystalline silicon or the graft base region of the emitter electrode of the PNP bipolar transistor, for example, and the short-circuit of the silicide film can be prevented by the sidewall.

The present invention is not limited to the above-described embodiment, and may take various other configurations without departing from the gist of the present invention.

[0112]

According to the present invention, since the surface of the first electrode and the surface of the second region and / or the surface of the second electrode of the bipolar transistor are silicided,
Contact resistance between the first electrode, the second region and / or the metal electrode connected to the second electrode, the resistance of the first electrode,
The resistance of the region and / or the second electrode can be reduced. As a result, the switching speed of the bipolar transistor can be increased, and noise can be reduced to improve high-frequency characteristics.

According to the present invention, the surface of the first electrode of the bipolar transistor and the second region and / or the second
When the surface of the first electrode is silicided, since the side wall is formed by the second insulating film on the side wall of the first electrode, a short circuit between the first region and the second region is prevented. Can be. Thereby, the bipolar transistor can be favorably operated. Therefore, even if the element is miniaturized, a short circuit between the first region and the second region can be prevented by the sidewall, so that higher integration of the semiconductor device can be achieved.

When a bipolar transistor and a resistor are formed on a semiconductor substrate, and the surface of the resistor is covered with a second insulating film forming a side wall of a side wall of the first electrode of the bipolar transistor, the resistance is increased. Is not silicided, so that the resistance value does not decrease due to silicidation, and a desired high resistance value can be obtained. In this case, as compared with the conventional manufacturing process, only the step of forming the second insulating film and the step of performing anisotropic etching using the second insulating film as a mask are added. In addition, it is possible to reduce the increase in the number and to easily incorporate it into a series of manufacturing steps. Therefore, the performance of the semiconductor device can be improved without significantly increasing the manufacturing cost.

In the case where a bipolar transistor and a MOS transistor are formed on a semiconductor substrate, the
When the S transistor is configured to be covered with the second insulating film, an effect of securing the same characteristics as those of the conventional MOS transistor can be obtained. On the other hand, when the surface of the gate electrode and the source / drain region of the MOS transistor is silicided, the contact resistance with the metal electrode and the diffusion resistance of the source / drain region are reduced to reduce the MO resistance.
The effect of increasing the speed of the S transistor and preventing the gate-source / drain short circuit by the side wall of the second insulating film, miniaturizing the MOS transistor, and achieving high integration can be obtained.

That is, according to the present invention, a high-performance semiconductor device can be manufactured without increasing the number of steps and without increasing the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram (cross-sectional view) of a semiconductor device according to an embodiment of the present invention;

FIGS. 2A and 2B are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

FIGS. 3C and 3D are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

FIGS. 4E and 4F are process diagrams showing a manufacturing process of the semiconductor device of FIG. 1;

FIG. 5 is a process diagram showing a process of manufacturing the semiconductor device of FIG. 1;

FIG. 6 is a schematic configuration diagram (cross-sectional view) of a semiconductor device according to another embodiment of the present invention.

FIGS. 7A and 7B are process diagrams showing the manufacturing process of the semiconductor device of FIG. 6;

FIGS. 8C and 8D are process diagrams showing the manufacturing process of the semiconductor device of FIG. 6;

FIGS. 9A and 9E are process diagrams showing a manufacturing process of the semiconductor device of FIG. 6;

FIG. 10 is a process diagram showing a manufacturing process of the semiconductor device of FIG. 6;

FIG. 11A is a schematic configuration diagram (cross-sectional view) of a main part of a semiconductor device according to still another embodiment of the present invention; B FIG.
FIG. 13 is a cross-sectional view showing another embodiment of the bipolar transistor in the semiconductor device of FIG.

FIG. 12 is a schematic configuration diagram (cross-sectional view) of a conventional BiCMOS semiconductor device.

13A and 13B are process diagrams showing a manufacturing process of the semiconductor device of FIG. 12;

14C and 14D are process diagrams showing the steps of manufacturing the semiconductor device of FIG. 12;

FIGS. 15E and 15F are process diagrams showing a manufacturing process of the semiconductor device of FIG. 12;

[Explanation of symbols]

1 polycrystalline silicon resistor, 2 NPN bipolar transistor, 3 NMOS transistor, 4 PMOS transistor, 11 P type semiconductor substrate, 12 buried layer,
13 epitaxial layer, 14 channel stop region, 15 P-type semiconductor well region, 16 N-type semiconductor well region, 17 base region, 17B graft base region, 18, 19 source / drain region, 18L, 1
9L LDD region, 20, 45 Emitter region, 21
Collector extraction region, 22 device isolation layer, 23 gate oxide film, 24, 42, 48 insulating film, 25, 26 polycrystalline silicon film, 27 WSi film, 28 sidewall, 29 interlayer insulating film, 31, 47 silicide film, 3
2 Oxide film, 33, 34 resist pattern, 41 semiconductor substrate, 43S single crystal layer, 43P polycrystal layer, 4
6,49 polycrystalline silicon film, G gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8234 21/8249 F-term (Reference) 4M104 AA01 BB01 BB24 CC01 CC05 DD04 DD06 DD26 DD37 DD64 DD84 EE09 EE12 GG10 GG14 GG15 GG19 5F003 AP00 BA93 BB05 BB06 BB08 BC08 BE07 BE08 BE90 BF03 BF90 BG10 BH00 BH07 BH08 BH18 BJ15 BJ20 BP31 BP41 BP93 BP94 BS09 5F048 AA01 AA10 AC05 AC10 BB05 CA13 BG08 BB08 BC01 BC06 5F082 AA06 AA08 BA04 BA11 BA28 BA31 BA36 BA39 BA47 BC01 BC09 BC15 DA03 EA13 EA15 EA31

Claims (12)

[Claims] 1. A surface of a first electrode connected to the first region of a bipolar transistor having a first region, a second region, and a third region, and a surface of the second region and / or the second region. The surface of the second electrode connected to the first electrode is silicided, an insulating sidewall is formed on the side of the first electrode, and the silicide formed on the first electrode and the second region and And / or a silicide formed on the second electrode is in contact with the sidewall. 2. The semiconductor device according to claim 1, wherein the bipolar transistor and the resistor are provided on the same semiconductor substrate, and the same insulating film as the insulating sidewall is formed so as to cover the resistor. 13. The semiconductor device according to claim 1. 3. The bipolar transistor and the MOS transistor are formed on the same semiconductor substrate, and the same insulating film as the insulating sidewall is formed to cover a gate electrode and a source / drain region of the MOS transistor. The semiconductor device according to claim 1, wherein: 4. The bipolar transistor and the MOS transistor are formed on the same semiconductor substrate, and the same silicide film as the silicide film formed on the first electrode and the second region of the bipolar transistor is formed on the MOS transistor. 2. The semiconductor device according to claim 1, wherein said semiconductor device is formed on a surface of said gate electrode and a surface of said source / drain region. 5. An insulating film which has the bipolar transistor, the MOS transistor and a resistor on the same semiconductor, and covers the gate electrode and the source / drain regions of the MOS transistor and the resistor and is the same as the insulating sidewall. The semiconductor device according to claim 1, wherein the semiconductor device is formed. 6. The bipolar transistor, the MOS transistor, and a resistor on the same semiconductor, and the same silicide film as the silicide film formed on the first electrode and the second region of the bipolar transistor is formed on the MO.
2. The insulating film according to claim 1, wherein an insulating film is formed on the surface of the gate electrode and the surface of the source / drain region of the S transistor, and covers the resistance and is the same as the insulating sidewall. Semiconductor device. 7. A method of manufacturing a semiconductor device in which a bipolar transistor having a first region, a second region, and a third region is formed on a semiconductor substrate, wherein the second region is formed on the semiconductor substrate. Forming the second region and a second electrode connected to the second region; forming a first insulating film on the entire surface; and forming an opening in the first insulating film to define the first region. Forming a polycrystalline silicon film over the entire surface, and then patterning the polycrystalline silicon film to form a first electrode made of the polycrystalline silicon film connected to the first region; Forming a second insulating film on the entire surface; performing anisotropic etching on the second insulating film to connect the surface of the first electrode to the second region and / or the second region. When the exposed surface of the second electrode Forming a side wall on the side wall of the first electrode; forming a high melting point metal on the entire surface; and annealing the surface to form a surface of the first electrode and the second region and / or the second region. Silicidizing the surface of the second electrode connected to the two regions. 8. A method of manufacturing a semiconductor device comprising a bipolar transistor having a first region, a second region, and a third region and a resistor on the same semiconductor substrate, wherein the semiconductor device is provided outside the region where the bipolar transistor is formed. Forming an insulating element isolation layer on the semiconductor substrate; forming the second region on the semiconductor substrate in the formation region of the bipolar transistor; or forming the second region and the second region connected to the second region. Forming an electrode that defines the first region of the bipolar transistor in the first insulating film after forming a first insulating film on the entire surface; After forming the silicon film, the polysilicon film is patterned to form a first electrode made of polysilicon connected to the first region of the bipolar transistor. Forming and forming a resistor made of a polycrystalline silicon film on the device isolation layer; forming a second insulating film on the entire surface; and covering the second insulating film on the resistor with a mask Performing anisotropic etching on the second insulating film to expose the surface of the first electrode and the surface of the second region and / or the second electrode connected to the second region. And a step of forming a sidewall on the side wall of the first electrode, and after forming a refractory metal on the entire surface, annealing is performed, and the surface of the first electrode and the second region and / or A method for manufacturing a semiconductor device, comprising: a step of silicidizing a surface of a second electrode connected to a second region; and a step of removing the mask. 9. A bipolar transistor having a first region, a second region and a third region on the same semiconductor substrate, and an MO.
A method of manufacturing a semiconductor device having an S transistor, wherein the second region is formed in the semiconductor substrate in the formation region of the bipolar transistor, or the second region and the second region are connected to the second region. A step of forming a second electrode, a step of forming a gate electrode of the MOS transistor via an insulating film on the semiconductor substrate in a region where the MOS transistor is formed, and a step of forming a first insulating film on the entire surface Forming an opening defining the first region of the bipolar transistor in the first insulating film; forming a polycrystalline silicon film on the entire surface; and patterning the polycrystalline silicon film to form the bipolar transistor. A first region made of polycrystalline silicon connected to the first region;
Forming an electrode, performing anisotropic etching on the first insulating film to form a sidewall on the gate electrode, and performing ion implantation using the gate electrode and the sidewall as a mask. Forming a source / drain region of the MOS transistor; forming a second insulating film over the entire surface; covering the second insulating film on the MOS transistor with a mask; Anisotropically etching the film to expose the surface of the first electrode and the surface of the second region and / or the surface of the second electrode connected to the second region in the bipolar transistor; Forming a side wall on the side wall of the first electrode; forming a high melting point metal on the entire surface; and then performing annealing to make the surface of the first electrode and the second The method of manufacturing a semiconductor device, characterized in that it comprises a step of siliciding a surface of the second electrode connected to the region and / or the second region, and removing the mask. 10. After the step of forming a second insulating film on the entire surface, the second insulating film on the MOS transistor is not covered with a mask, but is directly covered with the surface of the first electrode and the second region. By performing a step of silicidizing the surface, the above M
10. The method according to claim 9, wherein the surface of the gate electrode and the surface of the source / drain region of the OS transistor are also silicided. 11. A bipolar transistor having a first region, a second region and a third region on the same semiconductor substrate,
A method of manufacturing a semiconductor device having an OS transistor and a resistor, comprising: forming an insulating element isolation layer on the semiconductor substrate outside the bipolar transistor formation region and the MOS transistor formation region; Forming the second region on the semiconductor substrate in the transistor formation region, or forming the second region and a second electrode connected to the second region; and forming the second region in the MOS transistor formation region. Forming a gate electrode of the MOS transistor on a semiconductor substrate via an insulating film; forming a first insulating film on the entire surface; and defining the first region of the bipolar transistor on the first insulating film. Forming a polycrystalline silicon film over the entire surface, and then patterning the polycrystalline silicon film to form the The made of polycrystalline silicon connected to said first region of La transistor 1
Forming a resistor made of a polycrystalline silicon film on the element isolation layer; and performing anisotropic etching on the first insulating film to form a sidewall on the gate electrode. Forming a source / drain region of the MOS transistor by performing ion implantation using the gate electrode and the side wall as a mask; forming a second insulating film over the entire surface; Covering the second insulating film on the MOS transistor with a mask; and performing anisotropic etching on the second insulating film to form a surface of the first electrode, the second region and the second region in the bipolar transistor. And / or exposing a surface of a second electrode connected to the second region and forming a sidewall on a side wall of the first electrode; Forming a refractory metal on the entire surface and then annealing to silicidize the surface of the first electrode and the surface of the second region and / or the second electrode connected to the second region. And a step of removing the mask. 12. In the step of covering the second insulating film with a mask, the second insulating film on the resistor is covered with the mask, but the second insulating film on the MOS transistor is covered with the mask. 12. An uncovered structure.
13. The method for manufacturing a semiconductor device according to item 5.