JP2002042466A - Semiconductor device and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the pulse widths of internal clock signals are easily adjusted. SOLUTION: The pulse widths of internal clock signals of an SDRAM are decided by the delay time of a delaying circuit 26. The delay time of the circuit 26 is made variable in four steps by the presence or the absence of the blow-out of fuses 43 and 44. Compared with a conventional scheme in which the pulse widths of the internal clock signals are changed by the modification of a circuit, the pulse widths of the signals are easily adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly to a semiconductor device and a semiconductor memory device that operate in synchronization with an external clock signal.

[0002]

2. Description of the Related Art Conventionally, a synchronous DRAM (hereinafter referred to as an SDRAM) has an external clock signal EXT.
An internal clock generation circuit that generates an internal clock signal INTCLK in synchronization with CLK is provided. The pulse width of internal clock signal INTCLK is determined by the delay time of the delay circuit regardless of the pulse width of external clock signal EXTCLK. In the SDRAM, various internal control signals are generated by using both the rising edge and the falling edge of internal clock signal INTCLK as a trigger to control the internal circuit.

[0003]

However, if the pulse width of the internal clock signal INTCLK deviates from the design value due to a change in process parameters, the timing of the internal control signal deviates from the design value, resulting in an insufficient operation margin. I will.

Conventionally, when the pulse width of the internal clock signal INTCLK deviates from the design value, the pulse width has been adjusted by circuit revision. In addition, even when the circuit is revised, how much the pulse width should be adjusted has been determined by circuit simulation. Therefore, it is not easy to adjust the pulse width of the internal clock signal INTCLK.

[0005] Therefore, a main object of the present invention is to provide a semiconductor device and a semiconductor memory device capable of easily adjusting the pulse width of an internal clock signal.

[0006]

A semiconductor device according to the present invention is a semiconductor device that operates in synchronization with an external clock signal, and includes at least one fuse, and a delay time of the semiconductor device depends on whether the fuse is cut or not. At least 2
A delay circuit that can be changed into stages, and a delay circuit coupled to the delay circuit, generating a leading edge of the internal clock signal in response to a leading edge of the external clock signal, and generating the leading edge, and after a delay time of the delay circuit elapses An internal clock generating circuit for generating a trailing edge of the internal clock signal, and an internal circuit for performing a predetermined operation in synchronization with a leading edge and a trailing edge of the internal clock signal are provided.

Preferably, the delay circuit includes a capacitor charged by applying a predetermined voltage between its terminals, and a variable resistance circuit whose resistance value can be changed in at least two stages depending on whether or not a fuse is blown. A switching element for discharging the charge of the capacitor through the variable resistor circuit in response to the leading edge of the external clock signal, and an internal clock for responding to the fact that the voltage between the terminals of the capacitor has dropped below its threshold voltage. An inverter for outputting a signal for generating a trailing edge of the signal.

Further, another semiconductor device according to the present invention comprises:
A semiconductor device operating in synchronization with an external clock signal, including a delay circuit having a predetermined delay time,
Generates the leading edge of the internal clock signal in response to the leading edge of the external clock signal. During normal operation, generates the leading edge of the internal clock signal and then generates the trailing edge of the internal clock signal after the delay time of the delay circuit has elapsed. In a test mode, an internal clock generating circuit for generating a trailing edge of an internal clock signal in response to an external signal, and an internal circuit performing a predetermined operation in synchronization with a leading edge and a trailing edge of the internal clock signal are provided. It is a thing.

[0009] Preferably, the external signal is a trailing edge of the external clock signal. Preferably, the delay circuit includes at least one fuse, and the delay time can be changed depending on whether the fuse is cut or not.

Still another semiconductor device according to the present invention is a semiconductor device that operates in synchronization with an external clock signal, and includes a first delay circuit having a predetermined delay time, A second delay circuit that changes in accordance with the voltage of the external pin, and is coupled to the first and second delay circuits to generate a leading edge of the internal clock signal in response to a leading edge of the external clock signal; In the test mode, the trailing edge of the internal clock signal is generated after the delay time of the first delay circuit has elapsed after the leading edge of the internal clock signal has been generated. And an internal circuit for performing a predetermined operation in synchronization with the leading and trailing edges of the internal clock signal. .

Preferably, the second delay circuit includes a plurality of serially connected inverters each having a power supply node connected to an external pin and each driven by a voltage externally applied through the external pin.

Preferably, the second delay circuit further has an input node connected to an external pin, an output node connected to a power supply node of a plurality of inverters, and a voltage of the same level as the voltage of the external pin. It includes an analog buffer provided to the power supply node of each inverter.

Preferably, the first delay circuit includes at least one fuse, and the delay time can be changed depending on whether the fuse is cut or not.

Further, a semiconductor memory device according to the present invention comprises:
A semiconductor memory device that operates in synchronization with an external clock signal, wherein a delay circuit whose delay time can be changed, and a delay time of the delay circuit during a normal operation are set to a predetermined first time; A setting circuit for setting the delay time of the delay circuit to a predetermined second time according to the external address signal in the test mode; and an internal clock signal coupled to the delay circuit and responding to a leading edge of the external clock signal. An internal clock generating circuit that generates a leading edge of the internal clock signal and generates a trailing edge of the internal clock signal after a delay time of the delay circuit has elapsed since the leading edge of the internal clock signal is generated. And an internal circuit for performing a predetermined operation.

Preferably, the delay circuit includes a capacitor charged by applying a predetermined voltage between its terminals, a plurality of resistance elements connected in series, and a transistor connected in parallel to each resistance element. A variable resistance circuit, a switching element that discharges the charge of the capacitor through the variable resistance circuit in response to the leading edge of the external clock signal, and that the voltage between the terminals of the capacitor drops below its threshold voltage. And a setting circuit configured to set a resistance value of the variable resistance circuit by turning on or off each transistor of the variable resistance circuit, which outputs a signal for generating a trailing edge of the internal clock signal.

Preferably, the setting circuit is activated in a test mode, and applies a first or second voltage to an input electrode of each transistor in response to an external address signal to make each transistor conductive or non-conductive. The circuit includes a logic circuit, a latch circuit for latching an input voltage of each transistor, and a reset circuit for resetting the input voltage of each transistor to a predetermined first or second voltage.

[0017]

[First Embodiment] FIG. 1 is a block diagram showing a configuration of an SDRAM according to a first embodiment of the present invention. Referring to FIG. 1, the SDRAM includes a clock buffer 1, a control signal buffer 2, an address buffer 3, a mode register 4, a control circuit 5, four memory arrays 6 to 9 (banks # 0 to # 3), and an I / O buffer. 10 is provided.

The clock buffer 1 has an external control signal CK
E is activated by the external clock signal EXTCLK
To generate an internal clock signal INTCLK in synchronization with the control signal buffer 2, the address buffer 3, and the control circuit 5. The control signal buffer 2 synchronizes with the internal clock signal INTCLK from the clock buffer 1 to control the external address signals A0 to A0.
Am (where m is an integer of 0 or more) and bank select signals BA0 and BA1 are latched and applied to the control circuit 5.

The mode register 4 stores an external address signal A
The mode designated by 0 to Am or the like is stored, and an internal command signal corresponding to the mode is output. Each of the memory arrays 6 to 9 is arranged in a matrix,
Includes a plurality of memory cells for storing bit data. The plurality of memory cells are grouped in advance by n + 1 (where n is an integer of 0 or more).

Control circuit 5 generates various internal signals in accordance with signals from control signal buffer 2, address buffer 3 and mode register 4 in synchronization with the rising and falling edges of internal clock signal INTCLK from clock buffer 1. Then, the entire SDRAM is controlled. During write operation and read operation, control circuit 5 controls four memory arrays 6 to 6 according to bank select signals BA0 and BA1.
9, and selects n + of the memory arrays according to the address signals A0 to Am.
One memory cell is selected. The selected n + 1 memory cells are activated and coupled to I / O buffer 10.

I / O buffer 10 applies externally input data D0-Dn to selected n + 1 memory cells during a write operation, and reads data Q0 from n + 1 memory cells during a read operation. To Qn are output to the outside.

FIG. 2 is a circuit block diagram showing a configuration of an internal clock generation circuit included in clock buffer 1. 2, the internal clock generation circuit includes P-channel MOS transistors 11 to 13 and an N-channel MOS transistor.
S transistors 14 to 17, inverters 18 to 25, and a delay circuit 26 are provided.

MOS transistors 11, 14, 15 and MOS transistors 12, 13, 16, 17 are connected in series between the line of power supply potential VCC and the line of ground potential GND, respectively. External clock signal EXTCL
K is directly input to the gates of MOS transistors 14 and 13 and is also input to the gate of N-channel MOS transistor 15 via inverters 19 to 23.
The drain of P channel MOS transistor 11 is connected to the drain of P channel MOS transistor 13. Signal V13 appearing at the drain of P-channel MOS transistor 13 is inverted by inverter 24 to become signal VI. The signal VI is output from the MOS transistors 12, 1
7, and is delayed by the delay circuit 26 to become a signal VO. Signal VO is inverted by inverter 18 and input to the gates of MOS transistors 11 and 16. Signal V13 is inverted by inverter 25 to become internal clock signal INTCLK.

When external clock signal EXTCLK is at "L" level, N-channel MOS transistor 14 is turned off, and N-channel MOS transistor 15 and P
The channel MOS transistor 13 conducts. Also, the signal V13 goes to “H” level and the internal clock signal IN
TCLK and signals VI and VO become "L" level,
P channel MOS transistor 11 and N channel M
OS transistor 17 is turned off, and P-channel MOS transistor 12 and N-channel MOS transistor 16 are turned on.

When external clock signal EXTCLK rises from "L" level to "H" level, P channel M
The OS transistor 13 is turned off, and the N-channel MOS transistor 14 is turned on, so that the signal V13 goes low. N channel MOS transistor 1
5 becomes non-conductive after the delay time of the inverters 19 to 23 elapses. When signal V13 goes to "L" level, internal clock signal INTCLK and signal VI rise to "H" level, P channel MOS transistor 12 is turned off, and N channel MOS transistor 17 is turned on. After the delay time of the delay circuit 26 elapses after the signal VI goes to the “H” level, the signal VO goes to the “H” level to turn on the P-channel MOS transistor 11 and turn off the N-channel MOS transistor 16, Signal V13 is raised to "H" level. Signal V
13 goes high, the internal clock signal INT
CLK and signal VI attain "L" level, P-channel MOS transistor 12 is turned on, and N-channel MOS transistor 17 is turned off. After the delay time of delay circuit 26 elapses after signal VI attains the "L" level, signal VO attains the "L" level, and P-channel MOS
Transistor 11 becomes non-conductive and N-channel M
The OS transistor 16 conducts.

When external clock signal EXTCLK falls from "H" level to "L" level, the operation returns to the case where external clock signal EXTCLK is at "L" level. Thus, the pulse width T of the internal clock signal INTCLK is
Is determined by the delay time of the delay circuit 26 without depending on the pulse width of the external clock signal EXTCLK.

As shown in FIG. 3, the delay circuit 26 includes P-channel MOS transistors 30 and 31 and an N-channel MOS transistor.
S transistors 32 to 36, inverter 37, resistance elements 38 to 40, capacitors 41 and 42, and fuse 4
3,44. P-channel MOS transistor 30,
Resistance elements 38 and 39 and N-channel MOS transistor 33 are connected in series between a line of power supply potential VCC and a line of ground potential GND. MOS transistor 3
Gates 0 and 33 receive signal VI. N channel M
OS transistor 32 and fuse 43 are connected in parallel to resistance elements 38 and 39, respectively.

The fuse 44 and the N-channel MOS transistor 35 are connected between the power supply potential VCC line and the ground potential G.
It is connected in series with the ND line. N-channel MO
S-transistor 36 is connected in parallel to N-channel MOS transistor 35, and has a gate connected to a constant voltage VA (about 1).
V). A signal appearing at node N44 between fuse 44 and N-channel MOS transistor 35 is inverted by inverter 37 and input to the gates of N-channel MOS transistors 32 and 35.

Capacitor 41 is connected between the drain (node N30) of P-channel MOS transistor 30 and ground potential G.
Connected to the ND line. P channel MOS transistor 31, resistance element 40 and N channel MOS
Transistor 34 is connected in series between a line of power supply potential VCC and a line of ground potential GND, and forms an inverter having a predetermined threshold potential. The gates of MOS transistors 31 and 34 are connected to node N30. Capacitor 42 is connected between the drain (node N31) of P-channel MOS transistor 31 and the line of ground potential GND. The signal appearing at node N31 becomes signal VO.

When both fuses 43 and 44 are not blown, N-channel MOS transistor 36 flows because gate voltage VA of N-channel MOS transistor 36 is only slightly higher than its threshold voltage (0.7 V). The resulting current is smaller than the current that the fuse 44 can flow. Therefore, node N44 attains "H" level, and N-channel MOS transistors 32 and 35 are turned off.

When signal VI is at "L" level, P-channel MOS transistor 30 and N-channel MOS transistor 34 are turned on, and N-channel MOS transistor 33 and P-channel MOS transistor 3 are turned on.
1 is turned off, and the capacitor 41 is charged to the power supply voltage VCC. When signal VI rises from the "L" level to the "H" level, P-channel MOS transistor 30 is turned off and N-channel MOS transistor 33 is turned on, so that the charge charged in capacitor 41 is transferred to resistance element 38. , Fuse 43 and N-channel MO
It flows out to the ground potential GND line via the S transistor 33. When node N30 attains "L" level, P-channel MOS transistor 31 conducts and N-channel MOS transistor 34 conducts, capacitor 42 is charged, and the potential of node N31, that is, signal VO attains "H" level. . Therefore, pulse width T of internal clock signal INTCLK in this case is determined by the time constant of capacitor 41 and resistance element 39.

When the fuse 43 is blown and the fuse 44 is not blown, the charge charged in the capacitor 41 is discharged through the resistance elements 38 and 39.
The discharge time is longer than when the fuses 43 and 44 are not blown, and the pulse width of the internal clock signal INTCLK is wider.

When both fuses 43 and 44 are cut, the potential of node N44 attains the "L" level and N-channel MOS transistors 32 and 35 conduct, so that the charge charged in capacitor 41 becomes N Channel M
It is discharged through the OS transistor 32 and the resistance element 39. When the resistance value of resistance element 39 is smaller than the resistance value of resistance element 38, the discharge time is shorter than when fuses 43 and 44 are not blown, and the pulse width of internal clock signal INTCLK is narrower.

The fuse 43 is not blown and the fuse 44
Is disconnected, the potential of the node N44 becomes “L”.
Level and N-channel MOS transistors 32, 3
5 conducts, the electric charge charged in capacitor 41 is discharged through N-channel MOS transistor 32 and fuse 43. Therefore, the discharge time is the shortest, and the pulse width of the internal clock signal INTCLK is the narrowest. As described above, the pulse width T of the internal clock signal INTCLK depends on whether the fuses 43 and 44 are cut or not.
Can be changed in four stages.

FIG. 4 is a time chart showing the operation of the internal clock generation circuit shown in FIGS. 2 and 3. FIG.
, When external clock signal EXTCLK rises from “L” level to “H” level at a certain time, internal clock signal INTCLK and signal VI
Is raised to "H" level. When signal VI attains the "H" level, the electric charge charged in capacitor 41 of FIG. 3 is discharged. This discharge time is determined by the fuses 43 and 44.
Is adjusted in four stages depending on the presence or absence of cutting. When the charge of capacitor 41 is discharged and node N30 attains the "L" level, P-channel MOS transistor 31 is turned on and N-channel MOS transistor 34 is turned off, so that signal VO changes from the "L" level to the "H" level. Will be launched.

When signal VO attains "H" level, internal clock signal INTCLK and signal VI attain "L" level. When signal VI attains an "L" level, P-channel MOS transistor 30 in FIG. 3 conducts, N-channel MOS transistor 33 conducts, node N30 attains an "H" level, and P-channel MOS transistor 31 does not conduct. At the same time, the N-channel MOS transistor 34 becomes conductive, and the electric charge charged in the capacitor 42 is discharged through the resistance element 40, so that the signal VO becomes "L" level.

In the first embodiment, the pulse width T of the internal clock signal INTCLK can be changed depending on whether the fuses 43 and 44 in the delay circuit 26 are cut or not. Therefore, the pulse width T of the internal clock signal INTCLK is adjusted by circuit revision. Internal clock signal INT
The pulse width T of CLK can be easily adjusted.

[Second Embodiment] FIG. 5 is a circuit block diagram showing a configuration of an internal clock generation circuit of an SDRAM according to a second embodiment of the present invention. Referring to FIG. 5, this internal clock generating circuit differs from the internal clock generating circuit of FIG. 2 in that inverter 18 includes inverters 51 and 52,
The test mode enable signal TM is introduced instead of the NOR gates 53 and 54 and the OR gate 55.

Signal TM is supplied to inverter 51 via NO
While being input to one input node of the R gate 53,
The signal is input to one input node of the NOR gate 54. External clock signal EXTCLK is input to the other input node of NOR gate 53 via inverter 52. Output signal VO of delay circuit 26 is input to the other input node of NOR gate 54. OR gate 55 receives output signals of NOR gates 53 and 54, and the output signal is input to the gates of P-channel MOS transistor 11 and N-channel MOS transistor 16.

Next, the operation of the internal clock generation circuit will be described. During normal operation, test mode enable signal TM is set to the "L" level of the inactivation level.
In this case, the output signal of NOR gate 53 is fixed at "L" level, and this internal clock generating circuit has the same configuration as the internal clock generating circuit of FIG.

In the test mode, test mode enable signal TM is set to the active level of "H". In this case, the output signal of NOR gate 54 is fixed at the “L” level, and external clock signal EXTCLK is applied to gates of P-channel MOS transistor 11 and N-channel MOS transistor 16 via inverter 52, NOR gate 53 and OR gate 55. Is input to Therefore, as shown in FIG. 6, the internal clock signal INTCL
The pulse width of K is determined not by the delay time of the delay circuit 26 but by the pulse width of the external clock signal EXTCLK.

In the second embodiment, in the test mode, the pulse width of internal clock signal INTCLK is determined by the pulse width of external clock signal EXTCLK, so that the pulse width of internal clock signal INTCLK is adjusted to an arbitrary value. be able to. Therefore, it is possible to easily determine how much the pulse width of internal clock signal INTCLK should be adjusted without performing a circuit simulation as in the related art.

[Third Embodiment] FIG. 7 is a circuit diagram showing a configuration of a delay circuit of an SDRAM according to a third embodiment of the present invention, which is compared with FIG. Referring to FIG. 7, this delay circuit differs from the delay circuit of FIG. 3 in that resistance elements 38 and 39, N-channel MOS transistor 32,
35, 36, fuses 43, 44 and inverter 37
Are removed, the resistance elements 61 to 63, the N channel MOS transistors 64 and 65, the inverters 66 to 68, the transfer gates 69 and 70, and the NAND gate 71,
72 is added.

The resistance elements 61 to 63 are connected to the nodes N30 and N30.
It is connected in series with the drain of the channel MOS transistor 33. N-channel MOS transistors 64, 6
5 is connected in parallel to the resistance elements 61 and 62, respectively.
The test mode enable signal TM is supplied to the NAND gate 7
1, 72 are input to one input node. Address signals A1 and A2 are supplied to transfer gates 69 and 7, respectively.
0 is input to the other input node of the NAND gates 71 and 72. The test mode set signal TMSET is
Directly input to the gates of the transfer gates 69, 70 on the N-channel MOS transistor side, the transfer gates 69, 70
70 is input to the gate on the P-channel MOS transistor side. The output signal of NAND gate 72 is input to the gate of N-channel MOS transistor 65 via inverter 68.

Next, the operation of the delay circuit will be described. In the normal operation mode, signal TM is at "L" level. In this case, the output signals of NAND gates 71 and 72 attain "H" level, and N-channel MOS transistor 64 is turned on and N-channel MOS transistor 65 is turned off. Therefore, the charge charged in capacitor 41 is applied to N-channel MOS transistor 64
The pulse width of the internal clock signal INTCLK is determined by the time constant of the capacitor 41 and the resistance elements 62 and 63.

In the test mode, signal TM is at "H" level. As shown in FIG. 8, in the test mode entry cycle, signal TMSET is applied to external clock signal E.
It is output as a positive pulse of one shot in synchronization with a signal CLK synchronized with XTCLK. At this time, the address signal A
1 and A2 are set to "H" level and "L" level, respectively.
65 becomes non-conductive, the electric charge of the capacitor 41 is discharged through the resistance elements 61 to 63, and the internal clock signal INT
The pulse width of CLK becomes maximum.

At that time, the address signals A1, A2
Are set to "L" level and "H" level, respectively, N channel MOS transistors 64 and 65 conduct, and the charge of capacitor 41 is discharged through N channel MOS transistors 64 and 65 and resistance element 63. , The pulse width of the internal clock signal INTCLK is minimized.

At that time, the address signals A1, A2
Are set to “H” level, N channel M
The OS transistor 64 is turned off, the N-channel MOS transistor 65 is turned on, and the charge of the capacitor 41 is transferred to the resistance element 61 and the N-channel MOS transistor 6.
5, and the pulse width of the internal clock signal INTCLK becomes the width between the above two cases.

At that time, the address signals A1, A2
Are set to “L” level, N channel M
When the OS transistor 64 conducts and the N channel M
The OS transistor 65 becomes non-conductive, and the capacitor 41
Is discharged through N-channel MOS transistor 64 and resistance elements 62 and 63. If the resistance value of the resistance element 62 is set to a value different from the resistance value of the resistance element 61,
The pulse width of the internal clock signal INTCLK can be changed in four stages by the combination of the levels of the address signals A1 and A2.

In the third embodiment, the pulse width of internal clock signal INTCLK can be changed in the test mode depending on the combination of the levels of address signals A1 and A2. Therefore, the internal clock signal INTCL is not required without performing the circuit simulation as in the related art.
It is easy to determine how much the pulse width of K should be adjusted.

[Fourth Embodiment] FIG. 9 is a circuit diagram showing a configuration of a delay circuit of an SDRAM according to a fourth embodiment of the present invention, which is compared with FIG. Referring to FIG. 9, this delay circuit is different from delay circuit 26 of FIG.
Resistance elements 38 and 39, N-channel MOS transistor 3
2, 35, 36, fuses 43, 44 and inverter 37 are removed, resistance elements 75a-75e, N-channel MOS transistors 76a-76d, latch circuit 77a
-77d and inverters 85 and 86 are added.

The resistance elements 75a to 75e are connected to the node N30
And the drain of N channel MOS transistor 33 are connected in series. N channel MOS transistor 76
a to 76d are connected in parallel to the resistance elements 75a to 75d, respectively. Each of latch circuits 77a to 77d has an NA
It includes an ND gate 80, a clocked inverter 81, a NOR gate 82, and inverters 83 and 84.

The test mode set signal TMSET is N
Input to one input node of AND gate 80. Address signals A1 to A4 are supplied to latch circuits 77a to 77a, respectively.
7d is input to the other input node of the NAND gate 80 and the control node of the clocked inverter 81. NA
The output signal of the ND gate 80 is the clocked inverter 8
1 is input to the inversion control node. Clocked inverter 81 is activated when the control node attains “H” level and the inversion control node attains “L” level.

Test mode enable signal TM is input to one input node of NOR gate 82 via clocked inverter 81. Test mode reset signal T
MRESET is input to the other input node of NOR gate 82. Inverters 83 and 84 are connected to NOR gate 8
2 in a ring shape. Latch circuit 7
Output signals from NOR gates 82 of 7a and 77b are input to the gates of N-channel MOS transistors 76a and 76b, respectively. Output signals of NOR gates 82 of latch circuits 77c and 77d are supplied to inverters 85 and 86, respectively.
N channel MOS transistors 76c and 76d
Input to the gate.

FIG. 10 is a time chart showing the operation of the delay circuit shown in FIG. In the normal operation mode, signal TM is at "L" level and signal TMRESET is at "H" level. In this case, the output signal of NOR gate 82 becomes "L", and this "L" level signal is latched by inverters 83 and 84. For this reason,
N channel MOS transistors 76a and 76b become non-conductive and N channel MOS transistors 75c and 75c
75d conducts, and the electric charge of the capacitor 41 is
a, 75b, N-channel MOS transistors 76c, 7
The pulse width of the internal clock signal INTCLK is determined by the time constant of the capacitor 41 and the resistance elements 75a, 75b, and 75e.

In the test mode, signal TM goes to "H" level and signal TMRESET goes to "L" level.
When a test mode set command is input in this state, signal TMSET is generated by one shot pulse. At this time, if the address signals A1 to A4 are set to “H” level, the output signal of the NAND gate 80 goes to “L” level to activate the clocked inverter 81, and the output signal of the clocked inverter 81 becomes “H”. The output signal of NOR gate 82 attains an L level and an H level.
This "H" level signal is latched by inverters 83 and 84. As a result, N-channel MOS transistors 76a and 76b become conductive and N-channel MOS transistors 76c and 76d become non-conductive, and the electric charge of capacitor 41 becomes N-channel MOS transistor 7
6a, 76b and the resistance elements 75c to 75e, and the pulse width of the internal clock signal INTCLK is
It is determined by the time constant of the capacitor 41 and the resistance elements 75c to 75e.

At this time, the address signals A1 to A4
Is set to the “L” level, the output signal of NAND gate 80 attains the “H” level, and clocked inverter 8
1 is not activated, and the level of the output signal of the NAND gate 82 does not change. Therefore, the address signals A1 to A
By the combination of the four levels, the conduction / non-conduction of each of N channel MOS transistors 76a to 76d can be set in a desired combination, and internal clock signal INTCL
The pulse width of K can be set to a desired value. Each time a combination of the test mode set command and the address signals A1 to A4 is serially input, the internal clock signal INT
The pulse width of CLK changes. When a test mode reset command is input, signal TMRESET goes to "H" level and signal TM goes to "L" level.
The output signal of R gate 82 is reset to "L" level.

In the fourth embodiment, the test mode set command and the address signals A1 to A1 are set in the test mode.
The pulse width of the internal clock signal INTCLK can be adjusted by serially inputting the combination of A4. Therefore, it is possible to easily determine how much the pulse width of internal clock signal INTCLK should be adjusted without performing a circuit simulation as in the related art.

[Fifth Embodiment] FIG. 11 is a circuit block diagram showing a configuration of an internal clock generation circuit of an SDRAM according to a fifth embodiment of the present invention. Referring to FIG.
This internal clock generating circuit differs from the internal clock generating circuit of FIG. 2 in that the inverter 18 is removed and an inverter 91, NOR gates 92 and 93, a delay circuit 94 and an OR gate 95 are added. The output signal of inverter 24 is input to one input node of NOR gates 92 and 93. The signal TM is input to the other input node of the NOR gate 92 and the inverter 91
, And is input to the other input node of the NOR gate 93. Output signals from the NOR gates 92 and 93 are input to the OR gate 95 via the delay circuits 26 and 94, respectively. The output signal of OR gate 95 is output from P-channel MOS transistor 11 and N-channel MOS transistor 1
6 is input to the gate.

In the normal operation mode, signal TM is "L".
Level, and the output signal of the inverter 24 is supplied to the NOR gate 92, the delay circuit 26 and the OR gate 95 via the M gate.
Input to the gates of OS transistors 11 and 16
Output signals of R gate 93 and delay circuit 94 are both fixed at "L" level. Therefore, the pulse width of internal clock signal INTCLK is determined by the delay time of delay circuit 26.

In the test mode, signal TM attains the "H" level, and the output signal of inverter 24 is supplied to NOR gate 93, delay circuit 94 and OR gate 95 to output the signal MO.
Input to the gates of S transistors 11 and 16, NOR
The output signals of gate 92 and delay circuit 26 are both fixed at "L" level. Therefore, the pulse width of internal clock signal INTCLK is determined by the delay circuit of delay circuit 94. The delay time of the delay circuit 94 is adjustable.

That is, as shown in FIG. 12, the delay circuit 94 includes an external pin 100, an inverter 101, clocked inverters 102a to 102d, and an N-channel MOS.
The transistor 107 is included. Clocked inverter 10
2a to 102d are connected to external pin 100 and ground potential G, respectively.
P-channel MOS connected in series between ND line
Transistors 103 and 104 and N-channel MOS transistors 105 and 106 are included. The gates of MOS transistors 103 and 106 serve as input nodes, and the gates of MOS transistors 104 and 105 serve as inversion control nodes and control nodes, respectively.
The drains of the transistors 04 and 105 are output nodes.

The output signal VI of the NOR gate 93 is input to the first-stage clocked inverter 102a. Output signals from the clocked inverters 102a to 102c are input to clocked inverters 102b to 102d at the subsequent stage, respectively. The output signal of the clocked inverter 102a at the last stage becomes the output signal VO of the delay circuit 94. N-channel MOS transistor 107 is connected between an output node of clocked inverter 102d in the final stage and a line of ground potential GND. The signal TM is input to the gates of the N-channel MOS transistors 105 of the clocked inverters 102a to 102d, and is also input to the clocked inverters 102a to 102d
It is input to the gate of d-channel P-channel MOS transistor 104 and the gate of N-channel MOS transistor 107.

In the normal operation mode, signal TM is "L".
Level and the clocked inverters 102a-102
d is inactivated and N-channel MOS transistor 10
7, and the output signal VO of the delay circuit 94 is fixed at the "L" level.

In the test mode, signal TM attains "H" level, clocked inverters 102a-102d are activated, and N-channel MOS transistor 107 is turned off. Clocked inverters 102a-102d
Is dependent on the potential of the external pin 100,
The lower the potential of the external pin 100, the shorter it becomes, and the higher the potential of the external pin 100, the longer it becomes. Therefore, by adjusting the potential of the external pin 100, the delay time of the delay circuit 94, that is, the pulse width of the internal clock signal INTCLK can be adjusted to a desired value.

In the fifth embodiment, the pulse width of internal clock signal INTCLK changes according to the potential of external pin 100 in the test mode. Therefore, it is possible to easily determine how much the pulse width of internal clock signal INTCLK should be adjusted without performing a circuit simulation as in the related art. In addition, the fuses 43 and 44 of the delay circuit 26 may be cut based on the result to set the delay time of the delay circuit 26, so that the pulse width of the internal clock signal INTCLK can be easily adjusted.

[Sixth Embodiment] FIG. 13 is a circuit diagram showing a configuration of a delay circuit 110 included in an internal clock generation circuit of an SDRAM according to a sixth embodiment of the present invention. The internal clock generation circuit is obtained by replacing the delay circuit 95 of the internal clock generation circuit of FIG. 13, delay circuit 110 includes an external pin 111, an analog buffer 112, a P-channel MOS transistor 118, a NAND gate 119, and inverters 120a to 120c.

The analog buffer 112 is a P channel M
OS transistors 113 and 114 and N-channel MO
Includes S transistors 115-117. MOS transistors 113 and 115 and MOS transistor 114,
116 are connected in series between the line of the internal power supply potential VDD and the node N117. P channel MOS
The gates of transistors 113 and 114 are both connected to the drain of P-channel MOS transistor 113 (node N1).
13). P channel MOS transistor 1
Reference numerals 13 and 114 constitute a current mirror circuit. The gate of N-channel MOS transistor 115 is connected to external pin 111. N channel MOS transistor 1
The gate of 16 has its drain (output node N111).
4) is connected. N channel MOS transistor 11
7 is connected between node N117 and the line of ground potential GND, and its gate receives signal TM.

When signal TM is at "L" level, N channel MOS transistor 117 is rendered non-conductive, and analog buffer 112 is inactivated. Signal TM is "H"
Level, N-channel MOS transistor 117
Is conducted, and the analog buffer 112 is activated. N
The channel MOS transistor 115 has an external pin 11
A current having a value corresponding to the potential of 1 flows. N channel MOS
Transistor 111 and P-channel MOS transistor 1
13 are connected in series, and a P-channel MOS transistor 1
13 and 114 constitute a current mirror circuit, and since the P-channel MOS transistor 114 and the N-channel MOS transistor 116 are connected in series, currents of the same value flow through the MOS transistors 113 to 116. Therefore, the potential of node N114 is at the same level as the potential of external pin 111.

P channel MOS transistor 118
Connected between the line of internal power supply potential VDD and node N114, the gate thereof receives signal TM. Each of inverters 120a to 120c has a P-channel M connected in series between node N114 and a line of ground potential GND.
OS transistor 121 and N-channel MOS transistor 122 are included. MOS transistors 121 and 12
2 is an input node, and the MOS transistor 1
The drains of 21 and 122 become output nodes. NAND
Gate 119 receives input signal VI and signal TM,
The output signal is input to the first-stage inverter 120a. The output signals of the inverters 120a and 120b are input to the subsequent inverters 120b and 120c, respectively. The output signal of the final-stage inverter 120c becomes the output signal VO of the delay circuit 110.

In the normal operation mode, signal TM attains "L" level, analog buffer 112 is inactivated, P-channel MOS transistor 118 conducts, node N114 attains "H" level, and NAND gate 119 Becomes "H" level and the output signal V
O is fixed at the “L” level.

In the test mode, signal TM attains "H" level, analog buffer 112 is activated, P-channel MOS transistor 118 is turned off, and NA
The ND gate 119 operates as an inverter for the input signal VI. Node N114 is analog buffer 11
2 keeps the same potential as the external pin 111, and the delay time of each of the inverters 120 a to 120 c depends on the potential of the external pin 111. Therefore, the external pins 111
, The delay time of the delay circuit 110, that is, the pulse width of the internal clock signal INTCLK can be changed.

Also in the sixth embodiment, the same effects as in the fifth embodiment can be obtained. [Seventh Embodiment] FIG. 14 is a circuit block diagram showing a structure of an internal clock generation circuit of an SDRAM according to a seventh embodiment of the present invention. Referring to FIG. 14, the internal clock generating circuit differs from the internal clock generating circuit of FIG. 2 in that inverter 18 is replaced by inverter 131, NOR gates 132 and 133 and OR gate 134.

The signal TM is directly input to one input node of the NOR gate 132 and the signal TM
To one input node of the NOR gate 133. Output signal VO of delay circuit 26 is applied to NOR gate 1
32 is input to the other input node. The signal DQM is N
Input to the other input node of OR gate 133. OR
Gate 134 receives output signals of NOR gates 132 and 133, and the output signal is
Input to the gate.

Next, the operation of the internal clock generation circuit will be described. At the time of normal operation, signal TM attains an "L" level, and output signal VO of delay circuit 26 is input to the gates of MOS transistors 11 and 16 via NOR gate 132 and OR gate 134.
The output signal of gate 133 is fixed at the “L” level.
Therefore, the pulse width of internal clock signal INTCLK is determined by the delay time of delay circuit 26.

In the test mode, signal TM attains "H" level, and signal DQM is applied to NOR gate 133 and OR gate.
Input to the gates of MOS transistors 11 and 16 via gate 134, and the output signal of NOR gate 132 is fixed at "L" level.

As shown in FIG. 15, the external clock signal E
Internal clock signal INTCLK rises from "L" level to "H" level in response to the rising edge of XTCLK. When external control signal DQM rises from "L" level to "H" level while internal clock signal INTCLK is at "H" level, the output signal of OR gate 134 attains "L" level and P-channel MOS transistor 1
1 conducts, the signal V13 goes to "H" level, and the internal clock signal INTCLK goes to "L" level. Therefore, the pulse width of the internal clock signal INTCLK can be changed by changing the timing at which the signal DQM changes to the “H” level.

In the seventh embodiment, the pulse width of internal clock signal INTCLK changes when the timing at which external control signal DQM is set to the “H” level is changed in the test mode. Therefore, the internal clock signal INTC can be set without performing the circuit simulation as in the related art.
It is possible to easily determine how much the LK pulse width should be adjusted.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0080]

As described above, the semiconductor device according to the present invention includes at least one fuse, the delay time of which can be changed in at least two stages depending on whether or not the fuse is blown, and the delay circuit coupled to the delay circuit. And an internal clock generating circuit for generating a leading edge of the internal clock signal in response to a leading edge of the external clock signal, and generating a trailing edge of the internal clock signal after a delay time of the delay circuit has elapsed after generating the leading edge. Are provided. Therefore, the pulse width of the internal clock signal can be adjusted depending on whether or not the fuse is blown, so that the pulse width of the internal clock signal can be easily adjusted as compared with the related art that has been adjusted by circuit revision.

Preferably, the delay circuit comprises a capacitor charged by applying a predetermined voltage between its terminals, and a variable resistor circuit whose resistance value can be changed in at least two stages depending on whether the fuse is cut or not. A switching element that discharges the charge of the capacitor through the variable resistor circuit in response to the leading edge of the external clock signal; and an internal element that responds to the fact that the voltage between the terminals of the capacitor has dropped below its threshold voltage. An inverter that outputs a signal for generating a trailing edge of the clock signal. in this case,
The time constant of the capacitor and the variable resistance circuit is changed depending on whether the fuse is cut or not, and the delay time of the delay circuit is changed.

Another semiconductor device according to the present invention includes a delay circuit having a predetermined delay time,
Generates the leading edge of the internal clock signal in response to the leading edge of the external clock signal. During normal operation, generates the leading edge of the internal clock signal and then generates the trailing edge of the internal clock signal after the delay time of the delay circuit has elapsed. In the test mode, an internal clock generation circuit for generating a trailing edge of the internal clock signal in response to an external signal is provided. Therefore, since the pulse width of the internal clock signal can be changed by changing the input timing of the external signal in the test mode, how much the pulse width of the internal clock signal should be adjusted without performing the circuit simulation as in the related art Can be easily obtained.

Preferably, the external signal is the trailing edge of the external clock signal. In this case, the pulse width of the internal clock signal can be changed by changing the pulse width of the external clock signal.

Preferably, the delay circuit includes at least one fuse, and its delay time can be changed depending on whether the fuse is cut or not. In this case, since the pulse width of the internal clock signal can be adjusted depending on whether or not the fuse is cut, the pulse width of the internal clock signal can be easily adjusted as compared with the conventional case where adjustment is made by circuit revision.

In still another semiconductor device according to the present invention, there is provided a first delay circuit having a predetermined delay time, and a second delay circuit having a delay time varying according to the voltage of an external pin. Generating the leading edge of the internal clock signal in response to the leading edge of the external clock signal, and generating the leading edge of the internal clock signal in a normal operation after the elapse of the delay time of the first delay circuit during normal operation. The trailing edge is generated, and in the test mode, the leading edge of the internal clock signal is generated, and then the second edge is generated.
And an internal clock generating circuit for generating the trailing edge of the internal clock signal after the delay time of the delay circuit has elapsed. Therefore, since the pulse width of the internal clock signal can be changed by changing the voltage of the external pin in the test mode, it is necessary to determine how much the pulse width of the internal clock signal should be adjusted without performing a circuit simulation as in the related art. It can be easily obtained.

Preferably, the second delay circuit includes a plurality of series-connected inverters each having a power supply node connected to an external pin and each driven by a voltage externally applied through the external pin. in this case,
By changing the voltage of the external pin, the delay time of each inverter can be changed, and the delay time of the delay circuit can be changed.

Preferably, the second delay circuit further includes an analog buffer for applying a voltage of the same level as the voltage of the external pin to the power supply node of each inverter. In this case, since the current is amplified by the analog buffer, the current supplied to the external pin can be small.

Preferably, the first delay circuit includes at least one fuse, and the delay time can be changed depending on whether the fuse is cut or not. In this case, since the pulse width of the internal clock signal can be adjusted depending on whether or not the fuse is cut, the pulse width of the internal clock signal can be easily adjusted as compared with the conventional case where adjustment is made by circuit revision.

In the semiconductor memory device according to the present invention, the delay circuit whose delay time can be changed and the delay time of the delay circuit during normal operation are set to a predetermined first time, and the test mode is set. At the time, a setting circuit for setting the delay time of the delay circuit to a predetermined second time according to the external address signal, and generating a leading edge of the internal clock signal in response to a leading edge of the external clock signal, And an internal clock generating circuit for generating a trailing edge of the internal clock signal after a delay time of the delay circuit has elapsed after the leading edge has been generated. Therefore, since the pulse width of the internal clock signal can be changed by changing the external address signal, it is easy to determine how much the pulse width of the internal clock signal should be adjusted without performing a circuit simulation as in the related art. Can be.

Preferably, the delay circuit includes a capacitor charged by applying a predetermined voltage between its terminals, a plurality of resistance elements connected in series, and a transistor connected in parallel to each resistance element. A variable resistance circuit, a switching element that discharges the charge of the capacitor through the variable resistance circuit in response to the leading edge of the external clock signal, and that the voltage between the terminals of the capacitor drops below its threshold voltage. And an inverter that outputs a signal for generating a trailing edge of the internal clock signal.
The setting circuit sets the resistance value of the variable resistance circuit by making each transistor of the variable resistance circuit conductive or non-conductive. In this case, the time constant of the capacitor and the variable resistance circuit is changed according to the external address signal, and the delay time of the delay circuit is changed.

Preferably, the setting circuit is activated in a test mode, and applies a first or second voltage to an input electrode of each transistor in response to an external address signal to make each transistor conductive or non-conductive. The circuit includes a logic circuit, a latch circuit for latching an input voltage of each transistor, and a reset circuit for resetting the input voltage of each transistor to a predetermined first or second voltage. In this case, the delay time of the delay circuit can be changed at a predetermined cycle by inputting an external address signal at a predetermined cycle.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an SDRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a configuration of an internal clock generation circuit included in the SDRAM shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a delay circuit shown in FIG. 2;

4 is a time chart showing an operation of the internal clock generation circuit shown in FIG.

FIG. 5 is a circuit block diagram showing a configuration of an internal clock generation circuit of an SDRAM according to a second embodiment of the present invention.

FIG. 6 is a time chart illustrating an operation of the internal clock generation circuit illustrated in FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of an internal clock generation circuit of an SDRAM according to a third embodiment of the present invention;

8 is a time chart showing an operation of the internal clock generation circuit shown in FIG.

FIG. 9 is a circuit diagram showing a configuration of an internal clock generation circuit of an SDRAM according to a fourth embodiment of the present invention.

FIG. 10 is a time chart illustrating an operation of the internal clock generation circuit illustrated in FIG. 9;

FIG. 11 is an SDRAM according to a fifth embodiment of the present invention.
FIG. 3 is a circuit block diagram showing a configuration of an internal clock generation circuit of FIG.

FIG. 12 is a circuit diagram showing a configuration of delay circuit 94 shown in FIG. 11;

FIG. 13 is an SDRAM according to a sixth embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a delay circuit included in the internal clock generation circuit of FIG.

FIG. 14 is an SDRAM according to a seventh embodiment of the present invention.
FIG. 3 is a circuit block diagram showing a configuration of an internal clock generation circuit of FIG.

15 is a time chart illustrating an operation of the internal clock generation circuit illustrated in FIG.

[Explanation of symbols]

1 clock buffer, 2 control signal buffer, 3 address buffer, 4 mode register, 5 control circuit, 6
-9 memory array, 10 I / O buffer, 11-1
3, 30, 31, 103, 104, 113, 114, 1
18, 121 P-channel MOS transistors, 14 to 1
7, 32 to 36, 76a to 76d, 105 to 107,1
15 to 117, 122 N-channel MOS transistors, 18 to 25, 37, 51, 52, 66 to 68, 83
~ 86, 91, 101, 131 inverters, 26, 9
4,110 delay circuit, 38-40, 75a-75e resistance element, 41,42 capacitor, 53,54,82,
92, 93, 132, 133 NOR gate, 55, 9
5,134 OR gate, 69,70 transfer gate, 71,72,80,119 NAND gate,
81, 102a-102d Clocked inverter, 1
00,111 External pins, 112 Analog buffer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) G11C 11/34 371A

Claims (12)

[Claims] 1. A semiconductor device that operates in synchronization with an external clock signal, the semiconductor device including at least one fuse, and a delay circuit whose delay time can be changed in at least two stages depending on whether the fuse is cut or not. A delay circuit for generating a leading edge of the internal clock signal in response to a leading edge of the external clock signal, and generating a leading edge of the internal clock signal after a delay time of the delay circuit. A semiconductor device comprising: an internal clock generating circuit to generate; and an internal circuit performing a predetermined operation in synchronization with a leading edge and a trailing edge of the internal clock signal. 2. A delay circuit comprising: a capacitor charged by a predetermined voltage applied between its terminals; a variable resistance circuit whose resistance value can be changed in at least two stages depending on whether the fuse is cut or not; A switching element that discharges the charge of the capacitor through the variable resistance circuit in response to a leading edge of the external clock signal, and that a voltage between terminals of the capacitor drops below a threshold voltage thereof. 2. The semiconductor device according to claim 1, further comprising an inverter for outputting a signal for generating a trailing edge of said internal clock signal. 3. A semiconductor device that operates in synchronization with an external clock signal, the semiconductor device including a delay circuit having a predetermined delay time, wherein a leading edge of the internal clock signal is responsive to a leading edge of the external clock signal. During normal operation, generates a leading edge of the internal clock signal and then generates a trailing edge of the internal clock signal after a delay time of the delay circuit elapses, and responds to an external signal in a test mode to generate the trailing edge of the internal clock signal. A semiconductor device comprising: an internal clock generation circuit that generates a trailing edge of an internal clock signal; and an internal circuit that performs a predetermined operation in synchronization with a leading edge and a trailing edge of the internal clock signal. 4. The semiconductor device according to claim 3, wherein said external signal is a trailing edge of said external clock signal. 5. The semiconductor device according to claim 3, wherein said delay circuit includes at least one fuse, and a delay time of said delay circuit can be changed depending on whether said fuse is cut or not. 6. A semiconductor device that operates in synchronization with an external clock signal, comprising: a first delay circuit having a predetermined delay time; and a second delay circuit having a delay time that changes according to the voltage of an external pin. A delay circuit, coupled to the first and second delay circuits, for generating a leading edge of an internal clock signal in response to a leading edge of the external clock signal, and for generating a leading edge of the internal clock signal during normal operation Then, after the delay time of the first delay circuit has elapsed, the trailing edge of the internal clock signal is generated, and in the test mode, the leading edge of the internal clock signal is generated, and then the delay time of the second delay circuit is generated. A semiconductor device comprising: an internal clock generation circuit that generates a trailing edge of the internal clock signal after a lapse of time; and an internal circuit that performs a predetermined operation in synchronization with a leading edge and a trailing edge of the internal clock signal. 7. The second delay circuit includes a plurality of series-connected inverters each having a power supply node connected to the external pin and each being driven by a voltage externally applied through the external pin. The semiconductor device according to claim 6, comprising: 8. The second delay circuit further has an input node connected to the external pin, an output node connected to a power supply node of the plurality of inverters, and a second input terminal having the same level as a voltage of the external pin. The semiconductor device according to claim 7, further comprising an analog buffer that applies a voltage to a power supply node of each inverter. 9. The first delay circuit according to claim 6, wherein the first delay circuit includes at least one fuse, and a delay time of the first delay circuit can be changed depending on whether the fuse is cut or not. Semiconductor device. 10. A semiconductor memory device that operates in synchronization with an external clock signal, wherein the delay time can be changed, and in normal operation, the delay time of the delay circuit is set to a first predetermined value. A setting circuit for setting a delay time of the delay circuit to a predetermined second time in accordance with an external address signal in a test mode; a leading edge of the external clock signal coupled to the delay circuit An internal clock signal generating a leading edge of the internal clock signal in response to the internal clock signal, and generating a trailing edge of the internal clock signal after a delay time of the delay circuit has elapsed after generating the leading edge; and the internal clock signal. Semiconductor memory device having an internal circuit that performs a predetermined operation in synchronization with the leading edge and trailing edge of the semiconductor memory device. 11. The delay circuit includes a capacitor charged with a predetermined voltage applied between its terminals, a plurality of resistance elements connected in series, and a transistor connected in parallel to each resistance element. A variable resistor circuit, a switching element that discharges a charge of the capacitor through the variable resistor circuit in response to a leading edge of the external clock signal, and a voltage between terminals of the capacitor is lower than a threshold voltage thereof. And an inverter for outputting a signal for generating a trailing edge of the internal clock signal, wherein the setting circuit conducts or non-conducts each transistor of the variable resistance circuit, thereby setting a resistance of the variable resistance circuit. The semiconductor memory device according to claim 10, wherein a value is set. 12. The setting circuit is activated in the test mode, and applies a first voltage or a second voltage to an input electrode of each transistor in response to the external address signal to make each transistor conductive or non-conductive. 12. The semiconductor memory device according to claim 11, further comprising: a logic circuit that performs an operation, a latch circuit that latches an input voltage of each transistor, and a reset circuit that resets an input voltage of each transistor to a predetermined first or second voltage. .