JP2002033785A - Atm device and bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To arbitrate a bus use, corresponding to the priority of data to be transferred on a bus, using a comparatively simple configuration. SOLUTION: Respective interfaces 2 and 3 simultaneously output priorities, corresponding to non-ATM lines 6 and 7 as receiving sources or transmitting destinations of data stored in an ATM cell to a bus 1. When the priority transmitted by an interface itself is highest, a bus use request signal containing its own address is transmitted to the bus 1. A bus control module 4 receives the bus use request signal on the bus 1, determines one of interfaces 2 and 3 to apply the bus usage and outputs a bus usage permission signal containing its address to the bus 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration technique for a bus system for transmitting and receiving data between a plurality of modules via a bus.

[0002]

2. Description of the Related Art Devices using a bus system for transmitting and receiving data between a plurality of modules via a bus include, for example, a plurality of non-ATMs (Asynchronous Transfer Modes).
Converts the data sent from the line into ATM cells and creates an ATM
2. Description of the Related Art An ATM multiplexing apparatus is known which transmits data on a line, demultiplexes an ATM cell sent from the ATM line, and transmits the data to the plurality of non-ATM lines.

In such an ATM multiplexer, non-AT
A bus is connected between a non-ATM line interface module accommodating an M line and an ATM line interface module accommodating an ATM line. Then, using this bus, the ATM cells transmitted from the ATM line are received by the ATM line interface module, and are transmitted to the non-ATM line interface module, and the data transmitted from the non-ATM line is transmitted to the non-ATM line. An ATM cell is received by the line interface module and converted into an ATM cell, and this is transmitted to the ATM line interface module.

[0004]

Now, such an AT
Conventionally, in an M multiplexer, arbitration of the right to use the bus, in order to allow only one interface module to use the bus at the same time when a plurality of interface modules simultaneously request the use of the bus for ATM cell transmission, is simply performed. This is performed by granting the bus use right to each interface module according to a predetermined order.

Since such arbitration of the right to use the bus uses priority control of the right to use the bus on a per-interface module basis, the priority of the right to use the bus depends on the priority of the ATM cells transmitted and received on the bus. Control cannot be performed. For this reason, the bus use of the ATM cell that should be transmitted with priority is postponed to the bus use of the ATM cell with lower priority, and as a result, the transmission of the ATM cell that should be transmitted with priority to the line is performed. However, there has been a problem that the data is delayed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to arbitrate bus use rights according to the priority of data transferred on a bus with a relatively simple configuration. To be able to do it.

[0007]

According to the present invention, there is provided a data bus connected to a plurality of modules, and a bus control means connected to the data bus.

A first transmitting means for transmitting, to each of the plurality of modules, a priority of data to be transmitted to the data bus and a transmission request with its own address to the data bus; And a second transmitting means for transmitting the data to be transmitted to the data bus when a transmission permission signal including its own address is received from the bus.

Further, the bus control means selects one of the addresses transmitted to the data bus by the line interface unit which has transmitted the highest priority of the data to the data bus, and causes the selection. The transmission permission signal including the address is transmitted to the data bus.

According to the present invention, a data bus used for data transfer is used as it is, and the bus control unit and a plurality of modules have a relatively simple configuration for exchanging the priority of data and the address of each module. It is possible to arbitrate for the right to use the bus in accordance with the priority of the data transferred on the data bus.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below by taking an application to an ATM multiplexer as an example.

FIG. 1 shows the configuration of an ATM multiplexer to which the present embodiment is applied.

In the drawing, reference numeral 1 denotes a bus, reference numeral 2 denotes a non-ATM line interface, reference numeral 3 denotes an ATM line interface, reference numeral 4 denotes a bus control module, reference numeral 5 denotes an ATM line, and reference numeral 6 denotes a non-ATM line voice communication line. Reference numeral 7 denotes a data communication line which is a non-ATM line.

In the above configuration, the non-ATM line interface 2 converts the data sent from the voice communication line 6 and the data communication line 7 accommodated therein into ATM cells, and connects the ATM line interface 3 to the ATM cell destination to the ATM cells. The internal cell is generated by adding the indicated bus routing header. Then, the internal cell is transmitted to the bus 1. AT
The M line interface 3 checks the bus routing header of the internal cell transmitted by the non-ATM line interface 2 and, if it indicates the address of the module accommodated therein, receives the internal cell and stores it therein. Take out the ATM cell stored in the ATM cell 5
Send to

On the other hand, the ATM line interface 3 is a non-ATM line in which an ATM cell sent from the ATM line 5 accommodated by the ATM line interface 3 is connected to the voice communication line 6 of the destination of the cell by a corresponding VPI / VCI. An internal cell is generated by adding a bus routing header indicating the non-ATM line interface 2 to which the interface 2 or the data communication line 7 is connected. Then, the internal cell is transmitted to the bus 1. The non-ATM line interface 2
The bus routing header of the internal cell transmitted by the TM line interface 3 is checked. If the bus routing header indicates the address of a module accommodated therein, the internal cell is received and data is transmitted from the ATM cell stored therein. And sends it to the destination non-ATM line.

The bus control module 4 arbitrates the right of the non-ATM line interface 2 and the ATM line interface 3 to use the bus 1 for transmitting ATM cells.

The details of each section will be described below.

First, the configuration of the bus 1 is shown in FIG.

As shown in the figure, a bus 1 includes a data bus 11 having a width of 32 bits, a data clock bus 13 for transmitting a data clock for defining a data cycle, and a frame for defining a frame cycle which is a cycle of 18 data cycles. Frame clock bus 12 for transmitting clock
And ACK / NACK indicating normal / abnormal reception of ATM cell
And a 2-bit ACK / NACK bus 14 for transmitting signals. Here, the data cycle is a cycle for transmitting one 32-bit data on the data bus 11. The reason why the data clock bus 12 has two bits is that two data clocks having different phases are transmitted as data clocks for stable operation.

Next, FIG. 3 shows a transmission format on the data bus 11.

As shown in the figure, the transmission format on the data bus 11 is such that, in each of 18 frame cycles, a priority class signal (Priority) 1001 is transmitted in the first data cycle of the frame cycle.
In the second data cycle, the bus use right request signal (Bus re
quest) 1002, the above-described internal cell 1003 in the third to seventeenth data cycles, and the bus use right grant signal (Granted Terminus) in the eighteenth data cycle.
l) 1004 is transferred. Here, the bus routing header (Bus routing header) 100 in the third data cycle among the third to seventeenth data cycles, which are the transmission data cycles of the internal cell.
5 is transmitted in the remaining fourth to seventeenth cycles.

Next, FIG. 4 shows a configuration of the bus control module 4.

As shown, the bus control module 4
Includes a timing generation unit 41, a bus arbitration control unit 42,
It has transmitting units 43 and 44 and a receiving unit 45.

The timing generator 41 generates the above-mentioned data clock and frame clock, and transmits them to the data clock bus 12 and the frame clock bus 13 via the transmitter 43, respectively.

The bus arbitration control unit 42 receives a bus use right request signal via the reception unit 45 in the second data cycle in each frame cycle based on the data clock and the frame clock generated by the timing generation unit 41, Arbitration of the bus right according to the bus use right request signal is performed. In the eighteenth data cycle, the transmission section 44 in the high impedance state is controlled to the transmission state in the other data cycle, and the non-ATM line interface 2 or the ATM which grants the right to use the bus via the transmission section 44
A bus use right permission signal including the address of the line interface 3 is transmitted to the data bus 11. Bus arbitration control unit 4
Details of the arbitration of the right to use the bus in 2 will be described later.

Next, the configuration of the non-ATM line interface 2 is shown in FIG.

As shown, the non-ATM line interface 2 comprises an interface unit 21 and an ATM cell processing unit 2.
A set of 2 is provided for each non-ATM line 6, 7 such as a voice communication line or a data communication line to be accommodated. Also, non-ATM
The line interface 2 has a routing information table 23, a transmission buffer unit 27, a reception buffer unit 28, a timing generation unit 29, a bus control unit 30, a reception unit 31, and a transmission unit 32 in addition to the above.

Here, the timing generator 29 receives the data clock and the frame clock from the data clock bus 12 and the frame clock bus 13, respectively, and generates a timing signal indicating a frame cycle and a data cycle based on the data clock and the frame clock. Supply to each part.

The ATM cell processing unit 22 includes a routing information adding unit 221, an ATM cell assembling unit 222,
And an ATM cell disassembly unit 223.

The bus control unit 30 includes a priority class generation unit 301, a priority class decoder 302, a priority class match detection unit 303, an address register 304, an address decoder 305, an address match detection unit 306,
It has a selector 307 and a control unit 310.

Next, the configuration of the ATM line interface 3 is shown in FIG.

As shown, the configuration of the ATM line interface 3 is substantially the same as that of the non-ATM line interface 2. However, this is different from the non-ATMM line interface 2 in that the ATM cell processing unit 22 is not provided with the ATM cell assembling unit 222 and the ATM cell disassembling unit 223.

Here, the non-ATM line interface 2 and the ATM line interface 3 are given unique addresses in advance. Non-ATM line interface 2
The ATM line interface 3 stores the address given to itself in the address register 30 of the bus control unit 30.
4 is stored. The non-ATM lines 6 and 7 accommodated by the non-ATM line interface 2 and the ATM lines 5 accommodated by the ATM line interface 3 respectively include:
A unique channel number is assigned in advance within the non-ATM line interface 2 or the ATM line interface 3. And, by this, non-ATM lines 6, 7 and AT
Each of the M lines 5 is uniquely specified by a combination of an address and a channel number.

The details of the ATM cell transfer operation using the bus 1 in the ATM multiplexer having the above configuration will be described below.

First, the operation when an internal cell is transmitted from the non-ATM line interface 2 to the bus 1 will be described.

In the non-ATM line interface 2,
The interface unit 21 receives data transmitted from the non-ATM lines 6 and 7 accommodated therein and inputs the data to the ATM cell processing unit 22.

In response to this, the routing information generation unit 221 of the ATM cell processing unit 22 sets the non-A
The VPI / VCI, address and channel number corresponding to the TM lines 6 and 7 are read out, and the ATM cell assembling section 222
Give to. Here, the address is the address of the ATM line interface 3, and the channel number is the channel number of the ATM line 5 in which the VPI / VCI corresponding to the non-ATM line is set.

Next, the ATM cell assembling section 222 receives the VPI / VCI received from the routing information generating section 221.
In the header, and assemble an ATM cell including the data received from the interface unit 21 in the payload.
Furthermore, an internal cell is generated by adding a bus routing header including the address and the channel number given from the routing information generation unit 221 to the head of the ATM cell. Then, the internal cell is transmitted to the transmission buffer unit 27.
Send to

The transmission buffer unit 27 temporarily stores the internal cells received from each of the ATM cell processing units 22, and appropriately selects one internal cell to be transmitted from the internal cells. And
Notifying the control unit 310 of the bus control unit 30 of the request for transmitting the internal cell, and the ATM transmitting the selected internal cell.
The priority class generation unit 301 is notified of the channel numbers of the non-ATM lines 6 and 7 accommodated by the cell processing unit 22 and the interface unit 21 of the set.

When a transmission request for an internal cell is generated, the transmission request is controlled by the control based on the frame cycle and the data cycle indicated by the timing signal output by the timing generation section 29 in the frame cycle immediately after the generation of the transmission request. Is performed.

First Data Cycle (Transmission / Reception of Priority Class Signal 1001) The priority class generation section 301 sends the transmission buffer section 27 according to the correspondence between the preset channel number and the priority level.
Output the priority level corresponding to the channel number notified from. This priority level is 0, which is the same as the bit width of bus 1.
The priority is expressed in 32 stages of ~ 31. Here, it is assumed that the larger the stage, the higher the priority.

The priority class decoder 302 decodes the priority level output from the priority class generator 301 into a 32-bit priority class signal 1001. Priority level n
In the case of expressing the priority of the first stage, only the n-th bit is set to a Low level signal, and all other bits are set to High level.
Decoding is performed by setting the signal to the h level.

The control section 310 causes the selector 307 to select the output of the priority class decoder 302 and sets the transmission section 32 in the transmission state. As a result, the priority class signal 1001 decoded by the priority class decoder 302 is output to the bus 1.

On the other hand, the priority class match detection unit 303 determines the priority indicated by the priority class signal 1001 decoded by the priority class decoder 302 and the highest priority among the priorities indicated by the priority class signals on the data bus 1. It is determined whether or not they match, and the result is notified to the control unit 310.

Here, each bit of the data bus 1 is Lo
Represents the logical sum of all outputs for that bit, where the w level is significant. Therefore, any non-ATM line interface 2 or ATM line interface 3
However, the bit that outputs the Low-level signal is always L
As a bit of the ow level, it is received by each of the non-ATM line interface 2 and the ATM line interface 3.

Second Data Cycle (Transmission of Bus Use Right Request Signal 1002) In the bus control unit 30, when the priority class match detection unit 303 notifies a mismatch, the control unit 310 The right acquisition is determined to be unsuccessful, and the process from the first data cycle described above is performed again in the next frame cycle as a process for this transmission request.

On the other hand, when the matching is notified from the priority class matching detecting section 303, the control section 310 controls the bus obtained by the address decoder 305 decoding its own address stored in the address register 304 into 32 bits. The selector 307 selects the usage right request signal 1002 and sets the transmission unit 32 to the transmission state. As a result, the bus use right request signal 1002 is output to the bus 1. Here, 0 is the same as the bit width of the bus 1 in the address.
If the address is n, the address decoder 305 sets only the n-th bit to a low-level signal and sets all other bits to a high-level signal. To perform decoding.

Eighteenth data cycle (reception of bus use permission signal 1004) In bus control unit 30, address match detection unit 306
Fetches a bus use permission signal 1004 from the bus 1 via the receiving unit 31 and detects a match / mismatch between the address indicated by the signal and its own address stored in the address register 303. Then, the result is sent to the control unit 3
Notify 10. When the notification from the address match detection unit 306 does not match, the control unit 310 determines that the acquisition of the bus use right for this transmission request has failed, and as a process for this transmission request, in the next frame cycle,
The operation from the data cycle is performed again.

On the other hand, in the case of a match, the control unit 310 assumes that the bus use right has been acquired, and in the third to seventeenth data cycles of the next frame cycle, the transmission buffer unit 27 Causes the selected internal cell to be transmitted. Then, the transmission buffer unit 2 is provided to the selector 307.
7 is selected, and the transmission unit 32 is set to the transmission state. As a result, the internal cells are output to the bus 1.

Thus, the transmission of the internal cells from the non-ATM line interface 2 to the bus 1 is completed.

In the third to seventeenth data cycles before the eighteenth data cycle, the non-ATM line interface 2 or the ATM line interface 3 which has acquired the right to use the bus in the immediately preceding frame cycle. Transmission of the internal cell to the bus 1 is performed.

After the transmission of the internal cell, the transmission buffer unit 27 determines whether the transmitted internal cell has been normally received by ACK / NA.
The ACK / NACK signal on the CK bus 14 is received and confirmed. If it has not been received normally, appropriate abnormal processing such as retransmission is performed.

By the way, the bus control module 4 outputs the bus use permission signal 1004 received by the non-ATM line interface 2 in the eighteenth data cycle to the bus 1 as described above.

That is, in the bus control module 4, the bus arbitration control unit 42 requests the bus use right from the bus 1 in the second data cycle in each frame cycle based on the data clock and the frame clock generated by the timing generation unit 41. The signal 1002 is taken. Here, among the 32 bits of the bus use right request signal, the position of the bit which is a Low level signal is as follows:
At this time, the address of the non-ATM line interface 2 or the ATM line interface 3 requesting the right to use the bus in the highest priority class is shown. For example, n
If the n-th bit and the m-th bit are Low level signals, it means that the non-ATM line interface 2 or the ATM line interface 3 of the address n and the address m has requested the bus use right.

Therefore, if the address of the non-ATM line interface 2 or the ATM line interface 3 requesting the right to use the bus is one, the bus arbitration control unit 42 sets the address as the address permitting the right to use the bus. In the case of (1), one of them is selected, and the selected address is used as the address for granting the right to use the bus. Here, this selection is made so that the right to use the bus is not continuously granted only to the same address, that is, the right to use the bus is given to each address at an equal opportunity.

In the 18th data cycle, the bus arbitration control unit 42 controls the transmission unit 44 in the high impedance state to the transmission state in the other data cycle, and sets the bus use right permission signal 1004 including the selected address.
Is transmitted to the bus 11 via the transmission unit 44.

The internal cells transmitted from the non-ATM line interface 2 to the bus 1 as described above
It is received by the M line interface 3 and processed as follows.

That is, in the ATM line interface 3, in the third data cycle, the address coincidence detecting unit 306 fetches the bus routing header 1005 from the bus 1 via the receiving unit 31, and stores the address indicated by the signal and the address register 303. Detects a match / mismatch with its own address stored in. Then, the control unit 310 is notified of the result. When the notification from the address match detection unit 306 indicates a match, the control unit 310 sends the data fetched from the bus 1 via the reception unit 31 to the reception buffer 28 in the third to seventeenth data cycles,
That is, an instruction is made to process the internal cell 1003 as a valid internal cell.

In response to this instruction, received data buffer unit 28 checks internal cell 1003 instructed to be processed as a valid internal cell. Then, the internal cell 10
ACK / NA indicating whether or not 03 has been successfully received
The CK signal is output from the ACK / NACK bus 14. If normal reception is possible, the internal cell 1003
From the channel number included in the bus routing header 1005, the ATM accommodating the ATM line 5 to which the ATM cell 1006 included in the internal cell 1003 is to be transmitted.
The M cell processing unit 22 is determined. And this decided A
The ATM cell 1006 extracted from the internal cell 1003 is transmitted to the TM cell processing unit 22. This ATM cell 1
The ATM cell processing unit 22 that has received 006 transmits the ATM cell 1006 to the ATM line 5 accommodated therein.

The operation for transmitting an internal cell from the non-ATM line interface 2 to the bus 1 has been described above.

Next, the operation when an internal cell is transmitted from the ATM line interface 3 to the bus 1 will be described.

The operation of the ATM line interface 3 in this case is the same as the operation of the non-AT at the time of transmitting an internal cell from the non-ATM line interface 2 to the bus 1 as described above.
The operation in the M line interface 2 is substantially the same. However, the processing in the ATM cell processing unit 22 and the processing for generating the priority level in the priority class generation unit 301 are different.

First, the processing in the ATM cell processing section 22 will be described.

The interface unit 21 receives an ATM cell sent from the ATM line 5 accommodated therein, and
It is input to the TM cell processing unit 22. In response to this, ATM
The routing information generation unit 221 of the cell processing unit 22 stores the V
Based on the correspondence between the PI / VCI, the address, and the channel number, the address and the channel number corresponding to the VPI / VCI of the header of the ATM cell received from the interface unit 21 are obtained, and the bus routing header including this is transferred to the ATM cell. Add to generate internal cells. Then, the generated internal cell is transmitted to the transmission buffer 27.
Here, the address is a non-A address that accommodates the non-ATM lines 6 and 7 that are the destinations of the data stored in this ATM cell.
The address of the TM line interface 2 is used, and the channel number is the channel number of the non-ATM lines 6 and 7 which are the destinations of the data stored in the ATM cells.

Next, a process of generating a priority level in the priority class generation unit 301 will be described.

The transmission buffer unit 27 temporarily stores the internal cells received from each ATM cell processing unit 22, and appropriately selects one internal cell to be transmitted from them. And
The control unit 310 of the bus control unit 30 is notified of the transmission request of the internal cell, and notifies the priority class generation unit 301 of the set of the address and the channel number included in the bus routing header of the selected internal cell.

Priority class generating section 301 outputs a priority level corresponding to the set of address and channel number notified from control section 310 in accordance with a preset set of address and channel number and priority level. .

The operation of transmitting an internal cell in the other ATM line interface 3 is the same as the operation of transmitting an internal cell in the non-ATM line interface 2 described above.

The internal cells transmitted from the ATM line interface 3 to the bus 1 as described above are received by one of the non-ATM line interfaces 2 and processed. The operation of receiving an internal cell at the non-ATM line interface is substantially the same as the above-described operation of receiving an internal cell at the ATM line interface 3 when transmitting an internal cell from the non-ATM line interface 2 to the bus 1. However, the difference is that the ATM cell processing unit 22 that has received the ATM cell decomposes the ATM cell to restore data, and transmits the data to the non-ATM lines 6 and 7 via the interface unit 21.

The embodiment of the present invention has been described above.

As described above, according to the present embodiment, priority is given to the transfer of ATM cells on the bus 1 for each of the non-ATM lines 6 and 7 through which data stored in the ATM cells is transmitted and received. Can be. Here, generally, the priority of an ATM cell is roughly determined by the type of the non-ATM lines 6 and 7 for transmitting and receiving data stored in the ATM cell. Therefore, according to the present embodiment, it is possible to arbitrate the right to use the bus in accordance with the priority of the data transferred on the bus 1. According to the present embodiment, such arbitration of the right to use the bus can be performed without providing a signal bus for controlling the right to use the bus in addition to the bus 1 for transferring the ATM cells. With the configuration, it can be realized.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the invention.

For example, in the above-described embodiment, a case has been described in which the transfer of ATM cells on the bus 1 is preferentially controlled for each of the non-ATM lines 6 and 7 through which data stored in the ATM cells is transmitted and received. However, the priority control unit is
It is not always necessary to provide each non-ATM line 6 and 7. AT
The priority control may be performed in an arbitrary unit indicating the priority of the M cell. For example, arbitration of the bus use right may be performed for each ATM cell by generating a priority class according to the quality class or VPI / VCI of each ATM cell.

In the above embodiment, the bus system according to the present invention is applied to an ATM multiplexing device as an example. However, the bus system according to the present invention is used for an ATM switch and other modules. The present invention can be applied to any device that transfers data using a bus. For example,
An ATM switch to which the bus system according to the present invention is applied can be configured by providing an ATM line interface 3 in place of the non-ATM line interface 2 in the configuration shown in FIG.

In the bus routing header described in this embodiment, in addition to the destination address and the channel number of the internal cell, the internal cell receiving side transmits the ATM cell included in the internal cell to the line. Priority information for performing priority control on, and information specifying a mode such as loopback transfer of an ATM cell may be included.

[0076]

As described above, according to the present invention, arbitration of the right to use the bus according to the priority of the data transferred on the bus can be performed with a relatively simple configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an ATM multiplexer to which an embodiment of the present invention is applied.

FIG. 2 is a diagram showing a configuration of a bus 1 shown in FIG.

FIG. 3 is a diagram showing a transmission format of data transmitted on a bus 1 shown in FIG.

FIG. 4 is a configuration diagram of a bus control module shown in FIG. 1;

FIG. 5 is a configuration diagram of a non-ATM line interface shown in FIG. 1;

FIG. 6 is a configuration diagram of an ATM line interface shown in FIG. 1;

[Explanation of symbols]

1 ... bus, 2 ... non-ATM line interface, 3 ...
ATM line interface, 4: Bus control module, 5: ATM line, 6: Voice communication line, 7: Data communication line, 21: Interface unit, 22: AT
M cell processing unit, 23 ... routing information table, 2
7: transmission buffer unit 28: reception buffer unit 29
... Timing generation unit, 30 ... Bus control unit, 31, 4
5 receiving unit, 32, 43, 44 transmitting unit, 41 timing generating unit, 42 bus arbitration control unit, 221
Routing information adding unit 222 ATM cell assembling unit 223 ATM cell decomposing unit 301 Priority class generating unit 302 Priority class decoder 303
Priority class match detecting section, 304 ... address register,
305: address decoder, 306: address match detection unit, 307: selector, 310: control unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K030 GA04 HA10 HB14 JA01 JA06 KA03 KA11 KA13 KA21 LA03 5K032 AA01 CA06 CD01 DA01 DA13 DB25 5K034 AA03 AA11 BB06 FF12 MM21

Claims (4)

[Claims] 1. An ATM device for transmitting and receiving ATM cells between a plurality of line interface units accommodating an ATM (Asynchronous Transfer Mode) line or a non-ATM line, comprising: a data bus connected to the plurality of line interface units; A bus control unit connected to the data bus, wherein each of the plurality of line interface units transmits a priority request of an ATM cell to be transmitted to the data bus and a transmission request with its own address, First transmission means for transmitting to the data bus, and second transmission means for transmitting an ATM cell to the data bus when receiving a transmission permission signal including its own address from the data bus, The bus control means, wherein a line interface unit that has transmitted the priority of the highest-order ATM cell to the data bus transmits the priority to the data bus. ATM apparatus characterized by and select one of the address, and transmits the transmission permission signal including the address selected to the data bus. 2. The ATM device according to claim 1, wherein said second transmitting means adds an address of a line interface unit of a transmission destination of the cell to an ATM cell and transmits the ATM cell to said data bus. The ATM device, wherein each of the plurality of line interface units further includes a receiving unit that receives an ATM cell with its own address. 3. A non-ATM (Asynchronous Transfer)
Mode) An ATM device for transmitting and receiving ATM cells between at least one non-ATM line interface unit accommodating a line and an ATM line interface unit accommodating at least one ATM line, wherein the at least one non-ATM line A data bus connected to the interface unit and the ATM line interface unit; and a bus control unit connected to the data bus. The non-ATM line interface unit includes First transmitting means for storing the transmitted data in an ATM cell and transmitting the data to the ATM line interface via the data bus; and transmitting the data from the ATM line interface via the data bus. Sends data stored in ATM cells to the non-ATM line that it contains A first receiving unit, and a transmission request with its own address and a priority determined according to a non-ATM line from which data stored in the ATM cell to be transmitted by the first transmitting unit is transmitted. ,
Transmitting to the data bus and receiving a transmission permission signal including its own address from the data bus;
And a first control unit for causing the transmitting unit to transmit the ATM cell to be transmitted, wherein the ATM line interface unit is transmitted from the non-ATM line interface unit via the data bus. Second receiving means for transmitting an ATM cell to the ATM line accommodated therein, and ATM transmitted from the ATM line accommodated therein.
Via the data bus to the non-ATM line interface unit, and a non-ATM transmission destination of the data stored in the ATM cell to be transmitted by the second transmission unit. When a transmission request including a priority determined according to the ATM line and its own address is transmitted to the data bus, and a transmission permission signal including the own address is received from the data bus, the second transmission means And second control means for transmitting the ATM cell to be transmitted. The bus control means, wherein the line interface unit which has transmitted the highest priority of the ATM cell to the data bus is A selecting one of the addresses transmitted to the data bus and transmitting the transmission permission signal including the selected address to the data bus. M equipment. 4. A bus system for transmitting and receiving data between a plurality of modules, comprising: a data bus connected to the plurality of modules; and a bus control means connected to the data bus. When there is data to be transmitted on the data bus, each module sets the priority of the data to be transmitted in a first cycle which is a periodic timing commonly determined in advance for each module. Along with transmitting to the data bus, determining means for determining whether or not the highest priority among the priorities transmitted to the data bus matches the priority transmitted by itself, and in the determining means, If it is determined that the highest priority among the priorities transmitted on the data bus matches the priority transmitted by itself, each module is determined in advance. And a first cycle for transmitting its own address to the data bus in a second cycle which is a periodically determined periodic timing.
When a transmission permission signal including its own address is received from the data bus in a third cycle which is a periodic timing commonly determined in advance for each module, the transmission means is determined in common for each module in advance. And a second transmission unit that transmits the data to be transmitted to the data bus in a fourth cycle that is a periodic timing, wherein the bus control unit performs the second cycle in the second cycle. And a third transmission unit for selecting one address from the addresses received from the data bus and transmitting a transmission permission signal including the selected address to the data bus in the third cycle. And the bus system.