JP2002027303A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device for obtaining an improved image. SOLUTION: This image pickup device adjusts an acceleration voltage vP between a photoelectric cathode PC and a solid image pickup element 1 that are provided in a vacuum container VE and a read speed fR of a solid image pickup element 1. Since the values vP and fR can be adjusted by adjusting thumbs TM1 and TM2, an improved image can be obtained. Further, the acceleration voltage vP can be controlled linking with the read speed fR by using a lookup table.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus for picking up an image, and more particularly, to an image pickup apparatus using an electron impact type multiplier having a built-in charge transfer type solid state image pickup device.

[0002]

2. Description of the Related Art A conventional imaging apparatus using an electron impact type multiplier or an electron drive type multiplier (EB-CCD) is described in Japanese Patent Application Laid-Open No. 61-133540. The imaging apparatus described in the publication includes a photocathode provided in a vacuum vessel, and a solid-state imaging device (CCD) arranged opposite to the photocathode and applied with a voltage between the photocathode.
This imaging device converts a light (energy ray) image into electrons in response to the incident light, collides the converted electrons with a CCD arranged in a vacuum, and reads out a pixel signal from the CCD. is there.

[0003]

However, the above-described imaging apparatus has a problem that a video signal of an input image contains noise or an image having a sufficient resolution cannot be obtained. The present invention has been made in view of such a problem, and has as its object to provide an imaging device capable of obtaining a high-quality image.

[0004]

In order to solve the above problems, the present invention provides a photocathode provided in a vacuum vessel, and a solid state photovoltaic device in which a voltage is applied between the photocathode and the photocathode. In an imaging apparatus including an imaging unit having an imaging element, a high-voltage application circuit that varies the voltage, a solid-state imaging device driving circuit that varies a signal reading speed from the solid-state imaging device, the high-voltage application circuit, and the solid-state imaging device. An output adjusting unit attached to the image pickup unit for adjusting an output of the image pickup element drive circuit. According to the present apparatus, a high-quality image can be obtained by the above adjustment.

The output adjusting means preferably includes first and second adjusting means for independently adjusting the outputs of the high-voltage applying circuit and the solid-state image sensor driving circuit. The adjusting means provides high operability and high quality. Images can be obtained.

Further, the present apparatus is characterized by comprising control means for changing the output of the high-voltage application circuit and the output of the solid-state imaging device drive circuit in an interlocked manner. As a result, the time required for obtaining a high-quality image manually can be reduced as compared with the case of manually obtaining the image.

The output of the high-voltage application circuit and the output of the solid-state image pickup device drive circuit correspond to each other on a one-to-one basis, and a storage means for storing this relationship is provided.
When one of the outputs of the high voltage application circuit and the solid-state imaging device drive circuit is set to a new output by adjusting one of the first and second adjustment means, the data is stored corresponding to one of the outputs. The other is adjusted so that the other output becomes the other output stored in the means. With the control of such a lookup method,
The calculation time by the control means can be reduced.

This control means adjusts one of the first and second adjustment means so that when one of the output of the high-voltage application circuit and the solid-state imaging device drive circuit is set to a new output, At this time, based on image information captured by the solid-state imaging device, the other may be feedback-controlled so that the image information has a predetermined value. With such feedback control, the above adjustment based on actual image information can be performed, and a higher quality image can be obtained.

In this device, the outputs of both the high-voltage application circuit and the solid-state imaging device drive circuit correspond one-to-one.
Storage means for storing this relationship, wherein the control means
And adjusting one of the second adjusting means, when one of the outputs of the high-voltage application circuit and the solid-state imaging device driving circuit is set to a new output, the storage means corresponds to one of the outputs. The other is adjusted so that the other output becomes the stored other output, and thereafter, based on the image information captured by the solid-state imaging device at the time of this adjustment, the other is adjusted so that this image information becomes a predetermined value. Is feedback controlled. By combining such a look-up method and a feedback method, it is possible to shorten the calculation time by the control means and obtain a higher quality image based on actual image information.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An imaging apparatus according to an embodiment will be described below. The same reference numerals are used for the same elements or elements having the same functions, and overlapping descriptions are omitted. The imaging apparatus according to the present embodiment includes an electron impact type multiplier or an electron driving type multiplier (EB-CCD) and its driving circuit.

FIG. 1 is a system configuration diagram of an imaging apparatus according to an embodiment.

First, the physical structure of the main part of the EB-CCD will be described.

[0013] This device uses energy rays (including visible light).
A condensing lens LS that condenses the image hν, and a window member WM that is arranged to face the lens LS and that forms an input face plate of the vacuum vessel VE. The pressure in the vacuum vessel VE is reduced, and the semiconductor solid-state imaging device 1 and the photocathode (photocathode) PC are arranged in the vacuum vessel VE. Note that the photocathode PC is provided on the inner surface of the window material WM, and the vacuum vessel VE, the semiconductor solid-state imaging device 1, and the photocathode PC are the EB-CCD body 1
0.

The photocathode PC is formed by stacking and depositing materials such as Sb, Na, K, and Cs. The photocathode PC can also be formed by evaporating Cs in a vacuum on a GaAsP crystal that has been bonded to the window material WM in advance. The photocathode PC contains a material capable of lowering the work function by containing an alkali metal or the like and emitting electrons in response to the incident energy ray hν (for example, CsS).
b). The photocathode PC has Cr,
A bias potential is applied through an electrode (not shown) formed by sequentially depositing Ni and Cu.

The semiconductor solid-state imaging device 1 is a back-illuminated solid-state solid-state imaging device. An n-type layer is formed on a surface opposite to a light incident surface on the basis of a p-type semiconductor substrate. This is a buried channel type CCD in which transfer electrodes of the CCD are formed. The semiconductor solid-state imaging device 1 includes an imaging region 1i in which pixels made of a CCD (charge coupled device) are two-dimensionally arranged, and a storage region 1a having the same structure as the imaging region 1i and being adjacent thereto. Have.

In the back-illuminated solid-state solid-state imaging device, the thickness of the imaging region 1i is set smaller than the thickness of the peripheral portion. The imaging region 1i of the present example is thinned to a thickness of about 20 μm by etching the semiconductor substrate from the back surface which is the light incident surface. On the other hand, the accumulation region 1a is maintained at a thickness of about 300 μm before etching.

The imaging region 1i of the semiconductor solid-state imaging device 1 is
It faces the photocathode PC, and an electron image (photoelectron) generated by the photocathode PC according to the incidence of the energy ray hν is directly incident. Since the photoelectrons are accelerated by the electric field inside the container, when kinetic energy is lost in the silicon substrate in the imaging region 1i, about 200 to 600
Electron-hole pairs are generated. The multiplied electrons thus generated move to the transfer electrode side of the CCD formed on the side opposite to the electron incident surface, and reach the potential well of the imaging region 1i.

The charges generated in the image pickup area 1i are transferred to the storage area 1a. The storage area 1a is formed by two-dimensionally arranging CCDs for storing the electric charges. Note that two directions perpendicular and perpendicular to the thickness direction of the semiconductor solid-state imaging device 1 are referred to as a vertical direction (column) and a horizontal direction (row), respectively.

The semiconductor solid-state imaging device 1 includes a horizontal shift register 1hs which is located on the opposite side of the imaging region 1i with respect to the accumulation region 1a and which horizontally transfers electric charges transferred vertically from the accumulation region 1a. ing. The horizontal shift register 1hs is formed of a one-dimensional CCD.

A capacitor 1c for temporarily storing the charge transferred via the horizontal shift register 1hs is connected to the end of the horizontal shift register 1hs in the charge transfer direction. A reset signal receiving transistor (FET) 1tr is connected in series to the capacitor 1c. When a reset signal R is input to the gate of the reset signal receiving transistor 1tr, the capacitor 1c is switched from the power supply VDD to the capacitor 1c.
And positive charges are fully accumulated on one electrode side of the capacitor 1c.

After the reset, when negative charges (electrons) are transferred to the capacitor 1c via the horizontal shift register 1hs, a part of the positive charges in the capacitor 1c disappears and are proportional to the charges flowing into the capacitor 1c. The reduced voltage is subtracted from the voltage across the capacitor 1c at the time of reset, and is input to the gate of the pixel signal output transistor 1to.
The pixel signal output transistor 1to includes a capacitor 1c
Are connected in parallel, and when the pixel signal output transistor 1to conducts according to a signal input, the power supply V
A current flows from DD to the ground via the resistor 1r.

Between both ends of the resistor 1r, a voltage level input to the pixel signal output transistor 1to, in other words, an output voltage corresponding to the charge amount of each pixel sequentially transferred through the horizontal shift register 1hs. Appears, and this is output to the outside as a pixel signal.

The capacitor 1c and the transistor 1t
r, 1to and the resistor 1r are formed in a semiconductor substrate constituting the solid-state imaging device 1.

Next, the EB-CCD drive circuit 2 will be described.

The driving circuit 2 has a vertical scanning circuit 2vs. The vertical scanning circuit 2vs applies two-phase transfer voltages P _V1 and P _V2 for vertically transferring an electron group generated in response to the incidence of electrons on the imaging region 1i to the CCD in the imaging region 1i. The vertical scanning circuit 2 vs.
The two-phase transfer voltages P ′ _V1 and P ′ _V2 for vertically transferring the electron group for each pixel transferred from the storage region 1a are stored in C of the storage region 1a.
Apply to CD. In other words, these areas 1i, 1a
In, the vertical scanning circuit 2vs applies a two-phase transfer voltage between the CCDs adjacent in the vertical direction so that the pixel groups arranged in the horizontal direction are simultaneously transferred in the vertical direction.

The driving circuit 2 has a horizontal scanning circuit 2hs. The horizontal scanning circuit 2hs applies a two-phase transfer voltage to the CCD of the horizontal shift register 1hs. In other words,
The two-phase transfer voltages P _H1 and P _{H are} applied between the horizontally adjacent CCDs.
_{Apply H2} . Pixel charges are accumulated in each CCD arrayed in the horizontal direction of the horizontal shift register 1hs, and these charges are sequentially transferred in the horizontal direction by application of the transfer voltage.

The vertical and horizontal scanning circuits 2vs, 2hs
According to the input clock signal C, the transfer voltage P (=
P _V1 , P _V2 , P ′ _V1 , P ′ _V2 , P _H1 , P _H2 ). The frequency of the transfer voltage P is proportional to the frequency of the clock signal C. That is, the higher the frequency of the clock signal C, the higher the frequency of the transfer voltage P.

Semiconductor solid-state imaging device 1 according to the incidence of electrons
A multiplied electron group is generated in the imaging region 1i, but the potential of the semiconductor solid-state imaging device 1 itself is the ground potential, and when the transfer voltage P is negative, the solid-state image pickup device 1 directly below the transfer electrode formed on each pixel. A potential well is formed in the buried n-type region;
The generated electrons are accumulated.

Note that not all of these electron groups are necessarily captured in one pixel of the CCD. For example, when the pixel size is 24 μm × 24 μm, an acceleration voltage V _{P of 8} kV is used.
Is applied, the electron group is distributed in about 2.5 pixels on average.

At the time of imaging, exposure (image accumulation)
The period T1 and the vertical transfer period T2 are set alternately. The exposure period T1 is set to, for example, 0.5 s, and the vertical transfer period is set to, for example, 0.5 ms.

In the exposure period T1, that is, at the time of electron incidence, a negative constant voltage is applied to each pixel of the imaging region 1i so that a potential well is formed in each pixel, and the generated charges (electrons) are applied to each pixel. To accumulate.

In the subsequent vertical transfer period T2, the vertical
Direct transfer voltage P_V1, P_V2, P ' _V1, P '_V2Imaging area
Applied to the region 1i and the accumulation region 1a, and
Is transferred to the storage area 1a. In this vertical transfer,
The transfer electrode of the imaging region 1i and the transfer electrode of the storage region 1a
The transfer voltage P is applied so that the H level is applied alternately._V1, P _V2
And P '_V1, P '_V2Is applied. Frequency of each voltage
The number is set to, for example, 1 MHz (period: about 1 μs).

Thereafter, during the next exposure period T1, the transfer voltages P ' _V1 and P' _V2 are applied to the storage region 1a, so that the electric charge stored in each CCD in the storage region 1a is shifted horizontally for each horizontal line. At the same time as the transfer to the register 1hs, the transfer voltages P _H1 and P _H2 in the horizontal direction are applied to the horizontal shift register 1hs, and the charge of each CCD is sequentially output from the end of the horizontal shift register 1hs, and the charge is read from each CCD. A reset signal R is applied every time.

At this time, the frequencies of the transfer voltages P ′ _V1 and P ′ _V2 are set to, for example, 17 kHz (period: about 60 μs).
The transfer voltages P _H1 and P _H2 and the frequency of the reset signal R are 14
MHz (period: about 75 ns).

Accordingly, the vertical transfer voltages P _V1 , P _V2 and the transfer voltages P ′ _V1 , P ′ _V2 in the vertical transfer period T2 are set.
(Repetition frequency) f _V2 is the same, and the frequency f _V1 of the vertical transfer voltages P ′ _V1 and P ′ _V2 in the readout period (t1) set within the exposure period T1 is lower than this. Also, the frequency (repetition frequency) f of the transfer voltages P _H1 and P _H2 in the horizontal direction during the readout period (t1)
_H is higher than the frequency f _V1, f _{V 2,} is identical to the frequency (repetition frequency) f _R of the reset signal R.

The driving circuit 2 includes a vertical and horizontal scanning circuit 2v
A timing control circuit 2t that outputs a clock signal C at s and 2hs is provided. Timing control circuit 2t of this example
Is a frequency selector, and three different base clock signals CLK1, CLK2, CLK3 (CLK1
Frequency <frequency of CLK2 <frequency of CLK3) is selected and output as the clock signal C. Which one to select is determined based on the timing control signal input to the timing control circuit 2t. The timing control circuit 2t can also be configured by a programmable divider whose output frequency varies in accordance with an input timing control signal.

The timing control circuit 2t also generates the above-mentioned reset signal R based on the selected clock signal. The frequency f _R of the reset signal R is proportional to the frequency of a selected one of the base clock signals CLK1, CLK2 and CLK3. Since the above-mentioned reset needs to be performed each time charge of one pixel flows into the capacitor 1c, the horizontal shift register 1hs
When the signal charge is transferred at high speed (when the clock frequency is high), the reset cycle is short. When the signal charge is transferred at a low speed (when the clock frequency is low), the reset period is reduced. Becomes longer.

That is, the frequency of the reset signal R is set to f _R
(Hz), this is the pixel signal readout speed, and in the present apparatus, the pixel signal readout speed f _R (H
z) can be changed based on the timing control signal.

[0039] Here, between the photocathode PC and semiconductor solid-state imaging device 1, the high voltage V _P has been applied from the high voltage generating circuit 2HV, electrons generated in the photocathode PC in proportion to the voltage Accelerated. High voltage generating circuit 2HV is variable voltage source, it is possible to change the accelerating voltage V _P on the basis of a high voltage control signal input to the high voltage generating circuit 2HV.

The electrons generated in the photocathode PC are accelerated by acceleration voltage V _P, entering the imaging region 1i. The electron group generated by the electron incidence is transferred as described above, and is output as a pixel signal while being reset for each pixel. Here, in the reset, the amount of charge accumulated in the capacitor 1c fluctuates, and this is input to the pixel signal output transistor 1to as a noise voltage. However, in the conventional imaging apparatus, it has been impossible to detect an electron beam image composed of several to several tens of electrons per unit area due to such noise. This unit area corresponds to the area of one pixel.

The imaging apparatus of the present embodiment satisfies the following relation (A). (Number _{1) n 0 (f R /} f R0) 1/2 <(V P -V TH) / E V P (V): Photocathode PC and solid state imaging device 1
Acceleration voltage f _R (Hz) applied between the following: reading speed n _{0 of the} pixel signal output from the amplifier The root mean square value of the number of noise charges input to the amplifier when the reading speed of the pixel signal output from the amplifier is f _R0 (Hz) V _TH (V): The photocathode PC when electron multiplication starts Threshold voltage E (eV) between semiconductor solid-state imaging device 1 and electron-hole binding energy in semiconductor imaging region 1i

The present imaging device converts an energy ray image into electrons in response to the incidence of the energy ray image, and converts the converted electrons into a semiconductor imaging region 1i of the semiconductor solid-state imaging device 1 arranged in a vacuum.
And reads out pixel signals from the semiconductor solid-state imaging device 1 via the amplifier 1to.

When a weak energy ray image is incident on a conventional imaging device, the pixel signal output from the semiconductor solid-state imaging device 1 is buried in a noise charge component, and this cannot be detected. In an imaging device,
By satisfying the above relationship, the noise level can be suppressed lower than the weak electron beam image emitted in response to the incidence of the weak energy beam image, so that a weak energy beam image that could not be detected conventionally can be captured. it can.

It is more preferable that the present imaging device satisfies the following relationship (B). (Equation 2) 3 × n ₀ (f _R / f _R0 ) ^1/2 <[(V _P −V _TH ) / E] −3 × [(V _P −V
_TH ) / E] ^1/2

(I) The noise level fluctuates with time, and (ii) the pixel signal generated by the collision of the weak electron beam image with the semiconductor solid-state imaging device 1 also fluctuates because of fluctuation.

To describe (i) in detail, for example, f _R
Assuming that the number of noise charges n ₀ generated when the frequency is 150 kHz is 15 on average, the number of noise charges when f _R is 300 kHz is equivalent to an average of 15 × (300/150) ^1/2 ≒ 21 electrons. And three times this average value (21 × 3 = 63)
), The number of noise charges fluctuates so that 99% of the noise is present.

The (ii) will be described in detail.
For example, about 640 electrons are generated by one photoelectron injected into the i CCD, and the 640 electrons have an electron density gradient and are distributed in about 2.5 pixels. At least 300 or more electrons are taken in by the pixel, and (30 pixels on average) per unit pixel.
0) ^1/2 ≒ 17 shot noises are generated, and the level of the shot noise fluctuates so that 99% of the shot noise exists below a value that is three times (17 × 3 = 51) the average value. It will be.

Therefore, in the present imaging apparatus, the relationship (B) is set such that the noise does not affect the pixel signal even if these fluctuations occur, that is, 99% or more of the noise is below the pixel signal level. Are satisfied, and these are separated. Therefore, according to the present apparatus, the detection accuracy of the weak energy ray image can be further improved.

In particular, when the semiconductor solid-state imaging device 1 is made of silicon (Si), the electron-hole coupling energy E is theoretically set to 3.6 eV. Further, according to the trial experiment, by setting the E value to 5 eV, a weak energy ray image can be detected with higher accuracy. In such a case, the threshold voltage V _TH is preferably set to 4.8 kV.

The semiconductor solid-state imaging device 1 is an FT
The present invention relates to an interline transfer (IT) type CCD, FFT (Full Fra
me Transfer) type CCD.

Note that n ₀ = 15, f _R0 = 150 kHz,
An example of setting parameters when V _TH = 4.8 kV and E = 5 eV will be described.

[0052] For example, f _R = If set to 300kHz, the V _P to satisfy the relationship (A) 5.12 (k
V).

[0053] For example, when set to f _R = 300kHz, the V _P for satisfying the above relationship (B) 5.27 (k
V).

With this setting, when one electron is output from the photocathode PC in response to the incidence of a single photon, this can be detected.

Next, the configuration of an imaging system having the above-described imaging device will be described.

FIG. 2 is a block diagram of the present imaging system. The imaging apparatus includes a camera head 30 that houses the EB-CCD main body 10 as an imaging device, a camera controller 40 that controls the EB-CCD main body 10, and the like, and a computer 50 that gives commands to the camera controller 40 and inputs video output. . Note that the camera head 30 and the controller 40 constitute an imaging unit, and these are separate bodies, but may be integrated.

The camera head 30 includes an EB-CCD main body 10, a driving circuit (solid-state imaging device driving circuit) 2, a first stage video amplifier (preamplifier) 3 for amplifying an output signal from the semiconductor solid-state imaging device 1, and a high voltage V _P. And a lens LS is provided on the camera head 30 on the subject light image incident side.

The CCD drive circuit 2 applies the above-described two-phase or three-phase transfer voltage P to the transfer electrodes of the solid-state solid-state image pickup device 1. This timing is determined by the timing generation circuit 2t1 provided in the camera head 30 and the camera. Controller 4
It is generated by the timing generation circuit 2t2 provided in 0. In other words, the timing control circuit 2t shown in FIG. 1 is separated into timing generation circuits 2t1 and 2t2, the timing generation circuit 2t2 transmits a synchronization signal to the timing generation circuit 2t1, and the timing generation circuit 2t1 A clock used for a transfer voltage P generated by the CCD drive circuit 2 is generated based on the synchronization signal and a timing control signal from the CPU 24. In addition,
The timing generation circuit 2t2 generates a base clock for the entire system.

The camera controller 40 includes a high-voltage control circuit 23 for controlling the high-voltage generation circuit 2hv by a high-voltage control signal. The high-voltage generation circuit 2hv and the high-voltage control circuit 23 constitute a high-voltage application circuit. The high voltage application circuit is controlled by the CPU 24, and its voltage is variable. Several volts (for example, 0 to 0) output from the CPU 24
The DC voltage signal (6 volts) is converted into a voltage approximately 1000 times higher by the high voltage application circuit.

Further, the camera controller 40 includes a video amplifier (main amplifier) 2 for amplifying the output of the preamplifier 3.
2, an A / D converter 25 for converting the output of the main amplifier 22 into a digital signal, a frame memory 27 for storing an image output signal for one screen output from the A / D converter 25, and a frame memory. And a D / A converter 29 for converting the digital signal accumulated or generated in 27 into an analog signal and outputting the analog signal.

The video output of the D / A converter 29 is input to a display or a computer 50 with a display.
The input image to the B-CCD main body 10 is displayed. Various commands for controlling the apparatus are input to the computer 50, and the CPU 24 sets the acceleration voltage _VP and the signal reading speed f _R independently according to the command input from the computer 50. A highly accurate pixel signal can be output from the EB-CCD body 10.

Next, the operation of the present system will be described.

When light passes through the face plate WM shown in FIG. 1 and enters the photocathode PC, the EB-CCD
A pixel signal is output from the main body 10. This signal is amplified by the preamplifier 3 and the main amplifier 22 and then A / D
The signal is sent to the conversion circuit 25, converted into a digital signal, and temporarily stored in the frame memory 27.
The image is input to the computer as an image output via the A conversion circuit 29. The analog video output is supplied to the computer 50
Then, it is converted into a digital signal again and the video information is stored in the memory. This analog video signal may be output directly to a television or the like.

The image output signal in the dark state for one screen (one frame) is stored in the frame memory 27, and the dark image data is subtracted from the digital image data stored in the frame memory 27. , Background noise can be reduced. Frame memory 27
Is set when the power of the camera controller 40 is turned on or when the CP
Updating can be performed by external control via U24, and it is possible to cope with an output change in a dark state due to aging of the image sensor or the like. When overflow from the frame memory 27 is detected, feedback control may be performed to control the clock C to decrease.

In this embodiment, the camera head 30
The high voltage application circuits 2hv, 23 and C
Output adjusting means TM1 and TM2 for manually adjusting the output of the CD drive circuit 2 are provided.

That is, the acceleration voltage v _P output from the high voltage generation circuit 2hv is changed by adjusting the high voltage control signal, and is applied between the photocathode PC of the EB-CCD body 10 and the solid state image pickup device 1. . Since the high-voltage control signal is changed by an adjustment knob (first adjustment unit) TM1 provided as an output adjustment unit provided in the housing, the acceleration voltage v _P can be adjusted by adjusting the adjustment knob TM1. The knob TM1 outputs an analog or digital control signal, controls the volume V1 that controls the magnitude of the high-voltage control signal, and controls the high voltage applied between the photocathode 13 and the solid-state image sensor 1.
Note that the output of the knob TM1 may be input to the CPU 24. In this case, the CPU 24 controls the high voltage control circuit 23 based on a signal from the knob TM1 to generate a desired high voltage.

A volume V for varying the frequency of the synchronization signal output from the timing generation circuit 2t2.
2 is provided in the synchronization signal path. When the volume V2 is adjusted by adjusting the knob TM2 (second adjusting means) provided on the housing, the frequency of the synchronization signal output from the timing generation circuit 2t2 is adjusted, and the frequency-adjusted synchronization signal is generated by the timing generation. The frequency of the CCD drive signal input to the CCD drive circuit 2 via the circuit 2t1 is varied.

The knob TM2 outputs an analog or digital control signal, and the volume V2 is
Controlled by this signal. The volume V2 may be a programmable divider that varies an output frequency according to a division ratio set by a control signal, or a plurality of dividers having different division ratios to which a base clock is input are connected in parallel. Alternatively, an output selector may be arranged on the rear side of the frequency divider group, and one of the frequency divider outputs may be selected by a control signal.

The output of the knob TM2 may be input to the CPU 24. In this case, the CPU 24 operates the timing generation circuit 2t1 based on the signal from the knob TM2.
To generate a CCD drive signal of a desired frequency.

As described above, the above-described image pickup apparatus includes:
In an imaging apparatus including a photocathode PC provided in a vacuum vessel VE disposed in a housing and a solid-state imaging device 1 disposed opposite to the photocathode PC and applied with a voltage between the photocathode PC, High-voltage application circuits 2hv, 23, which vary the speed of reading, solid-state imaging device drive circuit 2, which varies the signal reading speed (CCD output signal, CCD drive signal) from solid-state imaging device 1, high-voltage application circuits 2hv, 23, and solid-state Output adjusting means TM1 and TM2 attached to the housing for adjusting the output of the image sensor driving circuit 2 are provided, and a high quality image can be obtained by the adjustment.

The output adjusting means includes a high voltage application circuit 2hv,
23 and first and second adjusting means TM1 and TM2 for adjusting the outputs of the solid-state image sensor driving circuit 2 independently of each other.
Is provided. By these adjusting means TM1 and TM2, a high quality image can be obtained with high operability. Adjusting means TM
1, the output of the TM2, the high voltage application circuits 2hv, 23, and the output of the solid-state imaging device drive circuit 2 may be adjusted in association with each other. As a result, the time required for obtaining a high-quality image manually can be reduced as compared with the case of manually obtaining the image. In conjunction,
In addition to a mechanical link mechanism, a stepping motor can be used. Such an operation may be performed by the computer 50, or may be performed by using the CPU 24 inside the apparatus. In other words, the present imaging apparatus controls the control units 24 and 50 that change the outputs of the high-voltage application circuits 2 hv and 23 and the solid-state imaging device drive circuit 2 in an interlocked manner.
Is provided. Here, it is assumed that the computer 50 performs the above operation as a control unit.

That is, the computer 50 obtains the acceleration voltage v _P and the read speed f _R in a one-to-one correspondence so as to satisfy the above-mentioned relationship (A) or (B), and uses a look-up table method. , And if one is confirmed,
Confirm the other. More specifically, in the present device, the outputs of both the high-voltage application circuits 2hv and 23 and the solid-state imaging device drive circuit 2 are in one-to-one correspondence, and are provided with storage means (not shown) for storing this relationship. The control means 50 adjusts one of the first and second adjustment means TM1 and TM2, so that the output of one of the high voltage application circuits 2hv and 23 and the solid-state imaging device drive circuit 2 becomes a new output. When set, the other output is adjusted so that the other output stored in the storage means corresponds to the one output. The control time of the computer 50 can be reduced by such a lookup-type control.

Further, the computer 50 may perform feedback control based on the information of the captured image. That is, the computer 50 includes the first and second
When either one of the high voltage application circuits 2hv, 23 and the output of the solid-state image sensor driving circuit 2 are set to a new output by adjusting one of the adjusting means TM1, TM2, the solid-state image sensor 1 Based on image information (digital or analog video output input to a computer) captured by the computer, so that the image information has a predetermined value (a maximum luminance during video output is a specific value equal to or lower than a saturation level). Feedback control.

For example, the predetermined value is set to a value VS−ΔV slightly lower than the saturation level VS in the solid-state image sensor 1. For example, when the reading speed f _R is increased by the knob TM2, the computer 50 sets the maximum value of the luminance in the video signal output from the solid-state imaging device 1 (the maximum voltage VM when converted to the output voltage of the solid-state imaging device 1). The high voltage application circuits 2hv and 23 are feedback-controlled so that the maximum voltage VM matches the predetermined value VS−ΔV. On the other hand, when lowering the accelerating voltage V _P, it is conceivable to feedback control of the reading speed f _R Along with this. With such feedback control, the above adjustment based on actual image information can be performed, and a higher quality image can be obtained.

Further, the look-up table method and the feedback control method may be combined.

That is, in the present apparatus, the outputs of both the high-voltage application circuits 2hv and 23 and the solid-state imaging device drive circuit 2 correspond one-to-one, and a storage means (not shown) for storing this relationship is provided. By adjusting one of the first and second adjusting means TM1 and TM2, the output (for example, f _R ) of one of the high-voltage applying circuits 2hv and 23 and the solid-state imaging device driving circuit 2 is newly obtained. If one of the outputs is set to the appropriate output (f _R )
The other output (V _P) stored in said storage means in response to said adjust the other output the (V _P) to become the other 2HV, 23, after which the solid-state imaging element during the adjustment Based on the image information (video output) captured by 1, the other 2hv, 23 is feedback-controlled so that this image information has a predetermined value (the voltage VM matches the predetermined value VS−ΔV). By combining such a look-up method and a feedback method, it is possible to shorten the calculation time by the control means and obtain a higher quality image based on actual image information.

Adjustment of the knobs TM1 and TM2 is performed according to the EB-C
A video signal (CCD output signal) output from the CD is displayed on a display provided in the computer 50, and the operation is performed while observing the image. In the present apparatus, these adjustments, since the acceleration voltage V _P and the signal reading speed f _R may each variably, as described above, can be displayed on the display device an image of high precision. In addition, the apparatus shown in FIG. 2 can also perform the following modifications. Further, in the following description of the apparatus, the configuration without any special description is the same as the above.

FIG. 3 is a block diagram of such an image pickup apparatus. The knobs TM1 and TM2 as output adjustment means are attached to the controller 40, and the knobs TM1 and TM2
The adjustment amount of TM2 is directly input to the CPU (control means) 24. The CPU 24 independently controls the acceleration voltage v _P by the high voltage application circuits 2 hv and 23 and the reading speed f _R by the solid-state imaging device drive circuit 2 in accordance with the input adjustment amounts of the knobs TM 1 and TM 2. The digital video signal output from the A / D conversion circuit 25 is directly input to the computer 50. Of course, it may be input from the D / A conversion circuit 29 side.

[0079]

According to the imaging apparatus of the present invention, a high-quality image can be obtained by adjusting the acceleration voltage and the signal reading speed by the output adjusting means.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of an imaging apparatus.

FIG. 2 is a block diagram of an imaging system.

FIG. 3 is a block diagram of another imaging system.

[Explanation of symbols]

PC: Photocathode, VE: Vacuum container, 1: Semiconductor solid-state imaging device, 1i: Semiconductor imaging region, 1to: Amplifier, TM
1, TM2: output adjusting means.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C022 AA15 AB31 AC42 AC69 AC78 CA02 5C024 AX00 CX37 EX03 GX09 GY01 GZ01 HX18 HX23 HX47 HX58

Claims (6)

[Claims] 1. An imaging apparatus comprising: a photocathode provided in a vacuum container; and an imaging unit having a solid-state imaging device disposed opposite to the photocathode and applied with a voltage between the photocathodes, A variable high-voltage application circuit, a solid-state imaging device driving circuit that varies a signal readout speed from the solid-state imaging device, and the imaging unit for adjusting outputs of the high-voltage application circuit and the solid-state imaging device driving circuit. An image pickup apparatus comprising: an output adjustment unit attached to the image pickup apparatus. 2. The apparatus according to claim 1, wherein the output adjustment unit includes first and second adjustment units that independently adjust the outputs of the high-voltage application circuit and the solid-state imaging device drive circuit. Imaging device. 3. The imaging apparatus according to claim 2, further comprising control means for changing the outputs of the high-voltage application circuit and the solid-state imaging device drive circuit in an interlocked manner. 4. The output of both the high-voltage application circuit and the solid-state imaging device drive circuit is in one-to-one correspondence, and comprises storage means for storing this relationship, and wherein the control means comprises the first and second control circuits. By adjusting any of the adjustment means,
When one of the outputs of the high-voltage application circuit and the solid-state imaging device drive circuit is set to a new output, the other output stored in the storage means corresponding to the one output is applied to the other output. The image pickup apparatus according to claim 3, wherein the other is adjusted so that the output of (1) is obtained. 5. The control means adjusts one of the first and second adjustment means so that the output of one of the high voltage application circuit and the solid-state imaging device drive circuit becomes a new output. 4. The imaging apparatus according to claim 3, wherein when set, based on image information captured by the solid-state imaging device at this time, the other is feedback-controlled so that the image information has a predetermined value. . 6. The output of both the high-voltage application circuit and the solid-state imaging device driving circuit has a one-to-one correspondence, and includes storage means for storing this relationship, and the control means includes the first and second control circuits. By adjusting any of the adjustment means,
When one of the outputs of the high-voltage application circuit and the solid-state imaging device drive circuit is set to a new output, the other output stored in the storage means corresponding to the one output is applied to the other output. The other is adjusted so that the output becomes, and then, based on the image information captured by the solid-state imaging device at the time of this adjustment, feedback control of the other is performed so that the image information has a predetermined value. The imaging device according to claim 3, wherein: