JP2002026982A - Packet switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high throughput by suppressing the delay time of a packet switch. SOLUTION: Packet contention control is conducted by using a control time slot in the unit of a fixed length lower than a maximum packet length. When packets are not filled in the control time slot, simultaneous arrivals of packet from input ports are permitted. In the case of containing one packet or more to the control time slot, the packets are contained by taking the priority into account and the packets with higher priority are transferred sequentially.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch applied to a packet switching system that handles variable-length packets, such as a router or an Ethernet (registered trademark) switch.
In particular, the present invention relates to a packet control method and a switch configuration in a packet switch having a buffer on an input side in a space division type packet switch.

[0002]

2. Description of the Related Art In a conventional virtual output buffer type packet switch, an input packet is divided into cells having a minimum packet length size and buffered, and contention control and switching are performed by a time slot of a cell unit having a minimum packet length size. Is going.

FIG. 12 shows a configuration of a conventional virtual output buffer type packet switch. FIFO buffers 2-1 to M
Transmits the header information of the arriving packet to the routing information control circuit 4, and based on the routing control signal from the routing information control circuit 4,
It is a circuit for sending a packet to -1-1 to MN.

The routing information control circuit 4 analyzes a packet header, analyzes which output port 11-1 to N is addressed, and transmits a routing control signal to the FIFO buffer control circuits 3-1 to M. .

[0005] The cell forming devices 50-1-1 to 50-N are devices that divide variable-length packets arriving at the input ports 1-1 to M into cells having a minimum packet length size, which is a time slot length.

The virtual output buffers 5-1-1 to M-N are:
Buffers corresponding to the output ports 11-1 to 11-N, which buffer packets until transmission is permitted by contention control.

Virtual output buffer control circuit 6-1-1 to M
-N manages the packets in the virtual output buffers 5-1-1 to M-N and sends a Req signal requesting the transmission of the buffered packets to the grant contention control circuits 7-1 to 7-1.
The transmission control circuit 90-1 transmits the packet to the N. When the transmission control circuits 90-1 to 90-M receive the grant signal, the packet is transmitted.

In the Grant conflict control circuits 7-1 to 7-1N, the virtual output buffers 5-1-1 to MN are connected to the output port 11-.
This is a circuit that performs contention control when a cell contention occurs when cells are transmitted to 1 to N.

[0009] The cell distribution devices 120-1 to 120-N are devices that distribute incoming cells to packet assembling buffers 130-1-M to NM corresponding to input ports based on a cell header.

[0010] Packet assembling buffers 130-1-M to N
-M is a buffer for assembling variable-length packets divided into cells into packets.

The packets arriving at the input ports 1-1 to M are buffered in the FIFO buffers 2-1 to M, and are sent from the FIFO buffer control circuits 3-1 to M to the routing information control circuit 4 by the FIFO buffers 2-1 to M. The routing control is performed by transmitting the header information of the M packets.
FIFO buffer control circuit 3
-1 to M, divided into cells of the minimum packet length (generally 64 bytes) by the cellifying devices 50-1-1 to MN, and then corresponded to the destination output ports 11-1 to 11-N in cell units. Buffering is performed on the virtual output buffers 5-1-1 to MN. Virtual output buffer control circuit 6-1-1
.. MN include header information of the first cell of the virtual output buffers 5-1-1 to MN in order to request transmission of the packets buffered in the virtual output buffers 5-1-1 to MN. Grant conflict control circuit 7-1
To N.

The grant conflict control circuits 7-1 to N perform conflict control, and select the input port 1-1 selected by the conflict control.
Granted to the transmission control circuits 90-1 to 90-M
Send a signal.

Depending on the result of the conflict control of the Grant conflict control circuits 7-1 to N, Grant signals to a plurality of output ports 11-1 to 11-N may arrive at the same input port 1-1 to M. It is necessary to select cells of one virtual output buffer 5-1-1 to M-N at the input ports 1-1 to M, and selection control is required at the transmission control circuits 90-1 to 90-M. FIG. 13 shows the document "McKeown, N .; Izzard, M .; Mekki
ttikul, A.; Ellerstick, W.; Horowitz, M., "Tiny Tera: ap
acket switch core "IEEE Micro Volume: 171, Jan.-Feb.1
997, Page (s): 26-33 ", which represents a contention control method called iSLIP in a switch. At this time, since there is a possibility that the output port may be vacant in one control, the input port not selected in the first control transmits the Req signal again, and outputs the Grant signal from the output port capable of outputting. Sends a packet when receiving a packet. As described above, in order to increase the throughput, Request processing-Grant processing-ac
The cycle of the cept process is performed a plurality of times.

According to the result of the final control, the switching fabric 100 is controlled, and the cells are transmitted to the switching fabric 100 and transmitted to the output ports 11-1 to 11-N. Since cells sent to the output ports 11-1 to 11-N need to be returned to packets, the cell distribution device 120-N
1 to N, all the cells constituting the packet are buffered in the packet assembling buffers 130-1-1 to NM corresponding to the input port until all the cells constituting the packet arrive at the output port, and all the cells constituting the packet are As soon as the cell arrives, it is output back to the packet.

[0015]

In such a conventional packet switch, considering the current network link speed of about 1 Gbps, even in a system in which processing is performed by dividing cells into short cells, contention control is performed in one cell transfer time. Can be terminated. However, when the link speed is increased in the future, there is a problem that the contention control is not performed in one cell time, the effective throughput is reduced, and a high-speed processor must be used for control.

Further, since switching is performed by dividing a packet into cells, an additional device for cell division and packet assembly is required.

The present invention has been made in view of such a background, and an object of the present invention is to provide a packet switch capable of achieving high speed. An object of the present invention is to provide a packet switch that can simplify the configuration. An object of the present invention is to provide a packet switch that can realize high throughput.

[0018]

SUMMARY OF THE INVENTION The present invention provides a virtual output buffer for temporarily storing packets arriving at an input port for each output port of the destination, and a plurality of packets addressed to the same output port of the virtual output buffers. The packet switch includes contention control means for granting packet transmission permission to any of the transmission requests.

Here, a feature of the present invention is that a fixed length control time slot is provided as a control unit of the contention control means, and the control time slot length is longer than the maximum length of the incoming packet. The control time slot is provided with means for storing one or more packets which are set long and stored in the virtual output buffer.

As described above, the packet switch of the present invention replaces the conventional contention control using the minimum packet length transfer time as the control time slot so that the contention control does not become a bottleneck in the transfer under the high-speed link speed. It is characterized in that contention control is performed using a transfer time longer than the packet length as a control time slot.

[0021] It is preferable that a means is provided for generating header information of the control time slot based on header information of the one or more packets stored in the control time slot.

As described above, the packet switch according to the present invention provides one packet for a plurality of packets in the virtual output buffer.
Contention control can be performed using header information of a plurality of packets that can be transmitted within one control time slot as one control information. As a result, it is possible to suppress the average delay time per packet caused by setting a long control time slot.

Preferably, the virtual output buffer is provided with means for classifying and buffering the incoming packet according to its priority.

For example, the storing means includes means for storing the one or more packets in the control time slot in the order of priority, and the means for generating the header information includes the one or more packets stored in the control time slot. Said 1
A means for generating header information in which the sum of the packet lengths of the above packets and the average value of the priorities are recorded is provided.

Thus, the packet switch according to the present invention can arrange the header information of a plurality of packets in order from the header information of the buffer having the highest priority when creating the control information.

Alternatively, the storing means includes means for storing the one or more packets in the control time slot individually for each priority, and the means for generating the header information includes the means for storing the header information in the control time slot. Said 1
It is also possible to adopt a configuration including means for generating header information in which the sum of the packet lengths of the above packets and their priorities are recorded.

Thus, the packet switch of the present invention can create control information for each priority when aggregating header information of a plurality of packets to create control information. Therefore, a high-priority packet can be processed before a low-priority packet.

[0028] The contention control means may include the one stored in the control time slot to which packet transmission permission has already been given.
Means for detecting whether or not the total of the packet lengths of the above packets is less than the control time slot length; and, when the detection result of the detecting means is less than the control time slot length, the other packet transmission request source The sum of the sum of the packet lengths of the one or more packets accommodated in another control time slot and the sum of the packet lengths of the one or more packets accommodated in the control time slot for which packet transmission permission has already been given is the It is preferable that the apparatus further comprises means for giving packet transmission permission also to the other packet transmission request source having a control time slot length or less.

Thus, the packet switch of the present invention can receive packets from a plurality of input ports at the output port as long as the packet length can be received in one control time slot. As a result, it is possible to suppress an increase in delay caused by setting a long control time slot.

In this case, the means for temporarily storing the plurality of control time slots arriving simultaneously at one output port and the plurality of control time slots stored in the means for temporarily storing are transmitted without colliding with each other. It is preferable to provide a means for transmitting the data with a time lag provided.

Alternatively, the means for granting the packet transmission permission to the other packet transmission request source may include information indicating a transmission order of the control time slots to the plurality of packet transmission request sources to which the packet transmission permission has been granted. It is preferable that the packet transmission request source includes means for transmitting the control time slot in accordance with the transmission order.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a packet switch according to an embodiment of the present invention will be described with reference to FIGS. 1, 3, 5, 7, and 8. FIG. FIG. 1 is a block diagram of a packet switch according to the first embodiment of the present invention. FIG. 3 is a block diagram of a main part of a packet switch according to a third embodiment of the present invention. FIG. 5 is a diagram for explaining a packet transmission flow according to the third embodiment of the present invention. FIG. 7 is a diagram for explaining the addition of an aggregated header according to the fifth embodiment of the present invention. FIG. 8 is a diagram for explaining the addition of the aggregated header according to the sixth embodiment of the present invention.

According to the present invention, as shown in FIG. 1, a virtual output buffer 5-1 for temporarily storing packets arriving at the input ports 1-1 to M for each of the output ports 11-1 to N of the destination is temporarily stored. G that grants packet transmission permission to any one of a plurality of virtual output buffers 5-1-1 to MN for a packet transmission request addressed to the same output port.
This is a packet switch including the runt conflict control circuits 7-1 to N.

Here, the feature of the present invention is that G
A fixed-length control time slot, which is a control unit of the runt contention control circuits 7-1 to 7-1N, is provided. The control time slot length is set longer than the maximum length of the arriving packet. -1 to M-N are provided with virtual output buffer control circuits 6-1-1 to MN for storing one or more packets stored in the control time slot.

Virtual output buffer control circuit 6-1-1 to M
-N, the one stored in the control time slot
The header information of the control time slot is generated based on the header information of the packet.

As shown in FIG. 7, the virtual output buffer control circuits 6-1-1 to M-N store the one or more packets in the control time slot in the order of higher priority, and Generating header information in which the sum of the packet lengths of the one or more packets stored in the slot and the average value of the priorities are recorded.

As shown in FIG. 8, the virtual output buffer control circuits 6-1-1 to M-N store the one or more packets in the control time slot according to their priority, and store the packets in the control time slot. Header information in which the sum of the packet lengths of the one or more packets and the priority thereof are recorded.

As shown in FIG. 3, the grant contention control circuits 7-1 to N determine the sum of the packet lengths of the one or more packets contained in the control time slot to which the packet transmission permission has already been given, by the control time. It detects whether or not the packet length is shorter than the slot length. If the detection result is shorter than the control time slot length, the packet length of the one or more packets stored in another control time slot of another packet transmission request source is detected. Packet transmission is also performed to the other packet transmission request source in which the sum of the total sum and the total sum of the packet lengths of the one or more packets accommodated in the control time slot for which packet transmission permission has already been granted is equal to or less than the control time slot length. Give permission.

At this time, the elastic buffers 14-1 to 14-N for temporarily storing the plurality of control time slots arriving at one output port at the same time, and the plural buffers stored in the elastic buffers 14-1 to 14-N. Elastic buffer control circuits 15-1 to 15-N for transmitting the control time slots with a time difference so that they are transmitted without colliding with each other.

Alternatively, as shown in FIG.
The contention control circuits 7-1 to N send information indicating the transmission order of the control time slots to a plurality of packet transmission request sources to which packet transmission permission has been given, and a virtual output buffer of the packet transmission request source. Control circuit 6-1-1
The MN transmits the control time slot according to the transmission order. Hereinafter, embodiments of the present invention will be described in more detail.

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described. `` K.Sasayama, Y.Yamada, K.Habara, and
K.Yukimatsu, "FRONTIERNET: frequency-routing-type ti
me-division interconnection network, "IEEE J. Lightw
ave Technol., vol. 15, no. 3, pp. 417-429, March 1997, there is a packet switch having a wavelength router in the switching fabric. FIG. 1 shows a packet switch configuration using a virtual output buffer using a switch configuration using a wavelength router.

The fixed wavelength light sources 8-1-1 to M-N are light sources that assign a specific wavelength to an electric signal. Multiplexer 9-
1 to M are devices for bundling a plurality of different wavelengths into one. The wavelength router 10 is a device that outputs an input optical packet based on a wavelength. Demultiplexers 12-1 to N
Is a device for separating bundled light having a plurality of wavelengths into individual wavelengths. The light receivers 13-1-1 to NM are devices that convert an optical signal into an electric signal. The elastic buffers 14-1 to 14-N are buffers for buffering packets arriving at the output ports 11-1 to 11-N until they are transmitted to the output line.

Elastic buffer control circuit 15-1
N is a circuit for controlling transmission of packets buffered in the elastic buffers 14-1 to 14-N.

The packet arriving at the input port 1-M is
Once buffered in the FIFO buffers 2-1 to M, the FIFO buffers 2-1 to M transmit the FIFO buffers 2-1 to M to the routing information control circuit 4.
The header information of the packet is transmitted to perform routing control. The result of the routing control is transmitted to the FIFO buffer control circuits 3-1 to M, and based on the information, buffering is performed in the virtual output buffers 5-1-1 to M-N. The information of the packets in the virtual output buffers 5-1-1 to M-N is transferred from the virtual output buffer control circuits 6-1-1 to M-N to Gr.
Ant is transmitted to the contention control circuits 7-1 to N to perform contention control, and Gr is provided to the virtual output buffer control circuits 6-1-1 to M-N of the input ports 1-1 to M selected by the contention control.
Transmit the ant signal.

Here, the virtual output buffers 5-1-1 to M
When transmitting the Req signal from −N to the Grant contention control circuits 7-1 to 7-1N, contention control and switching are performed using a fixed-length unit time slot longer than the maximum packet length. The maximum packet length is, for example, Ethernet
(Registered trademark) means 1526 bytes.

The fixed wavelength light sources 8-1-1 to M-N assign fixed wavelengths corresponding to the output ports 11-1 to 11-N, and when sending out from the input ports 1-1 to M, a plurality of wavelengths are combined. Multiplexed from 9-1 to M and transmitted to the wavelength router 10.
The optical packets arriving at the wavelength-multiplexed output ports 11-1 to 11-N are demultiplexed by the demultiplexers 12-1 to M and received by the photodetector 13-1.
-1 to M-N, and converts them into electric packets, and buffers them in elastic buffers 14-1 to 14-N for adjusting the timing, thereby controlling the elastic buffer control circuit 15.
Output based on -1 to N.

Although the present embodiment has been described using an example using a wavelength router, the same applies to a case where a switching fabric described in the related art is used.

Reference: McKeown, N .; Izzard, M .; Mekkittiku
l, A.; Ellersick, W.; Horowitz, M.; "Tiny Tera: a packet
switch core "IEEE Micro Volume: 171, Jan.-Feb.1997, Pa
ge (s): 26-33 ”is shown in FIG.
As shown in (a), contention control as shown in FIG. 2 is performed using the minimum packet length as a control time slot. In the control of the literature, the algorithm is to end the control in 9 cycles. When a similar algorithm is employed in the proposed packet switch, the required operating frequencies of the processors are compared. Table 1 below shows the minimum packet length and maximum packet length of Ethernet at 10 Gbp.
s, the transfer time and the required processor operating frequency for a link speed of 40 Gbps.

[0049]

[Table 1] When the contention control method using a fixed-length unit time slot longer than the maximum packet length of the present invention is used, it is possible to configure the control circuit with a processor having an extremely low operating frequency. That is, when processors having the same operating frequency are used, it is possible to implement a more complicated contention control algorithm such as priority control.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described. As shown in FIG. 2, requests (Req.) Are sent from virtual output buffers (VOQ) on a plurality of input ports.
The Grant contention control circuit that has received the signal selects a specific port by contention control and grants a Grant.
The t signal is transmitted to the corresponding input port. In the conventional method, contention control is performed using a time slot in the unit of a cell having a minimum packet length size. Therefore, one input port is selected by one contention control.

In the method of the present invention, contention control is performed using a control time slot of a fixed length unit longer than the maximum packet length. Therefore, when there are many short packets in the transfer method of one packet in one control time slot, the output port Although the free time occurs and the delay time increases,
By allowing the output port to receive packets from a plurality of input ports in one control time slot by control, the delay time can be reduced and the switch bandwidth can be used effectively.

In the case of this switch configuration, Grant
There are two ways to transmit a signal. In the second embodiment, a signal for controlling transmission is also transmitted to an output port, a simple Grant signal is transmitted to a plurality of selected input ports 1-1 to M, and the output elastic buffer 14 is selected. This is a configuration for transmitting the order of the input ports 1-1 to M.

A second embodiment will be described with reference to FIGS. FIG. 1 shows a configuration of a switch, and FIG. 3 shows a format of a grant signal and a packet transmission flow in the configuration of FIG. In this case, the packet may arrive at the output port at the same time, and the duplexer 12-for demultiplexing the packet multiplexed by the wavelength router 10 may be used.
1 to N and light receiver 13 corresponding to each input port 1-1 to M
Elastic buffers 14-1 to 14-N for performing buffering until packets converted into electricity by -1-1-1 to NM and optical receivers 13-1-1 to NM are transmitted;
Elastic buffer control circuits 15-1 to 15-N for performing transmission control for transmitting packets from the elastic buffers 14-1 to 14-N are required.

However, the grant conflict control circuits 7-1 to 7-1
The control signal that N transmits to the virtual output buffer control circuits 6-1 to N of the input ports 1-1 to M need only have the Ack and Nack information, so the Grant signal indicates the selected input port number. You only need to have it. Also, the virtual output buffer control circuit 6-1-1 of the input ports 1-1 to M
-M-N can transmit the packets in the virtual output buffers 5-1-1 to NM as soon as the Grant signal arrives, and there is no processing of complicated information such as timing information. Output buffer control circuits 6-1-1 to M-
N can be simplified.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. FIG. 4 shows a switch configuration, and FIG. 5 shows a grant signal format and a packet transmission flow in the configuration of FIG.
In the third embodiment, the timing at which transmission should be performed to the selected input ports 1-1 to M is determined by Grant.
Transmit it on a signal.

As described above, when the Grant signal has the transmission timing information, the signal becomes complicated because it has the timing information in addition to Ack and Nack, and the virtual output buffer control circuit of the input ports 1-1 to M is provided. 6-1-1
To MN perform transmission by adjusting the timing based on the signal, the circuit becomes complicated, but the output port 11 is controlled by the virtual output buffer control circuits 6-1-1 to M-N.
Since packets arriving at −1 to N are controlled so that only one packet exists at a certain timing,
It is only necessary to arrange one photodetector 13-1-1 to NM.

(Fourth Embodiment) A fourth embodiment of the present invention will be described below. Conventionally, as shown in FIG. 6 (a), when a packet arrives, it is divided into cells by a cellizer and buffered in a virtual output buffer. Since high-speed control is required for cell-by-cell control, it is difficult to complicate the control, and a high-speed processor must be used to perform complicated control. In addition, it is necessary to assemble the cells into packets at the output, so that it is necessary to provide a packet assembling buffer. Furthermore, since a packet is divided into a plurality of cells, a new header for identification must be added to each cell, which may increase overhead.

In the method of the present invention, as shown in FIG. 6B, the arriving packet is managed in the virtual output buffer in packet units. At this time, when a plurality of packets are buffered in the virtual output buffer, header information of a plurality of packets that can be transmitted in one control time slot is aggregated, and a Req signal including the information is created. , And performs competitive control by using it.

In order to control a plurality of packets at once,
It is possible to reduce the average delay time of one packet,
It is possible to solve the problem of unnecessary overhead relating to the cell division scheme in the conventional configuration.

The virtual output buffer control circuit is Gr
Since the Req signal is transmitted to the ant contention control circuit at regular intervals, the next Rq signal is transmitted after the previous Req signal is transmitted.
The header information of the packets buffered before the transmission of the eq signal is aggregated, and the packets are collectively subjected to contention control.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described. In the fifth embodiment of the present invention, as shown in FIG. 7, the virtual output buffer has a function of managing packets for each of a plurality of priorities. FIG. 7 shows an example in which there are three priorities. Here, the time slot length is 1536b
yte. Sorting is performed when packets are buffered in a virtual output buffer. As an example of this configuration, consider the case where the virtual output buffer further has a buffer for each priority. The packet arriving at the input port is buffered in a buffer corresponding to the destination and the priority. The virtual output buffer control circuit manages information about each priority buffer. The priority buffer is buffered by FIFO.

When aggregating header information of a plurality of packets that can be transmitted in a control time slot longer than the maximum packet length, header aggregation is performed in order from the packet information of the buffer having the highest priority (FIG. 7 (a)-(c)). )). If the time slot is not filled with the packet in the higher priority buffer and the packet in the lower priority buffer can be transmitted,
The header information is aggregated so that the information of the lower priority packet comes after the higher priority packet (FIG. 7A,
(C)). Even if a packet arrives at the input port later, it can be processed earlier than a lower priority packet arriving earlier if the priority is higher. The control information collected here describes the sum total of a plurality of packet lengths and the packet length weighted average of each priority as the collected priority.

Since the FIFO buffer does not look at the priority of individual packets arriving at the input, packets that require extremely high-speed transfer and packets that allow a certain delay time are processed in the order of arrival. Although individual requests cannot be satisfied, in the configuration of the fifth embodiment, packets are rearranged in the order of priority in the order of input.
Advanced packet processing is possible.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described. As shown in FIG. 8, the virtual output buffer has a function of managing packets for each of a plurality of priorities. FIG. 8 shows an example in which there are three priorities. Here, the time slot length is 1536 bytes. Sorting is performed when packets are buffered in a virtual output buffer. As an example of this configuration, when the virtual output buffer further has a buffer for each priority, the packet arriving at the input port is buffered in a buffer corresponding to the destination and the priority. The virtual output buffer control circuit manages information about each priority buffer. The priority buffer is buffered by FIFO.

When aggregating header information of a plurality of packets that can be transmitted in a control time slot longer than the maximum packet length, the headers are aggregated in order from the packet information of the buffer with the highest priority (FIG. 8 (a)-(c)). )). At this time, control information of only information of the packets buffered in the same priority buffer is created, and even in the same virtual output buffer, packets of different priorities are created.
Does not aggregate control information. The control information is for each priority, and the aggregated priority is a specific value set by CoS.

Thus, when a plurality of input ports are selected, a low-priority packet of one input port is not output to a link before a high-priority packet of another input port. , Even under high load,
Packet processing can be strictly implemented according to the priority of each packet.

(Summary of Embodiment) In the example of FIG. 9A, a plurality of packets can be transmitted from a specific input port in one control time slot. Sent in time slots. In the example of FIG. 9B, packets can be transmitted in priority order in one control time slot for a specific input port. In the example of FIG. 9C, a packet of one priority is transmitted from a specific input port in one control time slot.

In the example of FIG. 10A, a plurality of packets can be transmitted from a specific input port to one control time slot, and one control time slot can be transmitted for packets from different input ports. Transmission is performed for the portion that can be transmitted in the slot. As a result, FIG.
In the case of, a packet that could not be transmitted without waiting for one control time slot can be transmitted,
Delay time can be reduced. The example of FIG.
As in FIG. 10A, the delay time can be reduced, and a specific input port can be transmitted while satisfying the priority. In the example of FIG. 10C, transmission satisfying the priority can be performed over a plurality of input ports, and as shown in FIG. It is possible to prevent a state in which the packet is processed before a packet having a higher priority.

FIG. 11 shows a comparison simulation between the case where the control time slot is set to be equal to or longer than the maximum packet length and the contention control process in the output buffer type packet switch. Generated packet length is fixed length 530
A simulation was performed using the byte and packet generation distributions as exponential distributions. At this time, in the method of the present invention, 15
90 bytes are time slots. The priority (High: Low) was set to (1: 9). However, the time required for the contention control time is not considered.

In the case of a packet switch that performs contention control processing in a time slot longer than the maximum packet length transfer time of the present invention, it is possible to reduce the delay time for high priority packets regardless of the load. It is shown that

[0071]

As described above, according to the present invention,
By performing the packet contention control using a fixed length unit control time slot longer than the maximum packet length, the contention control is performed using the control time slot length, and high speed can be expected. Further, since packets are not divided into cells, there is no need to have a buffer for cell assembly. Furthermore, because the configuration allows simultaneous arrival of packets from multiple input ports at a certain control timing, even if packets are not filled in the control time slot, delay time is suppressed and high throughput is realized. It is possible to

[Brief description of the drawings]

FIG. 1 is a block diagram of a packet switch according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a conflict control operation of the present invention.

FIG. 3 is a block diagram of a main part of a packet switch according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a main part of a packet switch according to a third embodiment of the present invention.

FIG. 5 is a diagram for explaining a packet transmission flow according to a third embodiment of the present invention.

FIG. 6 is a diagram illustrating a buffer process according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining the addition of an aggregated header according to a fifth embodiment of the present invention.

FIG. 8 is a diagram for explaining the addition of an aggregated header according to a sixth embodiment of the present invention.

FIG. 9 is a diagram for explaining a packet transmission flow by the packet switch of the present invention.

FIG. 10 is a diagram for explaining a packet transmission flow by the packet switch of the present invention.

FIG. 11 is a diagram showing a simulation result of a buffering delay time comparing a conventional example with the present invention.

FIG. 12 is a block diagram of a conventional packet switch.

FIG. 13 is a diagram for explaining a conventional packet switch contention control algorithm.

[Explanation of symbols]

 1-1 to M input port 2-1-1 to M-N FIFO buffer 3-1-1 to M-N FIFO buffer control circuit 4 routing information control circuit 5-1-1 to M-N virtual output buffer 6- 1-1 to MN Virtual output buffer control circuit 7-1 to N Grant competition control circuit 8-1-1 to MN Fixed wavelength light source 9-1 to M multiplexer 10 Wavelength router 11-1 to N output Ports 12-1 to N Demultiplexer 13-1-1 to NM Receiver 14-1 to N Elastic buffer 15-1 to N Elastic buffer control circuit 50-1-1 to MN Cellular device 90-1 to M Transmission control circuit 100 Switching fabric 120-1 to N cell distribution device 130-1-1 to NM Packet assembly buffer

Claims (7)

[Claims] 1. A virtual output buffer for temporarily storing a packet arriving at an input port for each output port of the destination and temporarily storing the packet in response to a packet transmission request addressed to the same output port of the plurality of virtual output buffers. A contention control means for granting packet transmission permission, wherein a fixed length control time slot is provided as a control unit of the contention control means, and the control time slot length is larger than the maximum length of the arriving packet. A packet switch comprising: means for storing one or more packets stored in the virtual output buffer in the control time slot. 2. The packet switch according to claim 1, further comprising means for generating header information of the control time slot based on header information of the one or more packets stored in the control time slot. 3. The storing means includes means for storing the one or more packets in the control time slot in the order of priority, and the means for generating header information stores the one or more packets in the control time slot. 3. The packet switch according to claim 1, further comprising means for generating header information in which a sum of packet lengths of the one or more packets and an average value of the priorities are recorded. 4. The storing means comprises means for storing the one or more packets classified according to their priority, and the means for generating the header information includes the one or more packets stored in the control time slot. 3. The packet switch according to claim 1, further comprising means for generating header information in which the sum of the packet lengths of the packets and the priority thereof are recorded. 5. The contention control means detects whether or not the sum of the packet lengths of the one or more packets stored in the control time slot to which packet transmission permission has already been given is less than the control time slot length. And when the detection result of the detecting means is shorter than the control time slot length, the sum of the packet lengths of the one or more packets contained in the other control time slot of the other packet transmission request source and the packet already transmitted Means for granting packet transmission permission to the other packet transmission request source whose sum with the sum of the packet lengths of the one or more packets accommodated in the control time slot to which transmission permission is granted is equal to or less than the control time slot length. The packet switch according to claim 1, comprising: 6. A means for temporarily storing a plurality of control time slots arriving at one output port at the same time, and the plurality of control time slots stored in the temporarily storing means are transmitted without colliding with each other. 6. A packet switch according to claim 5, further comprising means for transmitting the packet with a time difference. 7. The means for granting a packet transmission permission to the other packet transmission request source also includes information indicating a transmission order of the plurality of control time slots to a plurality of packet transmission request sources to which the packet transmission permission has been granted. 6. A transmitting means, comprising: means for transmitting the control time slot according to the transmission order.
The packet switch as described.