JP2002026766A - Sliding correlator for spread spectrum communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sliding correlator for spread spectrum communication that outputs a correlation value of multi-channel analog signals subjected to spread spectrum processing and with a reduced circuit scale. SOLUTION: The sliding correlator for spread spectrum communication is provided with a PN code selector 16, that selects inverse spread codes at a speed higher than the speed of digital conversion by an analog/digital converter 11 and provides an output to a multiplier and an accumulation selector 17, that selects an accumulation of multiplication results stored in delay circuits 15A, B by the types of the inverse spread codes at a speed higher than the speed of digital conversion by the analog/digital converter 11 and provides the output to an adder 14 and can provide the output of a multi-channel correlation value with reduced circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a sliding correlator for spread spectrum communication used in a receiver of a spread spectrum communication system, and more particularly to a sliding correlator for spread spectrum communication capable of reducing a circuit scale.

[0002]

2. Description of the Related Art Mobile communication or wireless LAN (Local Area)
In the spread spectrum communication system used for the network, etc., when performing wireless transmission, the transmitter performs two-stage modulation of transmission data on a narrow band modulation (primary modulation) and a spread modulation (secondary modulation). ing. For this reason, when receiving data transmitted by radio, the receiver first performs despreading to return to the primary modulation state, and then reproduces the baseband signal using the detection circuit. That is, the receiver is configured to demodulate the received data in accordance with the two-stage modulation in the transmitter.

[0003] In a spread spectrum communication system receiver,
A correlation circuit for spread spectrum communication that outputs a correlation value for demodulating received data is used. This circuit includes a despreading circuit that performs despreading and correlation output on received data, and a despreading circuit. It comprises a demodulation circuit of a code division multiplex modulation wave for demodulating based on the output result.

[0004] As a despreading circuit of a correlation circuit for spread spectrum communication, a sliding correlator (hereinafter referred to as S) constituted by a logic circuit is used to acquire synchronization of received data and obtain a correlation with a detected synchronization phase.
C) has been conventionally used.

[0005] The SC uses a code sequence used on the transmission side as 1
The received data is despread by shifting the data on a chip-by-chip basis, and the correlation with the code sequence on the receiving side is obtained. In the SC, the correlation value of the received data can be obtained by despreading the received data for the number of chips corresponding to the code sequence length.

The configuration and operation of a conventional spread spectrum communication system SC will be described with reference to FIG. FIG.
FIG. 1 is a configuration block diagram of a conventional spread spectrum communication SC. The SC in FIG. 6 is a code division multiplex (Code Divisio).
n Multiple Access (hereinafter, referred to as CDMA) is used to determine the correlation of modulated received data.

A conventional SC for spread spectrum communication is A
It comprises a / D converter 61, a multiplier 62, a PN code register 63, an adder 64, and a delay circuit 65. Since the correlation value needs to be reset each time the processing of the received data for one symbol is completed, an F / F (Flip Flop) or a register having a reset function is used for the delay circuit 65.

Next, a conventional SC for spread spectrum communication will be described.
Will be described with reference to FIG. C from transmitter
The analog signal that has been DMA-modulated and transmitted is received by an antenna (not shown) of the receiver, and then input to the A / D converter 61 to be converted into digital reception data. Here, the chip rate of the analog signal is 4 Mcps, and the digital conversion in the A / D converter 61 is 16 Mb, which is usually four times that of digital conversion due to oversampling.
In ps, multiple bits are output per sample.

The received data converted into a digital signal by the A / D converter 61 is output to a multiplier 62 one sample at a time, and the multiplier 62 stores a PN (Pseudo Random Noise) code code stored in a PN code register 63. , Ie, despreading. The PN code is the same as that used for CDMA modulation at the transmitter. The multiplier 62 is 16 Mbp, like the A / D converter 61.
multiplies at a rate of 4 s or chip rate,
The PN code register 63 also outputs the PN code at 16 Mbps to the multiplier 62 one bit at a time.

The result of the multiplication by the multiplier 62 is sequentially
Is output to The adder 64 adds the accumulated result and the multiplication result stored in the delay circuit 65, outputs a new accumulated result as a correlation output, and outputs
Also output to The delay circuit 65 stores the input cumulative addition result.

When the integration by the cumulative addition of the multiplication results for one symbol is completed, the integrated value is output from the adder 64 as a correlation output. In the SC of FIG. 6, the output result of the adder 64 is stored in the delay circuit 65.
A similar result can be obtained even if the correlation value is output from the delay circuit 65. When the correlation value for one symbol is output, the delay circuit 65 resets the stored cumulative addition result in preparation for the correlation output of the next symbol. Also here, the adder 64 and the delay circuit 65 correspond to the A / D converter 61 and have a speed of 16 Mbps or 4 Mbps.
The cumulative addition and the input and output of the cumulative addition result are performed at the speed of.

The demodulation is further performed in a CDMA demodulation circuit (not shown) based on the correlation output output from the adder 64 in units of one symbol. The above is the operation of the conventional spread spectrum communication SC.

In CDMA communication, quadrature modulation is sometimes used as secondary modulation. The conventional SC for spread spectrum communication described above can also be applied to a complex SC that performs correlation output on orthogonally modulated received data.

A method of demodulating quadrature-modulated received data will be described below. The quadrature-modulated received data can be classified into an in-phase component and a quadrature component, respectively. Here, assuming that the in-phase component is R _I , the quadrature component is R _q , the in-phase component of the spreading code is C _I , and the quadrature component is C _q , the demodulated signal D obtained by despreading is D = (R _I + jR _q ). (C _I -jC _q ) = (R _I * C _I + R _q * C _q ) + j (−R _I * C _q + R _q * C _I ) (1) From equation (1), the in-phase component D _I and the quadrature component D _q of the demodulated signal are respectively D _I = R _I * C _I + R _q * C _q (2) D _q = −R _I * C _q + R _q * C _I (3) is represented. The purpose of the complex SC is to perform cumulative addition on D _I and D _{q in the} equations (2) and (3) and output correlation values for both components.

FIG. 7 is a block diagram showing the configuration of a complex SC for realizing the above-described method of demodulating received data. In the complex type SC of FIG. 7, the CDMA modulated analog signal received by the antenna (not shown) of the receiver is classified into an in-phase component and a quadrature component, and A / D converters 71A and 71A, respectively.
B. The in-phase and quadrature components of the spreading code are stored in a PN code register I73A and a PN code register Q73B, respectively.

In the complex type SC shown in FIG. 7, the digital received data and the spread code output from the A / D converter and the PN code register are registered in a register 75A for aligning the phases.
After being stored in .about.75D, it is input to the correlation operation unit 77. In the correlation operation unit 77, the digital reception data and the spread code are calculated by the multipliers 72A to 72D and the adders 74A to 74B according to the derivation formulas (2) and (3) of the demodulated signal of each component. The correlation value for one symbol of the in-phase component and the quadrature component is calculated by the unit 78 and output as the correlation output I and the correlation output Q.

In the complex type SC shown in FIG. 7, the CDMA modulated analog signal is transmitted at a chip rate of 4 Mbps, and each element of the complex type SC operates at a 16 Mbps speed by inputting a 16 Mbps clock.

FIG. 8 shows the complex type SC of FIG. 7 having a phase correction function. Conventionally, a method of detecting the head position of a symbol of received data using a matched filter and adjusting the timing of generating a spreading code has been used as the phase correction. Since a change also occurs, the synchronization may be lost and a correlation output with a desired accuracy may not be obtained. The complex type SC in FIG. 8 is characterized in that the demodulation phase is adjusted by detecting the optimum phase from the correlation output result. Further, the SC has an extremely small circuit scale of 1/100 to 1/1000 as compared with the matched filter, and thus is often used for the correlation output of the CDMA modulation.

The description related to the conventional SC and the matched filter is disclosed in Japanese Patent Application Laid-Open No. 9-20 / 07/1997.
No. 0179, "Multi-user demodulation method and apparatus" (applicant: Kokusai Electric Co., Ltd., Takayama Co., Ltd., inventor: Kenzo Urabe et al.) And the like.

In the complex type SC shown in FIG. 8, PN codes from the PN code register I83A and the PN code register Q83B are used.
The phases of the code codes are shifted at sample intervals, and the PN code codes at the respective timings are registered in register rows 85C to 85C.
E, input to 85F to 85H. Complex SC of FIG.
In this example, three registers are connected to each register row, and the PN code is shifted to the right register at every clock, and the PN code corresponding to the three timing shifts is output. it can.

The PN code input to the register row at each sample interval is converted into three complex SC87s together with the reception data digitally converted by the A / D converters 81A and 81B.
A to 87C. Complex type SC87A ~
87C has the same configuration as the complex SC77 in FIG.
Three types of timing shifts (EEAR in the figure respectively)
(Corresponding to Y, MAIN, and LATE) are output.

The complex type SC of FIG. 8 is also similar to FIG.
The modulated analog signal is transmitted at a chip rate of 4 Mbps, and each element of the complex SC has 16 Mbps or 4 Mbps.
When the s clock is input, the device operates at a speed of 16 Mbps or 4 Mbps.

The PN code code is output at different timings by the complex type SC shown in FIG. 8 and a correlation output corresponding to the PN code is output. By detecting the optimum timing from the result of the correlation output, the phase shift is confirmed. be able to.
Also, by feeding back the timing detection result to a PN code register or the like, it is possible to perform demodulation processing in an optimal state in synchronization with the CDMA modulated analog signal.

[0024]

However, the conventional spread spectrum communication SC requires a number of SC circuits corresponding to the number of channels to be demodulated, so that the circuit scale in the receiver is increased. In particular, with the rapid increase in the use of mobile communication in recent years, there is a demand for a receiver for spread spectrum communication that can demodulate received data of many channels and can be developed at low cost.

For example, a base station is one of the devices that require signal reception and decoding of many channels. A general base station handles radio signals transmitted on four carriers, and 32 users are assigned per carrier, that is, 32 channels are allocated, so that a total of 128 channels can be demodulated.

In order to simply perform the above-described correlation processing for all channels at the time of transmission and reception, it is assumed that the number of antennas is 2 and at least three delayed wave components are taken.
Processing must be performed on 8 × 2 × 3 = 768 signals. For this reason, in the conventional method of preparing an SC circuit for each signal to be processed, the circuit size of the base station increases, and as a result, the development cost increases.

As an example of a conventional receiver for spread spectrum communication capable of reducing the circuit scale, March 26, 1996
Japanese Patent Application Laid-Open No. Hei 8-84098, "Spread Spectrum Communication Device" (Applicant: Canon Inc., Inventor: Ichiro Kato), Japanese Patent Application Laid-Open No. 11-30, November 5, 1999
No. 8149 “four-phase correlator” (applicant: Mitsubishi Electric Corporation, inventor: Kazuaki Ishioka et al.).

However, even in a conventional receiver for spread spectrum communication, an SC for demodulating received data of one channel is used.
The circuit scale of the circuit has been reduced, and a considerable number of SCs are required to demodulate received data of multiple channels as in the past.
Since a circuit is required, a fundamental solution for reducing the circuit scale has not been reached.

The present invention has been made in view of the above circumstances, and has as its object to provide a sliding correlator for spread spectrum communication that can cope with multi-channel received data and reduce the circuit scale.

[0030]

According to the present invention, there is provided a sliding correlator for spread spectrum communication in which a received analog signal spread spectrum by a plurality of types of spread signals has a fixed sample rate. To multiply the digital received signal with the despread signal corresponding to each spread signal in a time-division manner according to the type of the despread signal, and time-divide the cumulative addition of the multiplication result into the spread signal type. And outputs the accumulated addition result as a correlation output in the type of the despread signal. Since the correlation value for the multi-channel received signal can be output by one SC, the circuit scale is reduced and the development cost is reduced. Is what you can do.

[0031]

Embodiments of the present invention will be described with reference to the drawings. Note that the function realizing means described below may be any circuit or device as long as the function can be realized, and some or all of the functions may be realized by software. is there. Further, the function realizing means may be realized by a plurality of circuits, or the plurality of function realizing means may be realized by a single circuit.

The sliding correlator for spread spectrum communication according to the embodiment of the present invention switches a plurality of PN code codes at a speed higher than the digital conversion speed of the A / D converter to perform multiplication with received data, and performs the multiplication result. Is switched at a speed higher than the digital conversion speed of the A / D converter for each PN code code, and the result of the cumulative addition for one symbol is output as a correlation value. Costs can be reduced. The despreading code sequence storage means in the claims corresponds to the PN code register in the figure, and the delay register corresponds to a delay circuit.

The configuration of the SC for spread spectrum communication according to the embodiment of the present invention will be described with reference to FIG. Figure 1
FIG. 1 is a configuration block diagram of an SC for spread spectrum communication according to an embodiment of the present invention. The SC for spread spectrum communication according to the embodiment of the present invention includes an A / D converter 11.
, A multiplier 12, and PN code registers 13A and 13
B, adder 14, delay circuits 15A and 15B, P
It comprises an N code selector 16 and a cumulative addition selector 17.

The A / D converter 11 converts a CDMA modulated analog signal received by an antenna (not shown) into a digital signal and outputs the digital signal to the multiplier 12 as received data. A / D
The converter 11 performs digital conversion at a speed of 16 Mbps.

The multiplier 12 multiplies the received data digitally converted by the A / D converter 11 with the PN code output from the PN code register 13A or 13B via the PN code selector 16 by 1 bit. Then, the multiplication result is output to the adder 14. The multiplier 12 performs multiplication at a rate of 32 Mbps, which is twice the digital conversion of the A / D converter 11, or 8 Mbps, which is twice the chip rate.

The PN code registers 13A and 13B are:
The PN code selector, which is a spreading code used in the CDMA modulation at the transmitter, is transmitted one bit at a time.
Output to Also, the PN code registers 13A and 13B
Store different PN code codes. In other words, the PN code registers 13A and 13B store despread codes corresponding to two different channels. Here, the PN code registers 13A and 13B have
A code generator may be used.

The adder 14 outputs the multiplication result output from the multiplier 12 and the delay circuit 15 via the accumulative addition selector 17.
Addition is performed with the cumulative addition result output from A or 15B, which is the cumulative addition of the previous multiplication results, and the new cumulative addition result is output to the delay circuits 15A and 15B.

The adder 14 outputs the cumulative addition of the received data for one symbol to a CDMA demodulation circuit (not shown) as a correlation output in addition to the delay circuit 15A or 15B. The adder 14 is also 32 Mbps similarly to the multiplier 12.
Addition is performed at the speed. Further, the adder 14 can add the number of bits necessary for performing the cumulative addition for one symbol.

The delay circuits 15A and 15B are
Is stored at a predetermined timing. Since it is necessary to reset the correlation value each time the accumulation of one symbol is completed, the delay circuits 15A and 15A
An F / F or register having a reset function is used for 5B.

The PN code selector 16 selects one of the PN code codes output from the PN code register 13A or 13B and sets the selected PN code code to 1
The data is output to the multiplier 12 bit by bit. The PN code selector 16 selects and outputs a PN code at a speed of 32 Mbps or 8 Mbps.

The accumulative addition selector 17 includes a delay circuit 15A
Or 15B, and outputs the cumulative addition result stored in the selected delay circuit to the adder 14. The cumulative addition selector 17 selects a delay circuit and outputs the result of the cumulative addition at a speed of 32 Mbps.

Next, the S for spread spectrum communication of the present invention
The operation of C will be described with reference to FIG. C from transmitter
The analog signal that has been DMA-modulated and transmitted is received by an antenna of the receiver, and then input to the A / D converter 11, where it is converted into digital received data at a rate of 16 Mbps. In the SC for spread spectrum communication according to the embodiment of the present invention, analog signals are transmitted at a chip rate of 4 Mcps.

The received data converted into a digital signal by the A / D converter 11 is output to the multiplier 12 bit by bit. Further, the PN code selector 16 operates at a speed of 32 Mbps or 8 Mbps at the PN code register 13A or 13P.
The PN code output from B (hereinafter referred to as PN code A and PN code B) are alternately selected and output to the multiplier 12 bit by bit. The multiplier 12 multiplies the received data and the PN code by 1 bit, and outputs the multiplication result to the adder 14.

As described above, the PN code selector 16 is 32 Mbps or 8 Mbps, that is, the A / D converter 1
The selection and output of the PN code are performed at twice the speed of the digital conversion or twice the chip rate. In other words, the PN code selector 16 alternately outputs the PN code code A or the PN code code B to the multiplier 12 while the A / D converter 11 digitally converts and outputs the 1-bit received data. . The multiplier 12 is also 32 Mbps
Alternatively, since the multiplication is performed at a speed of 8 Mbps, the SC for spread spectrum communication according to the present invention has two different PNs.
Correlation values based on code codes can be obtained alternately. Therefore, in the SC for spread spectrum communication of the present invention, it is possible to obtain a correlation output of the received data for two channels.

The result of multiplication of the received data and the PN code in the multiplier 12 is output to the adder 14. When there is no cumulative addition result in the delay circuits 15A and 15B, the adder 14 outputs the input multiplication result as it is as the cumulative addition result. The delay circuit 15A or 15B
Are stored according to the PN code code at a predetermined timing. That is,
Since the cumulative addition result based on the PN code code A or the PN code code B is alternately stored in the delay circuit 15A or 15B, the cumulative addition result can be stored for each PN code code. In the SC for spread spectrum communication of the present invention, the delay circuit 15A stores the cumulative addition result based on the PN code code A, and the delay circuit 15B stores the cumulative addition result based on the PN code code B.

The cumulative addition selector 17 has a capacity of 32 Mbp.
delay circuit 15A or 15B at a speed of 8 s or 8 Mbps
Are alternately selected and output to the adder 14. Further, a correlation output may be output from the cumulative addition selector 17. The cumulative addition selector 17 selects the cumulative addition result so that the adder 14 performs addition with the multiplication result based on the same PN code. Therefore, the adder 14 adds the cumulative addition result based on the same PN code and the multiplication result in the multiplier 12, and uses the result as the cumulative addition result.
5A and 15B and a correlation output.

The adder 14 outputs the cumulative addition result to the CDMA demodulation circuit as a correlation output over one symbol of the received data. In the CDMA demodulation circuit, the baseband signal is reproduced based on the correlation output, and the received data corresponding to the primary modulation of the transmitter is demodulated. 1 of received data
When the cumulative addition for the symbol is completed, the delay circuits 15A and 15B reset the stored cumulative addition result,
The correlation output for the next symbol is made ready. The above is the SC for spread spectrum communication according to the embodiment of the present invention.
Operation.

In the SC for spread spectrum communication of the present invention, the result of the cumulative addition in the adder
A and 15B are also stored, so that when the cumulative addition for one symbol of the received data is completed, the cumulative addition selector 17 selects the cumulative addition result from the delay circuit 15A or 15B and outputs the result as a correlation output to the CDMA demodulation circuit. May be output.

According to the SC for spread spectrum communication of the embodiment of the present invention, the PN code code is switched faster than the digital conversion of the received data, the multiplication with the received data is performed in a time division manner, and the digital conversion of the received data is performed. By switching the accumulative addition of the multiplication result at higher speed, correlation output of a plurality of channels can be performed by one SC circuit, and the SC circuit scale can be reduced. Furthermore, SC
Since the circuit scale can be reduced, it is possible to reduce the circuit scale of the entire spread spectrum communication receiver using the SC circuit, thereby reducing development costs.

The SC for spread spectrum communication according to the embodiment of the present invention includes two PN code registers for storing different PN code codes, and includes a multiplier 12, an adder 14, a PN code selector 16, and a cumulative adder. The selector 17 operates at twice the speed of the digital conversion of the A / D converter 11. Therefore, correlation output of the received data for two channels can be performed, so that one conventional SC circuit can be saved.

Particularly, in the configuration of the SC circuit, since the cumulative addition of the result of multiplication with the despreading code is performed in units of several to several tens of bits,
Adders make up the majority of the circuit. According to the present invention, a correlation output of received data of a plurality of channels can be obtained without increasing the number or scale of the adders, so that the SC circuit scale can be significantly reduced as compared with the related art.

According to the SC for spread spectrum communication of the embodiment of the present invention, the multiplier 12, the adder 14, the PN
If the operation speeds of the code selector 16 and the accumulative addition selector 17 are n times as fast as the digital conversion of the A / D converter 11 (n is a natural number), one SC circuit in FIG. It can be performed. in this case,
In addition to increasing the operation speed of these elements by n times, it can be realized by providing n PN code registers and delay circuits, and the number of adders occupying most of the SC circuit remains the same as the conventional one. Thus, there is an effect that the circuit scale of the receiver for spread spectrum communication using the SC circuit can be further reduced.

The SC circuit is often realized by an integrated circuit such as an LSI.
Since the calculation at 0 Mbps is realized, the correlation output of about several channels can be easily performed. Further, in the SC for spread spectrum communication of the present invention, the number of channels capable of performing a correlation output may be adjusted in accordance with the performance of an element such as a multiplier or an adder.

FIG. 2 is a block diagram showing a configuration of a spread spectrum communication SC according to a second embodiment of the present invention. Hereinafter, the configuration and operation of the SC for spread spectrum communication of FIG. 2 will be described focusing on the differences from the SC for spread spectrum communication of FIG.

The SC for spread spectrum communication of FIG.
In the same manner as described above, correlation output of received data of two channels is performed. In the spread spectrum communication SC of FIG. 2, delay circuits 25A and 25B are connected in series. The cumulative addition result output from the adder 24 is first stored in the delay circuit 25A. Further, when a new cumulative addition result is output from the adder 24, the cumulative addition result stored in the delay circuit 25A is shifted to the delay circuit 25B, and the new cumulative addition result is stored in the delay circuit 25A.

As a result of shifting the cumulative addition result from delay circuit 25A, the cumulative addition result stored in delay circuit 25B is output to adder 24. As in the case of the spread spectrum communication SC in FIG. 1, the multiplication result of the multiplier 22 based on the PN code stored in the PN code register 23A or 23B is alternately input to the adder 24.
In the adder 24, cumulative addition based on each PN code is performed alternately.

The operation and operating speed of each element in FIG. 2 are the same as those of the element corresponding to the SC for spread spectrum communication in FIG. Further, the cumulative addition result for one symbol of the received data may be output from the delay circuit 25A or 25B as a correlation output to a CDMA demodulation circuit (not shown).

According to the SC for spread spectrum communication according to the second embodiment of the present invention, the delay circuits 25A and 25B are connected in series, and the accumulated addition result is shifted and stored to output to the adder. There is no need to select the cumulative addition result. Therefore, the S for spread spectrum communication shown in FIG.
Since it is not necessary to provide the accumulative addition selector 17 in C, there is an effect that the circuit scale and the development cost can be further reduced. Also in the spread spectrum communication SC of FIG. 2, the number of channels that can be correlated can be increased by the same method as in FIG. At this time, all the delay circuits need to be connected in series.

[0059]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of a complex SC which is a specific embodiment of the SC for spread spectrum communication according to the present invention will be described with reference to FIG. FIG. 3 shows the SC for spread spectrum communication of the present invention.
FIG. 3 is a configuration block diagram of a complex SC which is a specific embodiment of the present invention. A complex SC according to a specific embodiment of the present invention includes A / D converters 31A and 31B and a PN code register I33A.
, PN code register Q33B, and F / Fs 35A to 3
5D and a correlation operation unit 37.

The A / D converters 31A and 31B convert the CDMA quadrature modulated analog signal received by an antenna (not shown) into digital data and output it as received data. Among these, the A / D converter 31A performs digital conversion of the in-phase component of the analog signal, and outputs the result to the F / F 35A.
The / D converter 31B performs digital conversion of the orthogonal component of the analog signal, and outputs the result to the F / F 35B. The A / D converters 31A and 31B perform digital conversion at a speed of 16 Mbps.

The PN code register I33A stores a PN code I, which is a spreading code used for CDMA modulation of an in-phase component of an analog signal in the transmitter.
The N code I is output to the F / F 35C bit by bit. The PN code register Q33B stores a PN code code Q, which is a spreading code used in CDMA modulation of an orthogonal component of an analog signal in the transmitter, and outputs the PN code code Q to the F / F 35D bit by bit. I do. Each of the PN code register I33A and the PN code register Q33B outputs a PN code at a speed of 16 Mbps. Further, a code generator may be used for the PN code register I33A and the PN code register Q33B.

Each of the F / Fs 35A to 35D stores the received data digitally converted by each A / D converter or the PN code output from each PN code register one bit at a time. 37. A clock frequency of 16 Mbps is input to each F / F, and data input / output is performed in synchronization with this frequency.

FIG. 3 shows the configuration of the correlation operation section 37.
This will be described with reference to FIG. The correlation operation unit 37 includes multipliers 32A to 32A.
32D, adders 34A and 34B, and selector 36
And an accumulator 38. The accumulator 38 includes an adder 34C and F / Fs 35E to 35H.

The multipliers 32A to 32D are provided with F / Fs 35A to
The multiplication of the received data output from 35D and the PN code is performed. The adders 34A and 34B add the multiplication results of the respective multipliers. The multiplication results of the multipliers 32A and 32B are output to the adder 34A, and the multiplication results of the multipliers 32C and 32D are output to the adder 34B, where the addition is performed.
Each of the multipliers 32A to 32D and the adder 34B has 16
The calculation is performed at a speed of Mbps.

The selector 36 is provided with an adder 34A or 34B
Are alternately selected and output to the accumulator. A clock frequency of 32 Mbps or 8 Mbps is input to the selector 36, and the addition result is selected and output in synchronization with this frequency.

The accumulator 38 accumulates the demodulated signal of the received data of the in-phase component or the quadrature component output from the selector 36 for one symbol and outputs it as a correlation output to a CDMA demodulation circuit (not shown).

In the cumulative adder 38, an adder 34C performs addition of the cumulative addition result of the in-phase component or the quadrature component and the newly input demodulated signal, and outputs the addition result to the F / F 35F as a new cumulative addition result. I do. F / F35E-3
Of 5H, F / Fs 35F and 35H store the cumulative addition result of adder 34C. The F / Fs 35F and 35H are connected in series, and are sequentially shifted when the accumulated addition result is stored, and perform the same operation as the delay circuits 25A and 25B in the spread spectrum communication SC of FIG.

In the F / F 35F, when the cumulative addition of the in-phase component or the quadrature component demodulated signal is completed for one symbol, the stored cumulative addition result is output to the F / F 35G. Also F
/ F35E stores the correlation value output from the selector 36 and outputs it to the adder 34C in synchronization with the clock frequency.
The F / F 35G stores the cumulative addition result output from the F / F 35F, and outputs the result as a correlation output to the CDMA demodulation circuit in synchronization with the clock frequency.

In the accumulator 38, each F / F has 3
A clock frequency of 2 Mbps or 8 Mbps is input and operates in synchronization with this frequency. Also, F / F
When the cumulative addition of the correlation values for one symbol of the in-phase component or the quadrature component is completed, the stored cumulative addition results are reset.

Next, a complex type SC according to a specific embodiment of the present invention will be described.
Will be described with reference to FIG. C from transmitter
The analog signal transmitted by the DMA quadrature modulation is received by an antenna (not shown) of the receiver and separated into an in-phase component and a quadrature component. Here, the analog signal is 4
It is transmitted at a chip rate of Mcps. The in-phase component of the analog signal is supplied to the A / D converter 31A, and the quadrature component is supplied to the A / D converter 31A.
The data is input to the D converter 31B and converted into digital received data at a rate of 16 Mbps. The received data output from the A / D converter 31A or 31B is stored in the F / F 35A or 35B bit by bit, and output to the correlation calculator 37 in synchronization with the clock frequency.

The PN code registers I33A and P33
The PN code codes of the in-phase component and the quadrature component stored in the N code register Q33B are 16 Mbp one bit at a time.
It is output at the speed of s and stored in the F / Fs 35C and 35D, respectively. P stored in F / F 35C and 35D
The N code is output to the correlation calculator 37 in synchronization with the clock frequency.

The received data and the PN code output from the F / Fs 35A to 35D are input to multipliers 32A to 32D in the correlation operation section 37, respectively, where they are multiplied. The multiplication results of the multipliers 32A and 32B are added by an adder 34A, and the multiplication results of the multipliers 32C and 32D are added by an adder 34B. With the configurations of the multiplier and the adder of the correlation operation unit 37, the above-described equations (2) and (3) for deriving the demodulated signal for the orthogonal modulation can be realized. That is, the adder 34A can obtain the demodulated signal of the in-phase component, and the adder 34B can obtain the demodulated signal of the quadrature component.

The selector 36 includes adders 34A and 34B
Alternately select the demodulated signal output at
Output to Selector 36 is 32 Mbps or 8 Mbps
Since the operation is performed at the speed of s, demodulated signals of the in-phase component and the quadrature component can be completely captured and output to the accumulator 38.

The demodulated signal output from the selector 36 is
In the accumulator 38, the data is first stored in the F / F 35E. The demodulated signal stored in the F / F 35E is 32 Mbp
The clock is output to the adder 34C in synchronization with the clock frequency of s. In the adder 34C, the demodulated signal output from the F / F 35E is added to the cumulative addition result stored in the F / F 35H, and the new cumulative addition result is added to the F / F 35F.
Is stored in At the same time, the cumulative addition result stored in the F / F 35F is shifted to the F / F 35H, and the cumulative addition result stored in the F / F 35H is shifted to the adder 34C. The demodulated signal of the in-phase component and the quadrature component is alternately output from the selector 36, and the accumulated addition result of each component is stored in the F / Fs 35F and 35H.
4C can alternately perform the cumulative addition of the correlation values of the respective components.

From the F / F 35F, the cumulative addition result of the demodulated signal for one symbol in each component is used as the correlation output as a correlation output.
/ F35G and output to the CDMA demodulation circuit in synchronization with the clock frequency of 32 Mbps or 8 Mbps. After outputting the correlation output, F / F 35F and 35
H resets the stored cumulative addition result to a state where a new cumulative addition result can be stored.

According to the complex SC according to the specific embodiment of the present invention, the in-phase component and the quadrature component of the A / D converter are twice as fast as the digital conversion or twice as fast as the chip rate in the correlation operation unit. A selector for selecting a demodulated signal and outputting the selected signal to the accumulator is provided. In the accumulator, the operation speed of each element is set to twice the digital conversion of the A / D converter or twice the chip rate, and the accumulation of both components is performed. Provision of the register row for storing the addition result has an effect of reducing the SC circuit scale as compared with the conventional case. Further, since the scale of the SC circuit can be reduced, the overall circuit scale of the receiver for spread spectrum communication using the complex SC circuit can be reduced, and the development cost can be reduced.

In particular, in the conventional complex SC shown in FIG. 7, a circuit group for performing the cumulative addition for each component and storing the result is necessary. In the embodiment of the present invention, this circuit group is used. Only one. In the SC circuit, since the adder performing the cumulative addition occupies most of the circuit scale, the complex type SC according to the embodiment of the present invention can reduce the number of the adders in the cumulative adder.
Has the effect of reducing the circuit scale of the entire receiver for spread spectrum communication using quadrature modulation and reducing the development cost.

FIG. 4 is a block diagram showing the configuration of a second complex SC according to a specific embodiment of the present invention. Hereinafter, the configuration and operation of the second complex type SC according to the specific embodiment of the present invention will be described.
The following description focuses on the differences from the complex SC shown in FIG.

In the complex type SC shown in FIG.
A selector 46A for alternately selecting and outputting the received data of the in-phase component or the quadrature component output from 5B to the multiplier 42A or 42B of the correlation operation unit 47, and an F / F 45C,
A selector 46B for alternately selecting and outputting the PN code code of the in-phase component or the quadrature component output from 5D to the multiplier 42A or 42B of the correlation operation unit 47 is provided.

That is, the selector 46A is connected to the F / F 45A
The received data of the in-phase component output from the
After outputting the quadrature component received data output from the F / F 45B to the multiplier 42B, the in-phase component received data is output to the multiplier 42B and the quadrature component received data to the multiplier 42A at the next timing. Switch as follows. The selector 46B performs the same operation. Selectors 46A and 46B
Receives a 32 Mbps clock frequency, and selects and outputs a data output destination in synchronization with this frequency.

The correlation operation unit 47 includes a minus multiplier 42C and a selector 46C. The minus multiplier 42C inverts the sign of the multiplication result of the multiplier 42B,
Output to the selector 46C. In addition, the selector 46C
One of the multiplication results of the multiplier 42B and the minus multiplier 42C is selected and output to the adder 44A. In the formula (3) for deriving the demodulated signal of the orthogonal component, since there is a term with a negative sign, the output of the minus multiplier 42C is selected by the selector 46C when outputting the demodulated signal of the received data of the orthogonal component. There is a need.

The adder 44A adds the multiplication result of the multiplier 42A and the output result from the selector 46C, calculates the correlation value of each component, and outputs the correlation value to the accumulator 48. In the correlation operation unit 47, the multipliers 42A and 42B, the minus multiplier 42C, the selector 46C, and the adder 44A all operate at a speed of 32 Mbps or 8 Mbps.

With the configuration and operation of the correlation calculator 47, the equations (2) and (3) for deriving the demodulated signal of the orthogonally-modulated received data can be realized. Further, since the received data and PN code of each component output to the multipliers 42A and 42B are switched at 32 Mbps or 8 Mbps, the adder 44A converts the correlation value of each component to 32M.
It can output alternately at bps or 8 Mbps. The operation of the other elements in the complex SC of FIG. 4 is the same as that of the complex SC of FIG.

The second complex SC according to a specific embodiment of the present invention
According to FIG. 3, the selectors 46A and 46B are provided to switch the output destinations of the received data and the PN code of each component, so that the number of multipliers and adders of the correlation operation unit can be reduced. There is an effect that the SC circuit scale can be further reduced as compared with the complex SC.

FIG. 5 is a block diagram showing the configuration of a complex SC corresponding to a phase correction function, which is a specific embodiment of the present invention. Hereinafter, the configuration of the complex SC corresponding to the phase correction function according to the specific embodiment of the present invention will be described focusing on differences from the complex SC of FIG.

The F / Fs 55C to 55E store the PN code of the in-phase component output from the PN code register I53A, and shift them in synchronization with the clock. F / F55
C to 55E (hereinafter referred to as an in-phase code register string) are connected in series. The F / Fs 55F to 55H store the orthogonal component PN code output from the PN code register Q53A, and shift them in synchronization with the clock. F /
F55C to 55E (hereinafter referred to as orthogonal code register string)
Are connected in series. Each of the F / Fs included in the in-phase code register row and the orthogonal code register row has 16 Mb.
A clock frequency of ps is input, and data is shifted and stored in synchronization with this frequency.

The selector 56A selects the PN code stored in each F / F of the in-phase code register row, and outputs it to the correlation calculator 57. The selector 56B selects a PN code stored in each F / F of the orthogonal code register row, and outputs the selected PN code to the correlation calculator 57. Selector 5
A clock frequency of 48 Mbps, which is three times the digital conversion speed of the A / D converters 51A and 51B, is input to 6A and 56B, and a PN code is selected and output in synchronization with the frequency.

In the correlation operation unit 57, the multipliers 52A and 52B and the adder 54A realize the equation (2) for deriving the demodulated signal of the in-phase component. Similarly, multipliers 52C and 52D,
The adder 54B realizes the equation (3) for deriving the demodulated signal of the orthogonal component. Each element operates at a rate of 48 Mbps.

In the cumulative adder 58, the cumulative addition of the demodulated signals of the in-phase components is performed by the adder 54C and the F / Fs 55I to 55I-5.
Performed using 5M. F / F55J, 55L and 55
M is a register for storing the cumulative addition result at each timing, and is connected in series. At each timing, the cumulative addition for one symbol is output from the F / F 55K via the F / F 55J as the correlation output I of the in-phase component. Similarly, the cumulative addition of the demodulated signals of the orthogonal components is performed using the adder 54D and the F / Fs 55N to 55R.
F / Fs 55O, 55Q and 55R are registers for storing the cumulative addition result at each timing, and are connected in series. At each timing, the cumulative addition for one symbol is output from the F / F 55P via the F / F 55O as the correlation output I of the orthogonal component.

Each F / F of the accumulator 58 has 48 Mb
A clock frequency of ps is input, and each F / F stores and shifts data in synchronization with this frequency. When the cumulative addition for one symbol is completed, the F / F storing the cumulative addition result of each component resets the stored cumulative addition result, and is ready to store a new cumulative addition result.

Next, the operation of the complex SC compatible with the phase correction function according to the specific embodiment of the present invention will be described with reference to FIG. An analog signal transmitted by CDMA orthogonal modulation from a transmitter is received by an antenna (not shown) of the receiver, and separated into an in-phase component and a quadrature component. Analog signals are transmitted at a chip rate of 4 Mcps as before.

The in-phase component of the analog signal is supplied to the A / D converter 5
1A, the orthogonal component is input to an A / D converter 51B, and is converted into digital received data at a rate of 16 Mbps. The received data output from the A / D converter 51A or 51B is stored in the F / F 55A or 55B and output to the correlation calculator 57 in synchronization with the clock frequency.

The PN code registers I53A, PN
The PN code of the in-phase component and the quadrature component stored in the code register I53B is 16 Mbps one bit at a time.
And stored in the F / Fs 55C and 55F, which are the first stage of the in-phase code register row and the quadrature code register row, respectively.

The PN code stored in the F / Fs 55C and 55F is shifted to the second-stage F / Fs 55D and 55G of each register row in synchronization with the clock frequency.
Similarly, the PN code stored in the F / Fs 55D and 55G is stored in the third stage F / Fs 55E and 55H of each register row.
The PN code stored in / F55E, 55H is shifted to selectors 56A, 56B in synchronization with the clock frequency. The PN code stored in the first and second stages of each register row is output to the selectors 56A and 56B when shifting to the next stage F / F.

The selectors 56A and 56B switch the input three PN code codes of each register row at a rate of 48 Mbps and output them to the correlation calculator 57. That is, the in-phase code register train and the orthogonal code register train have A /
Three different PN code codes output for each digital conversion timing of the D converter are stored. The selectors 56A and 56B receive the PN code code of each timing stored in each F / F.

The correlation calculator 57 calculates the demodulated signal of each component based on the input received data of each component and the PN code of each component at each timing, and outputs the signal to the accumulator 58. In the correlation operation section 57, the multipliers 52A and 52A
B, Expression (2) is calculated by the adder 54A using the multipliers 52C and 52C.
D and the adder 54B realize the equation (3). Since the selectors 56A and 56B output the PN code code at each timing, the correlation calculator 57 calculates the demodulated signal of each component three times for the same received data at each timing. Therefore, the multipliers 52A to 52D and the adders 54A and 54B operate at a speed of 48 Mbps.

The demodulated signal of the in-phase component output from the adder 54A is first stored in the F / F 55I in the accumulator 58. The demodulated signal stored in the F / F 55I is 4
The data is output to the adder 54C in synchronization with the clock frequency of 8 Mbps. In the adder 54C, the demodulated signal output from the F / F 55I is added to the cumulative addition result stored in the F / F 55M, and the new cumulative addition result is added to the F / F 55M.
Stored in F55J. At the same time, the cumulative addition result stored in the F / F 55J is stored in the F / F 55L, the cumulative addition result stored in the F / F 55L is stored in the F / F 55M,
The cumulative addition result stored in 55M is shifted to the adder 34C. The adder 54A outputs a demodulated signal of the in-phase component at each timing, and the accumulated addition results are stored in the F / Fs 55J to 55M. Can be performed alternately.

At each timing, the cumulative addition of the demodulated signal for one symbol is output from the F / F 55K as a correlation output, and synchronized with the clock frequency of 48 Mbps.
Input to MA demodulation circuit. Further, after outputting the correlation output, the F / Fs 55J to 55M reset the stored cumulative addition result, and make a state in which a new cumulative addition result can be stored.

The demodulated signal of the quadrature component output from the adder 54B is added to the adder 54D and the F / Fs 55N to 5N.
In the 5R circuit group, the cumulative addition at each timing is performed by the method described above, and the correlation output at each timing is performed.

The complex type SC corresponding to the phase correction function shown in FIG. 5 outputs the PN code code of each component at three timings different by 16 Mbps for each of the received data of the in-phase component or the quadrature component output at 16 Mbps. ,
The cumulative addition of the demodulated signal is performed at each timing,
The correlation output for one symbol is performed. The CDMA demodulation circuit determines the optimal timing by comparing the correlation outputs at the respective timings.
PN code register 53 is fed back to the generation timing of the code generator of the PN code register
A and 53B can output a PN code code with the optimal timing.

In the complex type SC corresponding to the phase correction function shown in FIG. 5, each correlation output is performed based on the PN code code of three different timings, but the number of timing samples may be another value. At this time, the operation speed of each element of the selectors 56A and 56B and the correlation operation unit 57 is A / D
It is necessary to make the number of samples times the digital conversion speed of the converters 51A and 51B, and to connect serially a number of registers in the accumulator 58 for storing the cumulative addition result of the demodulated signal of each component. Since the purpose is to perform phase correction within one symbol, the number of timing samples is C
It is preferable that the number of chips is not more than the number of chips at the time of DMA modulation.

According to the complex type SC corresponding to the phase correction function of the specific embodiment of the present invention, the PN code of the in-phase component or the quadrature component output at the timing of the number of samples is A /
A selector is provided for alternately selecting and outputting to the correlation operation unit at a speed that is multiple times the number of samples of the digital conversion of the D converter, and increasing the operation speed of each element of the correlation operation unit by the number of samples of the digital conversion of the A / D converter. In addition, the provision of the register row for storing the cumulative addition result of the demodulated signal at each timing in the cumulative adder has the effect of reducing the SC circuit scale as compared with the related art.

The conventional complex type SC corresponding to the phase correction function shown in FIG. 8 is provided with three correlation operation units of the complex type SC shown in FIG. 7 in order to obtain a correlation output at each timing. The total number of adders of the cumulative adder occupying is 6
Were used. In the complex type SC corresponding to the phase correction function according to the specific embodiment of the present invention, only one correlation operation unit is required and the total number of the adders of the accumulator is two.
This has the effect of reducing the circuit scale, and consequently the overall circuit scale of the receiver for spread spectrum communication using quadrature modulation, thereby reducing development costs.

[0104]

According to the present invention, a despread code corresponding to a spread code is time-division-converted to an analog signal which is spread and transmitted by a plurality of types of spread codes, faster than digital conversion of an analog signal. Switching and multiplying the received data by the received data, and performing the cumulative addition of the multiplication result by time-division switching to the type of the despreading code faster than the digital conversion of the analog signal, and outputting the cumulative addition result as a correlation value The circuit scale of the sliding correlator can be reduced, and the circuit scale of the entire receiver for spread spectrum communication can be reduced, and the development cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a sliding correlator for spread spectrum communication according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a sliding correlator for spread spectrum communication according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a sliding correlator for complex spread spectrum communication according to a specific embodiment of the present invention.

FIG. 4 is a configuration block diagram of a second complex type spread spectrum communication sliding correlator according to a specific embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a sliding correlator for complex type spread spectrum communication corresponding to a phase correction function according to a specific embodiment of the present invention.

FIG. 6 is a configuration block diagram of a conventional sliding correlator for spread spectrum communication.

FIG. 7 is a block diagram showing a configuration of a conventional sliding correlator for complex spread spectrum communication.

FIG. 8 is a block diagram showing a configuration of a conventional sliding correlator for complex spread spectrum communication supporting a phase correction function.

[Explanation of symbols]

11, 21, 61 ... A / D converter, 12, 22, 62
... Multipliers, 13A, 13B, 23A, 23B, 63 ...
PN code register, 14, 24, 64 ... adder,
15A, 15B, 25A, 25B, 65 ... delay circuit,
16, 26: PN code selector, 17: Cumulative addition selector

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5K022 EE01 EE11 EE32 5K047 AA16 BB01 CC01 DD01 DD02 GG34 HH15 HH45 JJ06 LL06 MM03 MM13 MM36 MM45

Claims (3)

[Claims] 1. An analog received signal spectrum-spread by a plurality of types of spread signals is converted into a digital received signal at a fixed sample rate, and the digital received signal is multiplied by a despread signal corresponding to each of the spread signals. Is performed in a time division manner on the type of the despread signal, the cumulative addition of the multiplication result is performed in a time division manner on the type of the spread signal, and the cumulative addition result is output as a correlation output to the type of the despread signal. Sliding correlator for spread spectrum communication. 2. An A / D converter for converting an analog received signal spectrum-spread by a plurality of types of spread signals into a digital received signal at a fixed sample rate, and storing a despread signal corresponding to each of the spread signals. Despreading code sequence storing means, a first selector for switching a plurality of types of the despreading signals output from the despreading code sequence storing means and outputting the signals in a time-division manner, the digital reception signal, and the first A multiplier that multiplies the despread signal output from the selector and outputs a demodulated signal; an adder that cumulatively adds the demodulated signal and outputs a cumulative addition result as a correlation output; and an output from the adder. A plurality of delay registers for classifying and storing the accumulated addition results for each of the despread signals; and switching between the accumulated addition results stored in the plurality of delay registers. A sliding correlator for spread spectrum communication, comprising: a second selector for relatively outputting to the adder. 3. An A / D converter for converting an analog received signal spectrum-spread by a plurality of types of spread signals into a digital received signal at a fixed sample rate, and storing a despread signal corresponding to each of the spread signals. A despreading code sequence storage unit, a selector for switching a plurality of types of the despreading signals output from the despreading code sequence storage unit and outputting the signals in a time-division manner, the digital reception signal, and a signal output from the selector. A multiplier that multiplies the despread signal and outputs a demodulated signal; an adder that accumulatively adds the demodulated signal and outputs the accumulated addition result as a correlation output; and a plurality of delay registers connected in series. When a new cumulative addition result is input from the adder, the stored cumulative addition result is shifted to the next-stage delay register, and the final-stage delay register Spread spectrum communication for the sliding correlator characterized by comprising a delay register string to be shifted out to the adder.