JP2002026321A - Mos field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a MOSFET which can reduced switching loss at a high frequency and has a low on-resistance. SOLUTION: This MOSFET has a p-type epitaxial layer 12 formed on the main surface of a p+-type semiconductor substrate 11, n+-type diffusion layers 17A and 17B separately formed in the epitaxial layer 12, and a gate electrode 14 formed on the epitaxial layer 12 through a gate insulating film 13 between the diffusion layers 17A and 17B. The MOSFET also has a contact plug 18 which is buried in a trench formed through the epitaxial layer 12 and electrically connects the diffusion layer 17A to the substrate 11, a source electrode 25 which is formed on the rear surface of the substrate 11 and electrically connected to the substrate 11, and a drain electrode 24 which is formed on the epitaxial layer 12 through an insulating fill insulated from the diffusion layer 17A and gate electrode 14 and electrically connected to the diffusion layer 17B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-resistance MOS field-effect transistor (hereinafter referred to as MOSFET) used for synchronous rectification and the like.

[0002]

2. Description of the Related Art In recent years, as a power supply used for a CPU of a computer or the like has been reduced in voltage, a power supply of a synchronous rectification system has been frequently used. Conventionally, a trench MOSFET has been used for this power supply.

A conventional low-resistance MOSFET will be described with reference to FIGS. 14A and 14B. FIG.
(A) is a sectional view showing a configuration of a conventional trench MOSFET.

In this trench MOSFET, the gate 1
01, a source 102, and a drain 103, a low on-resistance is realized by adopting a trench gate using a trench side wall as a channel in order to reduce the resistance.

[0005] As a high-speed switching element, as shown in FIG.
2. A lateral MOSFET having a drain 113 is used.

[0006]

However, FIG.
In the trench MOSFET as shown in FIG. 1A, the gate 101 is in direct contact with the drain layer via a thin oxide film, so that the parasitic capacitance between the gate and the drain is large. Therefore, it is not suitable for high-frequency switching. A horizontal MOSF as shown in FIG.
ET has a problem that the on-resistance is large.

The present invention has been made in view of the above problems, and has as its object to provide a MOSFET which can reduce switching loss at high frequencies and has a low on-resistance.

Further, such a MOSFET has a drawback that, when used with an L load, avalanche breakdown occurs when a voltage exceeds the withstand voltage of the element and the element is destroyed. SUMMARY OF THE INVENTION It is an object of the present invention to provide a MOSFET capable of improving the withstand voltage when avalanche breakdown occurs.

[0009]

In order to achieve the above object, a first MOS field effect transistor according to the present invention comprises a first conductivity type semiconductor substrate having a main surface and a back surface opposed to the main surface. A first semiconductor region formed on a main surface of the semiconductor substrate, and second and third semiconductor regions of a second conductivity type formed apart from each other in the first semiconductor region;
A gate electrode formed on the first semiconductor region between the second semiconductor region and the third semiconductor region via a gate insulating film, and embedded in a trench formed in the first semiconductor region. A conductor electrically connecting the second semiconductor region to the semiconductor substrate, a first main electrode formed on a back surface of the semiconductor substrate, and electrically connected to the semiconductor substrate; A second main electrode formed on the semiconductor region via an insulating film, insulated from the second semiconductor region and the gate electrode, and electrically connected to the third semiconductor region. And

A second MOS field-effect transistor according to the present invention is formed on a first conductivity type semiconductor substrate having a main surface and a back surface opposite to the main surface, and formed on the main surface of the semiconductor substrate. A first semiconductor region, a first conductivity type second semiconductor region selectively formed in the first semiconductor region, and a second conductivity type third semiconductor region formed in the second semiconductor region.
A semiconductor region and the third semiconductor region are separated from each other;
A second conductive type fourth semiconductor region formed in the first semiconductor region, and the first semiconductor region and the second semiconductor region between the third semiconductor region and the fourth semiconductor region;
A gate electrode formed via a gate insulating film, a conductor buried in a trench formed in the first semiconductor region and electrically connecting the third semiconductor region to the semiconductor substrate; A first main electrode formed on the back surface of the substrate and electrically connected to the semiconductor substrate; and a first main electrode formed on the first semiconductor region via an insulating film, and insulated from the third semiconductor region and the gate electrode. And a second main electrode electrically connected to the fourth semiconductor region.

According to a third MOS field effect transistor of the present invention, a second conductivity type semiconductor substrate having a main surface and a back surface opposite to the main surface is formed on the main surface of the semiconductor substrate. A first semiconductor region, a second semiconductor region of a first conductivity type selectively formed in the first semiconductor region, and a second semiconductor region of a second conductivity type formed in the second semiconductor region and separated from each other. 3, a fourth semiconductor region, and a gate electrode formed on the second semiconductor region between the third semiconductor region and the fourth semiconductor region via a gate insulating film;
A conductor buried in a trench formed in the first semiconductor region and electrically connecting the third semiconductor region to the semiconductor substrate; and a conductor formed on a back surface of the semiconductor substrate and electrically connected to the semiconductor substrate. A first main electrode, which is electrically connected, and an insulating film formed on the first semiconductor region,
A second main electrode electrically insulated from the third semiconductor region and the gate electrode and electrically connected to the fourth semiconductor region.

According to a fourth MOS field effect transistor of the present invention, there is provided a semiconductor substrate of a first conductivity type; a first semiconductor layer of a second conductivity type formed on the semiconductor substrate;
A second semiconductor layer of a second conductivity type formed between the semiconductor substrate and the first semiconductor layer; a first semiconductor region of a first conductivity type selectively formed on the first semiconductor layer; A second semiconductor region of a second conductivity type formed in the first semiconductor region, and the first semiconductor region being separated from the second semiconductor region.
A third semiconductor region of the second conductivity type formed in the semiconductor layer;
A gate electrode formed on the first semiconductor region between the second semiconductor region and the third semiconductor region via a gate insulating film, wherein the first semiconductor region and the second
A diode is formed by the semiconductor layer, and a withstand voltage of the diode is set lower than a withstand voltage between the second semiconductor region and the third semiconductor region.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a MOS field effect transistor (MO) according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of an SFET.

As shown in FIG. 1, ap + epitaxial layer 12 is formed on one surface of ap + type silicon semiconductor substrate (hereinafter, p + semiconductor substrate) 11. On this p-epitaxial layer 12, a gate 14 made of a polysilicon film is formed via a gate insulating film 13 of a silicon oxide film. A side wall insulating film 15A is formed on one side of the gate 14 and a side wall insulating film 15B is formed on the other side of the gate.
Are formed.

In the p-epitaxial layer 12 on one side of the gate 14, an n-diffusion layer 16 as a source layer is provided.
A and n + diffusion layers 17A are formed. The n + diffusion layer 17A is connected to the p + semiconductor substrate 11 by a contact plug 18 made of a conductive layer embedded in a trench in the p − epitaxial layer 12.

As the contact plug 18, a metal layer (for example, tungsten) or a low-resistance semiconductor layer is used. When a low-resistance semiconductor layer is used, a junction formed between the semiconductor layer and the n + diffusion layer 17A is eliminated above the semiconductor layer, and the semiconductor layer and the n + diffusion layer 17A are removed.
In order to electrically connect the diffusion layer 17A, it is necessary to provide a metal layer.

Further, in the p-epitaxial layer 12 on the other side of the gate 14, the n-type drain layer
A diffusion layer 16B and an n + diffusion layer 17B are formed.
p− epitaxial layer 1 including n + diffusion layers 17A and 17B
An insulating layer 19 is formed on 2 and the gate 14. In the insulating layer 19 on the n + diffusion layer 17B, a contact plug 2 made of a conductive layer (for example, tungsten) is formed.
0 is formed, and a first-layer drain electrode pattern (for example, aluminum) 21 is formed on the contact plug 20.

An insulating layer 22 is formed on the drain electrode pattern 21 and the insulating layer 19. A contact plug 23 made of a conductive layer (for example, tungsten) is formed in the insulating layer 22 on the drain electrode pattern 21.
Is formed on the contact plug 23 and the insulating layer 2.
On 2, a second-layer drain electrode (for example, aluminum) 24 is formed. This drain electrode 24
It is connected to the n + diffusion layer 17B via the contact plug 23, the drain electrode pattern 21, and the contact plug 20. On the other surface of p + semiconductor substrate 11, source electrode 25 is formed. Note that this p
-Instead of the epitaxial layer 12, a p-type well layer formed on the n-type epitaxial layer may be used.

This MOSFET is an nMOS transistor constituting a so-called CMOS. FIG.
This is a planar layout when the MOSFET is viewed from above, and shows a state in which the contact plug 18 (source trench contact portion), the contact plug 23 (drain contact hole), and the gate 14 are seen through. As can be seen from FIG. 2, the contact plug 18 connected to the source electrode 25 and the contact plug 23 connected to the drain electrode 24 are alternately arranged. As a result, the gate width W can be increased, and the on-resistance can be reduced.

The MOSFET of this embodiment shown in FIG.
In FIG. 14B, the drain electrode 24 and the source electrode 25 are formed on both sides of the wafer, and a current flows from one side of the wafer to the other side. Therefore, as shown in FIG. No voltage drop due to wiring resistance. That is, the resistance at the time of ON can be reduced (lower ON resistance).

On the other hand, in the device shown in FIG. 14B, since the source layer and the semiconductor substrate are connected by the p + diffusion layer, the portion of the p + diffusion layer connecting the source layer and the semiconductor substrate is formed. The area cannot be ignored, and the element pitch of the repetition becomes large, and the element resistance becomes large.

In the MOSFET of this embodiment, the n + diffusion layer 17A as the source layer and the p +
1 is connected by digging a trench and burying a conductive film, for example, a metal film, so that the resistance between the source layer and the semiconductor substrate can be reduced.

From these characteristics, the MO of this embodiment
The SFET has a feature that combines the low resistance of a vertical trench MOSFET and the high speed of a horizontal MOSFET.

As described above, according to the first embodiment, by reducing the parasitic capacitance between the gate and the drain, it is possible to suppress an increase in switching loss at a high frequency, and further, it is possible to further reduce the drain electrode and the source. By providing electrodes on both sides of the wafer and connecting the source layer and the semiconductor substrate with a conductive film by digging a trench, on-resistance can be reduced.

[Second Embodiment] In the second embodiment, in addition to the structure of the first embodiment, a structure for increasing the resistance when avalanche breakdown occurs is added. . In the second embodiment, the n-diffusion layers 16A and 16B and the side wall insulating films 15A and 15B are not provided, and the insulating film on the p − epitaxial layer 12 is also one layer. Has not changed. Further, a p-type well layer formed on an n-type epitaxial layer may be used instead of the p − epitaxial layer 12. When switching with an L load is performed in the semiconductor device of the first embodiment, a voltage may be applied exceeding the withstand voltage, and an object is to prevent the MOSFET from being destroyed at this time.

FIG. 3 is a block diagram showing a second embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a configuration of an OSFET.

In this MOSFET, the breakdown voltage of the vertical diode formed by the n + diffusion layer 17C as the drain layer and the p + semiconductor substrate 11 is determined by the breakdown voltage (n + diffusion) between the drain and the source of the lateral MOSFET. (The breakdown voltage between the layer 17A and the n + diffusion layer 17C).

Specifically, as shown in FIG. 3, the depth of the n + diffusion layer 17C as the drain layer is formed to be deeper than the n + diffusion layer 17B of the first embodiment. n +
The distance between the diffusion layer 17C and the p + semiconductor substrate 11 is reduced. With such a structure, the applied voltage is n +
Since the voltage is clamped by the vertical parasitic diode formed by the diffusion layer 17C and the p + semiconductor substrate 11, a large voltage is not applied to the channel of the MOSFET.

As described above, according to the second embodiment, a large voltage at the time of switching is not generated in the channel but in the vertical diode formed by the n + diffusion layer (drain layer) and the p + semiconductor substrate. Since the voltage can be applied, it is possible to prevent the MOSFET from being destroyed.

[Third Embodiment] In the third embodiment, the MOSFET of the second embodiment is made higher in withstand voltage.

FIG. 4 shows a third embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a configuration of an OSFET.

As shown in FIG. 4, ap − epitaxial layer (or n − epitaxial layer) 12 is formed on one surface of ap + semiconductor substrate 11. On this p-epitaxial layer 12, a gate insulating film 1 of a silicon oxide film is formed.
3, a gate 14 made of a polysilicon film is formed.

A p-type well layer 26 is formed in the p-epitaxial layer 12 on one side of the gate 14, and an n-type source layer is formed above the p-type well layer 26.
+ A diffusion layer 17A is formed. This n + diffusion layer 17A
Is formed by a contact plug 18 made of a conductive layer embedded in a trench in the p − epitaxial layer 12.
+ Connected to the semiconductor substrate 11.

As the contact plug 18, a metal layer (for example, tungsten) or a low-resistance semiconductor layer is used. When a low-resistance semiconductor layer is used, a junction formed between the semiconductor layer and the n + diffusion layer 17A is eliminated above the semiconductor layer, and the semiconductor layer and the n + diffusion layer 17A are removed.
In order to electrically connect the diffusion layer 17A, it is necessary to provide a metal layer.

An n-type RESURF layer 27 and an n + diffusion layer 17C, which are drain layers, are formed in the p-epitaxial layer 12 on the other side of the side of the gate 14. An insulating layer 19 is formed on such a structure. In the insulating layer 19 on the n + diffusion layer 17C, a contact plug 20 made of a conductive layer (for example, tungsten) is formed.
4 are formed. The drain electrode 24 is connected to the n + diffusion layer 17C via the contact plug 20. On the other surface of p + semiconductor substrate 11, source electrode 25 is formed. FIG.
This is a planar layout when T is viewed from above, and shows a state in which the contact plug 18 (source contact portion), the contact plug 23 (drain contact portion), and the gate 14 are seen through.

In this MOSFET, by providing the n-type RESURF layer 27 on the drain side, a higher breakdown voltage than in the second embodiment is achieved. That is, this MO
In the SFET, the n + diffusion layer 17C as the drain layer and the p +
The withstand voltage of the vertical diode formed with the semiconductor substrate 11 is set lower than the withstand voltage between the drain and the source of the MOSFET (the withstand voltage between the n-type resurf layer 27 and the n + diffusion layer 17A). + An n-type RESURF layer 27 is formed between the diffusion layer 17C and the channel.

With such a structure, the applied voltage is clamped by the vertical parasitic diode formed by the n + diffusion layer 17C and the p + semiconductor substrate 11, so that a large voltage is applied to the channel of the MOSFET. Never.
Furthermore, providing the n-type RESURF layer 27 on the drain side makes it difficult to form a depletion layer, so that the breakdown voltage between the drain and the source of the MOSFET can be increased.

As described above, according to the third embodiment, the large voltage generated at the time of switching or the like is generated not by the channel but by the vertical direction formed by the n + diffusion layer (drain layer) and the p + semiconductor substrate. , And the breakdown voltage between the drain layer and the source layer can be made high, so that the MOSFET can be prevented from being destroyed.

FIG. 6 is a sectional view showing the structure of a MOSFET according to a modification of the third embodiment of the present invention.

This MOSFET is different from the n-type resurf layer 27 provided on the drain side in the second embodiment.
Is replaced with two-stage n-type RESURF layers 27A and 27B. Other configurations are the same as those of the third embodiment.

In a MOSFET, a current usually flows.
When the pressure is reduced, as shown in FIG.
I will. In the MOSFET shown in FIG. 6, the n-type RESURF layer 2
The impurity concentration of 7B is made higher than that of the n-type RESURF layer 27A.
As a result, as shown in FIG.
The pressure resistance can be increased even when the pressure is high. For example, n-type Lisa
The total dose of impurities existing in the portion of the
× 10¹¹~ 5 × 10 ¹²/ Cm³Degree, and n-type
The total dose of impurities existing in the surf layer 27B is
2 × 10¹²~ 1 × 10¹³/ Cm³Good to be around
Good.

Further, the MO of the third embodiment shown in FIG.
Even in the SFET, the dose amount of the n-type RESURF layer 27 is 2 × 1
By setting to 0 ¹² to 1 × 10 ¹³ / cm ³ ,
Withstand voltage when current is flowing can be increased.

As described above, according to the modification of the third embodiment, the large voltage generated at the time of switching or the like is not generated in the channel but in the n + diffusion layer (drain layer).
And a p + semiconductor substrate, and a high voltage can be applied between the drain layer and the source layer, thereby preventing the MOSFET from being destroyed. Further, the breakdown voltage when a current flows through the MOSFET can be improved.

[Fourth Embodiment] In the fourth embodiment, a p + semiconductor substrate is replaced with an n + semiconductor substrate,
Accordingly, the conductivity types of the other layers are changed.

FIG. 9 shows a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view illustrating a configuration of an OSFET.

As shown in FIG. 9, on one surface of an n + type silicon semiconductor substrate (hereinafter referred to as n + semiconductor substrate) 31, an n − epitaxial layer (or p − epitaxial layer) 32 is formed. A p-type well layer 46 is selectively formed in the n − epitaxial layer 32, and a gate 34 made of a polysilicon film is formed on the p-type well layer 46 via a gate insulating film 33 of a silicon oxide film. Is formed. One of the side surfaces of the gate 34 has a sidewall insulating film 35A.
Is formed, and a sidewall insulating film 35B is formed on the other side of the side surface.

In the p-type well layer 46 on one side of the gate 34, n diffusion layers 36A and n serving as source layers are provided.
+ A diffusion layer 37A is formed. In the other p-type well layer 46 on the side of the gate 14, an n-diffusion layer 36B and an n + diffusion layer 37B, which are drain layers, are formed.

Further, an insulating layer 39 is formed on the structure. A contact plug 40 made of a conductive layer (for example, tungsten) is formed in the insulating layer 39 on the n + diffusion layer 37A, and a first-layer source electrode pattern 41 (for example, aluminum) is formed on the contact plug 40. Is formed.

On the source electrode pattern 41 and the insulating layer 39, an insulating layer 42 is formed. In the insulating layer 42 on the source electrode pattern 41, a contact plug 43 made of a conductive layer (for example, tungsten) is formed. On the contact plug 43 and the insulating layer 42, a second-layer source electrode 44 is formed. Is formed. The source electrode 44 is connected to the n + through the contact plug 43, the source electrode pattern 41, and the contact plug 40.
It is connected to the diffusion layer 37A.

The n + diffusion layer 37B is formed by a contact plug 38 made of a conductive layer embedded in the trench in the insulating layer 39 and the n− epitaxial layer 32.
It is connected to a semiconductor substrate 31.

For the contact plug 38, a metal layer (for example, tungsten) or a low-resistance semiconductor layer is used. When a low-resistance semiconductor layer is used, a junction formed between the semiconductor layer and the n + diffusion layer 37A is eliminated above the semiconductor layer, and the semiconductor layer and the n + diffusion layer 37A are eliminated.
In order to electrically connect the diffusion layer 37A, it is necessary to provide a metal layer. Further, a drain electrode 45 is formed on the other surface of the p + semiconductor substrate 31.

The fourth embodiment has the same effect as the first embodiment. Further, the resistance of the substrate is p
Since the n + semiconductor substrate is lower than the + semiconductor substrate, the fourth
In the embodiment, the resistance at the time of ON can be further reduced.

Fifth Embodiment By the way, the second embodiment
The method of improving the avalanche withstand capability described in the embodiment is not limited to the vertical type in which the source electrode and the drain electrode are on both sides of the substrate, but also the horizontal type MO as the output stage of the power IC.
This technique is applicable to SFETs.

A method for improving the avalanche resistance,
That is, the following method can be used to design the withstand voltage between the drain and the source when the gate voltage is zero higher than the withstand voltage of the vertical diode formed by the p base layer and the n + buried layer. .

A deep p diffusion layer is provided on the p base layer. Further, the distance between the gate and the drain is increased, and the n-type RESURF layer is formed as two layers having different concentrations. In addition, an antimony buried layer is used for the CMOS and bipolar transistor portions, and phosphorus is introduced into the buried layer of the power MOS transistor which is junction-separated to diffuse the buried layer upward, thereby forming a low-concentration epitaxial layer substantially. And thinner.

An example in which a technique for improving avalanche withstand capability is applied to a lateral MOSFET will be described below.

FIG. 10 is a sectional view showing the structure of a MOSFET according to the fifth embodiment of the present invention.

As shown in FIG. 10, p-semiconductor substrate 51
An n-epitaxial layer 52 is formed thereon.
On this n-epitaxial layer 52, a gate 54 made of a polysilicon film is formed via a gate insulating film 53 of a silicon oxide film.

In the n-epitaxial layer 52 on one side of the gate 54, a p-type well layer (p base layer) is provided.
56 are formed, and p +
A base layer 57B and an n + diffusion layer 57A as a source layer are formed. A source electrode 58 is formed on n + diffusion layer 57A and p + base layer 57B.

In the n-epitaxial layer 52 on the other side of the gate 54, an n-type RESURF layer 59 and an n + diffusion layer 57C, which are drain layers, are formed. Drain electrode 60 is formed on n + diffusion layer 57C. An n + buried layer 61 is formed near the boundary between the p − semiconductor substrate 51 and the n − epitaxial layer 52.

In this MOSFET, the withstand voltage of the vertical diode formed by the portion indicated by A in FIG. 10, the p-type well layer (p base layer) 56, the n − epitaxial layer 52, and the n + buried layer 61. Is set lower than the breakdown voltage between the n-type RESURF layer 59 as the drain layer and the n + diffusion layer 57A as the source layer. With such a structure, the applied voltage is clamped by the vertical diode, so that a large voltage is not applied to the channel of the MOSFET.

In other words, the horizontal MOSF shown in FIG.
When determining the withstand voltage of ET, the withstand voltage between the drain and the source when the gate voltage is set to zero is determined by the p-type well layer (p base layer) 56, the n − epitaxial layer 52, and the n + buried layer 6.
By designing the diode higher than the withstand voltage of the vertical diode formed by 1, it is possible to prevent the destruction of the MOSFET due to avalanche breakdown that occurs when an overvoltage is applied.

As described above, according to the fifth embodiment, the large voltage generated at the time of switching or the like is not generated by the channel but by the p-type well layer (p base layer) and the n +
Since a voltage can be applied to a vertical diode formed by the buried layer and a resurf layer is provided, a high breakdown voltage can be applied between the drain layer and the source layer.
ET can be prevented from being destroyed.

FIG. 11 is a sectional view showing the structure of a MOSFET according to a first modification of the fifth embodiment of the present invention.

This MOSFET is different from the fifth embodiment in that the n-type RESURF layer 59 provided on the drain side is replaced with two-stage n-type RESURF layers 59A and 59B,
The n-type resurf layer 59A overlaps the n-type well layer (p-base layer).

As described in the modification of the third embodiment, in the MOSFET, when a current is flowing, the breakdown voltage is generally lowered as shown in FIG. In the MOSFET shown in FIG. 11, by making the impurity concentration of n-type RESURF layer 59B higher than that of n-type RESURF layer 59A, the breakdown voltage can be increased even when a current flows, as shown in FIG. . For example, the total dose of impurities present in the portion of the n-type RESURF layer 59A is about 1 × 10 ^{11 to} 5 × 10 ¹² / cm ³ , and n
It is preferable that the total dose of the impurities existing in the portion of the mold RESURF layer 59B is about 2 × 10 ¹² to 1 × 10 ¹³ / cm ³ .

Also, M of the fifth embodiment shown in FIG.
In the case of OSFET, the dose of the n-type RESURF layer 59 is 2 ×
By setting to 10 ¹² to 1 × 10 ¹³ / cm ³ , the withstand voltage when a current flows can be increased.

In order to obtain a large current, the structure shown in FIG. 11 must be folded symmetrically, and the folded structure must be repeated.

As described above, according to the first modification shown in FIG. 11, the large voltage generated at the time of switching or the like is not generated by the channel but by the p-type well layer (p base layer) and the n-type well layer.
The voltage can be applied to the vertical diode formed by the + buried layer and the breakdown voltage between the drain layer and the source layer can be made high, so that the MOSFET can be prevented from being destroyed. Further, the breakdown voltage when a current flows through the MOSFET can be improved.

FIG. 12 is a sectional view showing a structure of a MOSFET according to a second modification of the fifth embodiment of the present invention.

This MOSFET further has a p-type well layer (p base layer) 56 compared to the first modification shown in FIG.
Are extended to overlap the n-type RESURF layer 59B.

In this MOSFET, the n-type resurf layer 5
By setting the impurity concentration of 9B higher than that of the n-type RESURF layer 59A, the breakdown voltage can be increased even when a current flows, as shown in FIG. For example, the total dose of impurities existing in the portion of the n-type RESURF layer 59A is 1
It is preferably about × 10 ^{11 to} 5 × 10 ¹² / cm ³ , and the total dose of impurities present in the portion of the n-type RESURF layer 59B is preferably about 2 × 10 ¹² to 1 × 10 ¹³ / cm ³ .

In order to obtain a large current, the structure shown in FIG. 12 must be folded symmetrically, and the folded structure must be repeated.

As described above, according to the second modification shown in FIG. 12, a large voltage generated at the time of switching or the like is not generated in the channel but in the p-type well layer (p base layer) and the n-type layer.
The voltage can be applied to the vertical diode formed by the + buried layer and the breakdown voltage between the drain layer and the source layer can be made high, so that the MOSFET can be prevented from being destroyed. Further, the breakdown voltage when a current flows through the MOSFET can be improved.

FIG. 13 is a sectional view showing the structure of a MOSFET according to a third modification of the fifth embodiment of the present invention.

This MOSFET is different from the first modification of the fifth embodiment in that a shallow p +
A deep p + base layer 57D is provided instead of the base layer 57B. In this MOSFET, the p + base layer 5
The breakdown voltage of the vertical diode formed by 7D, n − epitaxial layer 52 and n + buried layer 61 is determined by the breakdown voltage between n-type RESURF layer 59A as the drain layer and n + diffusion layer 57A as the source layer. It is easy to set lower. With such a structure, the applied voltage is clamped by the vertical diode, so that a large voltage
It is not applied to the channel of the OSFET.

[0078]

As described above, according to the present invention, a switching loss at a high frequency can be reduced and a MOSFET having a low on-resistance can be provided. Further, according to the present invention, it is possible to provide a MOSFET that can improve the withstand voltage when avalanche breakdown occurs.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a MOS field-effect transistor (MOSFET) according to a first embodiment of the present invention.

FIG. 2 is a planar layout when the MOSFET according to the first embodiment of the present invention is viewed from above.

FIG. 3 is a sectional view showing a configuration of a MOSFET according to a second embodiment of the present invention.

FIG. 4 is a sectional view showing a configuration of a MOSFET according to a third embodiment of the present invention.

FIG. 5 is a plan layout when a MOSFET according to a third embodiment of the present invention is viewed from above.

FIG. 6 shows a MOS transistor according to a modification of the third embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating a configuration of an FET.

FIG. 7 is a diagram showing current-voltage characteristics when current flows in a conventional MOSFET.

FIG. 8 shows a MOS according to a modification of the third embodiment of the present invention.
FIG. 3 is a diagram illustrating current-voltage characteristics when a current flows in the FET.

FIG. 9 is a sectional view showing a configuration of a MOSFET according to a fourth embodiment of the present invention.

FIG. 10 is a MOSFET according to a fifth embodiment of the present invention.
It is sectional drawing which shows a structure of.

FIG. 11 is a cross-sectional view showing a configuration of a MOSFET according to a first modification of the fifth embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating a configuration of a MOSFET according to a second modification of the fifth embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a configuration of a MOSFET according to a third modification of the fifth embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a structure of a conventional MOSFET.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... p + type silicon semiconductor substrate (p + semiconductor substrate) 12 ... p-epitaxial layer 13 ... gate insulating film 14 ... gate 15A ... sidewall insulating film 15B ... sidewall insulating film 16A ... n diffusion layer 16B ... n diffusion layer 17A ... n + diffusion layer 17B n + diffusion layer 17C n + diffusion layer 18 contact plug 19 insulating layer 20 contact plug 21 drain electrode pattern 22 insulating layer 23 contact plug 24 drain electrode 25 source electrode 26 ... p-type well layer 27 ... n-type RESURF layer 27A ... n-type RESURF layer 27B ... n-type RESURF layer 31 ... n + type silicon semiconductor substrate (n + semiconductor substrate) 32 ... n-epitaxial layer 46 ... p-type well layer 33 ... Gate insulating film 34 ... Gate 35A ... Side wall insulating film 35B ... Side wall insulating film 36A ... N diffusion layer 36B ... N diffusion layer 37A ... + Diffusion layer 37B n + diffusion layer 38 contact plug 39 insulating layer 40 contact plug 41 source electrode pattern 42 insulating layer 43 contact plug 44 source electrode 45 drain electrode 51 p-type silicon semiconductor substrate (P-semiconductor substrate) 52 ... n-epitaxial layer 53 ... gate insulating film 54 ... gate 56 ... p-type well layer (p base layer) 57A ... n + diffusion layer 57B ... p + base layer 57C ... n + diffusion layer 57D ... p + base layer 58 ... source electrode 59 ... n-type RESURF layer 59A ... n-type RESURF layer 59B ... n-type RESURF layer 60 ... drain electrode 61 ... n + buried layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 H01L 21/90 D 21/768 27/08 321E 21/8238 321D 27/092 321F 29/78 301D 301W 301X F term (reference) 5F033 HH03 HH08 JJ19 KK01 KK08 NN13 XX00 XX08 5F040 DA20 DA22 EB01 EB13 EC07 EC22 EF11 EF18 EM06 5F048 AA05 AA08 AB10 AC01 AC03 BB05 BE04 BF02 BF07

Claims (16)

[Claims] A semiconductor substrate of a first conductivity type having a main surface and a back surface opposite to the main surface; a first semiconductor region formed on the main surface of the semiconductor substrate; and a first semiconductor region. The second formed apart from each other
A conductive second and third semiconductor regions; a gate electrode formed on the first semiconductor region between the second semiconductor region and the third semiconductor region via a gate insulating film; A conductor buried in a trench formed in one semiconductor region and electrically connecting the second semiconductor region and the semiconductor substrate; and a conductor formed on a back surface of the semiconductor substrate and electrically connected to the semiconductor substrate. A first main electrode connected to the first semiconductor region; an insulating film formed on the first semiconductor region via an insulating film; insulated from the second semiconductor region and the gate electrode; and electrically connected to the third semiconductor region. And a second main electrode. 2. A diode is formed by the third semiconductor region and the semiconductor substrate, and a breakdown voltage of the diode is set lower than a breakdown voltage between the second semiconductor region and the third semiconductor region. The MOS field effect transistor according to claim 1, wherein 3. The third semiconductor region includes a low concentration region having a low impurity concentration disposed near the gate electrode and an impurity concentration lower than the low concentration region electrically connected to the second main electrode. 3. The MOS field-effect transistor according to claim 1, wherein the MOS field-effect transistor has a high-concentration region having a high density. 4. The low-concentration region has a first region disposed near the gate electrode, and a second region disposed between the first region and the high-concentration region. 4. The MOS field effect transistor according to claim 3, wherein the impurity concentration of the second region is higher than the impurity concentration of the first region. 5. A semiconductor substrate of a first conductivity type having a main surface and a back surface facing the main surface, a first semiconductor region formed on the main surface of the semiconductor substrate, and a first semiconductor region. A second semiconductor region of a first conductivity type selectively formed; a third semiconductor region of a second conductivity type formed in the second semiconductor region; and the second semiconductor region being separated from the third semiconductor region. A fourth semiconductor region of a second conductivity type formed in one semiconductor region; and a gate insulating film on the first semiconductor region and the second semiconductor region between the third semiconductor region and the fourth semiconductor region. A gate electrode formed through the first semiconductor region, a conductor buried in a trench formed in the first semiconductor region and electrically connecting the third semiconductor region and the semiconductor substrate, and a back surface of the semiconductor substrate Formed on and electrically connected to the semiconductor substrate. A first main electrode connected to the first semiconductor region; an insulating film formed on the first semiconductor region via an insulating film; insulated from the third semiconductor region and the gate electrode; and electrically connected to the fourth semiconductor region. And a second main electrode. 6. A diode is formed by the fourth semiconductor region and the semiconductor substrate, and a breakdown voltage of the diode is set lower than a breakdown voltage between the third semiconductor region and the fourth semiconductor region. The MOS field effect transistor according to claim 5, wherein 7. The fourth semiconductor region includes a low impurity concentration region disposed near the gate electrode and having a low impurity concentration, and an impurity concentration lower than the low concentration region electrically connected to the second main electrode. 7. The MOS field-effect transistor according to claim 5, wherein the MOS field-effect transistor has a high-concentration region having a high concentration. 8. The low-concentration region includes a first region disposed near the gate electrode, and a second region disposed between the first region and the high-concentration region. 8. The MOS field effect transistor according to claim 7, wherein the impurity concentration of the second region is higher than the impurity concentration of the first region. 9. A semiconductor substrate of a second conductivity type having a main surface and a back surface opposed to the main surface; a first semiconductor region formed on the main surface of the semiconductor substrate; A second semiconductor region of a first conductivity type selectively formed, and a second semiconductor region formed separately from the second semiconductor region in the second semiconductor region.
A conductive third and fourth semiconductor region; a gate electrode formed on the second semiconductor region between the third semiconductor region and the fourth semiconductor region via a gate insulating film; A conductor buried in a trench formed in one semiconductor region and electrically connecting the third semiconductor region to the semiconductor substrate; and a conductor formed on a back surface of the semiconductor substrate and electrically connected to the semiconductor substrate. A first main electrode connected to the first semiconductor region; an insulating film formed on the first semiconductor region via an insulating film; insulated from the third semiconductor region and the gate electrode; and electrically connected to the fourth semiconductor region. And a second main electrode. 10. The MOS field effect transistor according to claim 1, wherein the conductor is a metal layer. 11. The conductor is provided on a low-resistance semiconductor layer electrically connected to the semiconductor substrate and above the semiconductor layer, and electrically connects the semiconductor layer to the third semiconductor region. The MOS field-effect transistor according to claim 1, wherein the MOS field-effect transistor comprises: 12. A semiconductor substrate of a first conductivity type, a first semiconductor layer of a second conductivity type formed on the semiconductor substrate, and a first semiconductor layer formed between the semiconductor substrate and the first semiconductor layer. A second conductivity type second semiconductor layer; a first conductivity type first semiconductor region selectively formed in the first semiconductor layer; and a second conductivity type second semiconductor region formed in the first semiconductor region. A semiconductor region, a third semiconductor region of a second conductivity type formed in the first semiconductor layer so as to be separated from the second semiconductor region, and a third semiconductor region between the second semiconductor region and the third semiconductor region. A gate electrode formed on the first semiconductor region with a gate insulating film interposed therebetween; a diode is formed by the first semiconductor region and the second semiconductor layer; Lower than the breakdown voltage between the region and the third semiconductor region MOS field-effect transistor, characterized in that it is set. 13. A diode is formed by the first semiconductor region and the second semiconductor layer, and a breakdown voltage of the diode is set lower than a breakdown voltage between the second semiconductor region and the third semiconductor region. 13. The method according to claim 12, wherein
2. The MOS field effect transistor according to claim 1. 14. The third semiconductor region includes a low-concentration region having a low impurity concentration disposed near the gate electrode.
14. The MOS field-effect transistor according to claim 12, further comprising a high-concentration region that is electrically connected to the second main electrode and has a higher impurity concentration than the low-concentration region. 15. The low-concentration region includes a first region disposed near the gate electrode, and a second region disposed between the first region and the high-concentration region. 15. The MOS field effect transistor according to claim 14, wherein the impurity concentration of the second region is higher than the impurity concentration of the first region. 16. The MOS field effect transistor according to claim 15, wherein the second semiconductor layer is a buried layer.