JP2002025246A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To desirably prohibit a specific area from being written in a nonvolatile semiconductor storage device. SOLUTION: The memory cell array 21 of each bank 15a to 15d is provided with a storing part 21a. Write prohibition data to the memory cell array are selectively stored in the storing part in a setting mode. A decision circuit 26 holds the write prohibition data read from the storing part in an initial anode and controls an access to the memory cell array in accordance with the write prohibition data. A storing part control circuit 27 can select the storing part 21a in the setting mode and the initial mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device having, for example, a memory protection function.

[0002]

2. Description of the Related Art In recent years, ferroelectric RAMs (Ferroelectric
The development of non-volatile semiconductor storage devices such as Random Access Memory) is in progress. This non-volatile semiconductor memory device has the advantage of being able to retain data even when the power is turned off, and has the advantage of being able to read and write data required to execute a program at high speed. As the capacity of the nonvolatile semiconductor memory device increases, it becomes possible to replace both the conventional ROM and RAM with the nonvolatile semiconductor memory device.

[0003]

By the way, when both the conventional ROM and the RAM are replaced by the nonvolatile semiconductor memory device, the advantage that the control becomes easy and the circuit can be downsized are brought about. . However, when a system is configured with this type of nonvolatile semiconductor memory device, programs and data that have not been destroyed because they were previously written in ROM are stored in the writable nonvolatile semiconductor memory device. For this reason, there is a possibility that programs and data stored in the nonvolatile semiconductor memory device may be destroyed by an application program or the like whose operation verification is insufficient.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of prohibiting writing to a specific area. .

[0005]

According to the present invention, in order to solve the above-mentioned problems, a memory cell array divided into a plurality of banks and data provided in the memory cell array of each bank and designating whether writing or reading is possible are provided. A storage unit to be stored; and a discrimination circuit for restricting writing to the memory cell array of the bank in accordance with data stored in the storage unit.

Further, the present invention provides a memory cell array divided into a plurality of banks, a storage unit provided in the memory cell array of each bank for storing data designating whether writing or reading is possible, and a plurality of adjacent storage units. A data line shared by the banks for transmitting and receiving data to and from the memory cell array of each bank; and, in an initialization mode, fetching data read from the storage section of the selected bank via the data lines, A determination circuit for limiting writing to the memory cell array of the bank in accordance with the fetched data;

Further, the present invention provides a memory cell array divided into a plurality of banks, a storage unit provided in the memory cell array of each bank for storing data designating whether or not writing is possible, and a plurality of adjacent banks. And a data line for transmitting and receiving data to and from the memory cell array of each bank, and data read from the storage section of the selected bank during the initialization mode via the data line. A determination circuit that restricts writing to the memory cell array of the bank according to data; and a cutoff circuit that is inserted and connected to the data line and cuts off the data line in the initialization mode.

Further, the present invention comprises a memory cell array divided into a plurality of banks, and a discriminating circuit for limiting writing to the memory cell array of the bank, wherein the discriminating circuit has a fuse, The writing to the memory cell array of the bank is restricted in accordance with the data set in (1).

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention and shows, for example, a configuration of a nonvolatile semiconductor memory device having four banks. The number of banks is not limited to four. In this embodiment, a column address buffer 11, a row address buffer 12, a predecoder 1
3, command decoder 14, banks 15a, 15b, 1
5c and 15d, main amplifiers 16a and 16b, write buffers 17a and 17b, an output buffer 18, and an input buffer 19.

That is, the address signal is supplied to the predecoder 13 via the column address buffer 11 and the row address buffer 12. Also, two / RAS
(/ Indicates an inverted signal), / CAS, a write control signal / WE, a chip enable signal / CE, and the like are supplied to the command decoder 14. The row address signal, the column address signal, and the bank selection signals AS-0 to AS-3 output from the predecoder 13 are supplied to the banks 15a,
15b, 15c, and 15d.

Each of the banks 15a, 15b, 15c, 1
5d is a memory cell array 21, a column decoder (CD
C) 22, a sense amplifier (S / A) group 23, a row decoder (RDC) 24, a row driver (RDRV) 25, a determination circuit 26, and a storage control circuit 27.

The memory cell array 21 has a plurality of non-volatile memory cells (not shown) arranged in a matrix. The memory cell array 21 has a storage unit 21a. As described later, write-inhibited data for setting the memory cell array 21 to the write-inhibited state is selectively set in the storage unit 21a.

The column decoder 22 selects a column of the memory cell array 21 according to an address signal supplied from the predecoder 13. Sense amplifier group 23
Drives the column selected by the column decoder 21. Each sense amplifier group 23 has data lines DQ, / DQ
(/ Indicates an inverted signal).

The row decoder 24 selects a row of the memory cell array 21 according to an address signal supplied from the predecoder 13. The row driver 25 drives the row selected by the row decoder 24.

The determination circuit 26 determines whether the bank can be written according to the data set in the storage section 21a. The storage unit control circuit 27 includes a storage unit 21a
Control access to.

The main amplifier 16a has a data line D
It is connected to the sense amplifier group 23 of the banks 15a and 15b via Q and / DQ. This main amplifier 16
a amplifies the signal read from the memory cell array 21 and supplied via the sense amplifier group 23 and the data lines DQ and / DQ.

The main amplifier 16b has a data line D
Q and / DQ are connected to the sense amplifier group 23 of the banks 15c and 15d. This main amplifier 16
b amplifies the signal read from the memory cell array 21 and supplied via the sense amplifier group 23 and the data lines DQ and / DQ.

The output signals of the main amplifiers 16a and 16b are output to the outside via an output buffer 18.

The input buffer 19 is supplied with write data from outside. This write data is selectively supplied to the write buffers 17a and 17b. The write data output from the write buffer 17a is
The data is supplied to the sense amplifier group 23 of the banks 15a and 15b via the data lines DQ and / DQ. The write data supplied to the sense amplifier group 23 is written to a memory cell selected by the column decoder 22 and the row decoder 24.

The write data output from the write buffer 17b is supplied to the sense amplifier group 23 of the banks 15c and 15d via data lines DQ and / DQ. The write data supplied to the sense amplifier group 23 is written to a memory cell selected by the column decoder 22 and the row decoder 24.

The main amplifiers 16a and 16b, the write buffers 17a and 17b, the output buffer 18, and the input buffer 19 are operated according to the output signal of the command decoder 14.

In the above configuration, the operation of the semiconductor memory device shown in FIG. 1 in the normal operation mode will be schematically described.

The column address buffer 11 and the row address buffer 12 shape and amplify the supplied address signal and supply it to the predecoder 13. The predecoder 13 supplies a row address signal, a column address signal, and a bank selection signal AS-0 to AS-3 to the corresponding banks 15a to 15d based on the supplied address signal.
Supply. The column decoder 22 and row decoder 24 of the bank activated by the bank selection signal select a predetermined memory cell based on a row address signal and a column address signal.

When writing data, externally supplied data is supplied to the activated bank via the input buffer 19, the write buffer 17a or 17b, and the data line pair DQ and / DQ. In this bank, data is written to a memory cell selected by the row address signal and the column address signal. At this time, the storage unit 2
When write-inhibited data is set in 1a, the determination circuit 26 inhibits writing to the bank in which the write-inhibited data is set.

On the other hand, when reading data, data is read from the memory cell selected by the row address signal and the column address signal in the activated bank. This data is supplied to the corresponding main amplifier 16a or 16b via the data line pair DQ, / DQ. The data amplified by the main amplifier 16a or 16b is output to the outside through the output buffer 18.

FIG. 2 shows the configuration of the banks 15a to 15d. Since the configuration of each of these banks is the same, only the bank 15a will be described.

In FIG. 2, a plurality of column decoders 22 are provided.
AND circuit 22₁, 22₂~ 22 _nConsists of
I have. These AND circuits 22₁, 22₂~ 22_nInput
A column address signal is selectively supplied to the end. this
Ra and circuit 22₁, 22₂~ 22_nOutput signal
C, AND circuit 22₂~ 22_nOutput signal is sense
Sense amplifier 23 constituting a group of switches 23₂~ 23_nDirectly to
Supplied. The AND circuit 22₁Output signal is OR
A sensor constituting the sense amplifier group 23 via the circuit 22a
Samp 23₁Supplied to

The sense amplifiers 23 ₂ to 23 _n are activated when the output signals of the AND circuits 22 _{2 to} 22 _n attain a high level, and are connected to the data line pair DQ and / DQ. The sense amplifier 23 ₁ is activated when the output signal of the OR circuit 22a becomes a high level, the data line pair DQ, / D
Connected to Q.

The sense amplifiers 23 ₁ , 23 ₂ to 23 _n
Are connected to a data line pair DQ and / DQ at one end, and are connected to the bit line pairs BL1, / BL1, BL2 and / BL2 at the other end.
To BLn and / BLn are connected to each other.

The row decoder 24 includes a plurality of AND circuits 24 ₁ , 24 _{2 to} 24 _n . Row address signals are selectively supplied to the input terminals of these AND circuits 24 ₁ , 24 _{2 to} 24 _n . Of these AND circuits _{24 1, 24} 2 _{~24 n} output signals, the output of the AND circuit ₂₄ 2 to 24 _n signal is supplied directly row driver 25 to the driver circuit ₂₅ 2 to 25 _n configuration. The output signal of the AND circuit 24 ₁ is supplied to the driver circuit 25 ₁ via the OR circuit 24a. Driver circuits 25 ₁ , 25 ₂ to 2 selected according to the row address signal
5 the output signal of _n is assumed to be high.

The driver circuits 25 ₁ , 25 _{2 to} 25 _n
Are connected to word lines WL1, WL2 to WLn, respectively.

In the memory cell array 21, each bit line pair BL1, / BL1, BL2, / BL2 to BL
A memory cell MC is connected to the intersection of n, / BLn and word lines WL1, WL2 to WLn. Examples of the configuration of these memory cells MC are shown in FIGS.

Further, at the intersection of the word line WL1 and the bit line pair BL1, / BL1, the storage section 21a for storing the write inhibit data of the bank is provided.
The configuration of the storage unit 21a is the same as that of the other memory cells MC.

A signal PRG for setting each bank to a writable state and a signal 2 in the determination circuit are provided to the determination circuit 26.
6, a signal INI for initializing a latch circuit to be described later provided in 6, a bank selection signal AS-i (i is a bank number 0 to 3) for selecting a predetermined bank, and either of writing and reading. And a signal WR indicating whether the sense amplifier is connected is supplied, and an output signal of the sense amplifier is supplied via the data line pair DQ and / DQ. The output signal BA of the determination circuit 26 is supplied to all of the AND circuits 24 ₁ , 24 _{2 to} 24 _n constituting the row decoder 24.

The signals PRG, INI, and AS-i are supplied to the storage control circuits 27a and 27b.
These storage unit control circuits 27a and 27b have the same configuration as described later. The storage unit control circuit 27a
Is supplied to the OR circuit 24a, the output signal SC of the storage control circuit 27b is supplied to the pulse generation circuit 32, and the output signal of the pulse generation circuit 32 is supplied to the OR circuit 22. . The pulse generation circuit 32 outputs a pulse signal of a predetermined width with a predetermined time delay in synchronization with the rise of the output signal SC.

Furthermore, the AND circuit 22 ₁ of the output signal of the column decoder 22. and the AND circuit 24 ₁ of the output signal of the row decoder 24 is supplied to the AND circuit 28. Wherein between ground and the output terminal of the OR circuit 22a is connected N-channel MOS transistor 29, between the ground and the driver circuit 25 _first output terminal being connected to N-channel MOS transistor 30. These transistors 2
The output signals of the AND circuit 28 are supplied to the gates 9 and 30. The AND circuit 28 and the transistors 29 and 30 constitute a write-protection circuit 31 that deselects the storage unit 21a in the normal operation mode.

In the above configuration, the operation of the determination circuit 26 and the storage section control circuits 27a and 27b is set in the setting mode
The description will be made by dividing into three states of an initialization mode and a normal operation mode.

The discrimination circuit 26 and the storage section control circuits 27a, 2
7b shifts to the setting mode when the signal PRG goes high. Discrimination circuit 26 and storage unit control circuits 27a, 27
b transitions to the initialization mode when the signal PRG goes low and the signal INI goes high, and transitions to the normal operation mode when the signal INI goes low.

When writing is performed, the signal WR is at a high level, and when reading is performed, the signal WR is at a low level. The bank selection signal AS-i supplied to the selected bank is at a high level, and when the bank selection signal AS-i is at a low level, the bank is not selected.

First, the operation in the setting mode will be described. This setting mode is performed in the storage unit 21a of an arbitrary bank.
, Write-inhibit data for inhibiting writing to the bank is set. In the setting mode, the signal PRG becomes high level, so that the signal BA output from the determination circuit 26 is fixed at low level. This signal B
A indicates all AND circuits 24 constituting the row decoder 24.
_1, is supplied to the ₂₄ 2 to 24 _n. Therefore, the AND circuits 24 ₁ , 24 _{2 to} 24 _n output a low-level signal regardless of the row address signal. For this reason, the driver circuits 25 ₁ , 25 _{2 to} 25 _n are connected to the AND circuits 24 ₁ , 2
Without selecting a word line by the output signal of 4 ₂ to 24 _n.

At this time, the storage unit control circuits 27a and 27b
Performs an operation necessary for writing to a memory cell included in the storage unit 21a because the signal PRG is at a high level and the signal INI is at a high level. That is, the output signals SC of the storage unit control circuits 27a and 27b go to the high level. Therefore, OR circuit 22a, the output signal of the 24a are both high level, the sense amplifier 23 ₁ while being activated, the driver circuit 25 ₁ is activated. Therefore, the storage section 21a is selected by the bit line pair BL1, / BL1 and the word line WL1.

When the bank selection signal AS-i connected to the storage unit 21a goes high and a bank is selected,
Data supplied via the data line pair DQ, / DQ is written to the storage unit 21a. The determination circuit 26 is provided in the storage unit 21
The data line a is connected to the data line pair DQ and / DQ to take in the data of a. However, in the setting mode, the data line pair D
It is controlled not to take in the data of Q and / DQ.

As described above, when the write-inhibited data indicating whether each bank is writable is written, the operation as the nonvolatile semiconductor memory device becomes possible based on the data.

Next, a case where the nonvolatile semiconductor memory device is operated in a write-protected state will be described.

After the power is turned on, the nonvolatile semiconductor memory device is set to the initialization mode before data is read or written, and the data in the storage unit 21a is taken into the discrimination circuit 26.

First, the determination circuit 26 and the storage control circuit 27 in the initialization mode will be described. In the initialization mode, the signal PRG is at a low level, and the signal INI is at a high level. The storage control circuits 27a and 27b perform operations necessary for reading data from the memory cells of the storage 21a. That is, the storage unit control circuits 27a, 2
7b becomes high level, and the OR circuit 22
The output signals a and 24a become high level. For this reason,
The sense amplifier 23 ₁ connected to the storage unit 21a, the driver circuit 25 ₁ are activated, the bit line pair BL1, / BL
1. The storage unit 21a is selected by the word line WL1. As a result, the data read from the storage unit 21a is stored in the sense amplifier 23 ₁ and the data line pair DQ and / DQ.
Is supplied to the discriminating circuit 26 via. When the signal INI is at a high level, this data is held in a latch circuit of the discriminating circuit 26 described later.

In this way, after the data indicating whether the bank is writable is stored in the determination circuit 26, the data can be read out in the same manner as in a normal nonvolatile semiconductor memory device, and the data can be written to the writable bank. Be able to write.

That is, in the normal operation mode, the signal PRG is at the low level and the signal INI is at the low level. When writing data, the signal WR is set to the high level, and data is written to a predetermined cell of the bank (selected bank) where the AS-i is set to the high level.

At this time, when the selected bank is write-protected, the output signal BA of the determination circuit 26 is fixed at a low level. Therefore, writing cannot be performed because the word line is not selected. Writing to this bank is a case where the output signal BA of the discrimination circuit 26 is at a high level and a word line can be selected. At this time, the output signals of the storage control circuits 27a and 27b are fixed at a low level.

When the memory section 21a is selected by the row address signal and the column address signal in the normal operation mode, the write inhibit circuit 31 operates. That is, the AND circuit 24 ₁ in the normal operation mode, when the output signal of the AND circuit 22 ₁ becomes high level at the same time, the output signal of the AND circuit 28 becomes high level. Therefore, conducting the N-channel MOS transistors 29 and 30, the word line WL1 for selecting the storage unit 21a does not become a high level, the sense amplifier 23 ₁ does not operate. Therefore, it is possible to prevent the data from being written into the storage unit 21a in the normal operation mode and the write-protected data from being rewritten.

FIG. 3 shows an example of the discrimination circuit 26. The signal INI is supplied to one input terminal of an AND circuit 26a, and the signal PRG is supplied to the other input terminal of the AND circuit 26a via an inverter circuit 26b.

The data line DQ is connected to the pass gate 2
6c is connected to one end. This pass gate 26c
Is controlled by the output signal of the AND circuit 26a and the output signal of the AND circuit 26a inverted by the inverter circuit 26d. The other end of the pass gate 26c has
Latch circuit 26e composed of two inverter circuits
Are connected. The output terminal of the latch circuit 26e is connected to one end of the pass gate 26f.

On the other hand, the power supply VDD is supplied to one end of the pass gate 26g. These pass gates 26f, 2
6g is complementarily controlled by the signal WR and the signal inverted by the inverter circuit 26h. The other ends of the pass gates 26f and 26g are commonly connected. This connection node N1 is connected to one input terminal of the AND circuit 26i. The other input terminal of the AND circuit 26i is supplied with a bank selection signal AS-i. The signal BA is output from the output terminal of the AND circuit 26i. Further, an N-channel MOS transistor 26j is connected between the output terminal of the AND circuit 26i and the ground. The gate of the transistor 26j has an OR circuit 2
The output terminal of 6k is connected. The signal INI and the signal PRG are supplied to the input terminal of the OR circuit 26k.

In the above configuration, the pass gate 26c is
When the signal PRG is at a high level and when the signal INI is at a low level, the signal is turned off, and the signal on the data line DQ is not propagated. That is, the signal of the data line DQ is not taken in the setting mode and the normal operation mode.

When the signal PRG is at the low level and the signal INI is at the high level, the signal is conducted, and the signal on the data line DQ is transmitted to the latch circuit 26e. That is, the signal of the data line DQ is taken in the initialization mode.

On the other hand, when the signal WR is at a high level, that is, at the time of writing, the pass gate 26f conducts.
Therefore, the data latched by the latch circuit 26e is supplied to the AND circuit 26i via the pass gate 26f.

When writing is prohibited, the latch circuit 26e
Is set so that a high-level signal is latched at the input terminal of the connection node N1 when the signal WR is at a high level.
Goes low. Therefore, the signal BA is fixed at the low level. Therefore, the word line is in a non-selected state, and writing to the memory cell array 21 is prohibited.

When the signal WR is at a low level, that is, at the time of reading, the pass gate 26g is turned on.
Since one end of the pass gate 26g is fixed at a high level (VDD), the connection node N1 is at a high level. Therefore, at the time of reading, the bank selection signal AS-i
Goes high, the signal BA goes high,
The word line can be selected. Therefore, reading is possible even in a write-inhibited state in which the high level is latched by the latch circuit 26e.

Further, when the signal PRG or the signal INI supplied to the OR circuit 26k is at a high level,
In the setting mode or the initialization mode, the transistor 26
j is conducted. Therefore, the signal BA is fixed at the low level, and all the word lines are set to the non-selected state.

FIG. 4 shows the storage section control circuits 27a, 27
b shows an example.

In FIG. 4, signal INI and signal AS-i
Are supplied to the AND circuit 27c. AND circuit 27
The output signal of c is supplied to one end of the pass gate 27d. The signal INI is supplied to one end of a pass gate 27e. These pass gates 27d and 27e are operated complementarily by the signal PRG and the signal PRG inverted by the inverter circuit 27f. The other ends of the pass gate 27d and the pass gate 27e are commonly connected.

When signal PRG is at the high level, that is, in the setting mode, pass gate 27d is turned on.
Therefore, the output signal of the AND circuit 27c is
It is output as an output signal SC of the storage section control circuits 27a and 27b via 7d. In the setting mode, the bank to be set is selected and the write-inhibited data is written for each bank. Therefore, it is necessary to specify the bank. In the setting mode, when the signal INI is at a high level and the bank selection signal AS-i is at a high level, the signal SC goes to a high level. Therefore, the word line WL1 of the bank selected by the bank selection signal AS-i goes high, and the sense amplifier 23
₁ and the bit line pair BL1, / BL1 are the data line pair DQ,
/ DQ. Accordingly, data can be written to the storage unit 21a.

Since initialization can be performed simultaneously for each bank, there is no need to specify a bank. When the signal PRG is at a low level and the signal INI is at a high level, that is, in the initialization mode, the pass gate 27
e conducts. Therefore, the signal INI is output from the pass gate 27.
e. Therefore, the signal SC becomes high level. At this time, the storage unit 21a of the selected bank
Becomes high level, and the sense amplifier 23 ₁ and the bit line pair BL1, / BL1 are connected to the data line pair DQ, / DQ. Therefore, data stored in the storage unit 21a can be read.

According to the first embodiment, each bank 15
a to 15d include a determination circuit 26 and a storage unit control circuit 27;
a, 27b, and the write-inhibit data can be set in the storage unit 21a provided in the memory cell array 21 by the determination circuit 26 and the storage unit control circuits 27a, 27b. For this reason, writing is prohibited and only reading is possible for a memory cell array of a bank in which write-inhibited data is set in the storage unit 21a, and writing is performed for a memory cell array of a bank in which write-inhibited data is not set. And reading are possible.
Therefore, by storing important programs and data in the memory cell array where writing is prohibited, it is possible to prevent the programs and data from being destroyed.

(Second Embodiment) Next, a second embodiment of the present invention will be described.

In the first embodiment, each bank 15a,
A data line pair DQ and / DQ are connected between the main amplifier 16b and the write buffer 17a, respectively, and a data line pair DQ is connected between the banks 15c and 15d and the main amplifier 16b and the write buffer 17b.
Q and / DQ are connected. On the other hand, in the second embodiment, the banks 15a and 15b share the data line pair DQ and / DQ, and the banks 15c and 15d
And the case where the data line pair DQ and / DQ are shared between the two.

FIG. 5 shows a second embodiment. The banks 15a and 15b share the data line pair DQ and / DQ, and the banks 15c and 15d share the data line pair DQ and / DQ. Thus, bank 1
5a and bank 15b share data line pair DQ, / DQ, and bank 15c and bank 15d share data line pair DQ, / DQ.
/ DQ is shared, the storage unit 2 in the initialization mode
When the data read from 1a is latched by the latch circuit 26e, the data read from a certain bank needs to be supplied only to the discrimination circuit 26 in that bank.

Therefore, in the second embodiment, the determination circuit 26
The configuration is devised.

FIG. 6 shows an example of the discrimination circuit 26 applied to the second embodiment. The same parts as those in FIG. 3 are denoted by the same reference numerals, and only different parts will be described.

In FIG. 6, the difference from the determination circuit shown in FIG. 3 is the input signal of the AND circuit 26a. In the case of this embodiment, the bank selection signal AS-i is supplied to the input terminal of the AND circuit 26a. For this reason, the discriminating circuits 26 provided for each bank cannot be initialized at the same time, and the signals of the data lines DQ and / DQ can be taken into only the discriminating circuits 26 of the bank specified by the bank selection signal AS-i.

FIG. 7 shows an example of the storage control circuit 27 applied to the second embodiment. When the discrimination circuit 26 shown in FIG. 6 is used, the storage control circuit 27 is constituted by one NAND circuit 27g. The signal INI and the bank selection signal AS-i are supplied to the input terminal of the NAND circuit 27g.

When the storage control circuit 27 shown in FIG. 7 is used, it is necessary to specify a bank in both the setting mode and the initialization mode. The signal INI is at a high level in the setting mode and the initialization mode. Therefore, the signal SC is output to the bank for which the bank selection signal AS-i has been set to the high level. Therefore, the storage unit 21a of the selected bank can be accessed.

According to the second embodiment, the data line pairs DQ and / DQ can be shared between adjacent banks. Therefore, the number of wirings connecting each bank to the main amplifier 16 and the write buffer 17 can be reduced, so that the area can be reduced.

Further, in the initialization mode, the data read from the storage unit 21a of the selected bank can be supplied only to the discrimination circuit 26 of the selected bank. Therefore, erroneous setting of data in the latch circuit 26e can be prevented.

(Third Embodiment) FIG. 8 shows a third embodiment of the present invention. In the third embodiment, the data line pairs DQ and / DQ are shared between the banks 15a and 15b, and the data line pairs DQ and / DQ are shared between the banks 15c and 15d. At this time, D is applied to each data line pair DQ and / DQ.
Q-line cutoff circuits 51a and 51b are provided. The DQ line cutoff circuits 51a and 51b cut off the data line pair DQ and / DQ in the initialization mode. Therefore, it is possible to prevent data interference between banks sharing data line pair DQ and / DQ.

FIG. 9 shows an example of the DQ line cutoff circuits 51a and 51b. These DQ line cutoff circuits 51a, 51
Since b has the same configuration, only the DQ line cutoff circuit 51a will be described.

In FIG. 9, a signal INI is supplied to one end of a pass gate 51e, and one end of a pass gate 51f is grounded. The other ends of the pass gates 51e and 51f are commonly connected to a connection node N2. These pass gates 51e and 51f are operated complementarily by the signal PRG and the signal PRG inverted by the inverter circuit 51g.

A pass gate 51h is connected to the data line DQ.
Are inserted and connected, and a pass gate 51i is connected to the data line / DQ.
Is inserted and connected. These pass gates 51h, 51
i is the signal of the connection node N2 and the inverter circuit 5
Conduction or non-conduction is simultaneously performed by the signal of the connection node N2 inverted by 1j.

For example, in the setting mode, the signal PRG and the signal I
NI are both at a high level. Therefore, the pass gate 51f conducts, and the connection node N2 is set to low level. Therefore, pass gates 51h and 51i are both made conductive, and data lines DQ and / DQ are connected.

In the initialization mode, the signal PRG
Is at a low level and the signal INI is at a high level. Therefore, the pass gate 51e is turned on, and the connection node N2 is set to a high level in response to the signal INI. Therefore, both pass gates 51h and 51i are turned off, and data lines DQ and / DQ are cut off.

In the normal mode, the signal PRG is at low level and the signal INI is at low level. Therefore, the pass gate 51e is turned on, and the connection node N2 goes low in response to the signal INI. Therefore, both the pass gates 51h and 51i are conductive and the data lines DQ,
/ DQ is connected.

According to the third embodiment, the DQ line cutoff circuits 51a and 51b are inserted and connected to the data lines DQ and / DQ which are commonly connected to the banks.
1a and 51b, the data lines DQ,
/ DQ is shut off. Therefore, the data read from the storage unit 21a of the bank selected in the initialization mode can be supplied only to the discrimination circuit of that bank.
Therefore, erroneous setting of data can be prevented.

In the case of the second embodiment, it is difficult to simultaneously set the write-inhibit data in the discriminating circuits of a plurality of banks in the initialization mode. The data lines DQ and / DQ are cut off by the DQ line cutoff circuits 51a and 51b. Therefore, the write-inhibited data can be simultaneously set in the discriminating circuits of a plurality of banks. Therefore, the operation of setting write-inhibited data to the discrimination circuit can be sped up as compared with the second embodiment.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described. In the first to third embodiments, the determination circuit 26 has a latch circuit 26e, and the latch circuit 26e holds write-inhibited data read from the storage unit 21a.

On the other hand, in the fourth embodiment, write-inhibited data is held by a fuse instead of the latch circuit.

FIG. 10 shows a discrimination circuit 61 applied to the fourth embodiment. In FIG. 10, the power supply voltage VD
The fuses 61a and 61 are connected between the node to which D is supplied and the ground.
1b are connected in series. These fuses 61a, 6
The connection node 1b is connected to one end of the pass gate 61c.

On the other hand, a power supply voltage VDD is supplied to one end of the pass gate 61d. These pass gates 61d
The pass gate 61c is operated complementarily by the signal WR and the signal WR inverted by the inverter circuit 61e. These pass gate 61d and pass gate 61
The other ends of c are connected to each other and to one input terminal of an AND circuit 61f. A bank selection signal AS-i is supplied to the other input terminal of the AND circuit 61f.

As described above, the fuse 61 is
When a and 61b are provided, it is not necessary to provide the storage unit 21a in the memory cell array of each bank, and the storage unit control circuit 27 is not required.

In the above configuration, for example, the fuse 61a
Is cut off, one end of the pass gate 61c is always grounded. For this reason, in the first to third embodiments,
This is the same state as when write-inhibited data is held in the latch circuit 26e. Therefore, when the signal WR is set to a high level during data writing and the pass gate 61c is turned on, one input terminal of the AND circuit 61f is set to a low level. In this state, when the bank selection signal AS-i is set to a high level, the signal BA of the selected bank is set to a low level, and writing is prohibited.

At the time of reading, when signal WR is set to low level, pass gate 61d is turned on. Therefore, the AND circuit 6 is connected via the pass gate 61d.
One input terminal 1f is at a high level corresponding to the power supply voltage VDD. In this state, when the bank selection signal AS-i is set to the high level, the signal BA of the selected bank is output.
Is set to a high level, and reading is enabled.

According to the fourth embodiment, the fuse 61
a, 61b, and the write-inhibited data is set by the fuses 61a, 61b. Therefore, there is no need to provide the storage unit 21a in the memory cell array of each bank, and further, the storage unit control circuit 27 is not required, and the configuration can be simplified.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described.

In the first to third embodiments, when a ferroelectric RAM is used as a memory cell, a plate line may be driven when writing and reading to and from this memory cell. At this time, it is necessary to control the driver for driving the plate lines of the memory cells constituting the storage unit 21a using the output signal SC of the storage unit control circuit 27.

FIG. 11 shows a fifth embodiment of the present invention, in which a plate line activation circuit 70 is provided corresponding to the plate line PL1 of the memory cell constituting the storage section 21a. The plate activation circuit 70 has an OR circuit 71, a control circuit 72, a plate line driver 73, and a pulse generation circuit (PGC) 32b. The output signal of the pulse generation circuit 32b is supplied to one input terminal of the OR circuit 71, and the output signal of the control circuit 72 is supplied to the other input terminal. The output signal SC of the storage control circuit 27 is supplied to the input terminal of the pulse generation circuit 32b.
The pulse generation circuit 32b outputs a pulse having a preset width with a delay of a preset delay time in synchronization with the rise of the signal SC. The control circuit 72 is, for example, a decoder that selects driving of the plate line according to the address signal. The output signal of the OR circuit 71 is supplied to a plate line PL1 via a plate line driver 73.

According to the above configuration, since the plate line PL1 is controlled by the output signal SC of the storage control circuit 27, the plate line is also driven when selecting the storage 21a in the setting mode or the initialization mode.

FIG. 12 shows a modification of the present invention, and the same parts as those in FIG. 11 are denoted by the same reference numerals. In this modified example, as a memory cell array, for example, both ends of a capacitor (C) are connected between a source and a drain of a cell transistor (T) to form a unit cell, and a plurality of the unit cells are connected in series. Unit serial connection type ferroelectric RAM (STCRAM; Series conn
expected TC unit type ferroelectric RAM).

That is, in FIG. 12, the STCRAM
Is a plurality of transistors T10, T1 connected in series.
1, T12 and T13 are ferroelectric capacitors C10 and C1.
1, C12 and C13 are respectively connected in parallel. These transistors T10 to T13 and capacitors C10 to C
13 is connected to one end of a selection transistor T2.
1 is connected to the bit line BL. The other end of the block is connected to a plate line PL. S
The TCRAM is selected by setting the word line to a low level instead of a high level.

In such an STCRAM, a plate line activation circuit 70 similar to that shown in FIG. 11 is connected to plate line PL. A circuit 75 similar to the plate line activation circuit 70 is also connected to the gate of the selection transistor T21 (however, the pulse signal generation circuits 32c and 32d can independently set the pulse width and delay time, respectively). ing). Circuit 7 connected to selection transistor T21
In 5, the control circuit 74 is a circuit for selecting a selection transistor according to an address signal. With such a configuration, the block of the STCRAM is connected to the signal SC.
Can be selected.

FIG. 13 shows an example in which a computer system is configured using the ferroelectric RAM according to the present invention. The computer system includes, for example, a central processing unit (CPU) 80 and a storage device 81. In this example, the storage device 81 has a ROM and RA
A nonvolatile semiconductor memory device including a ferroelectric RAM of the present invention is applied in place of both M. The storage device 81, each bank ₁₅ 1 to 15 _n, for example basic software,
Data 1, data 2, program 1, and program 2 are stored, and a work area is set.

In such a configuration, for example, write-inhibited data is set in the basic software, data 1 that is not likely to be destroyed, and the storage unit 21a provided in the bank of the program 1. By doing so, it is possible to prevent the basic software, data 1 and program 1 from being destroyed. Therefore, a highly reliable system can be constructed using the ferroelectric RAM.

In each of the above embodiments, the present invention is applied to the ferroelectric R
The case where the present invention is applied to AM has been described. However, the present invention is not limited to this.
The present invention can also be applied to a nonvolatile semiconductor memory device such as a random access memory (RAM) that can read and write data at high speed.

In addition, it goes without saying that various modifications can be made without departing from the scope of the invention.

[0104]

As described in detail above, according to the present invention,
A semiconductor storage device capable of prohibiting writing to a specific area can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a bank shown in FIG. 1;

FIG. 3 is a circuit diagram showing an example of a determination circuit shown in FIGS. 1 and 2;

FIG. 4 is a circuit diagram showing an example of a memory control circuit shown in FIG.

FIG. 5 is a configuration diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating an example of a determination circuit illustrated in FIG. 5;

FIG. 7 is a circuit diagram illustrating an example of a storage control circuit illustrated in FIG. 5;

FIG. 8 is a configuration diagram showing a third embodiment of the present invention.

9 is a circuit diagram showing an example of a DQ line cutoff circuit shown in FIG.

FIG. 10 is a circuit diagram illustrating a fourth embodiment of the present invention and illustrating an example of a determination circuit.

FIG. 11 is a circuit diagram showing a fifth embodiment of the present invention and showing an example of a circuit for driving a plate line of a ferroelectric memory.

FIG. 12 is a circuit diagram showing a case where the circuit shown in FIG. 11 is applied to an STCRAM.

FIG. 13 is a block diagram illustrating an example of a computer system using the semiconductor storage device of the present invention.

[Explanation of symbols]

15a, 15b, 15c, 15d ... Bank, 21 ... memory cell array, 21a ... storage unit, 22 ... column decoder (CDC), 23 ... sense amplifier (S / A) _{group, 23 1, 23 2 ~23 n} ... sense amplifier , 24: row decoder (RDC), 25: row driver (RDRV), 26: discrimination circuit, 26a: latch circuit, 27, 27a, 27b: storage unit control circuit, 31: write inhibit circuit, DQ, / DQ: data Lines, AS-0 to AS-3 ... bank select signals, MC ... memory cells.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 16/02 G11C 17/00 601A

Claims (8)

[Claims] 1. A memory cell array divided into a plurality of banks, a storage unit provided in a memory cell array of each bank and storing data designating whether writing or reading is possible, and data stored in the storage unit And a discrimination circuit for restricting writing to the memory cell array of the bank according to the above. 2. A memory cell array divided into a plurality of banks, a storage unit provided in the memory cell array of each bank and storing data specifying whether writing or reading is possible, and shared by a plurality of adjacent banks And a data line for transmitting and receiving data to and from the memory cell array of each of the banks, and in the initialization mode, fetching data read from the storage section of the selected bank via the data line,
A semiconductor memory device comprising: a determination circuit that limits writing to a memory cell array of the bank in accordance with the fetched data. 3. A memory cell array divided into a plurality of banks, a storage unit provided in the memory cell array of each bank and storing data designating whether writing is possible, and shared by a plurality of adjacent banks, A data line for transmitting and receiving data to and from the memory cell array of each bank; and in an initialization mode, data read from the storage unit of the selected bank are fetched via the data line.
A determination circuit that limits writing to the memory cell array of the bank in accordance with the captured data; and a cutoff circuit that is inserted and connected to the data line and cuts off the data line in the initialization mode. Semiconductor storage device. 4. The semiconductor memory according to claim 1, further comprising a storage control circuit for restricting access to said storage during normal access to a memory cell array of each bank. apparatus. 5. The memory according to claim 1, wherein the determination circuit has a latch circuit for latching data read from the storage unit in an initialization mode, and stores the data in the memory cell array of the bank in accordance with the data latched by the latch circuit. 4. The semiconductor memory device according to claim 1, wherein writing is restricted. 6. The storage unit control circuit selects the storage unit in a setting mode for setting data in the storage unit and in an initialization mode for reading data set in the storage unit and setting the data in the discrimination circuit. 4. The semiconductor memory device according to claim 1, wherein selection of the storage unit is prohibited in a normal operation mode. 7. A memory cell array divided into a plurality of banks, and a discriminating circuit for restricting writing to the memory cell array of the bank, wherein the discriminating circuit has a fuse and is set to the fuse. A semiconductor memory device which limits writing to a memory cell array of the bank according to data. 8. The semiconductor memory device according to claim 1, wherein said memory cell array includes a plurality of ferroelectric memories arranged in a matrix.